File:  [DragonFly] / src / sys / bus / pci / i386 / pci_cfgreg.c
Revision 1.6: download - view: text, annotated - select for diffs
Sat Feb 7 15:56:58 2004 UTC (10 years, 7 months ago) by joerg
Branches: MAIN
CVS tags: HEAD
Add a tunable hw.pci_disable_bios_route to work around broken PCI-BIOSes.

Many BIOS implementations don't route an interrupt to cardbus bridges
by default and some doesn't provide a working call. This results in
panics on boot up. For the OLDCARD pcic, it was possible to force the
interrupt-less operation, but NEWCARD doesn't have such an option and
will never have.

    1: /*
    2:  * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
    3:  * Copyright (c) 2000, Michael Smith <msmith@freebsd.org>
    4:  * Copyright (c) 2000, BSDi
    5:  * All rights reserved.
    6:  *
    7:  * Redistribution and use in source and binary forms, with or without
    8:  * modification, are permitted provided that the following conditions
    9:  * are met:
   10:  * 1. Redistributions of source code must retain the above copyright
   11:  *    notice unmodified, this list of conditions, and the following
   12:  *    disclaimer.
   13:  * 2. Redistributions in binary form must reproduce the above copyright
   14:  *    notice, this list of conditions and the following disclaimer in the
   15:  *    documentation and/or other materials provided with the distribution.
   16:  *
   17:  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   18:  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   19:  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   20:  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   21:  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
   22:  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   23:  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   24:  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   25:  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
   26:  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   27:  *
   28:  * $FreeBSD: src/sys/i386/isa/pci_cfgreg.c,v 1.1.2.7 2001/11/28 05:47:03 imp Exp $
   29:  * $DragonFly: src/sys/bus/pci/i386/pci_cfgreg.c,v 1.6 2004/02/07 15:56:58 joerg Exp $
   30:  *
   31:  */
   32: 
   33: #include <sys/param.h>		/* XXX trim includes */
   34: #include <sys/systm.h>
   35: #include <sys/bus.h>
   36: #include <sys/kernel.h>
   37: #include <sys/module.h>
   38: #include <sys/malloc.h>
   39: #include <sys/sysctl.h>
   40: #include <vm/vm.h>
   41: #include <vm/pmap.h>
   42: #include <machine/md_var.h>
   43: #include <bus/pci/pcivar.h>
   44: #include <bus/pci/pcireg.h>
   45: #include <bus/isa/isavar.h>
   46: #include <bus/pci/i386/pci_cfgreg.h>
   47: #include <machine/segments.h>
   48: #include <machine/pc/bios.h>
   49: 
   50: #ifdef APIC_IO
   51: #include <machine/smp.h>
   52: #endif /* APIC_IO */
   53: 
   54: #define PRVERB(a) do {							\
   55: 	if (bootverbose)						\
   56: 		printf a ;						\
   57: } while(0)
   58: 
   59: static int pci_disable_bios_route = 0;
   60: SYSCTL_INT(_hw, OID_AUTO, pci_disable_bios_route, CTLFLAG_RD,
   61: 	&pci_disable_bios_route, 0, "disable interrupt routing via PCI-BIOS");
   62: TUNABLE_INT("hw.pci_disable_bios_route", &pci_disable_bios_route);
   63: 
   64: static int cfgmech;
   65: static int devmax;
   66: 
   67: static int	pci_cfgintr_valid(struct PIR_entry *pe, int pin, int irq);
   68: static int	pci_cfgintr_unique(struct PIR_entry *pe, int pin);
   69: static int	pci_cfgintr_linked(struct PIR_entry *pe, int pin);
   70: static int	pci_cfgintr_search(struct PIR_entry *pe, int bus, int device, int matchpin, int pin);
   71: static int	pci_cfgintr_virgin(struct PIR_entry *pe, int pin);
   72: 
   73: static void	pci_print_irqmask(u_int16_t irqs);
   74: static void	pci_print_route_table(struct PIR_table *prt, int size);
   75: static int	pcireg_cfgread(int bus, int slot, int func, int reg, int bytes);
   76: static void	pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes);
   77: static int	pcireg_cfgopen(void);
   78: 
   79: static struct PIR_table	*pci_route_table;
   80: static int		pci_route_count;
   81: 
   82: /*
   83:  * Some BIOS writers seem to want to ignore the spec and put
   84:  * 0 in the intline rather than 255 to indicate none. Some use
   85:  * numbers in the range 128-254 to indicate something strange and
   86:  * apparently undocumented anywhere. Assume these are completely bogus
   87:  * and map them to 255, which means "none".
   88:  */
   89: static int
   90: pci_i386_map_intline(int line)
   91: {
   92: 	if (line == 0 || line >= 128)
   93: 		return (PCI_INVALID_IRQ);
   94: 	return (line);
   95: }
   96: 
   97: static u_int16_t
   98: pcibios_get_version(void)
   99: {
  100: 	struct bios_regs args;
  101: 
  102: 	if (PCIbios.ventry == 0) {
  103: 		PRVERB(("pcibios: No call entry point\n"));
  104: 		return (0);
  105: 	}
  106: 	args.eax = PCIBIOS_BIOS_PRESENT;
  107: 	if (bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL))) {
  108: 		PRVERB(("pcibios: BIOS_PRESENT call failed\n"));
  109: 		return (0);
  110: 	}
  111: 	if (args.edx != 0x20494350) {
  112: 		PRVERB(("pcibios: BIOS_PRESENT didn't return 'PCI ' in edx\n"));
  113: 		return (0);
  114: 	}
  115: 	return (args.ebx & 0xffff);
  116: }
  117: 
  118: /* 
  119:  * Initialise access to PCI configuration space 
  120:  */
  121: int
  122: pci_cfgregopen(void)
  123: {
  124: 	static int		opened = 0;
  125: 	u_long			sigaddr;
  126: 	static struct PIR_table	*pt;
  127: 	u_int16_t		v;
  128: 	u_int8_t		ck, *cv;
  129: 	int			i;
  130: 
  131: 	if (opened)
  132: 		return (1);
  133: 
  134: 	if (pcireg_cfgopen() == 0)
  135: 		return (0);
  136: 
  137: 	v = pcibios_get_version();
  138: 	if (v > 0)
  139: 		printf("pcibios: BIOS version %x.%02x\n", (v & 0xff00) >> 8,
  140: 		       v & 0xff);
  141: 
  142: 	/*
  143: 	 * Look for the interrupt routing table.
  144: 	 *
  145: 	 * We use PCI BIOS's PIR table if it's available $PIR is the
  146: 	 * standard way to do this.  Sadly some machines are not
  147: 	 * standards conforming and have _PIR instead. We shrug and cope
  148: 	 * by looking for both.
  149: 	 */
  150: 	if (pcibios_get_version() >= 0x0210 && pt == NULL) {
  151: 		sigaddr = bios_sigsearch(0, "$PIR", 4, 16, 0);
  152: 		if (sigaddr == 0)
  153: 			sigaddr = bios_sigsearch(0, "_PIR", 4, 16, 0);
  154: 		if (sigaddr != 0) {
  155: 			pt = (struct PIR_table *)(uintptr_t)
  156: 			     BIOS_PADDRTOVADDR(sigaddr);
  157: 			for (cv = (u_int8_t *)pt, ck = 0, i = 0;
  158: 			     i < (pt->pt_header.ph_length); i++)
  159: 				ck += cv[i];
  160: 			if (ck == 0 && pt->pt_header.ph_length >
  161: 			    sizeof(struct PIR_header)) {
  162: 				pci_route_table = pt;
  163: 				pci_route_count = (pt->pt_header.ph_length -
  164: 				    sizeof(struct PIR_header)) /
  165: 				    sizeof(struct PIR_entry);
  166: 				printf("Using $PIR table, %d entries at %p\n",
  167: 				       pci_route_count, pci_route_table);
  168: 				if (bootverbose)
  169: 					pci_print_route_table(pci_route_table,
  170: 					    pci_route_count);
  171: 			}
  172: 		}
  173: 	}
  174: 	opened = 1;
  175: 	return (1);	
  176: }
  177: 
  178: /* 
  179:  * Read configuration space register
  180:  */
  181: u_int32_t
  182: pci_cfgregread(int bus, int slot, int func, int reg, int bytes)
  183: {
  184: 	uint32_t line;
  185: #ifdef APIC_IO
  186: 	uint32_t pin;
  187: 
  188: 	/*
  189: 	 * If we are using the APIC, the contents of the intline
  190: 	 * register will probably be wrong (since they are set up for
  191: 	 * use with the PIC.  Rather than rewrite these registers
  192: 	 * (maybe that would be smarter) we trap attempts to read them
  193: 	 * and translate to our private vector numbers.
  194: 	 */
  195: 	if ((reg == PCIR_INTLINE) && (bytes == 1)) {
  196: 
  197: 		pin = pcireg_cfgread(bus, slot, func, PCIR_INTPIN, 1);
  198: 		line = pcireg_cfgread(bus, slot, func, PCIR_INTLINE, 1);
  199: 
  200: 		if (pin != 0) {
  201: 			int airq;
  202: 
  203: 			airq = pci_apic_irq(bus, slot, pin);
  204: 			if (airq >= 0) {
  205: 				/* PCI specific entry found in MP table */
  206: 				if (airq != line)
  207: 					undirect_pci_irq(line);
  208: 				return (airq);
  209: 			} else {
  210: 				/* 
  211: 			 	 * PCI interrupts might be redirected to the
  212: 				 * ISA bus according to some MP tables. Use the
  213: 				 * same methods as used by the ISA devices
  214: 				 * devices to find the proper IOAPIC int pin.
  215: 				 */
  216: 				airq = isa_apic_irq(line);
  217: 				if ((airq >= 0) && (airq != line)) {
  218: 					/* XXX: undirect_pci_irq() ? */
  219: 					undirect_isa_irq(line);
  220: 					return (airq);
  221: 				}
  222: 			}
  223: 		}
  224: 		return (line);
  225:     	}
  226: #else
  227: 	/*
  228: 	 * Some BIOS writers seem to want to ignore the spec and put
  229: 	 * 0 in the intline rather than 255 to indicate none.  The rest of
  230: 	 * the code uses 255 as an invalid IRQ.
  231: 	 */
  232: 	if (reg == PCIR_INTLINE && bytes == 1) {
  233: 		line = pcireg_cfgread(bus, slot, func, PCIR_INTLINE, 1);
  234: 		return pci_i386_map_intline(line);
  235: 	}
  236: #endif /* APIC_IO */
  237: 	return (pcireg_cfgread(bus, slot, func, reg, bytes));
  238: }
  239: 
  240: /* 
  241:  * Write configuration space register 
  242:  */
  243: void
  244: pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes)
  245: {
  246: 	pcireg_cfgwrite(bus, slot, func, reg, data, bytes);
  247: }
  248: 
  249: int
  250: pci_cfgread(pcicfgregs *cfg, int reg, int bytes)
  251: {
  252: 	return (pci_cfgregread(cfg->bus, cfg->slot, cfg->func, reg, bytes));
  253: }
  254: 
  255: void
  256: pci_cfgwrite(pcicfgregs *cfg, int reg, int data, int bytes)
  257: {
  258: 	pci_cfgregwrite(cfg->bus, cfg->slot, cfg->func, reg, data, bytes);
  259: }
  260: 
  261: 
  262: /*
  263:  * Route a PCI interrupt
  264:  */
  265: int
  266: pci_cfgintr(int bus, int device, int pin, int oldirq)
  267: {
  268: 	struct PIR_entry	*pe;
  269: 	int			i, irq;
  270: 	struct bios_regs	args;
  271: 	u_int16_t		v;
  272: 
  273: 	int already = 0;
  274: 	int errok = 0;
  275:     
  276: 	v = pcibios_get_version();
  277: 	if (v < 0x0210) {
  278: 		PRVERB((
  279: 		  "pci_cfgintr: BIOS %x.%02x doesn't support interrupt routing\n",
  280: 		  (v & 0xff00) >> 8, v & 0xff));
  281: 		return (PCI_INVALID_IRQ);
  282: 	}
  283: 	if ((bus < 0) || (bus > 255) || (device < 0) || (device > 255) ||
  284: 	    (pin < 1) || (pin > 4))
  285: 		return (PCI_INVALID_IRQ);
  286: 
  287: 	/*
  288: 	 * Scan the entry table for a contender
  289: 	 */
  290: 	for (i = 0, pe = &pci_route_table->pt_entry[0]; i < pci_route_count;
  291: 	     i++, pe++) {
  292: 		if ((bus != pe->pe_bus) || (device != pe->pe_device))
  293: 			continue;
  294: 
  295: 		/*
  296: 		 * A link of 0 means that this intpin is not connected to
  297: 		 * any other device's interrupt pins and is not connected to
  298: 		 * any of the Interrupt Router's interrupt pins, so we can't
  299: 		 * route it.
  300: 		 */
  301: 		if (pe->pe_intpin[pin - 1].link == 0)
  302: 			continue;
  303: 
  304: 		if (pci_cfgintr_valid(pe, pin, oldirq)) {
  305: 			printf("pci_cfgintr: %d:%d INT%c BIOS irq %d\n", bus,
  306: 			       device, 'A' + pin - 1, oldirq);
  307: 			return (oldirq);
  308: 		}
  309: 
  310: 		/*
  311: 		 * We try to find a linked interrupt, then we look to see
  312: 		 * if the interrupt is uniquely routed, then we look for
  313: 		 * a virgin interrupt. The virgin interrupt should return
  314: 		 * an interrupt we can route, but if that fails, maybe we
  315: 		 * should try harder to route a different interrupt.
  316: 		 * However, experience has shown that that's rarely the
  317: 		 * failure mode we see.
  318: 		 */
  319: 		irq = pci_cfgintr_linked(pe, pin);
  320: 		if (irq != PCI_INVALID_IRQ)
  321: 			already = 1;
  322: 		if (irq == PCI_INVALID_IRQ) {
  323: 			irq = pci_cfgintr_unique(pe, pin);
  324: 			if (irq != PCI_INVALID_IRQ)
  325: 				errok = 1;
  326: 		}
  327: 		if (irq == PCI_INVALID_IRQ)
  328: 			irq = pci_cfgintr_virgin(pe, pin);
  329: 
  330: 		if (irq == PCI_INVALID_IRQ)
  331: 			break;
  332: 
  333: 		if (pci_disable_bios_route != 0)
  334: 			break;
  335: 		/*
  336: 		 * Ask the BIOS to route the interrupt. If we picked an
  337: 		 * interrupt that failed, we should really try other
  338: 		 * choices that the BIOS offers us.
  339: 		 *
  340: 		 * For uniquely routed interrupts, we need to try
  341: 		 * to route them on some machines. Yet other machines
  342: 		 * fail to route, so we have to pretend that in that
  343: 		 * case it worked.  Isn't PC hardware fun?
  344: 		 *
  345: 		 * NOTE: if we want to whack hardware to do this, then
  346: 		 * I think the right way to do that would be to have
  347: 		 * bridge drivers that do this. I'm not sure that the
  348: 		 * $PIR table would be valid for those interrupt
  349: 		 * routers.
  350: 		 */
  351: 		args.eax = PCIBIOS_ROUTE_INTERRUPT;
  352: 		args.ebx = (bus << 8) | (device << 3);
  353: 		/* pin value is 0xa - 0xd */
  354: 		args.ecx = (irq << 8) | (0xa + pin -1);
  355: 		if (!already &&
  356: 		    bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL)) &&
  357: 		    !errok) {
  358: 			PRVERB(("pci_cfgintr: ROUTE_INTERRUPT failed.\n"));
  359: 			return (PCI_INVALID_IRQ);
  360: 		}
  361: 		printf("pci_cfgintr: %d:%d INT%c routed to irq %d\n", bus,
  362: 		       device, 'A' + pin - 1, irq);
  363: 		return(irq);
  364: 	}
  365: 
  366: 	PRVERB(("pci_cfgintr: can't route an interrupt to %d:%d INT%c\n", bus,
  367: 	       device, 'A' + pin - 1));
  368: 	return (PCI_INVALID_IRQ);
  369: }
  370: 
  371: /*
  372:  * Check to see if an existing IRQ setting is valid.
  373:  */
  374: static int
  375: pci_cfgintr_valid(struct PIR_entry *pe, int pin, int irq)
  376: {
  377: 	uint32_t irqmask;
  378: 
  379: 	if (!PCI_INTERRUPT_VALID(irq))
  380: 		return (0);
  381: 	irqmask = pe->pe_intpin[pin - 1].irqs;
  382: 	if (irqmask & (1 << irq)) {
  383: 		PRVERB(("pci_cfgintr_valid: BIOS irq %d is valid\n", irq));
  384: 		return (1);
  385: 	}
  386: 	return (0);
  387: }
  388: 
  389: /*
  390:  * Look to see if the routing table claims this pin is uniquely routed.
  391:  */
  392: static int
  393: pci_cfgintr_unique(struct PIR_entry *pe, int pin)
  394: {
  395: 	int		irq;
  396: 	uint32_t	irqmask;
  397: 
  398: 	irqmask = pe->pe_intpin[pin - 1].irqs;
  399: 	if(irqmask != 0 && powerof2(irqmask)) {
  400: 		irq = ffs(irqmask) - 1;
  401: 		PRVERB(("pci_cfgintr_unique: hard-routed to irq %d\n", irq));
  402: 		return (irq);
  403: 	}
  404: 	return (PCI_INVALID_IRQ);
  405: }
  406: 
  407: /*
  408:  * Look for another device which shares the same link byte and
  409:  * already has a unique IRQ, or which has had one routed already.
  410:  */
  411: static int
  412: pci_cfgintr_linked(struct PIR_entry *pe, int pin)
  413: {
  414: 	struct PIR_entry	*oe;
  415: 	struct PIR_intpin	*pi;
  416: 	int			i, j, irq;
  417: 
  418: 	/*
  419: 	 * Scan table slots.
  420: 	 */
  421: 	for (i = 0, oe = &pci_route_table->pt_entry[0]; i < pci_route_count;
  422: 	     i++, oe++) {
  423: 		/* scan interrupt pins */
  424: 		for (j = 0, pi = &oe->pe_intpin[0]; j < 4; j++, pi++) {
  425: 
  426: 			/* don't look at the entry we're trying to match */
  427: 			if ((pe == oe) && (i == (pin - 1)))
  428: 				continue;
  429: 			/* compare link bytes */
  430: 			if (pi->link != pe->pe_intpin[pin - 1].link)
  431: 				continue;
  432: 			/* link destination mapped to a unique interrupt? */
  433: 			if (pi->irqs != 0 && powerof2(pi->irqs)) {
  434: 				irq = ffs(pi->irqs) - 1;
  435: 				PRVERB(("pci_cfgintr_linked: linked (%x) to hard-routed irq %d\n",
  436: 				       pi->link, irq));
  437: 				return(irq);
  438: 			} 
  439: 
  440: 			/*
  441: 			 * look for the real PCI device that matches this
  442: 			 * table entry
  443: 			 */
  444: 			irq = pci_cfgintr_search(pe, oe->pe_bus, oe->pe_device,
  445: 						 j, pin);
  446: 			if (irq != PCI_INVALID_IRQ)
  447: 				return (irq);
  448: 		}
  449: 	}
  450: 	return (PCI_INVALID_IRQ);
  451: }
  452: 
  453: /*
  454:  * Scan for the real PCI device at (bus)/(device) using intpin (matchpin) and
  455:  * see if it has already been assigned an interrupt.
  456:  */
  457: static int
  458: pci_cfgintr_search(struct PIR_entry *pe, int bus, int device, int matchpin, int pin)
  459: {
  460: 	devclass_t		pci_devclass;
  461: 	device_t		*pci_devices;
  462: 	int			pci_count;
  463: 	device_t		*pci_children;
  464: 	int			pci_childcount;
  465: 	device_t		*busp, *childp;
  466: 	int			i, j, irq;
  467: 
  468: 	/*
  469: 	 * Find all the PCI busses.
  470: 	 */
  471: 	pci_count = 0;
  472: 	if ((pci_devclass = devclass_find("pci")) != NULL)
  473: 		devclass_get_devices(pci_devclass, &pci_devices, &pci_count);
  474: 
  475: 	/*
  476: 	 * Scan all the PCI busses/devices looking for this one.
  477: 	 */
  478: 	irq = PCI_INVALID_IRQ;
  479: 	for (i = 0, busp = pci_devices; (i < pci_count) && (irq == PCI_INVALID_IRQ);
  480: 	     i++, busp++) {
  481: 		pci_childcount = 0;
  482: 		device_get_children(*busp, &pci_children, &pci_childcount);
  483: 		
  484: 		for (j = 0, childp = pci_children; j < pci_childcount; j++,
  485: 		     childp++) {
  486: 			if ((pci_get_bus(*childp) == bus) &&
  487: 			    (pci_get_slot(*childp) == device) &&
  488: 			    (pci_get_intpin(*childp) == matchpin)) {
  489: 				irq = pci_i386_map_intline(pci_get_irq(*childp));
  490: 				if (irq != PCI_INVALID_IRQ)
  491: 					PRVERB(("pci_cfgintr_search: linked (%x) to configured irq %d at %d:%d:%d\n",
  492: 					    pe->pe_intpin[pin - 1].link, irq,
  493: 					    pci_get_bus(*childp),
  494: 					    pci_get_slot(*childp),
  495: 					    pci_get_function(*childp)));
  496: 				break;
  497: 			}
  498: 		}
  499: 		if (pci_children != NULL)
  500: 			free(pci_children, M_TEMP);
  501: 	}
  502: 	if (pci_devices != NULL)
  503: 		free(pci_devices, M_TEMP);
  504: 	return (irq);
  505: }
  506: 
  507: /*
  508:  * Pick a suitable IRQ from those listed as routable to this device.
  509:  */
  510: static int
  511: pci_cfgintr_virgin(struct PIR_entry *pe, int pin)
  512: {
  513: 	int irq, ibit;
  514:     
  515: 	/*
  516: 	 * first scan the set of PCI-only interrupts and see if any of these
  517: 	 * are routable
  518: 	 */
  519: 	for (irq = 0; irq < 16; irq++) {
  520: 		ibit = (1 << irq);
  521: 
  522: 		/* can we use this interrupt? */
  523: 		if ((pci_route_table->pt_header.ph_pci_irqs & ibit) &&
  524: 		    (pe->pe_intpin[pin - 1].irqs & ibit)) {
  525: 			PRVERB(("pci_cfgintr_virgin: using routable PCI-only interrupt %d\n", irq));
  526: 			return (irq);
  527: 		}
  528: 	}
  529:     
  530: 	/* life is tough, so just pick an interrupt */
  531: 	for (irq = 0; irq < 16; irq++) {
  532: 		ibit = (1 << irq);
  533:     
  534: 		if (pe->pe_intpin[pin - 1].irqs & ibit) {
  535: 			PRVERB(("pci_cfgintr_virgin: using routable interrupt %d\n", irq));
  536: 			return (irq);
  537: 		}
  538: 	}
  539: 	return (PCI_INVALID_IRQ);
  540: }
  541: 
  542: static void
  543: pci_print_irqmask(u_int16_t irqs)
  544: {
  545: 	int i, first;
  546: 
  547: 	if (irqs == 0) {
  548: 		printf("none");
  549: 		return;
  550: 	}
  551: 	first = 1;
  552: 	for (i = 0; i < 16; i++, irqs >>= 1)
  553: 		if (irqs & 1) {
  554: 			if (!first)
  555: 				printf(" ");
  556: 			else
  557: 				first = 0;
  558: 			printf("%d", i);
  559: 		}
  560: }
  561: 
  562: /*
  563:  * Dump the contents of a PCI BIOS Interrupt Routing Table to the console.
  564:  */
  565: static void
  566: pci_print_route_table(struct PIR_table *ptr, int size)
  567: {
  568: 	struct PIR_entry *entry;
  569: 	struct PIR_intpin *intpin;
  570: 	int i, pin;
  571: 
  572: 	printf("PCI-Only Interrupts: ");
  573: 	pci_print_irqmask(ptr->pt_header.ph_pci_irqs);
  574: 	printf("\nLocation  Bus Device Pin  Link  IRQs\n");
  575: 	entry = &ptr->pt_entry[0];
  576: 	for (i = 0; i < size; i++, entry++) {
  577: 		intpin = &entry->pe_intpin[0];
  578: 		for (pin = 0; pin < 4; pin++, intpin++)
  579: 			if (intpin->link != 0) {
  580: 				if (entry->pe_slot == 0)
  581: 					printf("embedded ");
  582: 				else
  583: 					printf("slot %-3d ", entry->pe_slot);
  584: 				printf(" %3d  %3d    %c   0x%02x  ",
  585: 				       entry->pe_bus, entry->pe_device,
  586: 				       'A' + pin, intpin->link);
  587: 				pci_print_irqmask(intpin->irqs);
  588: 				printf("\n");
  589: 			}
  590: 	}
  591: }
  592: 
  593: /*
  594:  * See if any interrupts for a given PCI bus are routed in the PIR.  Don't
  595:  * even bother looking if the BIOS doesn't support routing anyways.
  596:  */
  597: int
  598: pci_probe_route_table(int bus)
  599: {
  600: 	int i;
  601: 	u_int16_t v;
  602: 
  603: 	v = pcibios_get_version();
  604: 	if (v < 0x0210)
  605: 		return (0);
  606: 	for (i = 0; i < pci_route_count; i++)
  607: 		if (pci_route_table->pt_entry[i].pe_bus == bus)
  608: 			return (1);
  609: 	return (0);
  610: }
  611: 
  612: /* 
  613:  * Configuration space access using direct register operations
  614:  */
  615: 
  616: /* enable configuration space accesses and return data port address */
  617: static int
  618: pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes)
  619: {
  620: 	int dataport = 0;
  621: 
  622: 	if (bus <= PCI_BUSMAX
  623: 	    && slot < devmax
  624: 	    && func <= PCI_FUNCMAX
  625: 	    && reg <= PCI_REGMAX
  626: 	    && bytes != 3
  627: 	    && (unsigned) bytes <= 4
  628: 	    && (reg & (bytes - 1)) == 0) {
  629: 		switch (cfgmech) {
  630: 		case 1:
  631: 			outl(CONF1_ADDR_PORT, (1 << 31)
  632: 			     | (bus << 16) | (slot << 11) 
  633: 			     | (func << 8) | (reg & ~0x03));
  634: 			dataport = CONF1_DATA_PORT + (reg & 0x03);
  635: 			break;
  636: 		case 2:
  637: 			outb(CONF2_ENABLE_PORT, 0xf0 | (func << 1));
  638: 			outb(CONF2_FORWARD_PORT, bus);
  639: 			dataport = 0xc000 | (slot << 8) | reg;
  640: 			break;
  641: 		}
  642: 	}
  643: 	return (dataport);
  644: }
  645: 
  646: /* disable configuration space accesses */
  647: static void
  648: pci_cfgdisable(void)
  649: {
  650: 	switch (cfgmech) {
  651: 	case 1:
  652: 		outl(CONF1_ADDR_PORT, 0);
  653: 		break;
  654: 	case 2:
  655: 		outb(CONF2_ENABLE_PORT, 0);
  656: 		outb(CONF2_FORWARD_PORT, 0);
  657: 		break;
  658: 	}
  659: }
  660: 
  661: static int
  662: pcireg_cfgread(int bus, int slot, int func, int reg, int bytes)
  663: {
  664: 	int data = -1;
  665: 	int port;
  666: 
  667: 	port = pci_cfgenable(bus, slot, func, reg, bytes);
  668: 	if (port != 0) {
  669: 		switch (bytes) {
  670: 		case 1:
  671: 			data = inb(port);
  672: 			break;
  673: 		case 2:
  674: 			data = inw(port);
  675: 			break;
  676: 		case 4:
  677: 			data = inl(port);
  678: 			break;
  679: 		}
  680: 		pci_cfgdisable();
  681: 	}
  682: 	return (data);
  683: }
  684: 
  685: static void
  686: pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes)
  687: {
  688: 	int port;
  689: 
  690: 	port = pci_cfgenable(bus, slot, func, reg, bytes);
  691: 	if (port != 0) {
  692: 		switch (bytes) {
  693: 		case 1:
  694: 			outb(port, data);
  695: 			break;
  696: 		case 2:
  697: 			outw(port, data);
  698: 			break;
  699: 		case 4:
  700: 			outl(port, data);
  701: 			break;
  702: 		}
  703: 		pci_cfgdisable();
  704: 	}
  705: }
  706: 
  707: /* check whether the configuration mechanism has been correctly identified */
  708: static int
  709: pci_cfgcheck(int maxdev)
  710: {
  711: 	uint32_t id, class;
  712: 	uint8_t header;
  713: 	uint8_t device;
  714: 	int port;
  715: 
  716: 	if (bootverbose) 
  717: 		printf("pci_cfgcheck:\tdevice ");
  718: 
  719: 	for (device = 0; device < maxdev; device++) {
  720: 		if (bootverbose) 
  721: 			printf("%d ", device);
  722: 
  723: 		port = pci_cfgenable(0, device, 0, 0, 4);
  724: 		id = inl(port);
  725: 		if (id == 0 || id == 0xffffffff)
  726: 			continue;
  727: 
  728: 		port = pci_cfgenable(0, device, 0, 8, 4);
  729: 		class = inl(port) >> 8;
  730: 		if (bootverbose)
  731: 			printf("[class=%06x] ", class);
  732: 		if (class == 0 || (class & 0xf870ff) != 0)
  733: 			continue;
  734: 
  735: 		port = pci_cfgenable(0, device, 0, 14, 1);
  736: 		header = inb(port);
  737: 		if (bootverbose)
  738: 			printf("[hdr=%02x] ", header);
  739: 		if ((header & 0x7e) != 0)
  740: 			continue;
  741: 
  742: 		if (bootverbose)
  743: 			printf("is there (id=%08x)\n", id);
  744: 
  745: 		pci_cfgdisable();
  746: 		return (1);
  747: 	}
  748: 	if (bootverbose) 
  749: 		printf("-- nothing found\n");
  750: 
  751: 	pci_cfgdisable();
  752: 	return (0);
  753: }
  754: 
  755: static int
  756: pcireg_cfgopen(void)
  757: {
  758: 	uint32_t mode1res,oldval1;
  759: 	uint8_t mode2res,oldval2;
  760: 
  761: 	oldval1 = inl(CONF1_ADDR_PORT);
  762: 
  763: 	if (bootverbose) {
  764: 		printf("pci_open(1):\tmode 1 addr port (0x0cf8) is 0x%08x\n",
  765: 		       oldval1);
  766: 	}
  767: 
  768: 	if ((oldval1 & CONF1_ENABLE_MSK) == 0) {
  769: 
  770: 		cfgmech = 1;
  771: 		devmax = 32;
  772: 
  773: 		outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK);
  774: 		outb(CONF1_ADDR_PORT + 3, 0);
  775: 		mode1res = inl(CONF1_ADDR_PORT);
  776: 		outl(CONF1_ADDR_PORT, oldval1);
  777: 
  778: 		if (bootverbose)
  779: 			printf("pci_open(1a):\tmode1res=0x%08x (0x%08lx)\n", 
  780: 			       mode1res, CONF1_ENABLE_CHK);
  781: 
  782: 		if (mode1res) {
  783: 			if (pci_cfgcheck(32)) 
  784: 				return (cfgmech);
  785: 		}
  786: 
  787: 		outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK1);
  788: 		mode1res = inl(CONF1_ADDR_PORT);
  789: 		outl(CONF1_ADDR_PORT, oldval1);
  790: 
  791: 		if (bootverbose)
  792: 			printf("pci_open(1b):\tmode1res=0x%08x (0x%08lx)\n", 
  793: 			       mode1res, CONF1_ENABLE_CHK1);
  794: 
  795: 		if ((mode1res & CONF1_ENABLE_MSK1) == CONF1_ENABLE_RES1) {
  796: 			if (pci_cfgcheck(32)) 
  797: 				return (cfgmech);
  798: 		}
  799: 	}
  800: 
  801: 	oldval2 = inb(CONF2_ENABLE_PORT);
  802: 
  803: 	if (bootverbose) {
  804: 		printf("pci_open(2):\tmode 2 enable port (0x0cf8) is 0x%02x\n",
  805: 		       oldval2);
  806: 	}
  807: 
  808: 	if ((oldval2 & 0xf0) == 0) {
  809: 
  810: 		cfgmech = 2;
  811: 		devmax = 16;
  812: 
  813: 		outb(CONF2_ENABLE_PORT, CONF2_ENABLE_CHK);
  814: 		mode2res = inb(CONF2_ENABLE_PORT);
  815: 		outb(CONF2_ENABLE_PORT, oldval2);
  816: 
  817: 		if (bootverbose)
  818: 			printf("pci_open(2a):\tmode2res=0x%02x (0x%02x)\n", 
  819: 			       mode2res, CONF2_ENABLE_CHK);
  820: 
  821: 		if (mode2res == CONF2_ENABLE_RES) {
  822: 			if (bootverbose)
  823: 				printf("pci_open(2a):\tnow trying mechanism 2\n");
  824: 
  825: 			if (pci_cfgcheck(16)) 
  826: 				return (cfgmech);
  827: 		}
  828: 	}
  829: 
  830: 	cfgmech = 0;
  831: 	devmax = 0;
  832: 	return (cfgmech);
  833: }