File:  [DragonFly] / src / sys / bus / pci / pci.c
Revision 1.13: download - view: text, annotated - select for diffs
Fri Jan 16 13:07:18 2004 UTC (10 years, 11 months ago) by joerg
Branches: MAIN
CVS tags: HEAD
Fix compile errors introduced with last commit

    1: /*
    2:  * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
    3:  * All rights reserved.
    4:  *
    5:  * Redistribution and use in source and binary forms, with or without
    6:  * modification, are permitted provided that the following conditions
    7:  * are met:
    8:  * 1. Redistributions of source code must retain the above copyright
    9:  *    notice unmodified, this list of conditions, and the following
   10:  *    disclaimer.
   11:  * 2. Redistributions in binary form must reproduce the above copyright
   12:  *    notice, this list of conditions and the following disclaimer in the
   13:  *    documentation and/or other materials provided with the distribution.
   14:  *
   15:  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   16:  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   17:  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   18:  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   19:  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
   20:  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   21:  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   22:  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   23:  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
   24:  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   25:  *
   26:  * $FreeBSD: src/sys/pci/pci.c,v 1.141.2.15 2002/04/30 17:48:18 tmm Exp $
   27:  * $DragonFly: src/sys/bus/pci/pci.c,v 1.13 2004/01/16 13:07:18 joerg Exp $
   28:  *
   29:  */
   30: 
   31: #include "opt_bus.h"
   32: #include "opt_pci.h"
   33: 
   34: #include "opt_simos.h"
   35: #include "opt_compat_oldpci.h"
   36: 
   37: #include <sys/param.h>
   38: #include <sys/systm.h>
   39: #include <sys/malloc.h>
   40: #include <sys/module.h>
   41: #include <sys/fcntl.h>
   42: #include <sys/conf.h>
   43: #include <sys/kernel.h>
   44: #include <sys/queue.h>
   45: #include <sys/types.h>
   46: #include <sys/buf.h>
   47: 
   48: #include <vm/vm.h>
   49: #include <vm/pmap.h>
   50: #include <vm/vm_extern.h>
   51: 
   52: #include <sys/bus.h>
   53: #include <machine/bus.h>
   54: #include <sys/rman.h>
   55: #include <machine/resource.h>
   56: #include <machine/md_var.h>		/* For the Alpha */
   57: #ifdef __i386__
   58: #include <bus/pci/i386/pci_cfgreg.h>
   59: #endif
   60: 
   61: #include <sys/pciio.h>
   62: #include "pcireg.h"
   63: #include "pcivar.h"
   64: 
   65: #include "pcib_if.h"
   66: 
   67: #ifdef __alpha__
   68: #include <machine/rpb.h>
   69: #endif
   70: 
   71: #ifdef APIC_IO
   72: #include <machine/smp.h>
   73: #endif /* APIC_IO */
   74: 
   75: static devclass_t	pci_devclass;
   76: 
   77: static void		pci_read_extcap(device_t dev, pcicfgregs *cfg);
   78: 
   79: struct pci_quirk {
   80: 	u_int32_t devid;	/* Vendor/device of the card */
   81: 	int	type;
   82: #define PCI_QUIRK_MAP_REG	1 /* PCI map register in weird place */
   83: 	int	arg1;
   84: 	int	arg2;
   85: };
   86: 
   87: struct pci_quirk pci_quirks[] = {
   88: 	/*
   89: 	 * The Intel 82371AB and 82443MX has a map register at offset 0x90.
   90: 	 */
   91: 	{ 0x71138086, PCI_QUIRK_MAP_REG,	0x90,	 0 },
   92: 	{ 0x719b8086, PCI_QUIRK_MAP_REG,	0x90,	 0 },
   93: 
   94: 	{ 0 }
   95: };
   96: 
   97: /* map register information */
   98: #define PCI_MAPMEM	0x01	/* memory map */
   99: #define PCI_MAPMEMP	0x02	/* prefetchable memory map */
  100: #define PCI_MAPPORT	0x04	/* port map */
  101: 
  102: static STAILQ_HEAD(devlist, pci_devinfo) pci_devq;
  103: u_int32_t pci_numdevs = 0;
  104: static u_int32_t pci_generation = 0;
  105: 
  106: device_t
  107: pci_find_bsf (u_int8_t bus, u_int8_t slot, u_int8_t func)
  108: {
  109: 	struct pci_devinfo *dinfo;
  110: 
  111: 	STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
  112: 		if ((dinfo->cfg.bus == bus) &&
  113: 		    (dinfo->cfg.slot == slot) &&
  114: 		    (dinfo->cfg.func == func)) {
  115: 			return (dinfo->cfg.dev);
  116: 		}
  117: 	}
  118: 
  119: 	return (NULL);
  120: }
  121: 
  122: device_t
  123: pci_find_device (u_int16_t vendor, u_int16_t device)
  124: {
  125: 	struct pci_devinfo *dinfo;
  126: 
  127: 	STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
  128: 		if ((dinfo->cfg.vendor == vendor) &&
  129: 		    (dinfo->cfg.device == device)) {
  130: 			return (dinfo->cfg.dev);
  131: 		}
  132: 	}
  133: 
  134: 	return (NULL);
  135: }
  136: 
  137: /* return base address of memory or port map */
  138: 
  139: static u_int32_t
  140: pci_mapbase(unsigned mapreg)
  141: {
  142: 	int mask = 0x03;
  143: 	if ((mapreg & 0x01) == 0)
  144: 		mask = 0x0f;
  145: 	return (mapreg & ~mask);
  146: }
  147: 
  148: /* return map type of memory or port map */
  149: 
  150: static int
  151: pci_maptype(unsigned mapreg)
  152: {
  153: 	static u_int8_t maptype[0x10] = {
  154: 		PCI_MAPMEM,		PCI_MAPPORT,
  155: 		PCI_MAPMEM,		0,
  156: 		PCI_MAPMEM,		PCI_MAPPORT,
  157: 		0,			0,
  158: 		PCI_MAPMEM|PCI_MAPMEMP,	PCI_MAPPORT,
  159: 		PCI_MAPMEM|PCI_MAPMEMP, 0,
  160: 		PCI_MAPMEM|PCI_MAPMEMP,	PCI_MAPPORT,
  161: 		0,			0,
  162: 	};
  163: 
  164: 	return maptype[mapreg & 0x0f];
  165: }
  166: 
  167: /* return log2 of map size decoded for memory or port map */
  168: 
  169: static int
  170: pci_mapsize(unsigned testval)
  171: {
  172: 	int ln2size;
  173: 
  174: 	testval = pci_mapbase(testval);
  175: 	ln2size = 0;
  176: 	if (testval != 0) {
  177: 		while ((testval & 1) == 0)
  178: 		{
  179: 			ln2size++;
  180: 			testval >>= 1;
  181: 		}
  182: 	}
  183: 	return (ln2size);
  184: }
  185: 
  186: /* return log2 of address range supported by map register */
  187: 
  188: static int
  189: pci_maprange(unsigned mapreg)
  190: {
  191: 	int ln2range = 0;
  192: 	switch (mapreg & 0x07) {
  193: 	case 0x00:
  194: 	case 0x01:
  195: 	case 0x05:
  196: 		ln2range = 32;
  197: 		break;
  198: 	case 0x02:
  199: 		ln2range = 20;
  200: 		break;
  201: 	case 0x04:
  202: 		ln2range = 64;
  203: 		break;
  204: 	}
  205: 	return (ln2range);
  206: }
  207: 
  208: /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
  209: 
  210: static void
  211: pci_fixancient(pcicfgregs *cfg)
  212: {
  213: 	if (cfg->hdrtype != 0)
  214: 		return;
  215: 
  216: 	/* PCI to PCI bridges use header type 1 */
  217: 	if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
  218: 		cfg->hdrtype = 1;
  219: }
  220: 
  221: /* read config data specific to header type 1 device (PCI to PCI bridge) */
  222: 
  223: static void *
  224: pci_readppb(device_t pcib, int b, int s, int f)
  225: {
  226: 	pcih1cfgregs *p;
  227: 
  228: 	p = malloc(sizeof (pcih1cfgregs), M_DEVBUF, M_WAITOK | M_ZERO);
  229: 	if (p == NULL)
  230: 		return (NULL);
  231: 
  232: 	p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_1, 2);
  233: 	p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_1, 2);
  234: 
  235: 	p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_1, 1);
  236: 
  237: 	p->iobase = PCI_PPBIOBASE (PCIB_READ_CONFIG(pcib, b, s, f,
  238: 						    PCIR_IOBASEH_1, 2),
  239: 				   PCIB_READ_CONFIG(pcib, b, s, f,
  240: 				   		    PCIR_IOBASEL_1, 1));
  241: 	p->iolimit = PCI_PPBIOLIMIT (PCIB_READ_CONFIG(pcib, b, s, f,
  242: 						      PCIR_IOLIMITH_1, 2),
  243: 				     PCIB_READ_CONFIG(pcib, b, s, f,
  244: 				     		      PCIR_IOLIMITL_1, 1));
  245: 
  246: 	p->membase = PCI_PPBMEMBASE (0,
  247: 				     PCIB_READ_CONFIG(pcib, b, s, f,
  248: 				     		      PCIR_MEMBASE_1, 2));
  249: 	p->memlimit = PCI_PPBMEMLIMIT (0,
  250: 				       PCIB_READ_CONFIG(pcib, b, s, f,
  251: 				       		        PCIR_MEMLIMIT_1, 2));
  252: 
  253: 	p->pmembase = PCI_PPBMEMBASE (
  254: 		(pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEH_1, 4),
  255: 		PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEL_1, 2));
  256: 
  257: 	p->pmemlimit = PCI_PPBMEMLIMIT (
  258: 		(pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f,
  259: 					     PCIR_PMLIMITH_1, 4),
  260: 		PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMLIMITL_1, 2));
  261: 
  262: 	return (p);
  263: }
  264: 
  265: /* read config data specific to header type 2 device (PCI to CardBus bridge) */
  266: 
  267: static void *
  268: pci_readpcb(device_t pcib, int b, int s, int f)
  269: {
  270: 	pcih2cfgregs *p;
  271: 
  272: 	p = malloc(sizeof (pcih2cfgregs), M_DEVBUF, M_WAITOK | M_ZERO);
  273: 	if (p == NULL)
  274: 		return (NULL);
  275: 
  276: 	p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_2, 2);
  277: 	p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_2, 2);
  278: 	
  279: 	p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_2, 1);
  280: 
  281: 	p->membase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE0_2, 4);
  282: 	p->memlimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT0_2, 4);
  283: 	p->membase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE1_2, 4);
  284: 	p->memlimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT1_2, 4);
  285: 
  286: 	p->iobase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE0_2, 4);
  287: 	p->iolimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT0_2, 4);
  288: 	p->iobase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE1_2, 4);
  289: 	p->iolimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT1_2, 4);
  290: 
  291: 	p->pccardif = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PCCARDIF_2, 4);
  292: 	return p;
  293: }
  294: 
  295: /* extract header type specific config data */
  296: 
  297: static void
  298: pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
  299: {
  300: #define REG(n,w)	PCIB_READ_CONFIG(pcib, b, s, f, n, w)
  301: 	switch (cfg->hdrtype) {
  302: 	case 0:
  303: 		cfg->subvendor      = REG(PCIR_SUBVEND_0, 2);
  304: 		cfg->subdevice      = REG(PCIR_SUBDEV_0, 2);
  305: 		cfg->nummaps	    = PCI_MAXMAPS_0;
  306: 		break;
  307: 	case 1:
  308: 		cfg->subvendor      = REG(PCIR_SUBVEND_1, 2);
  309: 		cfg->subdevice      = REG(PCIR_SUBDEV_1, 2);
  310: 		cfg->secondarybus   = REG(PCIR_SECBUS_1, 1);
  311: 		cfg->subordinatebus = REG(PCIR_SUBBUS_1, 1);
  312: 		cfg->nummaps	    = PCI_MAXMAPS_1;
  313: 		cfg->hdrspec        = pci_readppb(pcib, b, s, f);
  314: 		break;
  315: 	case 2:
  316: 		cfg->subvendor      = REG(PCIR_SUBVEND_2, 2);
  317: 		cfg->subdevice      = REG(PCIR_SUBDEV_2, 2);
  318: 		cfg->secondarybus   = REG(PCIR_SECBUS_2, 1);
  319: 		cfg->subordinatebus = REG(PCIR_SUBBUS_2, 1);
  320: 		cfg->nummaps	    = PCI_MAXMAPS_2;
  321: 		cfg->hdrspec        = pci_readpcb(pcib, b, s, f);
  322: 		break;
  323: 	}
  324: #undef REG
  325: }
  326: 
  327: /* read configuration header into pcicfgrect structure */
  328: 
  329: static struct pci_devinfo *
  330: pci_read_device(device_t pcib, int b, int s, int f)
  331: {
  332: #define REG(n, w)	PCIB_READ_CONFIG(pcib, b, s, f, n, w)
  333: 
  334: 	pcicfgregs *cfg = NULL;
  335: 	struct pci_devinfo *devlist_entry;
  336: 	struct devlist *devlist_head;
  337: 
  338: 	devlist_head = &pci_devq;
  339: 
  340: 	devlist_entry = NULL;
  341: 
  342: 	if (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_DEVVENDOR, 4) != -1) {
  343: 
  344: 		devlist_entry = malloc(sizeof(struct pci_devinfo),
  345: 				       M_DEVBUF, M_WAITOK | M_ZERO);
  346: 		if (devlist_entry == NULL)
  347: 			return (NULL);
  348: 
  349: 		cfg = &devlist_entry->cfg;
  350: 		
  351: 		cfg->bus		= b;
  352: 		cfg->slot		= s;
  353: 		cfg->func		= f;
  354: 		cfg->vendor		= REG(PCIR_VENDOR, 2);
  355: 		cfg->device		= REG(PCIR_DEVICE, 2);
  356: 		cfg->cmdreg		= REG(PCIR_COMMAND, 2);
  357: 		cfg->statreg		= REG(PCIR_STATUS, 2);
  358: 		cfg->baseclass		= REG(PCIR_CLASS, 1);
  359: 		cfg->subclass		= REG(PCIR_SUBCLASS, 1);
  360: 		cfg->progif		= REG(PCIR_PROGIF, 1);
  361: 		cfg->revid		= REG(PCIR_REVID, 1);
  362: 		cfg->hdrtype		= REG(PCIR_HEADERTYPE, 1);
  363: 		cfg->cachelnsz		= REG(PCIR_CACHELNSZ, 1);
  364: 		cfg->lattimer		= REG(PCIR_LATTIMER, 1);
  365: 		cfg->intpin		= REG(PCIR_INTPIN, 1);
  366: 		cfg->intline		= REG(PCIR_INTLINE, 1);
  367: #ifdef __alpha__
  368: 		alpha_platform_assign_pciintr(cfg);
  369: #endif
  370: 
  371: #ifdef APIC_IO
  372: 		if (cfg->intpin != 0) {
  373: 			int airq;
  374: 
  375: 			airq = pci_apic_irq(cfg->bus, cfg->slot, cfg->intpin);
  376: 			if (airq >= 0) {
  377: 				/* PCI specific entry found in MP table */
  378: 				if (airq != cfg->intline) {
  379: 					undirect_pci_irq(cfg->intline);
  380: 					cfg->intline = airq;
  381: 				}
  382: 			} else {
  383: 				/* 
  384: 				 * PCI interrupts might be redirected to the
  385: 				 * ISA bus according to some MP tables. Use the
  386: 				 * same methods as used by the ISA devices
  387: 				 * devices to find the proper IOAPIC int pin.
  388: 				 */
  389: 				airq = isa_apic_irq(cfg->intline);
  390: 				if ((airq >= 0) && (airq != cfg->intline)) {
  391: 					/* XXX: undirect_pci_irq() ? */
  392: 					undirect_isa_irq(cfg->intline);
  393: 					cfg->intline = airq;
  394: 				}
  395: 			}
  396: 		}
  397: #endif /* APIC_IO */
  398: 
  399: 		cfg->mingnt		= REG(PCIR_MINGNT, 1);
  400: 		cfg->maxlat		= REG(PCIR_MAXLAT, 1);
  401: 
  402: 		cfg->mfdev		= (cfg->hdrtype & PCIM_MFDEV) != 0;
  403: 		cfg->hdrtype		&= ~PCIM_MFDEV;
  404: 
  405: 		pci_fixancient(cfg);
  406: 		pci_hdrtypedata(pcib, b, s, f, cfg);
  407: 
  408: 		if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT)
  409: 			pci_read_extcap(pcib, cfg);
  410: 
  411: 		STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
  412: 
  413: 		devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
  414: 		devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
  415: 		devlist_entry->conf.pc_sel.pc_func = cfg->func;
  416: 		devlist_entry->conf.pc_hdr = cfg->hdrtype;
  417: 
  418: 		devlist_entry->conf.pc_subvendor = cfg->subvendor;
  419: 		devlist_entry->conf.pc_subdevice = cfg->subdevice;
  420: 		devlist_entry->conf.pc_vendor = cfg->vendor;
  421: 		devlist_entry->conf.pc_device = cfg->device;
  422: 
  423: 		devlist_entry->conf.pc_class = cfg->baseclass;
  424: 		devlist_entry->conf.pc_subclass = cfg->subclass;
  425: 		devlist_entry->conf.pc_progif = cfg->progif;
  426: 		devlist_entry->conf.pc_revid = cfg->revid;
  427: 
  428: 		pci_numdevs++;
  429: 		pci_generation++;
  430: 	}
  431: 	return (devlist_entry);
  432: #undef REG
  433: }
  434: 
  435: static void
  436: pci_read_extcap(device_t pcib, pcicfgregs *cfg)
  437: {
  438: #define REG(n, w)	PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
  439: 	int	ptr, nextptr, ptrptr;
  440: 
  441: 	switch (cfg->hdrtype) {
  442: 	case 0:
  443: 		ptrptr = 0x34;
  444: 		break;
  445: 	case 2:
  446: 		ptrptr = 0x14;
  447: 		break;
  448: 	default:
  449: 		return;		/* no extended capabilities support */
  450: 	}
  451: 	nextptr = REG(ptrptr, 1);	/* sanity check? */
  452: 
  453: 	/*
  454: 	 * Read capability entries.
  455: 	 */
  456: 	while (nextptr != 0) {
  457: 		/* Sanity check */
  458: 		if (nextptr > 255) {
  459: 			printf("illegal PCI extended capability offset %d\n",
  460: 			    nextptr);
  461: 			return;
  462: 		}
  463: 		/* Find the next entry */
  464: 		ptr = nextptr;
  465: 		nextptr = REG(ptr + 1, 1);
  466: 
  467: 		/* Process this entry */
  468: 		switch (REG(ptr, 1)) {
  469: 		case 0x01:		/* PCI power management */
  470: 			if (cfg->pp_cap == 0) {
  471: 				cfg->pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
  472: 				cfg->pp_status = ptr + PCIR_POWER_STATUS;
  473: 				cfg->pp_pmcsr = ptr + PCIR_POWER_PMCSR;
  474: 				if ((nextptr - ptr) > PCIR_POWER_DATA)
  475: 					cfg->pp_data = ptr + PCIR_POWER_DATA;
  476: 			}
  477: 			break;
  478: 		default:
  479: 			break;
  480: 		}
  481: 	}
  482: #undef REG
  483: }
  484: 
  485: #if 0
  486: /* free pcicfgregs structure and all depending data structures */
  487: 
  488: static int
  489: pci_freecfg(struct pci_devinfo *dinfo)
  490: {
  491: 	struct devlist *devlist_head;
  492: 
  493: 	devlist_head = &pci_devq;
  494: 
  495: 	if (dinfo->cfg.hdrspec != NULL)
  496: 		free(dinfo->cfg.hdrspec, M_DEVBUF);
  497: 	if (dinfo->cfg.map != NULL)
  498: 		free(dinfo->cfg.map, M_DEVBUF);
  499: 	/* XXX this hasn't been tested */
  500: 	STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
  501: 	free(dinfo, M_DEVBUF);
  502: 
  503: 	/* increment the generation count */
  504: 	pci_generation++;
  505: 
  506: 	/* we're losing one device */
  507: 	pci_numdevs--;
  508: 	return (0);
  509: }
  510: #endif
  511: 
  512: 
  513: /*
  514:  * PCI power manangement
  515:  */
  516: static int
  517: pci_set_powerstate_method(device_t dev, device_t child, int state)
  518: {
  519: 	struct pci_devinfo *dinfo = device_get_ivars(child);
  520: 	pcicfgregs *cfg = &dinfo->cfg;
  521: 	u_int16_t status;
  522: 	int result;
  523: 
  524: 	if (cfg->pp_cap != 0) {
  525: 		status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2) & ~PCIM_PSTAT_DMASK;
  526: 		result = 0;
  527: 		switch (state) {
  528: 		case PCI_POWERSTATE_D0:
  529: 			status |= PCIM_PSTAT_D0;
  530: 			break;
  531: 		case PCI_POWERSTATE_D1:
  532: 			if (cfg->pp_cap & PCIM_PCAP_D1SUPP) {
  533: 				status |= PCIM_PSTAT_D1;
  534: 			} else {
  535: 				result = EOPNOTSUPP;
  536: 			}
  537: 			break;
  538: 		case PCI_POWERSTATE_D2:
  539: 			if (cfg->pp_cap & PCIM_PCAP_D2SUPP) {
  540: 				status |= PCIM_PSTAT_D2;
  541: 			} else {
  542: 				result = EOPNOTSUPP;
  543: 			}
  544: 			break;
  545: 		case PCI_POWERSTATE_D3:
  546: 			status |= PCIM_PSTAT_D3;
  547: 			break;
  548: 		default:
  549: 			result = EINVAL;
  550: 		}
  551: 		if (result == 0)
  552: 			PCI_WRITE_CONFIG(dev, child, cfg->pp_status, status, 2);
  553: 	} else {
  554: 		result = ENXIO;
  555: 	}
  556: 	return(result);
  557: }
  558: 
  559: static int
  560: pci_get_powerstate_method(device_t dev, device_t child)
  561: {
  562: 	struct pci_devinfo *dinfo = device_get_ivars(child);
  563: 	pcicfgregs *cfg = &dinfo->cfg;
  564: 	u_int16_t status;
  565: 	int result;
  566: 
  567: 	if (cfg->pp_cap != 0) {
  568: 		status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2);
  569: 		switch (status & PCIM_PSTAT_DMASK) {
  570: 		case PCIM_PSTAT_D0:
  571: 			result = PCI_POWERSTATE_D0;
  572: 			break;
  573: 		case PCIM_PSTAT_D1:
  574: 			result = PCI_POWERSTATE_D1;
  575: 			break;
  576: 		case PCIM_PSTAT_D2:
  577: 			result = PCI_POWERSTATE_D2;
  578: 			break;
  579: 		case PCIM_PSTAT_D3:
  580: 			result = PCI_POWERSTATE_D3;
  581: 			break;
  582: 		default:
  583: 			result = PCI_POWERSTATE_UNKNOWN;
  584: 			break;
  585: 		}
  586: 	} else {
  587: 		/* No support, device is always at D0 */
  588: 		result = PCI_POWERSTATE_D0;
  589: 	}
  590: 	return(result);
  591: }
  592: 
  593: /*
  594:  * Some convenience functions for PCI device drivers.
  595:  */
  596: 
  597: static __inline void
  598: pci_set_command_bit(device_t dev, device_t child, u_int16_t bit)
  599: {
  600:     u_int16_t	command;
  601: 
  602:     command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
  603:     command |= bit;
  604:     PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
  605: }
  606: 
  607: static __inline void
  608: pci_clear_command_bit(device_t dev, device_t child, u_int16_t bit)
  609: {
  610:     u_int16_t	command;
  611: 
  612:     command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
  613:     command &= ~bit;
  614:     PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
  615: }
  616: 
  617: static void
  618: pci_enable_busmaster_method(device_t dev, device_t child)
  619: {
  620:     pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
  621: }
  622: 
  623: static void
  624: pci_disable_busmaster_method(device_t dev, device_t child)
  625: {
  626:     pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
  627: }
  628: 
  629: static void
  630: pci_enable_io_method(device_t dev, device_t child, int space)
  631: {
  632:     switch(space) {
  633:     case SYS_RES_IOPORT:
  634: 	pci_set_command_bit(dev, child, PCIM_CMD_PORTEN);
  635: 	break;
  636:     case SYS_RES_MEMORY:
  637: 	pci_set_command_bit(dev, child, PCIM_CMD_MEMEN);
  638: 	break;
  639:     }
  640: }
  641: 
  642: static void
  643: pci_disable_io_method(device_t dev, device_t child, int space)
  644: {
  645:     switch(space) {
  646:     case SYS_RES_IOPORT:
  647: 	pci_clear_command_bit(dev, child, PCIM_CMD_PORTEN);
  648: 	break;
  649:     case SYS_RES_MEMORY:
  650: 	pci_clear_command_bit(dev, child, PCIM_CMD_MEMEN);
  651: 	break;
  652:     }
  653: }
  654: 
  655: /*
  656:  * This is the user interface to PCI configuration space.
  657:  */
  658:   
  659: static int
  660: pci_open(dev_t dev, int oflags, int devtype, struct thread *td)
  661: {
  662: 	if ((oflags & FWRITE) && securelevel > 0) {
  663: 		return EPERM;
  664: 	}
  665: 	return 0;
  666: }
  667: 
  668: static int
  669: pci_close(dev_t dev, int flag, int devtype, struct thread *td)
  670: {
  671: 	return 0;
  672: }
  673: 
  674: /*
  675:  * Match a single pci_conf structure against an array of pci_match_conf
  676:  * structures.  The first argument, 'matches', is an array of num_matches
  677:  * pci_match_conf structures.  match_buf is a pointer to the pci_conf
  678:  * structure that will be compared to every entry in the matches array.
  679:  * This function returns 1 on failure, 0 on success.
  680:  */
  681: static int
  682: pci_conf_match(struct pci_match_conf *matches, int num_matches, 
  683: 	       struct pci_conf *match_buf)
  684: {
  685: 	int i;
  686: 
  687: 	if ((matches == NULL) || (match_buf == NULL) || (num_matches <= 0))
  688: 		return(1);
  689: 
  690: 	for (i = 0; i < num_matches; i++) {
  691: 		/*
  692: 		 * I'm not sure why someone would do this...but...
  693: 		 */
  694: 		if (matches[i].flags == PCI_GETCONF_NO_MATCH)
  695: 			continue;
  696: 
  697: 		/*
  698: 		 * Look at each of the match flags.  If it's set, do the
  699: 		 * comparison.  If the comparison fails, we don't have a
  700: 		 * match, go on to the next item if there is one.
  701: 		 */
  702: 		if (((matches[i].flags & PCI_GETCONF_MATCH_BUS) != 0)
  703: 		 && (match_buf->pc_sel.pc_bus != matches[i].pc_sel.pc_bus))
  704: 			continue;
  705: 
  706: 		if (((matches[i].flags & PCI_GETCONF_MATCH_DEV) != 0)
  707: 		 && (match_buf->pc_sel.pc_dev != matches[i].pc_sel.pc_dev))
  708: 			continue;
  709: 
  710: 		if (((matches[i].flags & PCI_GETCONF_MATCH_FUNC) != 0)
  711: 		 && (match_buf->pc_sel.pc_func != matches[i].pc_sel.pc_func))
  712: 			continue;
  713: 
  714: 		if (((matches[i].flags & PCI_GETCONF_MATCH_VENDOR) != 0) 
  715: 		 && (match_buf->pc_vendor != matches[i].pc_vendor))
  716: 			continue;
  717: 
  718: 		if (((matches[i].flags & PCI_GETCONF_MATCH_DEVICE) != 0)
  719: 		 && (match_buf->pc_device != matches[i].pc_device))
  720: 			continue;
  721: 
  722: 		if (((matches[i].flags & PCI_GETCONF_MATCH_CLASS) != 0)
  723: 		 && (match_buf->pc_class != matches[i].pc_class))
  724: 			continue;
  725: 
  726: 		if (((matches[i].flags & PCI_GETCONF_MATCH_UNIT) != 0)
  727: 		 && (match_buf->pd_unit != matches[i].pd_unit))
  728: 			continue;
  729: 
  730: 		if (((matches[i].flags & PCI_GETCONF_MATCH_NAME) != 0)
  731: 		 && (strncmp(matches[i].pd_name, match_buf->pd_name,
  732: 			     sizeof(match_buf->pd_name)) != 0))
  733: 			continue;
  734: 
  735: 		return(0);
  736: 	}
  737: 
  738: 	return(1);
  739: }
  740: 
  741: /*
  742:  * Locate the parent of a PCI device by scanning the PCI devlist
  743:  * and return the entry for the parent.
  744:  * For devices on PCI Bus 0 (the host bus), this is the PCI Host.
  745:  * For devices on secondary PCI busses, this is that bus' PCI-PCI Bridge.
  746:  */
  747: 
  748: pcicfgregs *
  749: pci_devlist_get_parent(pcicfgregs *cfg)
  750: {
  751: 	struct devlist *devlist_head;
  752: 	struct pci_devinfo *dinfo;
  753: 	pcicfgregs *bridge_cfg;
  754: 	int i;
  755: 
  756: 	dinfo = STAILQ_FIRST(devlist_head = &pci_devq);
  757: 
  758: 	/* If the device is on PCI bus 0, look for the host */
  759: 	if (cfg->bus == 0) {
  760: 		for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
  761: 		dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
  762: 			bridge_cfg = &dinfo->cfg;
  763: 			if (bridge_cfg->baseclass == PCIC_BRIDGE
  764: 				&& bridge_cfg->subclass == PCIS_BRIDGE_HOST
  765: 		    		&& bridge_cfg->bus == cfg->bus) {
  766: 				return bridge_cfg;
  767: 			}
  768: 		}
  769: 	}
  770: 
  771: 	/* If the device is not on PCI bus 0, look for the PCI-PCI bridge */
  772: 	if (cfg->bus > 0) {
  773: 		for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
  774: 		dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
  775: 			bridge_cfg = &dinfo->cfg;
  776: 			if (bridge_cfg->baseclass == PCIC_BRIDGE
  777: 				&& bridge_cfg->subclass == PCIS_BRIDGE_PCI
  778: 				&& bridge_cfg->secondarybus == cfg->bus) {
  779: 				return bridge_cfg;
  780: 			}
  781: 		}
  782: 	}
  783: 
  784: 	return NULL; 
  785: }
  786: 
  787: static int
  788: pci_ioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct thread *td)
  789: {
  790: 	device_t pci, pcib;
  791: 	struct pci_io *io;
  792: 	const char *name;
  793: 	int error;
  794: 
  795: 	if (!(flag & FWRITE))
  796: 		return EPERM;
  797: 
  798: 
  799: 	switch(cmd) {
  800: 	case PCIOCGETCONF:
  801: 		{
  802: 		struct pci_devinfo *dinfo;
  803: 		struct pci_conf_io *cio;
  804: 		struct devlist *devlist_head;
  805: 		struct pci_match_conf *pattern_buf;
  806: 		int num_patterns;
  807: 		size_t iolen;
  808: 		int ionum, i;
  809: 
  810: 		cio = (struct pci_conf_io *)data;
  811: 
  812: 		num_patterns = 0;
  813: 		dinfo = NULL;
  814: 
  815: 		/*
  816: 		 * Hopefully the user won't pass in a null pointer, but it
  817: 		 * can't hurt to check.
  818: 		 */
  819: 		if (cio == NULL) {
  820: 			error = EINVAL;
  821: 			break;
  822: 		}
  823: 
  824: 		/*
  825: 		 * If the user specified an offset into the device list,
  826: 		 * but the list has changed since they last called this
  827: 		 * ioctl, tell them that the list has changed.  They will
  828: 		 * have to get the list from the beginning.
  829: 		 */
  830: 		if ((cio->offset != 0)
  831: 		 && (cio->generation != pci_generation)){
  832: 			cio->num_matches = 0;	
  833: 			cio->status = PCI_GETCONF_LIST_CHANGED;
  834: 			error = 0;
  835: 			break;
  836: 		}
  837: 
  838: 		/*
  839: 		 * Check to see whether the user has asked for an offset
  840: 		 * past the end of our list.
  841: 		 */
  842: 		if (cio->offset >= pci_numdevs) {
  843: 			cio->num_matches = 0;
  844: 			cio->status = PCI_GETCONF_LAST_DEVICE;
  845: 			error = 0;
  846: 			break;
  847: 		}
  848: 
  849: 		/* get the head of the device queue */
  850: 		devlist_head = &pci_devq;
  851: 
  852: 		/*
  853: 		 * Determine how much room we have for pci_conf structures.
  854: 		 * Round the user's buffer size down to the nearest
  855: 		 * multiple of sizeof(struct pci_conf) in case the user
  856: 		 * didn't specify a multiple of that size.
  857: 		 */
  858: 		iolen = min(cio->match_buf_len - 
  859: 			    (cio->match_buf_len % sizeof(struct pci_conf)),
  860: 			    pci_numdevs * sizeof(struct pci_conf));
  861: 
  862: 		/*
  863: 		 * Since we know that iolen is a multiple of the size of
  864: 		 * the pciconf union, it's okay to do this.
  865: 		 */
  866: 		ionum = iolen / sizeof(struct pci_conf);
  867: 
  868: 		/*
  869: 		 * If this test is true, the user wants the pci_conf
  870: 		 * structures returned to match the supplied entries.
  871: 		 */
  872: 		if ((cio->num_patterns > 0)
  873: 		 && (cio->pat_buf_len > 0)) {
  874: 			/*
  875: 			 * pat_buf_len needs to be:
  876: 			 * num_patterns * sizeof(struct pci_match_conf)
  877: 			 * While it is certainly possible the user just
  878: 			 * allocated a large buffer, but set the number of
  879: 			 * matches correctly, it is far more likely that
  880: 			 * their kernel doesn't match the userland utility
  881: 			 * they're using.  It's also possible that the user
  882: 			 * forgot to initialize some variables.  Yes, this
  883: 			 * may be overly picky, but I hazard to guess that
  884: 			 * it's far more likely to just catch folks that
  885: 			 * updated their kernel but not their userland.
  886: 			 */
  887: 			if ((cio->num_patterns *
  888: 			    sizeof(struct pci_match_conf)) != cio->pat_buf_len){
  889: 				/* The user made a mistake, return an error*/
  890: 				cio->status = PCI_GETCONF_ERROR;
  891: 				printf("pci_ioctl: pat_buf_len %d != "
  892: 				       "num_patterns (%d) * sizeof(struct "
  893: 				       "pci_match_conf) (%d)\npci_ioctl: "
  894: 				       "pat_buf_len should be = %d\n",
  895: 				       cio->pat_buf_len, cio->num_patterns,
  896: 				       (int)sizeof(struct pci_match_conf),
  897: 				       (int)sizeof(struct pci_match_conf) * 
  898: 				       cio->num_patterns);
  899: 				printf("pci_ioctl: do your headers match your "
  900: 				       "kernel?\n");
  901: 				cio->num_matches = 0;
  902: 				error = EINVAL;
  903: 				break;
  904: 			}
  905: 
  906: 			/*
  907: 			 * Check the user's buffer to make sure it's readable.
  908: 			 */
  909: 			if (!useracc((caddr_t)cio->patterns,
  910: 				    cio->pat_buf_len, VM_PROT_READ)) {
  911: 				printf("pci_ioctl: pattern buffer %p, "
  912: 				       "length %u isn't user accessible for"
  913: 				       " READ\n", cio->patterns,
  914: 				       cio->pat_buf_len);
  915: 				error = EACCES;
  916: 				break;
  917: 			}
  918: 			/*
  919: 			 * Allocate a buffer to hold the patterns.
  920: 			 */
  921: 			pattern_buf = malloc(cio->pat_buf_len, M_TEMP,
  922: 					     M_WAITOK);
  923: 			error = copyin(cio->patterns, pattern_buf,
  924: 				       cio->pat_buf_len);
  925: 			if (error != 0)
  926: 				break;
  927: 			num_patterns = cio->num_patterns;
  928: 
  929: 		} else if ((cio->num_patterns > 0)
  930: 			|| (cio->pat_buf_len > 0)) {
  931: 			/*
  932: 			 * The user made a mistake, spit out an error.
  933: 			 */
  934: 			cio->status = PCI_GETCONF_ERROR;
  935: 			cio->num_matches = 0;
  936: 			printf("pci_ioctl: invalid GETCONF arguments\n");
  937: 			error = EINVAL;
  938: 			break;
  939: 		} else
  940: 			pattern_buf = NULL;
  941: 
  942: 		/*
  943: 		 * Make sure we can write to the match buffer.
  944: 		 */
  945: 		if (!useracc((caddr_t)cio->matches,
  946: 			     cio->match_buf_len, VM_PROT_WRITE)) {
  947: 			printf("pci_ioctl: match buffer %p, length %u "
  948: 			       "isn't user accessible for WRITE\n",
  949: 			       cio->matches, cio->match_buf_len);
  950: 			error = EACCES;
  951: 			break;
  952: 		}
  953: 
  954: 		/*
  955: 		 * Go through the list of devices and copy out the devices
  956: 		 * that match the user's criteria.
  957: 		 */
  958: 		for (cio->num_matches = 0, error = 0, i = 0,
  959: 		     dinfo = STAILQ_FIRST(devlist_head);
  960: 		     (dinfo != NULL) && (cio->num_matches < ionum)
  961: 		     && (error == 0) && (i < pci_numdevs);
  962: 		     dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
  963: 
  964: 			if (i < cio->offset)
  965: 				continue;
  966: 
  967: 			/* Populate pd_name and pd_unit */
  968: 			name = NULL;
  969: 			if (dinfo->cfg.dev && dinfo->conf.pd_name[0] == '\0')
  970: 				name = device_get_name(dinfo->cfg.dev);
  971: 			if (name) {
  972: 				strncpy(dinfo->conf.pd_name, name,
  973: 					sizeof(dinfo->conf.pd_name));
  974: 				dinfo->conf.pd_name[PCI_MAXNAMELEN] = 0;
  975: 				dinfo->conf.pd_unit =
  976: 					device_get_unit(dinfo->cfg.dev);
  977: 			}
  978: 
  979: 			if ((pattern_buf == NULL) ||
  980: 			    (pci_conf_match(pattern_buf, num_patterns,
  981: 					    &dinfo->conf) == 0)) {
  982: 
  983: 				/*
  984: 				 * If we've filled up the user's buffer,
  985: 				 * break out at this point.  Since we've
  986: 				 * got a match here, we'll pick right back
  987: 				 * up at the matching entry.  We can also
  988: 				 * tell the user that there are more matches
  989: 				 * left.
  990: 				 */
  991: 				if (cio->num_matches >= ionum)
  992: 					break;
  993: 
  994: 				error = copyout(&dinfo->conf,
  995: 					        &cio->matches[cio->num_matches],
  996: 						sizeof(struct pci_conf));
  997: 				cio->num_matches++;
  998: 			}
  999: 		}
 1000: 
 1001: 		/*
 1002: 		 * Set the pointer into the list, so if the user is getting
 1003: 		 * n records at a time, where n < pci_numdevs,
 1004: 		 */
 1005: 		cio->offset = i;
 1006: 
 1007: 		/*
 1008: 		 * Set the generation, the user will need this if they make
 1009: 		 * another ioctl call with offset != 0.
 1010: 		 */
 1011: 		cio->generation = pci_generation;
 1012: 		
 1013: 		/*
 1014: 		 * If this is the last device, inform the user so he won't
 1015: 		 * bother asking for more devices.  If dinfo isn't NULL, we
 1016: 		 * know that there are more matches in the list because of
 1017: 		 * the way the traversal is done.
 1018: 		 */
 1019: 		if (dinfo == NULL)
 1020: 			cio->status = PCI_GETCONF_LAST_DEVICE;
 1021: 		else
 1022: 			cio->status = PCI_GETCONF_MORE_DEVS;
 1023: 
 1024: 		if (pattern_buf != NULL)
 1025: 			free(pattern_buf, M_TEMP);
 1026: 
 1027: 		break;
 1028: 		}
 1029: 	case PCIOCREAD:
 1030: 		io = (struct pci_io *)data;
 1031: 		switch(io->pi_width) {
 1032: 		case 4:
 1033: 		case 2:
 1034: 		case 1:
 1035: 			/*
 1036: 			 * Assume that the user-level bus number is
 1037: 			 * actually the pciN instance number. We map
 1038: 			 * from that to the real pcib+bus combination.
 1039: 			 */
 1040: 			pci = devclass_get_device(pci_devclass,
 1041: 						  io->pi_sel.pc_bus);
 1042: 			if (pci) {
 1043: 				int b = pcib_get_bus(pci);
 1044: 				pcib = device_get_parent(pci);
 1045: 				io->pi_data = 
 1046: 					PCIB_READ_CONFIG(pcib,
 1047: 							 b,
 1048: 							 io->pi_sel.pc_dev,
 1049: 							 io->pi_sel.pc_func,
 1050: 							 io->pi_reg,
 1051: 							 io->pi_width);
 1052: 				error = 0;
 1053: 			} else {
 1054: 				error = ENODEV;
 1055: 			}
 1056: 			break;
 1057: 		default:
 1058: 			error = ENODEV;
 1059: 			break;
 1060: 		}
 1061: 		break;
 1062: 
 1063: 	case PCIOCWRITE:
 1064: 		io = (struct pci_io *)data;
 1065: 		switch(io->pi_width) {
 1066: 		case 4:
 1067: 		case 2:
 1068: 		case 1:
 1069: 			/*
 1070: 			 * Assume that the user-level bus number is
 1071: 			 * actually the pciN instance number. We map
 1072: 			 * from that to the real pcib+bus combination.
 1073: 			 */
 1074: 			pci = devclass_get_device(pci_devclass,
 1075: 						  io->pi_sel.pc_bus);
 1076: 			if (pci) {
 1077: 				int b = pcib_get_bus(pci);
 1078: 				pcib = device_get_parent(pci);
 1079: 				PCIB_WRITE_CONFIG(pcib,
 1080: 						  b,
 1081: 						  io->pi_sel.pc_dev,
 1082: 						  io->pi_sel.pc_func,
 1083: 						  io->pi_reg,
 1084: 						  io->pi_data,
 1085: 						  io->pi_width);
 1086: 				error = 0;
 1087: 			} else {
 1088: 				error = ENODEV;
 1089: 			}
 1090: 			break;
 1091: 		default:
 1092: 			error = ENODEV;
 1093: 			break;
 1094: 		}
 1095: 		break;
 1096: 
 1097: 	default:
 1098: 		error = ENOTTY;
 1099: 		break;
 1100: 	}
 1101: 
 1102: 	return (error);
 1103: }
 1104: 
 1105: #define	PCI_CDEV	78
 1106: 
 1107: static struct cdevsw pcicdev = {
 1108: 	/* name */	"pci",
 1109: 	/* maj */	PCI_CDEV,
 1110: 	/* flags */	0,
 1111: 	/* port */	NULL,
 1112: 	/* autoq */	0,
 1113: 
 1114: 	/* open */	pci_open,
 1115: 	/* close */	pci_close,
 1116: 	/* read */	noread,
 1117: 	/* write */	nowrite,
 1118: 	/* ioctl */	pci_ioctl,
 1119: 	/* poll */	nopoll,
 1120: 	/* mmap */	nommap,
 1121: 	/* strategy */	nostrategy,
 1122: 	/* dump */	nodump,
 1123: 	/* psize */	nopsize
 1124: };
 1125: 
 1126: #include "pci_if.h"
 1127: 
 1128: /*
 1129:  * New style pci driver.  Parent device is either a pci-host-bridge or a
 1130:  * pci-pci-bridge.  Both kinds are represented by instances of pcib.
 1131:  */
 1132: 
 1133: static void
 1134: pci_print_verbose(struct pci_devinfo *dinfo)
 1135: {
 1136: 	if (bootverbose) {
 1137: 		pcicfgregs *cfg = &dinfo->cfg;
 1138: 
 1139: 		printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 
 1140: 		       cfg->vendor, cfg->device, cfg->revid);
 1141: 		printf("\tbus=%d, slot=%d, func=%d\n",
 1142: 		       cfg->bus, cfg->slot, cfg->func);
 1143: 		printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
 1144: 		       cfg->baseclass, cfg->subclass, cfg->progif,
 1145: 		       cfg->hdrtype, cfg->mfdev);
 1146: 		printf("\tsubordinatebus=%x \tsecondarybus=%x\n",
 1147: 		       cfg->subordinatebus, cfg->secondarybus);
 1148: #ifdef PCI_DEBUG
 1149: 		printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 
 1150: 		       cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
 1151: 		printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
 1152: 		       cfg->lattimer, cfg->lattimer * 30, 
 1153: 		       cfg->mingnt, cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
 1154: #endif /* PCI_DEBUG */
 1155: 		if (cfg->intpin > 0)
 1156: 			printf("\tintpin=%c, irq=%d\n", cfg->intpin +'a' -1, cfg->intline);
 1157: 	}
 1158: }
 1159: 
 1160: static int
 1161: pci_porten(device_t pcib, int b, int s, int f)
 1162: {
 1163: 	return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
 1164: 		& PCIM_CMD_PORTEN) != 0;
 1165: }
 1166: 
 1167: static int
 1168: pci_memen(device_t pcib, int b, int s, int f)
 1169: {
 1170: 	return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
 1171: 		& PCIM_CMD_MEMEN) != 0;
 1172: }
 1173: 
 1174: /*
 1175:  * Add a resource based on a pci map register. Return 1 if the map
 1176:  * register is a 32bit map register or 2 if it is a 64bit register.
 1177:  */
 1178: static int
 1179: pci_add_map(device_t pcib, int b, int s, int f, int reg,
 1180: 	    struct resource_list *rl)
 1181: {
 1182: 	u_int32_t map;
 1183: 	u_int64_t base;
 1184: 	u_int8_t ln2size;
 1185: 	u_int8_t ln2range;
 1186: 	u_int32_t testval;
 1187: 
 1188: 
 1189: #ifdef PCI_ENABLE_IO_MODES
 1190: 	u_int16_t cmd;
 1191: #endif		
 1192: 	int type;
 1193: 
 1194: 	map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
 1195: 
 1196: 	if (map == 0 || map == 0xffffffff)
 1197: 		return 1; /* skip invalid entry */
 1198: 
 1199: 	PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4);
 1200: 	testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
 1201: 	PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4);
 1202: 
 1203: 	base = pci_mapbase(map);
 1204: 	if (pci_maptype(map) & PCI_MAPMEM)
 1205: 		type = SYS_RES_MEMORY;
 1206: 	else
 1207: 		type = SYS_RES_IOPORT;
 1208: 	ln2size = pci_mapsize(testval);
 1209: 	ln2range = pci_maprange(testval);
 1210: 	if (ln2range == 64) {
 1211: 		/* Read the other half of a 64bit map register */
 1212: 		base |= (u_int64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg+4, 4);
 1213: 	}
 1214: 
 1215: 	/*
 1216: 	 * This code theoretically does the right thing, but has
 1217: 	 * undesirable side effects in some cases where
 1218: 	 * peripherals respond oddly to having these bits
 1219: 	 * enabled.  Leave them alone by default.
 1220: 	 */
 1221: #ifdef PCI_ENABLE_IO_MODES
 1222: 	if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) {
 1223: 		cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
 1224: 		cmd |= PCIM_CMD_PORTEN;
 1225: 		PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
 1226: 	}
 1227: 	if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) {
 1228: 		cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
 1229: 		cmd |= PCIM_CMD_MEMEN;
 1230: 		PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
 1231: 	}
 1232: #else
 1233:         if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
 1234:                 return 1;
 1235:         if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
 1236: 		return 1;
 1237: #endif
 1238: 
 1239: 	resource_list_add(rl, type, reg,
 1240: 			  base, base + (1 << ln2size) - 1,
 1241: 			  (1 << ln2size));
 1242: 
 1243: 	if (bootverbose) {
 1244: 		printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d\n",
 1245: 		       reg, pci_maptype(base), ln2range,
 1246: 		       (unsigned int) base, ln2size);
 1247: 	}
 1248: 
 1249: 	return (ln2range == 64) ? 2 : 1;
 1250: }
 1251: 
 1252: static void
 1253: pci_add_resources(device_t pcib, int b, int s, int f, device_t dev)
 1254: {
 1255: 	struct pci_devinfo *dinfo = device_get_ivars(dev);
 1256: 	pcicfgregs *cfg = &dinfo->cfg;
 1257: 	struct resource_list *rl = &dinfo->resources;
 1258: 	struct pci_quirk *q;
 1259: 	int i;
 1260: 
 1261: 	for (i = 0; i < cfg->nummaps;) {
 1262: 		i += pci_add_map(pcib, b, s, f, PCIR_MAPS + i*4, rl);
 1263: 	}
 1264: 
 1265: 	for (q = &pci_quirks[0]; q->devid; q++) {
 1266: 		if (q->devid == ((cfg->device << 16) | cfg->vendor)
 1267: 		    && q->type == PCI_QUIRK_MAP_REG)
 1268: 			pci_add_map(pcib, b, s, f, q->arg1, rl);
 1269: 	}
 1270: 
 1271: 	if (cfg->intpin > 0 && cfg->intline != 255)
 1272: 		resource_list_add(rl, SYS_RES_IRQ, 0,
 1273: 				  cfg->intline, cfg->intline, 1);
 1274: }
 1275: 
 1276: static void
 1277: pci_add_children(device_t dev, int busno)
 1278: {
 1279: 	device_t pcib = device_get_parent(dev);
 1280: 	int maxslots;
 1281: 	int s, f;
 1282: 
 1283: 	maxslots = PCIB_MAXSLOTS(pcib);
 1284: 
 1285: 	for (s = 0; s <= maxslots; s++) {
 1286: 		int pcifunchigh = 0;
 1287: 		for (f = 0; f <= f; f++) {
 1288: 			struct pci_devinfo *dinfo = 
 1289: 				pci_read_device(pcib, busno, s, f);
 1290: 			if (dinfo != NULL) {
 1291: 				if (dinfo->cfg.mfdev)
 1292: 					pcifunchigh = 7;
 1293: 
 1294: 				pci_print_verbose(dinfo);
 1295: 				dinfo->cfg.dev = device_add_child(dev, NULL, -1);
 1296: 				device_set_ivars(dinfo->cfg.dev, dinfo);
 1297: 				pci_add_resources(pcib, busno, s, f,
 1298: 						  dinfo->cfg.dev);
 1299: 			}
 1300: 		}
 1301: 	}
 1302: }
 1303: 
 1304: static int
 1305: pci_probe(device_t dev)
 1306: {
 1307: 	static int once, busno;
 1308: 
 1309: 	device_set_desc(dev, "PCI bus");
 1310: 
 1311: 	if (bootverbose)
 1312: 		device_printf(dev, "physical bus=%d\n", pcib_get_bus(dev));
 1313: 
 1314: 	/*
 1315: 	 * Since there can be multiple independently numbered PCI
 1316: 	 * busses on some large alpha systems, we can't use the unit
 1317: 	 * number to decide what bus we are probing. We ask the parent
 1318: 	 * pcib what our bus number is.
 1319: 	 */
 1320: 	busno = pcib_get_bus(dev);
 1321: 	if (busno < 0)
 1322: 		return ENXIO;
 1323: 	pci_add_children(dev, busno);
 1324: 
 1325: 	if (!once) {
 1326: 		make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, "pci");
 1327: 		once++;
 1328: 	}
 1329: 
 1330: 	return 0;
 1331: }
 1332: 
 1333: static int
 1334: pci_print_resources(struct resource_list *rl, const char *name, int type,
 1335: 		    const char *format)
 1336: {
 1337: 	struct resource_list_entry *rle;
 1338: 	int printed, retval;
 1339: 
 1340: 	printed = 0;
 1341: 	retval = 0;
 1342: 	/* Yes, this is kinda cheating */
 1343: 	SLIST_FOREACH(rle, rl, link) {
 1344: 		if (rle->type == type) {
 1345: 			if (printed == 0)
 1346: 				retval += printf(" %s ", name);
 1347: 			else if (printed > 0)
 1348: 				retval += printf(",");
 1349: 			printed++;
 1350: 			retval += printf(format, rle->start);
 1351: 			if (rle->count > 1) {
 1352: 				retval += printf("-");
 1353: 				retval += printf(format, rle->start +
 1354: 						 rle->count - 1);
 1355: 			}
 1356: 		}
 1357: 	}
 1358: 	return retval;
 1359: }
 1360: 
 1361: static int
 1362: pci_print_child(device_t dev, device_t child)
 1363: {
 1364: 	struct pci_devinfo *dinfo;
 1365: 	struct resource_list *rl;
 1366: 	pcicfgregs *cfg;
 1367: 	int retval = 0;
 1368: 
 1369: 	dinfo = device_get_ivars(child);
 1370: 	cfg = &dinfo->cfg;
 1371: 	rl = &dinfo->resources;
 1372: 
 1373: 	retval += bus_print_child_header(dev, child);
 1374: 
 1375: 	retval += pci_print_resources(rl, "port", SYS_RES_IOPORT, "%#lx");
 1376: 	retval += pci_print_resources(rl, "mem", SYS_RES_MEMORY, "%#lx");
 1377: 	retval += pci_print_resources(rl, "irq", SYS_RES_IRQ, "%ld");
 1378: 	if (device_get_flags(dev))
 1379: 		retval += printf(" flags %#x", device_get_flags(dev));
 1380: 
 1381: 	retval += printf(" at device %d.%d", pci_get_slot(child),
 1382: 			 pci_get_function(child));
 1383: 
 1384: 	retval += bus_print_child_footer(dev, child);
 1385: 
 1386: 	return (retval);
 1387: }
 1388: 
 1389: static void
 1390: pci_probe_nomatch(device_t dev, device_t child)
 1391: {
 1392: 	struct pci_devinfo *dinfo;
 1393: 	pcicfgregs *cfg;
 1394: 	const char *desc;
 1395: 	int unknown;
 1396: 
 1397: 	unknown = 0;
 1398: 	dinfo = device_get_ivars(child);
 1399: 	cfg = &dinfo->cfg;
 1400: 	desc = pci_ata_match(child);
 1401: 	if (!desc) desc = pci_usb_match(child);
 1402: 	if (!desc) desc = pci_vga_match(child);
 1403: 	if (!desc) desc = pci_chip_match(child);
 1404: 	if (!desc) {
 1405: 		desc = "unknown card";
 1406: 		unknown++;
 1407: 	}
 1408: 	device_printf(dev, "<%s>", desc);
 1409: 	if (bootverbose || unknown) {
 1410: 		printf(" (vendor=0x%04x, dev=0x%04x)",
 1411: 			cfg->vendor,
 1412: 			cfg->device);
 1413: 	}
 1414: 	printf(" at %d.%d",
 1415: 		pci_get_slot(child),
 1416: 		pci_get_function(child));
 1417: 	if (cfg->intpin > 0 && cfg->intline != 255) {
 1418: 		printf(" irq %d", cfg->intline);
 1419: 	}
 1420: 	printf("\n");
 1421:                                       
 1422: 	return;
 1423: }
 1424: 
 1425: static int
 1426: pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
 1427: {
 1428: 	struct pci_devinfo *dinfo;
 1429: 	pcicfgregs *cfg;
 1430: 
 1431: 	dinfo = device_get_ivars(child);
 1432: 	cfg = &dinfo->cfg;
 1433: 
 1434: 	switch (which) {
 1435: 	case PCI_IVAR_SUBVENDOR:
 1436: 		*result = cfg->subvendor;
 1437: 		break;
 1438: 	case PCI_IVAR_SUBDEVICE:
 1439: 		*result = cfg->subdevice;
 1440: 		break;
 1441: 	case PCI_IVAR_VENDOR:
 1442: 		*result = cfg->vendor;
 1443: 		break;
 1444: 	case PCI_IVAR_DEVICE:
 1445: 		*result = cfg->device;
 1446: 		break;
 1447: 	case PCI_IVAR_DEVID:
 1448: 		*result = (cfg->device << 16) | cfg->vendor;
 1449: 		break;
 1450: 	case PCI_IVAR_CLASS:
 1451: 		*result = cfg->baseclass;
 1452: 		break;
 1453: 	case PCI_IVAR_SUBCLASS:
 1454: 		*result = cfg->subclass;
 1455: 		break;
 1456: 	case PCI_IVAR_PROGIF:
 1457: 		*result = cfg->progif;
 1458: 		break;
 1459: 	case PCI_IVAR_REVID:
 1460: 		*result = cfg->revid;
 1461: 		break;
 1462: 	case PCI_IVAR_INTPIN:
 1463: 		*result = cfg->intpin;
 1464: 		break;
 1465: 	case PCI_IVAR_IRQ:
 1466: 		*result = cfg->intline;
 1467: 		break;
 1468: 	case PCI_IVAR_BUS:
 1469: 		*result = cfg->bus;
 1470: 		break;
 1471: 	case PCI_IVAR_SLOT:
 1472: 		*result = cfg->slot;
 1473: 		break;
 1474: 	case PCI_IVAR_FUNCTION:
 1475: 		*result = cfg->func;
 1476: 		break;
 1477: 	case PCI_IVAR_SECONDARYBUS:
 1478: 		*result = cfg->secondarybus;
 1479: 		break;
 1480: 	case PCI_IVAR_SUBORDINATEBUS:
 1481: 		*result = cfg->subordinatebus;
 1482: 		break;
 1483: 	default:
 1484: 		return ENOENT;
 1485: 	}
 1486: 	return 0;
 1487: }
 1488: 
 1489: static int
 1490: pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
 1491: {
 1492: 	struct pci_devinfo *dinfo;
 1493: 	pcicfgregs *cfg;
 1494: 
 1495: 	dinfo = device_get_ivars(child);
 1496: 	cfg = &dinfo->cfg;
 1497: 
 1498: 	switch (which) {
 1499: 	case PCI_IVAR_SUBVENDOR:
 1500: 	case PCI_IVAR_SUBDEVICE:
 1501: 	case PCI_IVAR_VENDOR:
 1502: 	case PCI_IVAR_DEVICE:
 1503: 	case PCI_IVAR_DEVID:
 1504: 	case PCI_IVAR_CLASS:
 1505: 	case PCI_IVAR_SUBCLASS:
 1506: 	case PCI_IVAR_PROGIF:
 1507: 	case PCI_IVAR_REVID:
 1508: 	case PCI_IVAR_INTPIN:
 1509: 	case PCI_IVAR_IRQ:
 1510: 	case PCI_IVAR_BUS:
 1511: 	case PCI_IVAR_SLOT:
 1512: 	case PCI_IVAR_FUNCTION:
 1513: 		return EINVAL;	/* disallow for now */
 1514: 
 1515: 	case PCI_IVAR_SECONDARYBUS:
 1516: 		cfg->secondarybus = value;
 1517: 		break;
 1518: 	case PCI_IVAR_SUBORDINATEBUS:
 1519: 		cfg->subordinatebus = value;
 1520: 		break;
 1521: 	default:
 1522: 		return ENOENT;
 1523: 	}
 1524: 	return 0;
 1525: }
 1526: 
 1527: static struct resource *
 1528: pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
 1529: 		   u_long start, u_long end, u_long count, u_int flags)
 1530: {
 1531: 	struct pci_devinfo *dinfo = device_get_ivars(child);
 1532: 	struct resource_list *rl = &dinfo->resources;
 1533: 
 1534: #ifdef __i386__
 1535: 	pcicfgregs *cfg = &dinfo->cfg;
 1536: 	/*
 1537: 	 * Perform lazy resource allocation
 1538: 	 *
 1539: 	 * XXX add support here for SYS_RES_IOPORT and SYS_RES_MEMORY
 1540: 	 */
 1541: 	if (device_get_parent(child) == dev) {
 1542: 		/*
 1543: 		 * If device doesn't have an interrupt routed, and is
 1544: 		 * deserving of an interrupt, try to assign it one.
 1545: 		 */
 1546: 		if ((type == SYS_RES_IRQ) &&
 1547: 		    (cfg->intline == 255 || cfg->intline == 0) &&
 1548: 		    (cfg->intpin != 0) && (start == 0) && (end == ~0UL)) {
 1549: 			cfg->intline = PCIB_ROUTE_INTERRUPT(
 1550: 				device_get_parent(dev), child,
 1551: 				cfg->intpin);
 1552: 			if (cfg->intline != 255) {
 1553: 				pci_write_config(child, PCIR_INTLINE,
 1554: 				    cfg->intline, 1);
 1555: 				resource_list_add(rl, SYS_RES_IRQ, 0,
 1556: 				    cfg->intline, cfg->intline, 1);
 1557: 			}
 1558: 		}
 1559: 	}
 1560: #endif
 1561: 	return resource_list_alloc(rl, dev, child, type, rid,
 1562: 				   start, end, count, flags);
 1563: }
 1564: 
 1565: static int
 1566: pci_release_resource(device_t dev, device_t child, int type, int rid,
 1567: 		     struct resource *r)
 1568: {
 1569: 	struct pci_devinfo *dinfo = device_get_ivars(child);
 1570: 	struct resource_list *rl = &dinfo->resources;
 1571: 
 1572: 	return resource_list_release(rl, dev, child, type, rid, r);
 1573: }
 1574: 
 1575: static int
 1576: pci_set_resource(device_t dev, device_t child, int type, int rid,
 1577: 		 u_long start, u_long count)
 1578: {
 1579: 	struct pci_devinfo *dinfo = device_get_ivars(child);
 1580: 	struct resource_list *rl = &dinfo->resources;
 1581: 
 1582: 	resource_list_add(rl, type, rid, start, start + count - 1, count);
 1583: 	return 0;
 1584: }
 1585: 
 1586: static int
 1587: pci_get_resource(device_t dev, device_t child, int type, int rid,
 1588: 		 u_long *startp, u_long *countp)
 1589: {
 1590: 	struct pci_devinfo *dinfo = device_get_ivars(child);
 1591: 	struct resource_list *rl = &dinfo->resources;
 1592: 	struct resource_list_entry *rle;
 1593: 
 1594: 	rle = resource_list_find(rl, type, rid);
 1595: 	if (!rle)
 1596: 		return ENOENT;
 1597: 	
 1598: 	if (startp)
 1599: 		*startp = rle->start;
 1600: 	if (countp)
 1601: 		*countp = rle->count;
 1602: 
 1603: 	return 0;
 1604: }
 1605: 
 1606: static void
 1607: pci_delete_resource(device_t dev, device_t child, int type, int rid)
 1608: {
 1609: 	printf("pci_delete_resource: PCI resources can not be deleted\n");
 1610: }
 1611: 
 1612: static u_int32_t
 1613: pci_read_config_method(device_t dev, device_t child, int reg, int width)
 1614: {
 1615: 	struct pci_devinfo *dinfo = device_get_ivars(child);
 1616: 	pcicfgregs *cfg = &dinfo->cfg;
 1617: 
 1618: 	return PCIB_READ_CONFIG(device_get_parent(dev),
 1619: 				 cfg->bus, cfg->slot, cfg->func,
 1620: 				 reg, width);
 1621: }
 1622: 
 1623: static void
 1624: pci_write_config_method(device_t dev, device_t child, int reg,
 1625: 			u_int32_t val, int width)
 1626: {
 1627: 	struct pci_devinfo *dinfo = device_get_ivars(child);
 1628: 	pcicfgregs *cfg = &dinfo->cfg;
 1629: 
 1630: 	PCIB_WRITE_CONFIG(device_get_parent(dev),
 1631: 			  cfg->bus, cfg->slot, cfg->func,
 1632: 			  reg, val, width);
 1633: }
 1634: 
 1635: static int
 1636: pci_modevent(module_t mod, int what, void *arg)
 1637: {
 1638: 	switch (what) {
 1639: 	case MOD_LOAD:
 1640: 		STAILQ_INIT(&pci_devq);
 1641: 		break;
 1642: 
 1643: 	case MOD_UNLOAD:
 1644: 		break;
 1645: 	}
 1646: 
 1647: 	return 0;
 1648: }
 1649: 
 1650: static device_method_t pci_methods[] = {
 1651: 	/* Device interface */
 1652: 	DEVMETHOD(device_probe,		pci_probe),
 1653: 	DEVMETHOD(device_attach,	bus_generic_attach),
 1654: 	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
 1655: 	DEVMETHOD(device_suspend,	bus_generic_suspend),
 1656: 	DEVMETHOD(device_resume,	bus_generic_resume),
 1657: 
 1658: 	/* Bus interface */
 1659: 	DEVMETHOD(bus_print_child,	pci_print_child),
 1660: 	DEVMETHOD(bus_probe_nomatch,	pci_probe_nomatch),
 1661: 	DEVMETHOD(bus_read_ivar,	pci_read_ivar),
 1662: 	DEVMETHOD(bus_write_ivar,	pci_write_ivar),
 1663: 	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
 1664: 	DEVMETHOD(bus_alloc_resource,	pci_alloc_resource),
 1665: 	DEVMETHOD(bus_release_resource,	pci_release_resource),
 1666: 	DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
 1667: 	DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
 1668: 	DEVMETHOD(bus_setup_intr,	bus_generic_setup_intr),
 1669: 	DEVMETHOD(bus_teardown_intr,	bus_generic_teardown_intr),
 1670: 	DEVMETHOD(bus_set_resource,	pci_set_resource),
 1671: 	DEVMETHOD(bus_get_resource,	pci_get_resource),
 1672: 	DEVMETHOD(bus_delete_resource,	pci_delete_resource),
 1673: 
 1674: 	/* PCI interface */
 1675: 	DEVMETHOD(pci_read_config,	pci_read_config_method),
 1676: 	DEVMETHOD(pci_write_config,	pci_write_config_method),
 1677: 	DEVMETHOD(pci_enable_busmaster,	pci_enable_busmaster_method),
 1678: 	DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
 1679: 	DEVMETHOD(pci_enable_io,	pci_enable_io_method),
 1680: 	DEVMETHOD(pci_disable_io,	pci_disable_io_method),
 1681: 	DEVMETHOD(pci_get_powerstate,	pci_get_powerstate_method),
 1682: 	DEVMETHOD(pci_set_powerstate,	pci_set_powerstate_method),
 1683: 
 1684: 	{ 0, 0 }
 1685: };
 1686: 
 1687: static driver_t pci_driver = {
 1688: 	"pci",
 1689: 	pci_methods,
 1690: 	1,			/* no softc */
 1691: };
 1692: 
 1693: DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0);