File:  [DragonFly] / src / sys / bus / usb / ehcireg.h
Revision 1.2: download - view: text, annotated - select for diffs
Wed Feb 11 15:17:26 2004 UTC (10 years, 6 months ago) by joerg
Branches: MAIN
CVS tags: HEAD, DragonFly_1_0_RC1
Add defined(__FreeBSD__) and defined(__DragonFly__) where appropriate

    1: /*
    2:  * $NetBSD: ehcireg.h,v 1.13 2001/11/23 01:16:27 augustss Exp $
    3:  * $FreeBSD: src/sys/dev/usb/ehcireg.h,v 1.1 2003/04/14 14:04:07 ticso Exp $
    4:  * $DragonFly: src/sys/bus/usb/ehcireg.h,v 1.2 2004/02/11 15:17:26 joerg Exp $
    5:  */
    6: /*
    7:  * Copyright (c) 2001 The NetBSD Foundation, Inc.
    8:  * All rights reserved.
    9:  *
   10:  * This code is derived from software contributed to The NetBSD Foundation
   11:  * by Lennart Augustsson (lennart@augustsson.net).
   12:  *
   13:  * Redistribution and use in source and binary forms, with or without
   14:  * modification, are permitted provided that the following conditions
   15:  * are met:
   16:  * 1. Redistributions of source code must retain the above copyright
   17:  *    notice, this list of conditions and the following disclaimer.
   18:  * 2. Redistributions in binary form must reproduce the above copyright
   19:  *    notice, this list of conditions and the following disclaimer in the
   20:  *    documentation and/or other materials provided with the distribution.
   21:  * 3. All advertising materials mentioning features or use of this software
   22:  *    must display the following acknowledgement:
   23:  *        This product includes software developed by the NetBSD
   24:  *        Foundation, Inc. and its contributors.
   25:  * 4. Neither the name of The NetBSD Foundation nor the names of its
   26:  *    contributors may be used to endorse or promote products derived
   27:  *    from this software without specific prior written permission.
   28:  *
   29:  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
   30:  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
   31:  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
   32:  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
   33:  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   34:  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   35:  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   36:  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   37:  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   38:  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   39:  * POSSIBILITY OF SUCH DAMAGE.
   40:  */
   41: 
   42: /*
   43:  * The EHCI 0.96 spec can be found at
   44:  * http://developer.intel.com/technology/usb/download/ehci-r096.pdf
   45:  * and the USB 2.0 spec at
   46:  * http://www.usb.org/developers/data/usb_20.zip
   47:  */
   48: 
   49: #ifndef _DEV_PCI_EHCIREG_H_
   50: #define _DEV_PCI_EHCIREG_H_
   51: 
   52: /*** PCI config registers ***/
   53: 
   54: #define PCI_CBMEM		0x10	/* configuration base MEM */
   55: 
   56: #define PCI_INTERFACE_EHCI	0x20
   57: 
   58: #define PCI_USBREV		0x60	/* RO USB protocol revision */
   59: #define  PCI_USBREV_MASK	0xff
   60: #define  PCI_USBREV_PRE_1_0	0x00
   61: #define  PCI_USBREV_1_0		0x10
   62: #define  PCI_USBREV_1_1		0x11
   63: #define  PCI_USBREV_2_0		0x20
   64: 
   65: #define PCI_EHCI_FLADJ		0x61	/*RW Frame len adj, SOF=59488+6*fladj */
   66: 
   67: #define PCI_EHCI_PORTWAKECAP	0x62	/* RW Port wake caps (opt)  */
   68: 
   69: /* Regs ar EECP + offset */
   70: #define PCI_EHCI_USBLEGSUP	0x00
   71: #define PCI_EHCI_USBLEGCTLSTS	0x04
   72: 
   73: /*** EHCI capability registers ***/
   74: 
   75: #define EHCI_CAPLENGTH		0x00	/*RO Capability register length field */
   76: /* reserved			0x01 */
   77: #define EHCI_HCIVERSION		0x02	/* RO Interface version number */
   78: 
   79: #define EHCI_HCSPARAMS		0x04	/* RO Structural parameters */
   80: #define  EHCI_HCS_DEBUGPORT(x)	(((x) >> 20) & 0xf)
   81: #define  EHCI_HCS_P_INCICATOR(x) ((x) & 0x10000)
   82: #define  EHCI_HCS_N_CC(x)	(((x) >> 12) & 0xf) /* # of companion ctlrs */
   83: #define  EHCI_HCS_N_PCC(x)	(((x) >> 8) & 0xf) /* # of ports per comp. */
   84: #define  EHCI_HCS_PPC(x)	((x) & 0x10) /* port power control */
   85: #define  EHCI_HCS_N_PORTS(x)	((x) & 0xf) /* # of ports */
   86: 
   87: #define EHCI_HCCPARAMS		0x08	/* RO Capability parameters */
   88: #define  EHCI_HCC_EECP(x)	(((x) >> 8) & 0xff) /* extended ports caps */
   89: #define  EHCI_HCC_IST(x)	(((x) >> 4) & 0xf) /* isoc sched threshold */
   90: #define  EHCI_HCC_ASPC(x)	((x) & 0x4) /* async sched park cap */
   91: #define  EHCI_HCC_PFLF(x)	((x) & 0x2) /* prog frame list flag */
   92: #define  EHCI_HCC_64BIT(x)	((x) & 0x1) /* 64 bit address cap */
   93: 
   94: #define EHCI_HCSP_PORTROUTE	0x0c	/*RO Companion port route description */
   95: 
   96: /* EHCI operational registers.  Offset given by EHCI_CAPLENGTH register */
   97: #define EHCI_USBCMD		0x00	/* RO, RW, WO Command register */
   98: #define  EHCI_CMD_ITC_M		0x00ff0000 /* RW interrupt threshold ctrl */
   99: #define   EHCI_CMD_ITC_1	0x00010000
  100: #define   EHCI_CMD_ITC_2	0x00020000
  101: #define   EHCI_CMD_ITC_4	0x00040000
  102: #define   EHCI_CMD_ITC_8	0x00080000
  103: #define   EHCI_CMD_ITC_16	0x00100000
  104: #define   EHCI_CMD_ITC_32	0x00200000
  105: #define   EHCI_CMD_ITC_64	0x00400000
  106: #define  EHCI_CMD_ASPME		0x00000800 /* RW/RO async park enable */
  107: #define  EHCI_CMD_ASPMC		0x00000300 /* RW/RO async park count */
  108: #define  EHCI_CMD_LHCR		0x00000080 /* RW light host ctrl reset */
  109: #define  EHCI_CMD_IAAD		0x00000040 /* RW intr on async adv door bell */
  110: #define  EHCI_CMD_ASE		0x00000020 /* RW async sched enable */
  111: #define  EHCI_CMD_PSE		0x00000010 /* RW periodic sched enable */
  112: #define  EHCI_CMD_FLS_M		0x0000000c /* RW/RO frame list size */
  113: #define  EHCI_CMD_FLS(x)	(((x) >> 2) & 3) /* RW/RO frame list size */
  114: #define  EHCI_CMD_HCRESET	0x00000002 /* RW reset */
  115: #define  EHCI_CMD_RS		0x00000001 /* RW run/stop */
  116: 
  117: #define EHCI_USBSTS		0x04	/* RO, RW, RWC Status register */
  118: #define  EHCI_STS_ASS		0x00008000 /* RO async sched status */
  119: #define  EHCI_STS_PSS		0x00004000 /* RO periodic sched status */
  120: #define  EHCI_STS_REC		0x00002000 /* RO reclamation */
  121: #define  EHCI_STS_HCH		0x00001000 /* RO host controller halted */
  122: #define  EHCI_STS_IAA		0x00000020 /* RWC interrupt on async adv */
  123: #define  EHCI_STS_HSE		0x00000010 /* RWC host system error */
  124: #define  EHCI_STS_FLR		0x00000008 /* RWC frame list rollover */
  125: #define  EHCI_STS_PCD		0x00000004 /* RWC port change detect */
  126: #define  EHCI_STS_ERRINT	0x00000002 /* RWC error interrupt */
  127: #define  EHCI_STS_INT		0x00000001 /* RWC interrupt */
  128: #define  EHCI_STS_INTRS(x)	((x) & 0x3f)
  129: 
  130: #define EHCI_NORMAL_INTRS (EHCI_STS_IAA | EHCI_STS_HSE | EHCI_STS_PCD | EHCI_STS_ERRINT | EHCI_STS_INT)
  131: 
  132: #define EHCI_USBINTR		0x08	/* RW Interrupt register */
  133: #define EHCI_INTR_IAAE		0x00000020 /* interrupt on async advance ena */
  134: #define EHCI_INTR_HSEE		0x00000010 /* host system error ena */
  135: #define EHCI_INTR_FLRE		0x00000008 /* frame list rollover ena */
  136: #define EHCI_INTR_PCIE		0x00000004 /* port change ena */
  137: #define EHCI_INTR_UEIE		0x00000002 /* USB error intr ena */
  138: #define EHCI_INTR_UIE		0x00000001 /* USB intr ena */
  139: 
  140: #define EHCI_FRINDEX		0x0c	/* RW Frame Index register */
  141: 
  142: #define EHCI_CTRLDSSEGMENT	0x10	/* RW Control Data Structure Segment */
  143: 
  144: #define EHCI_PERIODICLISTBASE	0x14	/* RW Periodic List Base */
  145: #define EHCI_ASYNCLISTADDR	0x18	/* RW Async List Base */
  146: 
  147: #define EHCI_CONFIGFLAG		0x40	/* RW Configure Flag register */
  148: #define  EHCI_CONF_CF		0x00000001 /* RW configure flag */
  149: 
  150: #define EHCI_PORTSC(n)		(0x40+4*(n)) /* RO, RW, RWC Port Status reg */
  151: #define  EHCI_PS_WKOC_E		0x00400000 /* RW wake on over current ena */
  152: #define  EHCI_PS_WKDSCNNT_E	0x00200000 /* RW wake on disconnect ena */
  153: #define  EHCI_PS_WKCNNT_E	0x00100000 /* RW wake on connect ena */
  154: #define  EHCI_PS_PTC		0x000f0000 /* RW port test control */
  155: #define  EHCI_PS_PIC		0x0000c000 /* RW port indicator control */
  156: #define  EHCI_PS_PO		0x00002000 /* RW port owner */
  157: #define  EHCI_PS_PP		0x00001000 /* RW,RO port power */
  158: #define  EHCI_PS_LS		0x00000c00 /* RO line status */
  159: #define  EHCI_PS_IS_LOWSPEED(x)	(((x) & EHCI_PS_LS) == 0x00000400)
  160: #define  EHCI_PS_PR		0x00000100 /* RW port reset */
  161: #define  EHCI_PS_SUSP		0x00000080 /* RW suspend */
  162: #define  EHCI_PS_FPR		0x00000040 /* RW force port resume */
  163: #define  EHCI_PS_OCC		0x00000020 /* RWC over current change */
  164: #define  EHCI_PS_OCA		0x00000010 /* RO over current active */
  165: #define  EHCI_PS_PEC		0x00000008 /* RWC port enable change */
  166: #define  EHCI_PS_PE		0x00000004 /* RW port enable */
  167: #define  EHCI_PS_CSC		0x00000002 /* RWC connect status change */
  168: #define  EHCI_PS_CS		0x00000001 /* RO connect status */
  169: #define  EHCI_PS_CLEAR		(EHCI_PS_OCC|EHCI_PS_PEC|EHCI_PS_CSC)
  170: 
  171: #define EHCI_PORT_RESET_COMPLETE 2 /* ms */
  172: 
  173: #define EHCI_FLALIGN_ALIGN	0x1000
  174: 
  175: /* No data structure may cross a page boundary. */
  176: #define EHCI_PAGE_SIZE 0x1000
  177: #define EHCI_PAGE(x) ((x) &~ 0xfff)
  178: #define EHCI_PAGE_OFFSET(x) ((x) & 0xfff)
  179: #if defined(__FreeBSD__) || defined(__DragonFly__)
  180: #define EHCI_PAGE_MASK(x) ((x) & 0xfff)
  181: #endif
  182: 
  183: typedef u_int32_t ehci_link_t;
  184: #define EHCI_LINK_TERMINATE	0x00000001
  185: #define EHCI_LINK_TYPE(x)	((x) & 0x00000006)
  186: #define  EHCI_LINK_ITD		0x0
  187: #define  EHCI_LINK_QH		0x2
  188: #define  EHCI_LINK_SITD		0x4
  189: #define  EHCI_LINK_FSTN		0x6
  190: #define EHCI_LINK_ADDR(x)	((x) &~ 0x1f)
  191: 
  192: typedef u_int32_t ehci_physaddr_t;
  193: 
  194: /* Isochronous Transfer Descriptor */
  195: typedef struct {
  196: 	ehci_link_t	itd_next;
  197: 	/* XXX many more */
  198: } ehci_itd_t;
  199: #define EHCI_ITD_ALIGN 32
  200: 
  201: /* Split Transaction Isochronous Transfer Descriptor */
  202: typedef struct {
  203: 	ehci_link_t	sitd_next;
  204: 	/* XXX many more */
  205: } ehci_sitd_t;
  206: #define EHCI_SITD_ALIGN 32
  207: 
  208: /* Queue Element Transfer Descriptor */
  209: #define EHCI_QTD_NBUFFERS 5
  210: typedef struct {
  211: 	ehci_link_t	qtd_next;
  212: 	ehci_link_t	qtd_altnext;
  213: 	u_int32_t	qtd_status;
  214: #define EHCI_QTD_GET_STATUS(x)	(((x) >>  0) & 0xff)
  215: #define  EHCI_QTD_ACTIVE	0x80
  216: #define  EHCI_QTD_HALTED	0x40
  217: #define  EHCI_QTD_BUFERR	0x20
  218: #define  EHCI_QTD_BABBLE	0x10
  219: #define  EHCI_QTD_XACTERR	0x08
  220: #define  EHCI_QTD_MISSEDMICRO	0x04
  221: #define  EHCI_QTD_SPLITXSTATE	0x02
  222: #define  EHCI_QTD_PINGSTATE	0x01
  223: #define  EHCI_QTD_STATERRS	0x7c
  224: #define EHCI_QTD_GET_PID(x)	(((x) >>  8) & 0x3)
  225: #define EHCI_QTD_SET_PID(x)	((x) <<  8)
  226: #define  EHCI_QTD_PID_OUT	0x0
  227: #define  EHCI_QTD_PID_IN	0x1
  228: #define  EHCI_QTD_PID_SETUP	0x2
  229: #define EHCI_QTD_GET_CERR(x)	(((x) >> 10) &  0x3)
  230: #define EHCI_QTD_SET_CERR(x)	((x) << 10)
  231: #define EHCI_QTD_GET_C_PAGE(x)	(((x) >> 12) &  0x7)
  232: #define EHCI_QTD_SET_C_PAGE(x)	((x) << 12)
  233: #define EHCI_QTD_GET_IOC(x)	(((x) >> 15) &  0x1)
  234: #define EHCI_QTD_IOC		0x00008000
  235: #define EHCI_QTD_GET_BYTES(x)	(((x) >> 16) &  0x7fff)
  236: #define EHCI_QTD_SET_BYTES(x)	((x) << 16)
  237: #define EHCI_QTD_GET_TOGGLE(x)	(((x) >> 31) &  0x1)
  238: #define EHCI_QTD_TOGGLE		0x80000000
  239: 	ehci_physaddr_t	qtd_buffer[EHCI_QTD_NBUFFERS];
  240: } ehci_qtd_t;
  241: #define EHCI_QTD_ALIGN 32
  242: 
  243: /* Queue Head */
  244: typedef struct {
  245: 	ehci_link_t	qh_link;
  246: 	u_int32_t	qh_endp;
  247: #define EHCI_QH_GET_ADDR(x)	(((x) >>  0) & 0x7f) /* endpoint addr */
  248: #define EHCI_QH_SET_ADDR(x)	(x)
  249: #define EHCI_QH_ADDRMASK	0x0000007f
  250: #define EHCI_QH_GET_INACT(x)	(((x) >>  7) & 0x01) /* inactivate on next */
  251: #define EHCI_QH_INACT		0x00000080
  252: #define EHCI_QH_GET_ENDPT(x)	(((x) >>  8) & 0x0f) /* endpoint no */
  253: #define EHCI_QH_SET_ENDPT(x)	((x) <<  8)
  254: #define EHCI_QH_GET_EPS(x)	(((x) >> 12) & 0x03) /* endpoint speed */
  255: #define EHCI_QH_SET_EPS(x)	((x) << 12)
  256: #define  EHCI_QH_SPEED_FULL	0x0
  257: #define  EHCI_QH_SPEED_LOW	0x1
  258: #define  EHCI_QH_SPEED_HIGH	0x2
  259: #define EHCI_QH_GET_DTC(x)	(((x) >> 14) & 0x01) /* data toggle control */
  260: #define EHCI_QH_DTC		0x00004000
  261: #define EHCI_QH_GET_HRECL(x)	(((x) >> 15) & 0x01) /* head of reclamation */
  262: #define EHCI_QH_HRECL		0x00008000
  263: #define EHCI_QH_GET_MPL(x)	(((x) >> 16) & 0x7ff) /* max packet len */
  264: #define EHCI_QH_SET_MPL(x)	((x) << 16)
  265: #define EHCI_QG_MPLMASK		0x07ff0000
  266: #define EHCI_QH_GET_CTL(x)	(((x) >> 26) & 0x01) /* control endpoint */
  267: #define EHCI_QH_CTL		0x08000000
  268: #define EHCI_QH_GET_NRL(x)	(((x) >> 28) & 0x0f) /* NAK reload */
  269: #define EHCI_QH_SET_NRL(x)	((x) << 28)
  270: 	u_int32_t	qh_endphub;
  271: #define EHCI_QH_GET_SMASK(x)	(((x) >>  0) & 0xff) /* intr sched mask */
  272: #define EHCI_QH_SET_SMASK(x)	((x) <<  0)
  273: #define EHCI_QH_GET_CMASK(x)	(((x) >>  8) & 0xff) /* split completion mask */
  274: #define EHCI_QH_SET_CMASK(x)	((x) <<  8)
  275: #define EHCI_QH_GET_HUBA(x)	(((x) >> 16) & 0x7f) /* hub address */
  276: #define EHCI_QH_SET_HUBA(x)	((x) << 16)
  277: #define EHCI_QH_GET_PORT(x)	(((x) >> 23) & 0x7f) /* hub port */
  278: #define EHCI_QH_SET_PORT(x)	((x) << 23)
  279: #define EHCI_QH_GET_MULT(x)	(((x) >> 30) & 0x03) /* pipe multiplier */
  280: #define EHCI_QH_SET_MULT(x)	((x) << 30)
  281: 	ehci_link_t	qh_curqtd;
  282: 	ehci_qtd_t	qh_qtd;
  283: } ehci_qh_t;
  284: #define EHCI_QH_ALIGN 32
  285: 
  286: /* Periodic Frame Span Traversal Node */
  287: typedef struct {
  288: 	ehci_link_t	fstn_link;
  289: 	ehci_link_t	fstn_back;
  290: } ehci_fstn_t;
  291: #define EHCI_FSTN_ALIGN 32
  292: 
  293: #endif /* _DEV_PCI_EHCIREG_H_ */