--- src/sys/dev/acpica5/acpi_cpu.c 2006/12/22 23:26:14 1.17 +++ src/sys/dev/acpica5/acpi_cpu.c 2007/01/17 17:31:19 1.18 @@ -244,9 +244,9 @@ acpi_cpu_probe(device_t dev) acpi_PkgInt32(obj, 0, &cx_count); AcpiOsFree(obj); } else { - if (AcpiGbl_FADT->Plvl2Lat <= 100) + if (AcpiGbl_FADT.C2Latency <= 100) cx_count++; - if (AcpiGbl_FADT->Plvl3Lat <= 1000) + if (AcpiGbl_FADT.C3Latency <= 1000) cx_count++; if (cx_count > 0) cx_count++; @@ -319,7 +319,7 @@ acpi_cpu_attach(device_t dev) status = AcpiInstallNotifyHandler(sc->cpu_handle, ACPI_DEVICE_NOTIFY, acpi_cpu_notify, sc); if (device_get_unit(dev) == 0) - AcpiOsQueueForExecution(OSD_PRIORITY_LO, acpi_cpu_startup, NULL); + AcpiOsExecute(OSL_NOTIFY_HANDLER, acpi_cpu_startup, NULL); } else { sysctl_ctx_free(&acpi_cpu_sysctl_ctx); } @@ -396,11 +396,11 @@ acpi_cpu_throttle_probe(struct acpi_cpu_ /* Get throttling parameters from the FADT. 0 means not supported. */ if (device_get_unit(sc->cpu_dev) == 0) { - cpu_smi_cmd = AcpiGbl_FADT->SmiCmd; - cpu_pstate_cnt = AcpiGbl_FADT->PstateCnt; - cpu_cst_cnt = AcpiGbl_FADT->CstCnt; - cpu_duty_offset = AcpiGbl_FADT->DutyOffset; - cpu_duty_width = AcpiGbl_FADT->DutyWidth; + cpu_smi_cmd = AcpiGbl_FADT.SmiCommand; + cpu_pstate_cnt = AcpiGbl_FADT.PstateControl; + cpu_cst_cnt = AcpiGbl_FADT.CstControl; + cpu_duty_offset = AcpiGbl_FADT.DutyOffset; + cpu_duty_width = AcpiGbl_FADT.DutyWidth; } if (cpu_duty_width == 0 || (cpu_quirks & CPU_QUIRK_NO_THROTTLE) != 0) return (ENXIO); @@ -449,8 +449,8 @@ acpi_cpu_throttle_probe(struct acpi_cpu_ if (sc->cpu_p_blk_len < 4) return (ENXIO); gas.Address = sc->cpu_p_blk; - gas.AddressSpaceId = ACPI_ADR_SPACE_SYSTEM_IO; - gas.RegisterBitWidth = 32; + gas.SpaceId = ACPI_ADR_SPACE_SYSTEM_IO; + gas.BitWidth = 32; sc->cpu_p_cnt = acpi_bus_alloc_gas(sc->cpu_dev, &cpu_rid, &gas); if (sc->cpu_p_cnt != NULL) { ACPI_DEBUG_PRINT((ACPI_DB_INFO, "acpi_cpu%d: P_CNT from P_BLK\n", @@ -480,8 +480,9 @@ acpi_cpu_cx_probe(struct acpi_cpu_softc * instruction is present, flush the caches before entering C3 instead. * Otherwise, just disable C3 completely. */ - if (AcpiGbl_FADT->V1_Pm2CntBlk == 0 || AcpiGbl_FADT->Pm2CntLen == 0) { - if (AcpiGbl_FADT->WbInvd && AcpiGbl_FADT->WbInvdFlush == 0) { + if (AcpiGbl_FADT.Pm2ControlBlock == 0 || AcpiGbl_FADT.Pm2ControlLength == 0) { + if ((AcpiGbl_FADT.Flags & ACPI_FADT_WBINVD) != 0 && + (AcpiGbl_FADT.Flags & ACPI_FADT_WBINVD_FLUSH) == 0) { cpu_quirks |= CPU_QUIRK_NO_BM_CTRL; ACPI_DEBUG_PRINT((ACPI_DB_INFO, "acpi_cpu%d: no BM control, using flush cache method\n", @@ -521,15 +522,15 @@ acpi_cpu_cx_probe(struct acpi_cpu_softc goto done; /* Validate and allocate resources for C2 (P_LVL2). */ - gas.AddressSpaceId = ACPI_ADR_SPACE_SYSTEM_IO; - gas.RegisterBitWidth = 8; - if (AcpiGbl_FADT->Plvl2Lat <= 100) { + gas.SpaceId = ACPI_ADR_SPACE_SYSTEM_IO; + gas.BitWidth = 8; + if (AcpiGbl_FADT.C2Latency <= 100) { gas.Address = sc->cpu_p_blk + 4; cx_ptr->p_lvlx = acpi_bus_alloc_gas(sc->cpu_dev, &cpu_rid, &gas); if (cx_ptr->p_lvlx != NULL) { cpu_rid++; cx_ptr->type = ACPI_STATE_C2; - cx_ptr->trans_lat = AcpiGbl_FADT->Plvl2Lat; + cx_ptr->trans_lat = AcpiGbl_FADT.C2Latency; cpu_non_c3 = 1; cx_ptr++; sc->cpu_cx_count++; @@ -539,7 +540,7 @@ acpi_cpu_cx_probe(struct acpi_cpu_softc goto done; /* Validate and allocate resources for C3 (P_LVL3). */ - if (AcpiGbl_FADT->Plvl3Lat <= 1000 && + if (AcpiGbl_FADT.C3Latency <= 1000 && (cpu_quirks & CPU_QUIRK_NO_C3) == 0) { gas.Address = sc->cpu_p_blk + 5; @@ -547,7 +548,7 @@ acpi_cpu_cx_probe(struct acpi_cpu_softc if (cx_ptr->p_lvlx != NULL) { cpu_rid++; cx_ptr->type = ACPI_STATE_C3; - cx_ptr->trans_lat = AcpiGbl_FADT->Plvl3Lat; + cx_ptr->trans_lat = AcpiGbl_FADT.C3Latency; cx_ptr++; sc->cpu_cx_count++; } @@ -935,11 +936,9 @@ acpi_cpu_idle(void) * time if USB is loaded. */ if ((cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) { - AcpiGetRegister(ACPI_BITREG_BUS_MASTER_STATUS, &bm_active, - ACPI_MTX_DO_NOT_LOCK); + AcpiGetRegister(ACPI_BITREG_BUS_MASTER_STATUS, &bm_active); if (bm_active != 0) { - AcpiSetRegister(ACPI_BITREG_BUS_MASTER_STATUS, 1, - ACPI_MTX_DO_NOT_LOCK); + AcpiSetRegister(ACPI_BITREG_BUS_MASTER_STATUS, 1); cx_next_idx = min(cx_next_idx, cpu_non_c3); } } @@ -966,9 +965,8 @@ acpi_cpu_idle(void) */ if (cx_next->type == ACPI_STATE_C3) { if ((cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) { - AcpiSetRegister(ACPI_BITREG_ARB_DISABLE, 1, ACPI_MTX_DO_NOT_LOCK); - AcpiSetRegister(ACPI_BITREG_BUS_MASTER_RLD, 1, - ACPI_MTX_DO_NOT_LOCK); + AcpiSetRegister(ACPI_BITREG_ARB_DISABLE, 1); + AcpiSetRegister(ACPI_BITREG_BUS_MASTER_RLD, 1); } else ACPI_FLUSH_CPU_CACHE(); } @@ -979,7 +977,7 @@ acpi_cpu_idle(void) * get the time very close to the CPU start/stop clock logic, this * is the only reliable time source. */ - AcpiHwLowLevelRead(32, &start_time, &AcpiGbl_FADT->XPmTmrBlk); + AcpiHwLowLevelRead(32, &start_time, &AcpiGbl_FADT.XPmTimerBlock); CPU_GET_REG(cx_next->p_lvlx, 1); /* @@ -988,14 +986,14 @@ acpi_cpu_idle(void) * the processor has stopped. Doing it again provides enough * margin that we are certain to have a correct value. */ - AcpiHwLowLevelRead(32, &end_time, &AcpiGbl_FADT->XPmTmrBlk); - AcpiHwLowLevelRead(32, &end_time, &AcpiGbl_FADT->XPmTmrBlk); + AcpiHwLowLevelRead(32, &end_time, &AcpiGbl_FADT.XPmTimerBlock); + AcpiHwLowLevelRead(32, &end_time, &AcpiGbl_FADT.XPmTimerBlock); /* Enable bus master arbitration and disable bus master wakeup. */ if (cx_next->type == ACPI_STATE_C3 && (cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) { - AcpiSetRegister(ACPI_BITREG_ARB_DISABLE, 0, ACPI_MTX_DO_NOT_LOCK); - AcpiSetRegister(ACPI_BITREG_BUS_MASTER_RLD, 0, ACPI_MTX_DO_NOT_LOCK); + AcpiSetRegister(ACPI_BITREG_ARB_DISABLE, 0); + AcpiSetRegister(ACPI_BITREG_BUS_MASTER_RLD, 0); } /* Find the actual time asleep in microseconds, minus overhead. */