File:  [DragonFly] / src / sys / dev / disk / ata / ata-dma.c
Revision 1.11: download - view: text, annotated - select for diffs
Wed Feb 18 00:50:00 2004 UTC (10 years, 5 months ago) by dillon
Branches: MAIN
CVS tags: HEAD
ATAng stage 2: sync part of the ata_dma*() API.  No operational changes.

    1: /*-
    2:  * Copyright (c) 1998,1999,2000,2001,2002 Søren Schmidt <sos@FreeBSD.org>
    3:  * All rights reserved.
    4:  *
    5:  * Redistribution and use in source and binary forms, with or without
    6:  * modification, are permitted provided that the following conditions
    7:  * are met:
    8:  * 1. Redistributions of source code must retain the above copyright
    9:  *    notice, this list of conditions and the following disclaimer,
   10:  *    without modification, immediately at the beginning of the file.
   11:  * 2. Redistributions in binary form must reproduce the above copyright
   12:  *    notice, this list of conditions and the following disclaimer in the
   13:  *    documentation and/or other materials provided with the distribution.
   14:  * 3. The name of the author may not be used to endorse or promote products
   15:  *    derived from this software without specific prior written permission.
   16:  *
   17:  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   18:  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   19:  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   20:  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   21:  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
   22:  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   23:  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   24:  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   25:  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
   26:  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   27:  *
   28:  * $FreeBSD: src/sys/dev/ata/ata-dma.c,v 1.35.2.31 2003/05/07 16:46:11 jhb Exp $
   29:  * $DragonFly: src/sys/dev/disk/ata/ata-dma.c,v 1.11 2004/02/18 00:50:00 dillon Exp $
   30:  */
   31: 
   32: #include <sys/param.h>
   33: #include <sys/systm.h>
   34: #include <sys/ata.h>
   35: #include <sys/buf.h>
   36: #include <sys/malloc.h> 
   37: #include <sys/mpipe.h> 
   38: #include <sys/bus.h>
   39: #include <sys/disk.h>
   40: #include <sys/devicestat.h>
   41: #include <vm/vm.h>	     
   42: #include <vm/pmap.h>
   43: #include <bus/pci/pcivar.h>
   44: #include <machine/bus.h>
   45: #include <sys/rman.h>
   46: #include "ata-all.h"
   47: 
   48: /* prototypes */
   49: static void cyrix_timing(struct ata_channel *, int, int);
   50: static void promise_timing(struct ata_channel *, int, int);
   51: static void hpt_timing(struct ata_channel *, int, int);
   52: static int hpt_cable80(struct ata_channel *);
   53: 
   54: /* misc defines */
   55: #ifdef __alpha__
   56: #undef vtophys
   57: #define vtophys(va)	alpha_XXX_dmamap((vm_offset_t)va)
   58: #endif
   59: #define ATAPI_DEVICE(ch, device) \
   60: 	((device == ATA_MASTER && ch->devices & ATA_ATAPI_MASTER) || \
   61: 	 (device == ATA_SLAVE && ch->devices & ATA_ATAPI_SLAVE))
   62: 
   63: void *
   64: ata_dmaalloc(struct ata_channel *ch, int device, int flags)
   65: {
   66:     void *dmatab;
   67: 
   68:     KKASSERT(ch->dma_mpipe.max_count != 0);
   69:     dmatab = mpipe_alloc(&ch->dma_mpipe, flags);
   70:     KKASSERT(((uintptr_t)dmatab & PAGE_MASK) == 0);
   71:     return (dmatab);
   72: }
   73: 
   74: void
   75: ata_dmafree(struct ata_channel *ch, void *dmatab)
   76: {
   77:     if (dmatab)
   78: 	mpipe_free(&ch->dma_mpipe, dmatab);
   79: }
   80: 
   81: void
   82: ata_dmainit(struct ata_device *atadev, int apiomode, int wdmamode, int udmamode)
   83: {
   84:     struct ata_channel *ch = atadev->channel;
   85:     int device = atadev->unit;
   86:     device_t parent = device_get_parent(ch->dev);
   87:     int devno = (ch->unit << 1) + ATA_DEV(device);
   88:     int error;
   89: 
   90:     /* set our most pessimistic default mode */
   91:     atadev->mode = ATA_PIO;
   92: 
   93:     if (!ch->r_bmio)
   94: 	return;
   95: 
   96:     /* if simplex controller, only allow DMA on primary channel */
   97:     if (ch->unit == 1) {
   98: 	ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT,
   99: 		 ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) &
  100: 		 (ATA_BMSTAT_DMA_MASTER | ATA_BMSTAT_DMA_SLAVE));
  101: 	if (ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) & ATA_BMSTAT_DMA_SIMPLEX) {
  102: 	    ata_prtdev(atadev, "simplex device, DMA on primary only\n");
  103: 	    return;
  104: 	}
  105:     }
  106: 
  107:     /* DMA engine address alignment is usually 1 word (2 bytes) */
  108:     ch->alignment = 0x1;
  109: 
  110: #if 1
  111:     if (udmamode > 2 && !ch->device[ATA_DEV(device)].param->hwres_cblid) {
  112: 	ata_prtdev(atadev,"DMA limited to UDMA33, non-ATA66 cable or device\n");
  113: 	udmamode = 2;
  114:     }
  115: #endif
  116:     switch (ch->chiptype) {
  117: 
  118:     case 0x24db8086:	/* Intel ICH5 */
  119:     case 0x24ca8086:	/* Intel ICH4 mobile */
  120:     case 0x24cb8086:	/* Intel ICH4 */
  121:     case 0x248a8086:	/* Intel ICH3 mobile */ 
  122:     case 0x248b8086:	/* Intel ICH3 */
  123:     case 0x244a8086:	/* Intel ICH2 mobile */ 
  124:     case 0x244b8086:	/* Intel ICH2 */
  125: 	if (udmamode >= 5) {
  126: 	    int32_t mask48, new48;
  127: 	    int16_t word54;
  128: 
  129: 	    word54 = pci_read_config(parent, 0x54, 2);
  130: 	    if (word54 & (0x10 << devno)) {
  131: 		error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  132: 				    ATA_UDMA5,	ATA_C_F_SETXFER,ATA_WAIT_READY);
  133: 		if (bootverbose)
  134: 		    ata_prtdev(atadev, "%s setting UDMA5 on Intel chip\n",
  135: 			       (error) ? "failed" : "success");
  136: 		if (!error) {
  137: 		    mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
  138: 		    new48 = (1 << devno) + (1 << (16 + (devno << 2)));
  139: 		    pci_write_config(parent, 0x48,
  140: 				     (pci_read_config(parent, 0x48, 4) &
  141: 				     ~mask48) | new48, 4);
  142: 		    pci_write_config(parent, 0x54, word54 | (0x1000<<devno), 2);
  143: 		    atadev->mode = ATA_UDMA5;
  144: 		    return;
  145: 		}
  146: 	    }
  147: 	}
  148: 	/* make sure eventual ATA100 mode from the BIOS is disabled */
  149: 	pci_write_config(parent, 0x54, 
  150: 			 pci_read_config(parent, 0x54, 2) & ~(0x1000<<devno),2);
  151: 	/* FALLTHROUGH */
  152: 
  153:     case 0x24118086:	/* Intel ICH */
  154:     case 0x76018086:	/* Intel ICH */
  155: 	if (udmamode >= 4) {
  156: 	    int32_t mask48, new48;
  157: 	    int16_t word54;
  158: 
  159: 	    word54 = pci_read_config(parent, 0x54, 2);
  160: 	    if (word54 & (0x10 << devno)) {
  161: 		error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  162: 				    ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
  163: 		if (bootverbose)
  164: 		    ata_prtdev(atadev, "%s setting UDMA4 on Intel chip\n",
  165: 			       (error) ? "failed" : "success");
  166: 		if (!error) {
  167: 		    mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
  168: 		    new48 = (1 << devno) + (2 << (16 + (devno << 2)));
  169: 		    pci_write_config(parent, 0x48,
  170: 				     (pci_read_config(parent, 0x48, 4) &
  171: 				     ~mask48) | new48, 4);
  172: 		    pci_write_config(parent, 0x54, word54 | (1 << devno), 2);
  173: 		    atadev->mode = ATA_UDMA4;
  174: 		    return;
  175: 		}
  176: 	    }
  177: 	}	    
  178: 	/* make sure eventual ATA66 mode from the BIOS is disabled */
  179: 	pci_write_config(parent, 0x54, 
  180: 			 pci_read_config(parent, 0x54, 2) & ~(1 << devno), 2);
  181: 	/* FALLTHROUGH */
  182: 
  183:     case 0x71118086:	/* Intel PIIX4 */
  184:     case 0x84CA8086:	/* Intel PIIX4 */
  185:     case 0x71998086:	/* Intel PIIX4e */
  186:     case 0x24218086:	/* Intel ICH0 */
  187: 	if (udmamode >= 2) {
  188: 	    int32_t mask48, new48;
  189: 
  190: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  191: 				ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
  192: 	    if (bootverbose)
  193: 		ata_prtdev(atadev, "%s setting UDMA2 on Intel chip\n",
  194: 			   (error) ? "failed" : "success");
  195: 	    if (!error) {
  196: 		mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
  197: 		new48 = (1 << devno) + (2 << (16 + (devno << 2)));
  198: 		pci_write_config(parent, 0x48, 
  199: 				 (pci_read_config(parent, 0x48, 4) &
  200: 				 ~mask48) | new48, 4);
  201: 		atadev->mode = ATA_UDMA2;
  202: 		return;
  203: 	    }
  204: 	}
  205: 	/* make sure eventual ATA33 mode from the BIOS is disabled */
  206: 	pci_write_config(parent, 0x48, 
  207: 			 pci_read_config(parent, 0x48, 4) & ~(1 << devno), 4);
  208: 	/* FALLTHROUGH */
  209: 
  210:     case 0x70108086:	/* Intel PIIX3 */
  211: 	if (wdmamode >= 2 && apiomode >= 4) {
  212: 	    int32_t mask40, new40, mask44, new44;
  213: 
  214: 	    /* if SITRE not set doit for both channels */
  215: 	    if (!((pci_read_config(parent,0x40,4)>>(ch->unit<<8))&0x4000)) {
  216: 		new40 = pci_read_config(parent, 0x40, 4);
  217: 		new44 = pci_read_config(parent, 0x44, 4); 
  218: 		if (!(new40 & 0x00004000)) {
  219: 		    new44 &= ~0x0000000f;
  220: 		    new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8);
  221: 		}
  222: 		if (!(new40 & 0x40000000)) {
  223: 		    new44 &= ~0x000000f0;
  224: 		    new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20);
  225: 		}
  226: 		new40 |= 0x40004000;
  227: 		pci_write_config(parent, 0x40, new40, 4);
  228: 		pci_write_config(parent, 0x44, new44, 4);
  229: 	    }
  230: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  231: 				ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
  232: 	    if (bootverbose)
  233: 		ata_prtdev(atadev, "%s setting WDMA2 on Intel chip\n",
  234: 			   (error) ? "failed" : "success");
  235: 	    if (!error) {
  236: 		if (device == ATA_MASTER) {
  237: 		    mask40 = 0x0000330f;
  238: 		    new40 = 0x00002307;
  239: 		    mask44 = 0;
  240: 		    new44 = 0;
  241: 		}
  242: 		else {
  243: 		    mask40 = 0x000000f0;
  244: 		    new40 = 0x00000070;
  245: 		    mask44 = 0x0000000f;
  246: 		    new44 = 0x0000000b;
  247: 		}
  248: 		if (ch->unit) {
  249: 		    mask40 <<= 16;
  250: 		    new40 <<= 16;
  251: 		    mask44 <<= 4;
  252: 		    new44 <<= 4;
  253: 		}
  254: 		pci_write_config(parent, 0x40,
  255: 				 (pci_read_config(parent, 0x40, 4) & ~mask40)|
  256: 				 new40, 4);
  257: 		pci_write_config(parent, 0x44,
  258: 				 (pci_read_config(parent, 0x44, 4) & ~mask44)|
  259: 				 new44, 4);
  260: 		atadev->mode = ATA_WDMA2;
  261: 		return;
  262: 	    }
  263: 	}
  264: 	/* we could set PIO mode timings, but we assume the BIOS did that */
  265: 	break;
  266: 
  267:     case 0x12308086:	/* Intel PIIX */
  268: 	if (wdmamode >= 2 && apiomode >= 4) {
  269: 	    int32_t word40;
  270: 
  271: 	    word40 = pci_read_config(parent, 0x40, 4);
  272: 	    word40 >>= ch->unit * 16;
  273: 
  274: 	    /* Check for timing config usable for DMA on controller */
  275: 	    if (!((word40 & 0x3300) == 0x2300 &&
  276: 		  ((word40 >> (device == ATA_MASTER ? 0 : 4)) & 1) == 1))
  277: 		break;
  278: 
  279: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  280: 				ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
  281: 	    if (bootverbose)
  282: 		ata_prtdev(atadev, "%s setting WDMA2 on Intel chip\n",
  283: 			   (error) ? "failed" : "success");
  284: 	    if (!error) {
  285: 		atadev->mode = ATA_WDMA2;
  286: 		return;
  287: 	    }
  288: 	}
  289: 	break;
  290: 
  291:     case 0x522910b9:	/* AcerLabs Aladdin IV/V */
  292: 	/* the older Aladdin doesn't support ATAPI DMA on both master & slave */
  293: 	if (pci_get_revid(parent) < 0xc2 &&
  294: 	    ch->devices & ATA_ATAPI_MASTER && ch->devices & ATA_ATAPI_SLAVE) {
  295: 	    ata_prtdev(atadev, "two atapi devices on this channel, no DMA\n");
  296: 	    break;
  297: 	}
  298: 	if (udmamode >= 5 && pci_get_revid(parent) >= 0xc4) {
  299: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  300: 				ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
  301: 	    if (bootverbose)
  302: 		ata_prtdev(atadev, "%s setting UDMA5 on Acer chip\n",
  303: 			   (error) ? "failed" : "success");
  304: 	    if (!error) {
  305: 		int32_t word54 = pci_read_config(parent, 0x54, 4);
  306: 	
  307: 		pci_write_config(parent, 0x4b,
  308: 				 pci_read_config(parent, 0x4b, 1) | 0x01, 1);
  309: 		word54 &= ~(0x000f000f << (devno << 2));
  310: 		word54 |= (0x000f0005 << (devno << 2));
  311: 		pci_write_config(parent, 0x54, word54, 4);
  312: 		pci_write_config(parent, 0x53, 
  313: 				 pci_read_config(parent, 0x53, 1) | 0x03, 1);
  314: 		atadev->mode = ATA_UDMA5;
  315: 		return;
  316: 	    }
  317: 	}
  318: 	if (udmamode >= 4 && pci_get_revid(parent) >= 0xc2) {
  319: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  320: 				ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
  321: 	    if (bootverbose)
  322: 		ata_prtdev(atadev, "%s setting UDMA4 on Acer chip\n",
  323: 			   (error) ? "failed" : "success");
  324: 	    if (!error) {
  325: 		int32_t word54 = pci_read_config(parent, 0x54, 4);
  326: 	
  327: 		pci_write_config(parent, 0x4b,
  328: 				 pci_read_config(parent, 0x4b, 1) | 0x01, 1);
  329: 		word54 &= ~(0x000f000f << (devno << 2));
  330: 		word54 |= (0x00080005 << (devno << 2));
  331: 		pci_write_config(parent, 0x54, word54, 4);
  332: 		pci_write_config(parent, 0x53, 
  333: 				 pci_read_config(parent, 0x53, 1) | 0x03, 1);
  334: 		atadev->mode = ATA_UDMA4;
  335: 		return;
  336: 	    }
  337: 	}
  338: 	if (udmamode >= 2 && pci_get_revid(parent) >= 0x20) {
  339: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  340: 				ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
  341: 	    if (bootverbose)
  342: 		ata_prtdev(atadev, "%s setting UDMA2 on Acer chip\n",
  343: 			   (error) ? "failed" : "success");
  344: 	    if (!error) {
  345: 		int32_t word54 = pci_read_config(parent, 0x54, 4);
  346: 	
  347: 		word54 &= ~(0x000f000f << (devno << 2));
  348: 		word54 |= (0x000a0005 << (devno << 2));
  349: 		pci_write_config(parent, 0x54, word54, 4);
  350: 		pci_write_config(parent, 0x53, 
  351: 				 pci_read_config(parent, 0x53, 1) | 0x03, 1);
  352: 		ch->flags |= ATA_ATAPI_DMA_RO;
  353: 		atadev->mode = ATA_UDMA2;
  354: 		return;
  355: 	    }
  356: 	}
  357: 
  358: 	/* make sure eventual UDMA mode from the BIOS is disabled */
  359: 	pci_write_config(parent, 0x56, pci_read_config(parent, 0x56, 2) &
  360: 				       ~(0x0008 << (devno << 2)), 2);
  361: 
  362: 	if (wdmamode >= 2 && apiomode >= 4) {
  363: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  364: 				ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
  365: 	    if (bootverbose)
  366: 		ata_prtdev(atadev, "%s setting WDMA2 on Acer chip\n",
  367: 			   (error) ? "failed" : "success");
  368: 	    if (!error) {
  369: 		pci_write_config(parent, 0x53, 
  370: 				 pci_read_config(parent, 0x53, 1) | 0x03, 1);
  371: 		ch->flags |= ATA_ATAPI_DMA_RO;
  372: 		atadev->mode = ATA_WDMA2;
  373: 		return;
  374: 	    }
  375: 	}
  376: 	pci_write_config(parent, 0x53,
  377: 			 (pci_read_config(parent, 0x53, 1) & ~0x01) | 0x02, 1);
  378: 	/* we could set PIO mode timings, but we assume the BIOS did that */
  379: 	break;
  380: 
  381:     case 0x01bc10de:	/* NVIDIA nForce */
  382:     case 0x006510de:	/* NVIDIA nForce2 */
  383:     case 0x74411022:	/* AMD 768 */
  384:     case 0x74111022:	/* AMD 766 */
  385:     case 0x74091022:	/* AMD 756 */
  386:     case 0x74691022:	/* AMD 8111 */
  387:     case 0x05711106:	/* VIA 82C571, 82C586, 82C596, 82C686, 8231,8233,8235 */
  388: 	{
  389: 	    int via_modes[5][7] = {
  390: 		{ 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00 },	/* ATA33 */
  391: 		{ 0x00, 0x00, 0xea, 0x00, 0xe8, 0x00, 0x00 },	/* ATA66 */
  392: 		{ 0x00, 0x00, 0xf4, 0x00, 0xf1, 0xf0, 0x00 },	/* ATA100 */
  393: 		{ 0x00, 0x00, 0xf6, 0x00, 0xf2, 0xf1, 0xf0 },   /* VIA ATA133 */
  394: 		{ 0x00, 0x00, 0xc0, 0x00, 0xc5, 0xc6, 0xc7 }};  /* AMD/NVIDIA */
  395: 	    int *reg_val = NULL;
  396: 	    char *chip = "VIA";
  397: 
  398: 	    if (ata_find_dev(parent, 0x31471106, 0) ||		/* 8233a */
  399: 		ata_find_dev(parent, 0x31771106, 0)) {		/* 8235 */
  400: 		udmamode = imin(udmamode, 6);
  401: 		reg_val = via_modes[3];
  402: 	    }
  403: 	    else if (ata_find_dev(parent, 0x06861106, 0x40) ||	/* 82C686b */
  404: 		ata_find_dev(parent, 0x82311106, 0) ||		/* 8231 */
  405: 		ata_find_dev(parent, 0x30741106, 0) ||		/* 8233 */
  406: 		ata_find_dev(parent, 0x31091106, 0)) {		/* 8233c */
  407: 		udmamode = imin(udmamode, 5);
  408: 		reg_val = via_modes[2];
  409: 	    }
  410: 	    else if (ata_find_dev(parent, 0x06861106, 0x10) ||	/* 82C686a */
  411: 		     ata_find_dev(parent, 0x05961106, 0x12)) {	/* 82C596b */
  412: 		udmamode = imin(udmamode, 4);
  413: 		reg_val = via_modes[1];
  414: 	    }
  415: 	    else if (ata_find_dev(parent, 0x06861106, 0)) {	/* 82C686 */
  416: 		udmamode = imin(udmamode, 2);
  417: 		reg_val = via_modes[1];
  418: 	    }
  419: 	    else if (ata_find_dev(parent, 0x05961106, 0) ||	/* 82C596a */
  420: 		     ata_find_dev(parent, 0x05861106, 0x03)) {	/* 82C586b */
  421: 		udmamode = imin(udmamode, 2);
  422: 		reg_val = via_modes[0];
  423: 	    }
  424: 	    else if (ch->chiptype == 0x74411022 ||		/* AMD 768 */
  425: 		     ch->chiptype == 0x74111022) {		/* AMD 766 */
  426: 		udmamode = imin(udmamode, 5);
  427: 		reg_val = via_modes[4];
  428: 		chip = "AMD";
  429: 	    }
  430: 	    else if (ch->chiptype == 0x74691022) {		/* AMD 8111 */
  431: 		udmamode = imin(udmamode, 6);
  432: 		reg_val = via_modes[4];
  433: 		chip = "AMD";
  434: 	    }
  435: 	    else if (ch->chiptype == 0x74091022) {		/* AMD 756 */
  436: 		udmamode = imin(udmamode, 4);
  437: 		reg_val = via_modes[4];
  438: 		chip = "AMD";
  439: 	    }
  440: 	    else if (ch->chiptype == 0x01bc10de) {		/* nForce */
  441: 		udmamode = imin(udmamode, 5);
  442: 		reg_val = via_modes[4];
  443: 		chip = "NVIDIA";
  444: 	    }
  445: 	    else if (ch->chiptype == 0x006510de) {		/* nForce2 */
  446: 		udmamode = imin(udmamode, 6);
  447: 		reg_val = via_modes[4];
  448: 		chip = "NVIDIA";
  449: 	    }
  450: 	    else 
  451: 		udmamode = 0;
  452: 
  453: 	    if (udmamode >= 6) {
  454: 		error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  455: 				    ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY);
  456: 		if (bootverbose)
  457: 		    ata_prtdev(atadev, "%s setting UDMA6 on %s chip\n",
  458: 			       (error) ? "failed" : "success", chip);
  459: 		if (!error) {
  460: 		    pci_write_config(parent, 0x53 - devno, reg_val[6], 1);
  461: 		    atadev->mode = ATA_UDMA6;
  462: 		    return;
  463: 		}
  464: 	    }
  465: 	    if (udmamode >= 5) {
  466: 		error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  467: 				    ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
  468: 		if (bootverbose)
  469: 		    ata_prtdev(atadev, "%s setting UDMA5 on %s chip\n",
  470: 			       (error) ? "failed" : "success", chip);
  471: 		if (!error) {
  472: 		    pci_write_config(parent, 0x53 - devno, reg_val[5], 1);
  473: 		    atadev->mode = ATA_UDMA5;
  474: 		    return;
  475: 		}
  476: 	    }
  477: 	    if (udmamode >= 4) {
  478: 		error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  479: 				    ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
  480: 		if (bootverbose)
  481: 		    ata_prtdev(atadev, "%s setting UDMA4 on %s chip\n",
  482: 			       (error) ? "failed" : "success", chip);
  483: 		if (!error) {
  484: 		    pci_write_config(parent, 0x53 - devno, reg_val[4], 1);
  485: 		    atadev->mode = ATA_UDMA4;
  486: 		    return;
  487: 		}
  488: 	    }
  489: 	    if (udmamode >= 2) {
  490: 		error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  491: 				    ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
  492: 		if (bootverbose)
  493: 		    ata_prtdev(atadev, "%s setting UDMA2 on %s chip\n",
  494: 			       (error) ? "failed" : "success", chip);
  495: 		if (!error) {
  496: 		    pci_write_config(parent, 0x53 - devno, reg_val[2], 1);
  497: 		    atadev->mode = ATA_UDMA2;
  498: 		    return;
  499: 		}
  500: 	    }
  501: 	    if (wdmamode >= 2 && apiomode >= 4) {
  502: 		error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  503: 				    ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
  504: 		if (bootverbose)
  505: 		    ata_prtdev(atadev, "%s setting WDMA2 on %s chip\n",
  506: 			       (error) ? "failed" : "success", chip);
  507: 		if (!error) {
  508: 		    pci_write_config(parent, 0x53 - devno, 0x0b, 1);
  509: 		    pci_write_config(parent, 0x4b - devno, 0x31, 1);
  510: 		    atadev->mode = ATA_WDMA2;
  511: 		    return;
  512: 		}
  513: 	    }
  514: 	}
  515: 	/* we could set PIO mode timings, but we assume the BIOS did that */
  516: 	break;
  517: 
  518:     case 0x55131039:	/* SiS 5591 */
  519: 	if (ata_find_dev(parent, 0x06301039, 0x30) ||	/* SiS 630 */
  520: 	    ata_find_dev(parent, 0x06331039, 0) ||	/* SiS 633 */
  521: 	    ata_find_dev(parent, 0x06351039, 0) ||	/* SiS 635 */
  522: 	    ata_find_dev(parent, 0x06401039, 0) ||	/* SiS 640 */
  523: 	    ata_find_dev(parent, 0x06451039, 0) ||	/* SiS 645 */
  524: 	    ata_find_dev(parent, 0x06461039, 0) ||	/* SiS 645DX */
  525: 	    ata_find_dev(parent, 0x06481039, 0) ||      /* SiS 648 */
  526: 	    ata_find_dev(parent, 0x06501039, 0) ||	/* SiS 650 */
  527: 	    ata_find_dev(parent, 0x07301039, 0) ||	/* SiS 730 */
  528: 	    ata_find_dev(parent, 0x07331039, 0) ||	/* SiS 733 */
  529: 	    ata_find_dev(parent, 0x07351039, 0) ||	/* SiS 735 */
  530: 	    ata_find_dev(parent, 0x07401039, 0) ||	/* SiS 740 */
  531: 	    ata_find_dev(parent, 0x07451039, 0) ||	/* SiS 745 */
  532: 	    ata_find_dev(parent, 0x07461039, 0) ||	/* SiS 746 */
  533: 	    ata_find_dev(parent, 0x07501039, 0)) {	/* SiS 750 */
  534: 	    int8_t reg = 0x40 + (devno << 1);
  535: 	    int16_t val = pci_read_config(parent, reg, 2) & 0x0fff;
  536: 
  537: 	    if (udmamode >= 5) {
  538: 		error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  539: 				    ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
  540: 		if (bootverbose)
  541: 		    ata_prtdev(atadev, "%s setting UDMA5 on SiS chip\n",
  542: 			       (error) ? "failed" : "success");
  543: 		if (!error) {
  544: 		    pci_write_config(parent, reg, val | 0x8000, 2);
  545: 		    atadev->mode = ATA_UDMA5;
  546: 		    return;
  547: 		}
  548: 	    }
  549: 	    if (udmamode >= 4) {
  550: 		error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  551: 				    ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
  552: 		if (bootverbose)
  553: 		    ata_prtdev(atadev, "%s setting UDMA4 on SiS chip\n",
  554: 			       (error) ? "failed" : "success");
  555: 		if (!error) {
  556: 		    pci_write_config(parent, reg, val | 0x9000, 2);
  557: 		    atadev->mode = ATA_UDMA4;
  558: 		    return;
  559: 		}
  560: 	    }
  561: 	    if (udmamode >= 2) {
  562: 		error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  563: 				    ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
  564: 		if (bootverbose)
  565: 		    ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n",
  566: 			       (error) ? "failed" : "success");
  567: 		if (!error) {
  568: 		    pci_write_config(parent, reg, val | 0xb000, 2);
  569: 		    atadev->mode = ATA_UDMA2;
  570: 		    return;
  571: 		}
  572: 	    }
  573: 	} else if (ata_find_dev(parent, 0x05301039, 0) || /* SiS 530 */
  574: 		   ata_find_dev(parent, 0x05401039, 0) || /* SiS 540 */
  575: 		   ata_find_dev(parent, 0x06201039, 0) || /* SiS 620 */
  576: 		   ata_find_dev(parent, 0x06301039, 0)) { /* SiS 630 */
  577: 	    int8_t reg = 0x40 + (devno << 1);
  578: 	    int16_t val = pci_read_config(parent, reg, 2) & 0x0fff;
  579: 
  580: 	    if (udmamode >= 4) {
  581: 		error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  582: 				    ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
  583: 		if (bootverbose)
  584: 		    ata_prtdev(atadev, "%s setting UDMA4 on SiS chip\n",
  585: 			       (error) ? "failed" : "success");
  586: 		if (!error) {
  587: 		    pci_write_config(parent, reg, val | 0x9000, 2);
  588: 		    atadev->mode = ATA_UDMA4;
  589: 		    return;
  590: 		}
  591: 	    }
  592: 	    if (udmamode >= 2) {
  593: 		error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  594: 				    ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
  595: 		if (bootverbose)
  596: 		    ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n",
  597: 			       (error) ? "failed" : "success");
  598: 		if (!error) {
  599: 		    pci_write_config(parent, reg, val | 0xa000, 2);
  600: 		    atadev->mode = ATA_UDMA2;
  601: 		    return;
  602: 		}
  603: 	    }
  604: 	} else if (udmamode >= 2 && pci_get_revid(parent) > 0xc1) {
  605: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  606: 				ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
  607: 	    if (bootverbose)
  608: 		ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n",
  609: 			   (error) ? "failed" : "success");
  610: 	    if (!error) {
  611: 		pci_write_config(parent, 0x40 + (devno << 1), 0xa301, 2);
  612: 		atadev->mode = ATA_UDMA2;
  613: 		return;
  614: 	    }
  615: 	}
  616: 	if (wdmamode >=2 && apiomode >= 4) {
  617: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  618: 				ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
  619: 	    if (bootverbose)
  620: 		ata_prtdev(atadev, "%s setting WDMA2 on SiS chip\n",
  621: 			   (error) ? "failed" : "success");
  622: 	    if (!error) {
  623: 		pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2);
  624: 		atadev->mode = ATA_WDMA2;
  625: 		return;
  626: 	    }
  627: 	}
  628: 	/* we could set PIO mode timings, but we assume the BIOS did that */
  629: 	break;
  630: 
  631:     case 0x06801095:	/* SiI 0680 ATA133 controller */
  632: 	{
  633: 	    u_int8_t ureg = 0xac + (ATA_DEV(device) * 0x02) + (ch->unit * 0x10);
  634: 	    u_int8_t uval = pci_read_config(parent, ureg, 1);
  635: 	    u_int8_t mreg = ch->unit ? 0x84 : 0x80;
  636: 	    u_int8_t mask = ATA_DEV(device) ? 0x30 : 0x03;
  637: 	    u_int8_t mode = pci_read_config(parent, mreg, 1);
  638: 
  639: 	    /* enable UDMA mode */
  640: 	    pci_write_config(parent, mreg,
  641: 			     (mode & ~mask) | (device ? 0x30 : 0x03), 1);
  642:     	    if (udmamode >= 6) {
  643: 		error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  644: 				    ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY);
  645: 		if (bootverbose)
  646: 		    ata_prtdev(atadev, "%s setting UDMA6 on SiI chip\n",
  647: 			       (error) ? "failed" : "success");
  648: 		if (!error) {
  649: 		    pci_write_config(parent, ureg, (uval & 0x3f) | 0x01, 1);
  650: 		    atadev->mode = ATA_UDMA6;
  651: 		    return;
  652: 		}
  653: 	    }
  654:     	    if (udmamode >= 5) {
  655: 		error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  656: 				    ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
  657: 		if (bootverbose)
  658: 		    ata_prtdev(atadev, "%s setting UDMA5 on SiI chip\n",
  659: 			       (error) ? "failed" : "success");
  660: 		if (!error) {
  661: 		    pci_write_config(parent, ureg, (uval & 0x3f) | 0x02, 1);
  662: 		    atadev->mode = ATA_UDMA5;
  663: 		    return;
  664: 		}
  665: 	    }
  666:     	    if (udmamode >= 4) {
  667: 		error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  668: 				    ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
  669: 		if (bootverbose)
  670: 		    ata_prtdev(atadev, "%s setting UDMA4 on SiI chip\n",
  671: 			       (error) ? "failed" : "success");
  672: 		if (!error) {
  673: 		    pci_write_config(parent, ureg, (uval & 0x3f) | 0x03, 1);
  674: 		    atadev->mode = ATA_UDMA4;
  675: 		    return;
  676: 		}
  677: 	    }
  678:     	    if (udmamode >= 2) {
  679: 		error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  680: 				    ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
  681: 		if (bootverbose)
  682: 		    ata_prtdev(atadev, "%s setting UDMA2 on SiI chip\n",
  683: 			       (error) ? "failed" : "success");
  684: 		if (!error) {
  685: 		    pci_write_config(parent, ureg, (uval & 0x3f) | 0x07, 1);
  686: 		    atadev->mode = ATA_UDMA2;
  687: 		    return;
  688: 		}
  689: 	    }
  690: 
  691: 	    /* disable UDMA mode and enable WDMA mode */
  692: 	    pci_write_config(parent, mreg,
  693: 			     (mode & ~mask) | (device ? 0x20 : 0x02), 1);
  694: 	    if (wdmamode >= 2 && apiomode >= 4) {
  695: 		error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  696: 				    ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
  697: 		if (bootverbose)
  698: 		    ata_prtdev(atadev, "%s setting WDMA2 on SiI chip\n",
  699: 			       (error) ? "failed" : "success");
  700: 		if (!error) {
  701: 		    pci_write_config(parent, ureg - 0x4, 0x10c1, 2);
  702: 		    atadev->mode = ATA_WDMA2;
  703: 		    return;
  704: 		}
  705: 	    }
  706: 
  707: 	    /* restore PIO mode */
  708: 	    pci_write_config(parent, mreg, mode, 1);
  709: 	}
  710: 	/* we could set PIO mode timings, but we assume the BIOS did that */
  711: 	break;
  712: 
  713: 
  714:     case 0x06491095:	/* CMD 649 ATA100 controller */
  715: 	if (udmamode >= 5) {
  716: 	    u_int8_t umode;
  717: 
  718: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  719: 				ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
  720: 	    if (bootverbose)
  721: 		ata_prtdev(atadev, "%s setting UDMA5 on CMD chip\n",
  722: 			   (error) ? "failed" : "success");
  723: 	    if (!error) {
  724: 		umode = pci_read_config(parent, ch->unit ? 0x7b : 0x73, 1);
  725: 		umode &= ~(device == ATA_MASTER ? 0x35 : 0xca);
  726: 		umode |= (device == ATA_MASTER ? 0x05 : 0x0a);
  727: 		pci_write_config(parent, ch->unit ? 0x7b : 0x73, umode, 1);
  728: 		atadev->mode = ATA_UDMA5;
  729: 		return;
  730: 	    }
  731: 	}
  732: 	/* FALLTHROUGH */
  733: 
  734:     case 0x06481095:	/* CMD 648 ATA66 controller */
  735: 	if (udmamode >= 4) {
  736: 	    u_int8_t umode;
  737: 
  738: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  739: 				ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
  740: 	    if (bootverbose)
  741: 		ata_prtdev(atadev, "%s setting UDMA4 on CMD chip\n",
  742: 			   (error) ? "failed" : "success");
  743: 	    if (!error) {
  744: 		umode = pci_read_config(parent, ch->unit ? 0x7b : 0x73, 1);
  745: 		umode &= ~(device == ATA_MASTER ? 0x35 : 0xca);
  746: 		umode |= (device == ATA_MASTER ? 0x15 : 0x4a);
  747: 		pci_write_config(parent, ch->unit ? 0x7b : 0x73, umode, 1);
  748: 		atadev->mode = ATA_UDMA4;
  749: 		return;
  750: 	    }
  751: 	}
  752: 	if (udmamode >= 2) {
  753: 	    u_int8_t umode;
  754: 
  755: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  756: 				ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
  757: 	    if (bootverbose)
  758: 		ata_prtdev(atadev, "%s setting UDMA2 on CMD chip\n",
  759: 			   (error) ? "failed" : "success");
  760: 	    if (!error) {
  761: 		umode = pci_read_config(parent, ch->unit ? 0x7b : 0x73, 1);
  762: 		umode &= ~(device == ATA_MASTER ? 0x35 : 0xca);
  763: 		umode |= (device == ATA_MASTER ? 0x11 : 0x42);
  764: 		pci_write_config(parent, ch->unit ? 0x7b : 0x73, umode, 1);
  765: 		atadev->mode = ATA_UDMA2;
  766: 		return;
  767: 	    }
  768: 	}
  769: 	/* make sure eventual UDMA mode from the BIOS is disabled */
  770: 	pci_write_config(parent, ch->unit ? 0x7b : 0x73, 
  771: 			 pci_read_config(parent, ch->unit ? 0x7b : 0x73, 1)&
  772: 			 ~(device == ATA_MASTER ? 0x35 : 0xca), 1);
  773: 	/* FALLTHROUGH */
  774: 
  775:     case 0x06461095:	/* CMD 646 ATA controller */
  776: 	if (wdmamode >= 2 && apiomode >= 4) {
  777: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  778: 				ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
  779: 	    if (bootverbose)
  780: 		ata_prtdev(atadev, "%s setting WDMA2 on CMD chip\n",
  781: 			   error ? "failed" : "success");
  782: 	    if (!error) {
  783: 		int32_t offset = (devno < 3) ? (devno << 1) : 7;
  784: 
  785: 		pci_write_config(parent, 0x54 + offset, 0x3f, 1);
  786: 		atadev->mode = ATA_WDMA2;
  787: 		return;
  788: 	    }
  789: 	}
  790: 	/* we could set PIO mode timings, but we assume the BIOS did that */
  791: 	break;
  792: 
  793:     case 0xc6931080:	/* Cypress 82c693 ATA controller */
  794: 	if (wdmamode >= 2 && apiomode >= 4) {
  795: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  796: 				ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
  797: 	    if (bootverbose)
  798: 		ata_prtdev(atadev, "%s setting WDMA2 on Cypress chip\n",
  799: 			   error ? "failed" : "success");
  800: 	    if (!error) {
  801: 		pci_write_config(ch->dev, ch->unit ? 0x4e:0x4c, 0x2020, 2);
  802: 		atadev->mode = ATA_WDMA2;
  803: 		return;
  804: 	    }
  805: 	}
  806: 	/* we could set PIO mode timings, but we assume the BIOS did that */
  807: 	break;
  808: 
  809:     case 0x01021078:	/* Cyrix 5530 ATA33 controller */
  810: 	ch->alignment = 0xf;	/* DMA engine requires 16 byte alignment */
  811: 	if (udmamode >= 2) {
  812: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  813: 				ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
  814: 	    if (bootverbose)
  815: 		ata_prtdev(atadev, "%s setting UDMA2 on Cyrix chip\n",
  816: 			   (error) ? "failed" : "success");
  817: 	    if (!error) {
  818: 		cyrix_timing(ch, devno, ATA_UDMA2);
  819: 		atadev->mode = ATA_UDMA2;
  820: 		return;
  821: 	    }
  822: 	}
  823: 	if (wdmamode >= 2 && apiomode >= 4) {
  824: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  825: 				ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
  826: 	    if (bootverbose)
  827: 		ata_prtdev(atadev, "%s setting WDMA2 on Cyrix chip\n",
  828: 			   (error) ? "failed" : "success");
  829: 	    if (!error) {
  830: 		cyrix_timing(ch, devno, ATA_WDMA2);
  831: 		atadev->mode = ATA_WDMA2;
  832: 		return;
  833: 	    }
  834: 	}
  835: 	error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  836: 			    ATA_PIO0 + apiomode, ATA_C_F_SETXFER,
  837: 			    ATA_WAIT_READY);
  838: 	if (bootverbose)
  839: 	    ata_prtdev(atadev, "%s setting %s on Cyrix chip\n",
  840: 		       (error) ? "failed" : "success",
  841: 		       ata_mode2str(ATA_PIO0 + apiomode));
  842: 	cyrix_timing(ch, devno, ATA_PIO0 + apiomode);
  843: 	atadev->mode = ATA_PIO0 + apiomode;
  844: 	return;
  845: 
  846:     case 0x02121166:	/* ServerWorks CSB5 ATA66/100 controller */
  847: 	if (udmamode >= 5 && pci_get_revid(parent) >= 0x92) {
  848: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  849: 				ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
  850: 	    if (bootverbose)
  851: 		ata_prtdev(atadev, "%s setting UDMA5 on ServerWorks chip\n",
  852: 			   (error) ? "failed" : "success");
  853: 	    if (!error) {
  854: 		u_int16_t reg56;
  855: 
  856: 		pci_write_config(parent, 0x54, 
  857: 				 pci_read_config(parent, 0x54, 1) |
  858: 				 (0x01 << devno), 1);
  859: 		reg56 = pci_read_config(parent, 0x56, 2);
  860: 		reg56 &= ~(0xf << (devno * 4));
  861: 		reg56 |= (0x5 << (devno * 4));
  862: 		pci_write_config(parent, 0x56, reg56, 2);
  863: 		atadev->mode = ATA_UDMA5;
  864: 		return;
  865: 	    }
  866: 	}
  867: 	if (udmamode >= 4) {
  868: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  869: 				ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
  870: 	    if (bootverbose)
  871: 		ata_prtdev(atadev, "%s setting UDMA4 on ServerWorks chip\n",
  872: 			   (error) ? "failed" : "success");
  873: 	    if (!error) {
  874: 		u_int16_t reg56;
  875: 
  876: 		pci_write_config(parent, 0x54, 
  877: 				 pci_read_config(parent, 0x54, 1) |
  878: 				 (0x01 << devno), 1);
  879: 		reg56 = pci_read_config(parent, 0x56, 2);
  880: 		reg56 &= ~(0xf << (devno * 4));
  881: 		reg56 |= (0x4 << (devno * 4));
  882: 		pci_write_config(parent, 0x56, reg56, 2);
  883: 		atadev->mode = ATA_UDMA4;
  884: 		return;
  885: 	    }
  886: 	}
  887: 	/* FALLTHROUGH */
  888: 
  889:     case 0x02111166:	/* ServerWorks ROSB4 ATA33 controller */
  890: 	if (udmamode >= 2) {
  891: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  892: 				ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
  893: 	    if (bootverbose)
  894: 		ata_prtdev(atadev, "%s setting UDMA2 on ServerWorks chip\n",
  895: 			   (error) ? "failed" : "success");
  896: 	    if (!error) {
  897: 		u_int16_t reg56;
  898: 
  899: 		pci_write_config(parent, 0x54, 
  900: 				 pci_read_config(parent, 0x54, 1) |
  901: 				 (0x01 << devno), 1);
  902: 		reg56 = pci_read_config(parent, 0x56, 2);
  903: 		reg56 &= ~(0xf << (devno * 4));
  904: 		reg56 |= (0x2 << (devno * 4));
  905: 		pci_write_config(parent, 0x56, reg56, 2);
  906: 		atadev->mode = ATA_UDMA2;
  907: 		return;
  908: 	    }
  909: 	}
  910: 	if (wdmamode >= 2 && apiomode >= 4) {
  911: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  912: 				ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
  913: 	    if (bootverbose)
  914: 		ata_prtdev(atadev, "%s setting WDMA2 on ServerWorks chip\n",
  915: 			   (error) ? "failed" : "success");
  916: 	    if (!error) {
  917: 		int offset = (ch->unit * 2) + (device == ATA_MASTER);
  918: 		int word44 = pci_read_config(parent, 0x44, 4);
  919: 
  920: 		pci_write_config(parent, 0x54,
  921: 				 pci_read_config(parent, 0x54, 1) &
  922: 				 ~(0x01 << devno), 1);
  923: 		word44 &= ~(0xff << (offset << 8));
  924: 		word44 |= (0x20 << (offset << 8));
  925: 		pci_write_config(parent, 0x44, 0x20, 4);
  926: 		atadev->mode = ATA_WDMA2;
  927: 		return;
  928: 	    }
  929: 	}
  930: 	/* we could set PIO mode timings, but we assume the BIOS did that */
  931: 	break;
  932: 
  933:     case 0x4d69105a:	/* Promise TX2 ATA133 controllers */
  934:     case 0x5275105a:	/* Promise TX2 ATA133 controllers */
  935:     case 0x6269105a:	/* Promise TX2 ATA133 controllers */
  936:     case 0x7275105a:	/* Promise TX2 ATA133 controllers */
  937: 	ATA_OUTB(ch->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
  938: 	if (udmamode >= 6 && !(ATA_INB(ch->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) {
  939: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  940: 				ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY);
  941: 	    if (bootverbose)
  942: 		ata_prtdev(atadev, "%s setting UDMA6 on Promise chip\n",
  943: 			   (error) ? "failed" : "success");
  944: 	    if (!error) {
  945: 		atadev->mode = ATA_UDMA6;
  946: 		return;
  947: 	    }
  948: 	}
  949: 	/* FALLTHROUGH */
  950: 
  951:     case 0x4d68105a:	/* Promise TX2 ATA100 controllers */
  952:     case 0x6268105a:	/* Promise TX2 ATA100 controllers */
  953: 	ATA_OUTB(ch->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
  954: 	if (udmamode >= 5 && !(ATA_INB(ch->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) {
  955: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  956: 				ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
  957: 	    if (bootverbose)
  958: 		ata_prtdev(atadev, "%s setting UDMA5 on Promise chip\n",
  959: 			   (error) ? "failed" : "success");
  960: 	    if (!error) {
  961: 		atadev->mode = ATA_UDMA5;
  962: 		return;
  963: 	    }
  964: 	}
  965: 	ATA_OUTB(ch->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
  966: 	if (udmamode >= 4 && !(ATA_INB(ch->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) {
  967: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  968: 				ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
  969: 	    if (bootverbose)
  970: 		ata_prtdev(atadev, "%s setting UDMA4 on Promise chip\n",
  971: 			   (error) ? "failed" : "success");
  972: 	    if (!error) {
  973: 		atadev->mode = ATA_UDMA4;
  974: 		return;
  975: 	    }
  976: 	}
  977: 	if (udmamode >= 2) {
  978: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  979: 				ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
  980: 	    if (bootverbose)
  981: 		ata_prtdev(atadev, "%s setting UDMA on Promise chip\n",
  982: 			   (error) ? "failed" : "success");
  983: 	    if (!error) {
  984: 		atadev->mode = ATA_UDMA2;
  985: 		return;
  986: 	    }
  987: 	}
  988: 	if (wdmamode >= 2 && apiomode >= 4) {
  989: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  990: 				ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
  991: 	    if (bootverbose)
  992: 		ata_prtdev(atadev, "%s setting WDMA2 on Promise chip\n",
  993: 			   (error) ? "failed" : "success");
  994: 	    if (!error) {
  995: 		atadev->mode = ATA_WDMA2;
  996: 		return;
  997: 	    }
  998: 	}
  999: 	break;
 1000: 
 1001:     case 0x0d30105a:	/* Promise OEM ATA100 controllers */
 1002:     case 0x4d30105a:	/* Promise Ultra/FastTrak 100 controllers */
 1003: 	if (!ATAPI_DEVICE(ch, device) && udmamode >= 5 && 
 1004: 	    !(pci_read_config(parent, 0x50, 2)&(ch->unit ? 1<<11 : 1<<10))){
 1005: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
 1006: 				ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
 1007: 	    if (bootverbose)
 1008: 		ata_prtdev(atadev, "%s setting UDMA5 on Promise chip\n",
 1009: 			   (error) ? "failed" : "success");
 1010: 	    if (!error) {
 1011: 		promise_timing(ch, devno, ATA_UDMA5);
 1012: 		atadev->mode = ATA_UDMA5;
 1013: 		return;
 1014: 	    }
 1015: 	}
 1016: 	/* FALLTHROUGH */
 1017: 
 1018:     case 0x0d38105a:	/* Promise FastTrak 66 controllers */
 1019:     case 0x4d38105a:	/* Promise Ultra/FastTrak 66 controllers */
 1020: 	if (!ATAPI_DEVICE(ch, device) && udmamode >= 4 && 
 1021: 	    !(pci_read_config(parent, 0x50, 2)&(ch->unit ? 1<<11 : 1<<10))){
 1022: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
 1023: 				ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
 1024: 	    if (bootverbose)
 1025: 		ata_prtdev(atadev, "%s setting UDMA4 on Promise chip\n",
 1026: 			   (error) ? "failed" : "success");
 1027: 	    if (!error) {
 1028: 		promise_timing(ch, devno, ATA_UDMA4);
 1029: 		atadev->mode = ATA_UDMA4;
 1030: 		return;
 1031: 	    }
 1032: 	}
 1033: 	/* FALLTHROUGH */
 1034: 
 1035:     case 0x4d33105a:	/* Promise Ultra/FastTrak 33 controllers */
 1036: 	if (!ATAPI_DEVICE(ch, device) && udmamode >= 2) {
 1037: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
 1038: 				ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
 1039: 	    if (bootverbose)
 1040: 		ata_prtdev(atadev, "%s setting UDMA2 on Promise chip\n",
 1041: 			   (error) ? "failed" : "success");
 1042: 	    if (!error) {
 1043: 		promise_timing(ch, devno, ATA_UDMA2);
 1044: 		atadev->mode = ATA_UDMA2;
 1045: 		return;
 1046: 	    }
 1047: 	}
 1048: 	if (!ATAPI_DEVICE(ch, device) && wdmamode >= 2 && apiomode >= 4) {
 1049: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
 1050: 				ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
 1051: 	    if (bootverbose)
 1052: 		ata_prtdev(atadev, "%s setting WDMA2 on Promise chip\n",
 1053: 			   (error) ? "failed" : "success");
 1054: 	    if (!error) {
 1055: 		promise_timing(ch, devno, ATA_WDMA2);
 1056: 		atadev->mode = ATA_WDMA2;
 1057: 		return;
 1058: 	    }
 1059: 	}
 1060: 	error = ata_command(atadev, ATA_C_SETFEATURES, 0,
 1061: 			    ATA_PIO0 + apiomode, 
 1062: 			    ATA_C_F_SETXFER, ATA_WAIT_READY);
 1063: 	if (bootverbose)
 1064: 	    ata_prtdev(atadev, "%s setting PIO%d on Promise chip\n",
 1065: 		       (error) ? "failed" : "success",
 1066: 		       (apiomode >= 0) ? apiomode : 0);
 1067: 	promise_timing(ch, devno, ATA_PIO0 + apiomode);
 1068: 	atadev->mode = ATA_PIO0 + apiomode;
 1069: 	return;
 1070:     
 1071:     case 0x00041103:	/* HighPoint HPT366/368/370/372 controllers */
 1072:     case 0x00051103:	/* HighPoint HPT372 controllers */
 1073:     case 0x00081103:	/* HighPoint HPT374 controllers */
 1074: 	if (!ATAPI_DEVICE(ch, device) && udmamode >= 6 && hpt_cable80(ch) &&
 1075: 	    ((ch->chiptype == 0x00041103 && pci_get_revid(parent) >= 0x05) ||
 1076: 	     (ch->chiptype == 0x00051103 && pci_get_revid(parent) >= 0x01) ||
 1077: 	     (ch->chiptype == 0x00081103 && pci_get_revid(parent) >= 0x07))) {
 1078: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
 1079: 				ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY);
 1080: 	    if (bootverbose)
 1081: 		ata_prtdev(atadev, "%s setting UDMA6 on HighPoint chip\n",
 1082: 			   (error) ? "failed" : "success");
 1083: 	    if (!error) {
 1084: 		hpt_timing(ch, devno, ATA_UDMA6);
 1085: 		atadev->mode = ATA_UDMA6;
 1086: 		return;
 1087: 	    }
 1088: 	}
 1089: 	if (!ATAPI_DEVICE(ch, device) && udmamode >= 5 && hpt_cable80(ch) &&
 1090: 	    ((ch->chiptype == 0x00041103 && pci_get_revid(parent) >= 0x03) ||
 1091: 	     (ch->chiptype == 0x00051103 && pci_get_revid(parent) >= 0x01) ||
 1092: 	     (ch->chiptype == 0x00081103 && pci_get_revid(parent) >= 0x07))) {
 1093: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
 1094: 				ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
 1095: 	    if (bootverbose)
 1096: 		ata_prtdev(atadev, "%s setting UDMA5 on HighPoint chip\n",
 1097: 			   (error) ? "failed" : "success");
 1098: 	    if (!error) {
 1099: 		hpt_timing(ch, devno, ATA_UDMA5);
 1100: 		atadev->mode = ATA_UDMA5;
 1101: 		return;
 1102: 	    }
 1103: 	}
 1104: 	if (!ATAPI_DEVICE(ch, device) && udmamode >= 4 && hpt_cable80(ch)) {
 1105: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
 1106: 				ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
 1107: 	    if (bootverbose)
 1108: 		ata_prtdev(atadev, "%s setting UDMA4 on HighPoint chip\n",
 1109: 			   (error) ? "failed" : "success");
 1110: 	    if (!error) {
 1111: 		hpt_timing(ch, devno, ATA_UDMA4);
 1112: 		atadev->mode = ATA_UDMA4;
 1113: 		return;
 1114: 	    }
 1115: 	}
 1116: 	if (!ATAPI_DEVICE(ch, device) && udmamode >= 2) {
 1117: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
 1118: 				ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
 1119: 	    if (bootverbose)
 1120: 		ata_prtdev(atadev, "%s setting UDMA2 on HighPoint chip\n",
 1121: 			   (error) ? "failed" : "success");
 1122: 	    if (!error) {
 1123: 		hpt_timing(ch, devno, ATA_UDMA2);
 1124: 		atadev->mode = ATA_UDMA2;
 1125: 		return;
 1126: 	    }
 1127: 	}
 1128: 	if (!ATAPI_DEVICE(ch, device) && wdmamode >= 2 && apiomode >= 4) {
 1129: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
 1130: 				ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
 1131: 	    if (bootverbose)
 1132: 		ata_prtdev(atadev, "%s setting WDMA2 on HighPoint chip\n",
 1133: 			   (error) ? "failed" : "success");
 1134: 	    if (!error) {
 1135: 		hpt_timing(ch, devno, ATA_WDMA2);
 1136: 		atadev->mode = ATA_WDMA2;
 1137: 		return;
 1138: 	    }
 1139: 	}
 1140: 	error = ata_command(atadev, ATA_C_SETFEATURES, 0,
 1141: 			    ATA_PIO0 + apiomode, 
 1142: 			    ATA_C_F_SETXFER, ATA_WAIT_READY);
 1143: 	if (bootverbose)
 1144: 	    ata_prtdev(atadev, "%s setting PIO%d on HighPoint chip\n",
 1145: 		       (error) ? "failed" : "success",
 1146: 		       (apiomode >= 0) ? apiomode : 0);
 1147: 	hpt_timing(ch, devno, ATA_PIO0 + apiomode);
 1148: 	atadev->mode = ATA_PIO0 + apiomode;
 1149: 	return;
 1150: 
 1151:     case 0x000116ca:	/* Cenatek Rocket Drive controller */
 1152: 	if (wdmamode >= 0 &&
 1153: 	    (ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) & 
 1154: 	     ((device==ATA_MASTER)?ATA_BMSTAT_DMA_MASTER:ATA_BMSTAT_DMA_SLAVE)))
 1155: 	    atadev->mode = ATA_DMA;
 1156: 	else
 1157: 	    atadev->mode = ATA_PIO;
 1158: 	return;
 1159: 
 1160:     default:		/* unknown controller chip */
 1161: 	/* better not try generic DMA on ATAPI devices it almost never works */
 1162: 	if ((device == ATA_MASTER && ch->devices & ATA_ATAPI_MASTER) ||
 1163: 	    (device == ATA_SLAVE && ch->devices & ATA_ATAPI_SLAVE))
 1164: 	    break;
 1165: 
 1166: 	/* if controller says its setup for DMA take the easy way out */
 1167: 	/* the downside is we dont know what DMA mode we are in */
 1168: 	if ((udmamode >= 0 || wdmamode >= 2) &&
 1169: 	    (ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) &
 1170: 	     ((device==ATA_MASTER) ? 
 1171: 	      ATA_BMSTAT_DMA_MASTER : ATA_BMSTAT_DMA_SLAVE))) {
 1172: 	    atadev->mode = ATA_DMA;
 1173: 	    return;
 1174: 	}
 1175: 
 1176: 	/* well, we have no support for this, but try anyways */
 1177: 	if ((wdmamode >= 2 && apiomode >= 4) && ch->r_bmio) {
 1178: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
 1179: 				ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
 1180: 	    if (bootverbose)
 1181: 		ata_prtdev(atadev, "%s setting WDMA2 on generic chip\n",
 1182: 			   (error) ? "failed" : "success");
 1183: 	    if (!error) {
 1184: 		atadev->mode = ATA_WDMA2;
 1185: 		return;
 1186: 	    }
 1187: 	}
 1188:     }
 1189:     error = ata_command(atadev, ATA_C_SETFEATURES, 0, ATA_PIO0 + apiomode,
 1190: 			ATA_C_F_SETXFER, ATA_WAIT_READY);
 1191:     if (bootverbose)
 1192: 	ata_prtdev(atadev, "%s setting PIO%d on generic chip\n",
 1193: 		   (error) ? "failed" : "success", apiomode < 0 ? 0 : apiomode);
 1194:     if (!error)
 1195: 	atadev->mode = ATA_PIO0 + apiomode;
 1196:     else {
 1197: 	if (bootverbose)
 1198: 	    ata_prtdev(atadev, "using PIO mode set by BIOS\n");
 1199: 	atadev->mode = ATA_PIO;
 1200:     }
 1201: }
 1202: 
 1203: int
 1204: ata_dmasetup(struct ata_channel *ch, int device, struct ata_dmaentry *dmatab,
 1205: 	     caddr_t data, int32_t count)
 1206: {
 1207:     u_int32_t dma_count, dma_base;
 1208:     int i = 0;
 1209: 
 1210:     if (((uintptr_t)data & ch->alignment) || (count & ch->alignment)) {
 1211: 	ata_printf(ch, device, "non aligned DMA transfer attempted\n");
 1212: 	return -1;
 1213:     }
 1214: 
 1215:     if (!count) {
 1216: 	ata_printf(ch, device, "zero length DMA transfer attempted\n");
 1217: 	return -1;
 1218:     }
 1219:     
 1220:     dma_base = vtophys(data);
 1221:     dma_count = imin(count, (PAGE_SIZE - ((uintptr_t)data & PAGE_MASK)));
 1222:     data += dma_count;
 1223:     count -= dma_count;
 1224: 
 1225:     while (count) {
 1226: 	dmatab[i].base = dma_base;
 1227: 	dmatab[i].count = (dma_count & 0xffff);
 1228: 	i++; 
 1229: 	if (i >= ATA_DMA_ENTRIES) {
 1230: 	    ata_printf(ch, device, "too many segments in DMA table\n");
 1231: 	    return -1;
 1232: 	}
 1233: 	dma_base = vtophys(data);
 1234: 	dma_count = imin(count, PAGE_SIZE);
 1235: 	data += imin(count, PAGE_SIZE);
 1236: 	count -= imin(count, PAGE_SIZE);
 1237:     }
 1238:     dmatab[i].base = dma_base;
 1239:     dmatab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT;
 1240:     return 0;
 1241: }
 1242: 
 1243: void
 1244: ata_dmastart(struct ata_channel *ch, int device, 
 1245: 	     struct ata_dmaentry *dmatab, int dir)
 1246: {
 1247:     ch->flags |= ATA_DMA_ACTIVE;
 1248:     ATA_OUTL(ch->r_bmio, ATA_BMDTP_PORT, vtophys(dmatab));
 1249:     ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT, dir ? ATA_BMCMD_WRITE_READ : 0);
 1250:     ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, 
 1251: 	 (ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) | 
 1252: 	  (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR)));
 1253:     ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT, 
 1254: 	 ATA_INB(ch->r_bmio, ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP);
 1255: }
 1256: 
 1257: int
 1258: ata_dmadone(struct ata_device *atadev)
 1259: {
 1260:     struct ata_channel *ch;
 1261:     int error;
 1262: 
 1263:     ch = atadev->channel;
 1264: 
 1265:     ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT, 
 1266: 		ATA_INB(ch->r_bmio, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
 1267:     ch->flags &= ~ATA_DMA_ACTIVE;
 1268:     error = ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT);
 1269:     ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, 
 1270: 	     error | ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR);
 1271:     return error & ATA_BMSTAT_MASK;
 1272: }
 1273: 
 1274: int
 1275: ata_dmastatus(struct ata_channel *ch)
 1276: {
 1277:     return ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
 1278: }
 1279: 
 1280: static void
 1281: cyrix_timing(struct ata_channel *ch, int devno, int mode)
 1282: {
 1283:     u_int32_t reg20 = 0x0000e132;
 1284:     u_int32_t reg24 = 0x00017771;
 1285: 
 1286:     switch (mode) {
 1287:     case ATA_PIO0:	reg20 = 0x0000e132; break;
 1288:     case ATA_PIO1:	reg20 = 0x00018121; break;
 1289:     case ATA_PIO2:	reg20 = 0x00024020; break;
 1290:     case ATA_PIO3:	reg20 = 0x00032010; break;
 1291:     case ATA_PIO4:	reg20 = 0x00040010; break;
 1292:     case ATA_WDMA2:	reg24 = 0x00002020; break;
 1293:     case ATA_UDMA2:	reg24 = 0x00911030; break;
 1294:     }
 1295:     ATA_OUTL(ch->r_bmio, (devno << 3) + 0x20, reg20);
 1296:     ATA_OUTL(ch->r_bmio, (devno << 3) + 0x24, reg24);
 1297: }
 1298: 
 1299: static void
 1300: promise_timing(struct ata_channel *ch, int devno, int mode)
 1301: {
 1302:     u_int32_t timing = 0;
 1303:     struct promise_timing {
 1304: 	u_int8_t  pa:4;
 1305: 	u_int8_t  prefetch:1;
 1306: 	u_int8_t  iordy:1;
 1307: 	u_int8_t  errdy:1;
 1308: 	u_int8_t  syncin:1;
 1309: 	u_int8_t  pb:5;
 1310: 	u_int8_t  mb:3;
 1311: 	u_int8_t  mc:4;
 1312: 	u_int8_t  dmaw:1;
 1313: 	u_int8_t  dmar:1;
 1314: 	u_int8_t  iordyp:1;
 1315: 	u_int8_t  dmarqp:1;
 1316: 	u_int8_t  reserved:8;
 1317:     } *t = (struct promise_timing*)&timing;
 1318: 
 1319:     t->iordy = 1; t->iordyp = 1;
 1320:     if (mode >= ATA_DMA) {
 1321: 	t->prefetch = 1; t->errdy = 1; t->syncin = 1;
 1322:     }
 1323: 
 1324:     switch (ch->chiptype) {
 1325:     case 0x4d33105a:  /* Promise Ultra/Fasttrak 33 */
 1326: 	switch (mode) {
 1327: 	default:
 1328: 	case ATA_PIO0:	t->pa =	 9; t->pb = 19; t->mb = 7; t->mc = 15; break;
 1329: 	case ATA_PIO1:	t->pa =	 5; t->pb = 12; t->mb = 7; t->mc = 15; break;
 1330: 	case ATA_PIO2:	t->pa =	 3; t->pb =  8; t->mb = 7; t->mc = 15; break;
 1331: 	case ATA_PIO3:	t->pa =	 2; t->pb =  6; t->mb = 7; t->mc = 15; break;
 1332: 	case ATA_PIO4:	t->pa =	 1; t->pb =  4; t->mb = 7; t->mc = 15; break;
 1333: 	case ATA_WDMA2: t->pa =	 3; t->pb =  7; t->mb = 3; t->mc =  3; break;
 1334: 	case ATA_UDMA2: t->pa =	 3; t->pb =  7; t->mb = 1; t->mc =  1; break;
 1335: 	}
 1336: 	break;
 1337: 
 1338:     case 0x4d38105a:  /* Promise Ultra/Fasttrak 66 */
 1339:     case 0x4d30105a:  /* Promise Ultra/Fasttrak 100 */
 1340:     case 0x0d30105a:  /* Promise OEM ATA 100 */
 1341: 	switch (mode) {
 1342: 	default:
 1343: 	case ATA_PIO0:	t->pa = 15; t->pb = 31; t->mb = 7; t->mc = 15; break;
 1344: 	case ATA_PIO1:	t->pa = 10; t->pb = 24; t->mb = 7; t->mc = 15; break;
 1345: 	case ATA_PIO2:	t->pa =	 6; t->pb = 16; t->mb = 7; t->mc = 15; break;
 1346: 	case ATA_PIO3:	t->pa =	 4; t->pb = 12; t->mb = 7; t->mc = 15; break;
 1347: 	case ATA_PIO4:	t->pa =	 2; t->pb =  8; t->mb = 7; t->mc = 15; break;
 1348: 	case ATA_WDMA2: t->pa =	 6; t->pb = 14; t->mb = 6; t->mc =  6; break;
 1349: 	case ATA_UDMA2: t->pa =	 6; t->pb = 14; t->mb = 2; t->mc =  2; break;
 1350: 	case ATA_UDMA4: t->pa =	 3; t->pb =  7; t->mb = 1; t->mc =  1; break;
 1351: 	case ATA_UDMA5: t->pa =	 3; t->pb =  7; t->mb = 1; t->mc =  1; break;
 1352: 	}
 1353: 	break;
 1354:     }
 1355:     pci_write_config(device_get_parent(ch->dev), 0x60 + (devno<<2), timing, 4);
 1356: }
 1357: 
 1358: static void
 1359: hpt_timing(struct ata_channel *ch, int devno, int mode)
 1360: {
 1361:     device_t parent = device_get_parent(ch->dev);
 1362:     u_int32_t timing;
 1363: 
 1364:     if (ch->chiptype == 0x00081103 && pci_get_revid(parent) >= 0x07) {
 1365: 	switch (mode) {						/* HPT374 */
 1366: 	case ATA_PIO0:	timing = 0x0ac1f48a; break;
 1367: 	case ATA_PIO1:	timing = 0x0ac1f465; break;
 1368: 	case ATA_PIO2:	timing = 0x0a81f454; break;
 1369: 	case ATA_PIO3:	timing = 0x0a81f443; break;
 1370: 	case ATA_PIO4:	timing = 0x0a81f442; break;
 1371: 	case ATA_WDMA2: timing = 0x22808242; break;
 1372: 	case ATA_UDMA2: timing = 0x120c8242; break;
 1373: 	case ATA_UDMA4: timing = 0x12ac8242; break;
 1374: 	case ATA_UDMA5: timing = 0x12848242; break;
 1375: 	case ATA_UDMA6: timing = 0x12808242; break;
 1376: 	default:	timing = 0x0d029d5e;
 1377: 	}
 1378:     }
 1379:     else if ((ch->chiptype == 0x00041103 && pci_get_revid(parent) >= 0x05) ||
 1380: 	     (ch->chiptype == 0x00051103 && pci_get_revid(parent) >= 0x01)) {
 1381: 	switch (mode) {						/* HPT372 */
 1382: 	case ATA_PIO0:	timing = 0x0d029d5e; break;
 1383: 	case ATA_PIO1:	timing = 0x0d029d26; break;
 1384: 	case ATA_PIO2:	timing = 0x0c829ca6; break;
 1385: 	case ATA_PIO3:	timing = 0x0c829c84; break;
 1386: 	case ATA_PIO4:	timing = 0x0c829c62; break;
 1387: 	case ATA_WDMA2: timing = 0x2c829262; break;
 1388: 	case ATA_UDMA2: timing = 0x1c91dc62; break;
 1389: 	case ATA_UDMA4: timing = 0x1c8ddc62; break;
 1390: 	case ATA_UDMA5: timing = 0x1c6ddc62; break;
 1391: 	case ATA_UDMA6: timing = 0x1c81dc62; break;
 1392: 	default:	timing = 0x0d029d5e;
 1393: 	}
 1394:     }
 1395:     else if (ch->chiptype == 0x00041103 && pci_get_revid(parent) >= 0x03) {
 1396: 	switch (mode) {						/* HPT370 */
 1397: 	case ATA_PIO0:	timing = 0x06914e57; break;
 1398: 	case ATA_PIO1:	timing = 0x06914e43; break;
 1399: 	case ATA_PIO2:	timing = 0x06514e33; break;
 1400: 	case ATA_PIO3:	timing = 0x06514e22; break;
 1401: 	case ATA_PIO4:	timing = 0x06514e21; break;
 1402: 	case ATA_WDMA2: timing = 0x26514e21; break;
 1403: 	case ATA_UDMA2: timing = 0x16494e31; break;
 1404: 	case ATA_UDMA4: timing = 0x16454e31; break;
 1405: 	case ATA_UDMA5: timing = 0x16454e31; break;
 1406: 	default:	timing = 0x06514e57;
 1407: 	}
 1408: 	pci_write_config(parent, 0x40 + (devno << 2) , timing, 4);
 1409:     }
 1410:     else {							/* HPT36[68] */
 1411: 	switch (pci_read_config(parent, 0x41 + (devno << 2), 1)) {
 1412: 	case 0x85:	/* 25Mhz */
 1413: 	    switch (mode) {
 1414: 	    case ATA_PIO0:	timing = 0x40d08585; break;
 1415: 	    case ATA_PIO1:	timing = 0x40d08572; break;
 1416: 	    case ATA_PIO2:	timing = 0x40ca8542; break;
 1417: 	    case ATA_PIO3:	timing = 0x40ca8532; break;
 1418: 	    case ATA_PIO4:	timing = 0x40ca8521; break;
 1419: 	    case ATA_WDMA2:	timing = 0x20ca8521; break;
 1420: 	    case ATA_UDMA2:	timing = 0x10cf8521; break;
 1421: 	    case ATA_UDMA4:	timing = 0x10c98521; break;
 1422: 	    default:		timing = 0x01208585;
 1423: 	    }
 1424: 	    break;
 1425: 	default:
 1426: 	case 0xa7:	/* 33MHz */
 1427: 	    switch (mode) {
 1428: 	    case ATA_PIO0:	timing = 0x40d0a7aa; break;
 1429: 	    case ATA_PIO1:	timing = 0x40d0a7a3; break;
 1430: 	    case ATA_PIO2:	timing = 0x40d0a753; break;
 1431: 	    case ATA_PIO3:	timing = 0x40c8a742; break;
 1432: 	    case ATA_PIO4:	timing = 0x40c8a731; break;
 1433: 	    case ATA_WDMA2:	timing = 0x20c8a731; break;
 1434: 	    case ATA_UDMA2:	timing = 0x10caa731; break;
 1435: 	    case ATA_UDMA4:	timing = 0x10c9a731; break;
 1436: 	    default:		timing = 0x0120a7a7;
 1437: 	    }
 1438: 	    break;
 1439: 	case 0xd9:	/* 40Mhz */
 1440: 	    switch (mode) {
 1441: 	    case ATA_PIO0:	timing = 0x4018d9d9; break;
 1442: 	    case ATA_PIO1:	timing = 0x4010d9c7; break;
 1443: 	    case ATA_PIO2:	timing = 0x4010d997; break;
 1444: 	    case ATA_PIO3:	timing = 0x4010d974; break;
 1445: 	    case ATA_PIO4:	timing = 0x4008d963; break;
 1446: 	    case ATA_WDMA2:	timing = 0x2008d943; break;
 1447: 	    case ATA_UDMA2:	timing = 0x100bd943; break;
 1448: 	    case ATA_UDMA4:	timing = 0x100fd943; break;
 1449: 	    default:		timing = 0x0120d9d9;
 1450: 	    }
 1451: 	}
 1452:     }
 1453:     pci_write_config(parent, 0x40 + (devno << 2) , timing, 4);
 1454: }
 1455: 
 1456: static int
 1457: hpt_cable80(struct ata_channel *ch)
 1458: {
 1459:     device_t parent = device_get_parent(ch->dev);
 1460:     u_int8_t reg, val, res;
 1461: 
 1462:     if (ch->chiptype == 0x00081103 && pci_get_function(parent) == 1) {
 1463: 	reg = ch->unit ? 0x57 : 0x53;
 1464: 	val = pci_read_config(parent, reg, 1);
 1465: 	pci_write_config(parent, reg, val | 0x80, 1);
 1466:     }
 1467:     else {
 1468: 	reg = 0x5b;
 1469: 	val = pci_read_config(parent, reg, 1);
 1470: 	pci_write_config(parent, reg, val & 0xfe, 1);
 1471:     }
 1472:     res = pci_read_config(parent, 0x5a, 1) & (ch->unit ? 0x01 : 0x02);
 1473:     pci_write_config(parent, reg, val, 1);
 1474:     return !res;
 1475: }