File:  [DragonFly] / src / sys / dev / disk / ata / ata-dma.c
Revision 1.20: download - view: text, annotated - select for diffs
Tue Mar 9 21:39:59 2004 UTC (10 years, 5 months ago) by joerg
Branches: MAIN
CVS tags: HEAD
Remove a debug printf added with the last commit.

    1: /*-
    2:  * Copyright (c) 1998,1999,2000,2001,2002 Søren Schmidt <sos@FreeBSD.org>
    3:  * All rights reserved.
    4:  *
    5:  * Redistribution and use in source and binary forms, with or without
    6:  * modification, are permitted provided that the following conditions
    7:  * are met:
    8:  * 1. Redistributions of source code must retain the above copyright
    9:  *    notice, this list of conditions and the following disclaimer,
   10:  *    without modification, immediately at the beginning of the file.
   11:  * 2. Redistributions in binary form must reproduce the above copyright
   12:  *    notice, this list of conditions and the following disclaimer in the
   13:  *    documentation and/or other materials provided with the distribution.
   14:  * 3. The name of the author may not be used to endorse or promote products
   15:  *    derived from this software without specific prior written permission.
   16:  *
   17:  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   18:  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   19:  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   20:  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   21:  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
   22:  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   23:  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   24:  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   25:  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
   26:  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   27:  *
   28:  * $FreeBSD: src/sys/dev/ata/ata-dma.c,v 1.35.2.31 2003/05/07 16:46:11 jhb Exp $
   29:  * $DragonFly: src/sys/dev/disk/ata/ata-dma.c,v 1.20 2004/03/09 21:39:59 joerg Exp $
   30:  */
   31: 
   32: #include <sys/param.h>
   33: #include <sys/systm.h>
   34: #include <sys/ata.h>
   35: #include <sys/buf.h>
   36: #include <sys/malloc.h> 
   37: #include <sys/mpipe.h> 
   38: #include <sys/bus.h>
   39: #include <sys/disk.h>
   40: #include <sys/devicestat.h>
   41: #include <vm/vm.h>	     
   42: #include <vm/pmap.h>
   43: #include <bus/pci/pcivar.h>
   44: #include <machine/bus.h>
   45: #include <sys/rman.h>
   46: #include "ata-all.h"
   47: 
   48: /* prototypes */
   49: static void cyrix_timing(struct ata_device *, int, int);
   50: static void promise_timing(struct ata_device *, int, int);
   51: static void hpt_timing(struct ata_device *, int, int);
   52: static int hpt_cable80(struct ata_device *);
   53: 
   54: /* misc defines */
   55: #ifdef __alpha__
   56: #undef vtophys
   57: #define vtophys(va)	alpha_XXX_dmamap((vm_offset_t)va)
   58: #endif
   59: #define ATAPI_DEVICE(atadev) \
   60: 	((atadev->unit == ATA_MASTER && \
   61: 	  atadev->channel->devices & ATA_ATAPI_MASTER) || \
   62: 	 (atadev->unit == ATA_SLAVE && \
   63: 	 atadev->channel->devices & ATA_ATAPI_SLAVE))
   64: 
   65: int ata_dma_debug = 0;
   66: 
   67: int
   68: ata_dmaalloc(struct ata_device *atadev, int flags)
   69: {
   70:     struct ata_channel *ch = atadev->channel;
   71: 
   72:     if (atadev->dmastate.dmatab != NULL)
   73: 	return(0);
   74: 
   75:     KKASSERT(ch->dma_mpipe.max_count != 0);
   76:     atadev->dmastate.dmatab = mpipe_alloc(&ch->dma_mpipe, flags);
   77:     KKASSERT(((uintptr_t)atadev->dmastate.dmatab & PAGE_MASK) == 0);
   78: 
   79:     if (atadev->dmastate.dmatab != NULL)
   80: 	return(0);
   81:     return(ENOBUFS);
   82: }
   83: 
   84: void
   85: ata_dmafree(struct ata_device *atadev)
   86: {
   87:     struct ata_channel *ch = atadev->channel;
   88: 
   89:     if (atadev->dmastate.dmatab) {
   90: 	mpipe_free(&ch->dma_mpipe, atadev->dmastate.dmatab);
   91: 	atadev->dmastate.dmatab = NULL;
   92:     }
   93: }
   94: 
   95: void
   96: ata_dmafreetags(struct ata_channel *ch)
   97: {
   98: }
   99: 
  100: static void
  101: ata_dmacreate(struct ata_device *atadev, int apiomode, int mode)
  102: {
  103:     atadev->mode = mode;
  104: }
  105: 
  106: void
  107: ata_dmainit(struct ata_device *atadev, int apiomode, int wdmamode, int udmamode)
  108: {
  109:     device_t parent = device_get_parent(atadev->channel->dev);
  110:     int chiptype = atadev->channel->chiptype;
  111:     int chiprev = pci_get_revid(parent);
  112:     int channel = atadev->channel->unit;
  113:     int device = ATA_DEV(atadev->unit);
  114:     int devno = (channel << 1) + device;
  115:     int error;
  116: 
  117:     /* set our most pessimistic default mode */
  118:     atadev->mode = ATA_PIO;
  119: 
  120:     if (!atadev->channel->r_bmio)
  121: 	return;
  122: 
  123:     /* if simplex controller, only allow DMA on primary channel */
  124:     if (channel == 1) {
  125: 	ATA_OUTB(atadev->channel->r_bmio, ATA_BMSTAT_PORT,
  126: 		 ATA_INB(atadev->channel->r_bmio, ATA_BMSTAT_PORT) &
  127: 		 (ATA_BMSTAT_DMA_MASTER | ATA_BMSTAT_DMA_SLAVE));
  128: 	if (ATA_INB(atadev->channel->r_bmio, ATA_BMSTAT_PORT) & 
  129: 	    ATA_BMSTAT_DMA_SIMPLEX) {
  130: 	    ata_prtdev(atadev, "simplex device, DMA on primary only\n");
  131: 	    return;
  132: 	}
  133:     }
  134: 
  135:     /* DMA engine address alignment is usually 1 word (2 bytes) */
  136:     atadev->channel->alignment = 0x1;
  137: 
  138: #if 1
  139:     if (udmamode > 2 && !atadev->param->hwres_cblid) {
  140: 	ata_prtdev(atadev,"DMA limited to UDMA33, non-ATA66 cable or device\n");
  141: 	udmamode = 2;
  142:     }
  143: #endif
  144:     switch (chiptype) {
  145: 
  146:     case 0x24db8086:	/* Intel ICH5 */
  147:     case 0x24d18086:	/* Intel ICH5 SATA */
  148:     case 0x24ca8086:	/* Intel ICH4 mobile */
  149:     case 0x24cb8086:	/* Intel ICH4 */
  150:     case 0x248a8086:	/* Intel ICH3 mobile */ 
  151:     case 0x248b8086:	/* Intel ICH3 */
  152:     case 0x244a8086:	/* Intel ICH2 mobile */ 
  153:     case 0x244b8086:	/* Intel ICH2 */
  154: 	if (udmamode >= 5) {
  155: 	    int32_t mask48, new48;
  156: 	    int16_t word54;
  157: 
  158: 	    word54 = pci_read_config(parent, 0x54, 2);
  159: 	    if (word54 & (0x10 << devno)) {
  160: 		error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  161: 				    ATA_UDMA5,	ATA_C_F_SETXFER,ATA_WAIT_READY);
  162: 		if (bootverbose)
  163: 		    ata_prtdev(atadev, "%s setting UDMA5 on Intel chip\n",
  164: 			       (error) ? "failed" : "success");
  165: 		if (!error) {
  166: 		    mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
  167: 		    new48 = (1 << devno) + (1 << (16 + (devno << 2)));
  168: 		    pci_write_config(parent, 0x48,
  169: 				     (pci_read_config(parent, 0x48, 4) &
  170: 				     ~mask48) | new48, 4);
  171: 		    pci_write_config(parent, 0x54, word54 | (0x1000<<devno), 2);
  172: 		    ata_dmacreate(atadev, apiomode, ATA_UDMA5);
  173: 		    return;
  174: 		}
  175: 	    }
  176: 	}
  177: 	/* make sure eventual ATA100 mode from the BIOS is disabled */
  178: 	pci_write_config(parent, 0x54, 
  179: 			 pci_read_config(parent, 0x54, 2) & ~(0x1000<<devno),2);
  180: 	/* FALLTHROUGH */
  181: 
  182:     case 0x24118086:	/* Intel ICH */
  183:     case 0x76018086:	/* Intel ICH */
  184: 	if (udmamode >= 4) {
  185: 	    int32_t mask48, new48;
  186: 	    int16_t word54;
  187: 
  188: 	    word54 = pci_read_config(parent, 0x54, 2);
  189: 	    if (word54 & (0x10 << devno)) {
  190: 		error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  191: 				    ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
  192: 		if (bootverbose)
  193: 		    ata_prtdev(atadev, "%s setting UDMA4 on Intel chip\n",
  194: 			       (error) ? "failed" : "success");
  195: 		if (!error) {
  196: 		    mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
  197: 		    new48 = (1 << devno) + (2 << (16 + (devno << 2)));
  198: 		    pci_write_config(parent, 0x48,
  199: 				     (pci_read_config(parent, 0x48, 4) &
  200: 				     ~mask48) | new48, 4);
  201: 		    pci_write_config(parent, 0x54, word54 | (1 << devno), 2);
  202: 		    ata_dmacreate(atadev, apiomode, ATA_UDMA4);
  203: 		    return;
  204: 		}
  205: 	    }
  206: 	}	    
  207: 	/* make sure eventual ATA66 mode from the BIOS is disabled */
  208: 	pci_write_config(parent, 0x54, 
  209: 			 pci_read_config(parent, 0x54, 2) & ~(1 << devno), 2);
  210: 	/* FALLTHROUGH */
  211: 
  212:     case 0x71118086:	/* Intel PIIX4 */
  213:     case 0x84CA8086:	/* Intel PIIX4 */
  214:     case 0x71998086:	/* Intel PIIX4e */
  215:     case 0x24218086:	/* Intel ICH0 */
  216: 	if (udmamode >= 2) {
  217: 	    int32_t mask48, new48;
  218: 
  219: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  220: 				ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
  221: 	    if (bootverbose)
  222: 		ata_prtdev(atadev, "%s setting UDMA2 on Intel chip\n",
  223: 			   (error) ? "failed" : "success");
  224: 	    if (!error) {
  225: 		mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
  226: 		new48 = (1 << devno) + (2 << (16 + (devno << 2)));
  227: 		pci_write_config(parent, 0x48, 
  228: 				 (pci_read_config(parent, 0x48, 4) &
  229: 				 ~mask48) | new48, 4);
  230: 		ata_dmacreate(atadev, apiomode, ATA_UDMA2);
  231: 		return;
  232: 	    }
  233: 	}
  234: 	/* make sure eventual ATA33 mode from the BIOS is disabled */
  235: 	pci_write_config(parent, 0x48, 
  236: 			 pci_read_config(parent, 0x48, 4) & ~(1 << devno), 4);
  237: 	/* FALLTHROUGH */
  238: 
  239:     case 0x70108086:	/* Intel PIIX3 */
  240: 	if (wdmamode >= 2 && apiomode >= 4) {
  241: 	    int32_t mask40, new40, mask44, new44;
  242: 
  243: 	    /* if SITRE not set doit for both channels */
  244: 	    if (!((pci_read_config(parent,0x40,4)>>(channel<<8))&0x4000)) {
  245: 		new40 = pci_read_config(parent, 0x40, 4);
  246: 		new44 = pci_read_config(parent, 0x44, 4); 
  247: 		if (!(new40 & 0x00004000)) {
  248: 		    new44 &= ~0x0000000f;
  249: 		    new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8);
  250: 		}
  251: 		if (!(new40 & 0x40000000)) {
  252: 		    new44 &= ~0x000000f0;
  253: 		    new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20);
  254: 		}
  255: 		new40 |= 0x40004000;
  256: 		pci_write_config(parent, 0x40, new40, 4);
  257: 		pci_write_config(parent, 0x44, new44, 4);
  258: 	    }
  259: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  260: 				ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
  261: 	    if (bootverbose)
  262: 		ata_prtdev(atadev, "%s setting WDMA2 on Intel chip\n",
  263: 			   (error) ? "failed" : "success");
  264: 	    if (!error) {
  265: 		if (device == ATA_MASTER) {
  266: 		    mask40 = 0x0000330f;
  267: 		    new40 = 0x00002307;
  268: 		    mask44 = 0;
  269: 		    new44 = 0;
  270: 		}
  271: 		else {
  272: 		    mask40 = 0x000000f0;
  273: 		    new40 = 0x00000070;
  274: 		    mask44 = 0x0000000f;
  275: 		    new44 = 0x0000000b;
  276: 		}
  277: 		if (channel) {
  278: 		    mask40 <<= 16;
  279: 		    new40 <<= 16;
  280: 		    mask44 <<= 4;
  281: 		    new44 <<= 4;
  282: 		}
  283: 		pci_write_config(parent, 0x40,
  284: 				 (pci_read_config(parent, 0x40, 4) & ~mask40)|
  285: 				 new40, 4);
  286: 		pci_write_config(parent, 0x44,
  287: 				 (pci_read_config(parent, 0x44, 4) & ~mask44)|
  288: 				 new44, 4);
  289: 		ata_dmacreate(atadev, apiomode, ATA_WDMA2);
  290: 		return;
  291: 	    }
  292: 	}
  293: 	/* we could set PIO mode timings, but we assume the BIOS did that */
  294: 	break;
  295: 
  296:     case 0x12308086:	/* Intel PIIX */
  297: 	if (wdmamode >= 2 && apiomode >= 4) {
  298: 	    int32_t word40;
  299: 
  300: 	    word40 = pci_read_config(parent, 0x40, 4);
  301: 	    word40 >>= channel * 16;
  302: 
  303: 	    /* Check for timing config usable for DMA on controller */
  304: 	    if (!((word40 & 0x3300) == 0x2300 &&
  305: 		  ((word40 >> (device ? 4 : 0)) & 1) == 1))
  306: 		break;
  307: 
  308: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  309: 				ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
  310: 	    if (bootverbose)
  311: 		ata_prtdev(atadev, "%s setting WDMA2 on Intel chip\n",
  312: 			   (error) ? "failed" : "success");
  313: 	    if (!error) {
  314: 		ata_dmacreate(atadev, apiomode, ATA_WDMA2);
  315: 		return;
  316: 	    }
  317: 	}
  318: 	break;
  319: 
  320:     case 0x522910b9:	/* AcerLabs Aladdin IV/V */
  321: 	/* the older Aladdin doesn't support ATAPI DMA on both master & slave */
  322: 	if (chiprev < 0xc2 &&
  323: 	    atadev->channel->devices & ATA_ATAPI_MASTER && 
  324: 	    atadev->channel->devices & ATA_ATAPI_SLAVE) {
  325: 	    ata_prtdev(atadev, "two atapi devices on this channel, no DMA\n");
  326: 	    break;
  327: 	}
  328: #if !defined(NO_ATANG)
  329: 	pci_write_config(parent, 0x58 + (channel << 2), 0x00310001, 4);
  330: #endif
  331: 	if (udmamode >= 5 && chiprev >= 0xc4) {
  332: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  333: 				ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
  334: 	    if (bootverbose)
  335: 		ata_prtdev(atadev, "%s setting UDMA5 on Acer chip\n",
  336: 			   (error) ? "failed" : "success");
  337: 	    if (!error) {
  338: 		int32_t word54 = pci_read_config(parent, 0x54, 4);
  339: 	
  340: 		pci_write_config(parent, 0x4b,
  341: 				 pci_read_config(parent, 0x4b, 1) | 0x01, 1);
  342: 		word54 &= ~(0x000f000f << (devno << 2));
  343: 		word54 |= (0x000f0005 << (devno << 2));
  344: 		pci_write_config(parent, 0x54, word54, 4);
  345: 		pci_write_config(parent, 0x53, 
  346: 				 pci_read_config(parent, 0x53, 1) | 0x03, 1);
  347: 		ata_dmacreate(atadev, apiomode, ATA_UDMA5);
  348: 		return;
  349: 	    }
  350: 	}
  351: 	if (udmamode >= 4 && chiprev >= 0xc2) {
  352: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  353: 				ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
  354: 	    if (bootverbose)
  355: 		ata_prtdev(atadev, "%s setting UDMA4 on Acer chip\n",
  356: 			   (error) ? "failed" : "success");
  357: 	    if (!error) {
  358: 		int32_t word54 = pci_read_config(parent, 0x54, 4);
  359: 	
  360: 		pci_write_config(parent, 0x4b,
  361: 				 pci_read_config(parent, 0x4b, 1) | 0x01, 1);
  362: 		word54 &= ~(0x000f000f << (devno << 2));
  363: 		word54 |= (0x00080005 << (devno << 2));
  364: 		pci_write_config(parent, 0x54, word54, 4);
  365: 		pci_write_config(parent, 0x53, 
  366: 				 pci_read_config(parent, 0x53, 1) | 0x03, 1);
  367: 		ata_dmacreate(atadev, apiomode, ATA_UDMA4);
  368: 		return;
  369: 	    }
  370: 	}
  371: 	if (udmamode >= 2 && chiprev >= 0x20) {
  372: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  373: 				ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
  374: 	    if (bootverbose)
  375: 		ata_prtdev(atadev, "%s setting UDMA2 on Acer chip\n",
  376: 			   (error) ? "failed" : "success");
  377: 	    if (!error) {
  378: 		int32_t word54 = pci_read_config(parent, 0x54, 4);
  379: 	
  380: 		word54 &= ~(0x000f000f << (devno << 2));
  381: 		word54 |= (0x000a0005 << (devno << 2));
  382: 		pci_write_config(parent, 0x54, word54, 4);
  383: 		pci_write_config(parent, 0x53, 
  384: 				 pci_read_config(parent, 0x53, 1) | 0x03, 1);
  385: 		atadev->channel->flags |= ATA_ATAPI_DMA_RO;
  386: 		ata_dmacreate(atadev, apiomode, ATA_UDMA2);
  387: 		return;
  388: 	    }
  389: 	}
  390: 
  391: 	/* make sure eventual UDMA mode from the BIOS is disabled */
  392: 	pci_write_config(parent, 0x56, pci_read_config(parent, 0x56, 2) &
  393: 				       ~(0x0008 << (devno << 2)), 2);
  394: 
  395: 	if (wdmamode >= 2 && apiomode >= 4) {
  396: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  397: 				ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
  398: 	    if (bootverbose)
  399: 		ata_prtdev(atadev, "%s setting WDMA2 on Acer chip\n",
  400: 			   (error) ? "failed" : "success");
  401: 	    if (!error) {
  402: 		pci_write_config(parent, 0x53, 
  403: 				 pci_read_config(parent, 0x53, 1) | 0x03, 1);
  404: 		atadev->channel->flags |= ATA_ATAPI_DMA_RO;
  405: 		ata_dmacreate(atadev, apiomode, ATA_WDMA2);
  406: 		return;
  407: 	    }
  408: 	}
  409: 	pci_write_config(parent, 0x53,
  410: 			 (pci_read_config(parent, 0x53, 1) & ~0x01) | 0x02, 1);
  411: #if !defined(NO_ATANG)
  412: 	error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  413: 			    ATA_PIO0 + apiomode,
  414: 			    ATA_C_F_SETXFER, ATA_WAIT_READY);
  415: 	if (bootverbose)
  416: 	    ata_prtdev(atadev, "%s setting PIO%d on Acer chip\n",
  417: 			(error) ? "failed" : "success",
  418: 			(apiomode >= 0) ? apiomode : 0);
  419: 	if (!error) {
  420: 	    int32_t word54 = pci_read_config(parent, 0x54, 4);
  421: 	    int32_t timing;
  422: 
  423: 	    switch(ATA_PIO0 + apiomode) {
  424: 	    case ATA_PIO0: timing = 0x006d0003; break;
  425: 	    case ATA_PIO1: timing = 0x00580002; break;
  426: 	    case ATA_PIO2: timing = 0x00440001; break;
  427: 	    case ATA_PIO3: timing = 0x00330001; break;
  428: 	    case ATA_PIO4: timing = 0x00310001; break;
  429: 	    default:       timing = 0x006d0003; break;
  430: 	    }
  431: 	    pci_write_config(parent, 0x58 + (channel << 2), timing, 4);
  432: 	    word54 &= ~(0x000f000f << (devno << 2));
  433: 	    word54 |= (0x00000004 << (devno << 2));
  434: 	    pci_write_config(parent, 0x54, word54, 4);
  435: 	    atadev->mode = ATA_PIO0 + apiomode;
  436: 	    return;
  437: 	}
  438: #endif
  439: 	break;
  440: 
  441:     case 0x31491106:   /* VIA 8237 SATA part */
  442: 	if (udmamode) {
  443: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  444: 				ATA_UDMA + udmamode,
  445: 				ATA_C_F_SETXFER, ATA_WAIT_READY);
  446: 	    if (bootverbose)
  447: 		ata_prtdev(atadev, "%s setting UDMA%d on VIA chip\n",
  448: 			    (error) ? "failed" : "success", udmamode);
  449: 	    if (!error) {
  450: 		ata_dmacreate(atadev, apiomode, ATA_UDMA + udmamode);
  451: 		return;
  452: 	    }
  453: 	}
  454: 	/* we could set PIO mode timings, but we assume the BIOS did that */
  455: 	break;
  456: 
  457:     case 0x01bc10de:	/* NVIDIA nForce */
  458:     case 0x006510de:	/* NVIDIA nForce2 */
  459:     case 0x74691022:   /* AMD 8111 */
  460:     case 0x74411022:	/* AMD 768 */
  461:     case 0x74111022:	/* AMD 766 */
  462:     case 0x74091022:	/* AMD 756 */
  463:     case 0x05711106:	/* VIA 82C571, 82C586, 82C596, 82C686, 8231,8233,8235 */
  464: 	{
  465: 	    int via_modes[5][7] = {
  466: 		{ 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00 },   /* VIA ATA33 */
  467: 		{ 0x00, 0x00, 0xea, 0x00, 0xe8, 0x00, 0x00 },   /* VIA ATA66 */
  468: 		{ 0x00, 0x00, 0xf4, 0x00, 0xf1, 0xf0, 0x00 },   /* VIA ATA100 */
  469: 		{ 0x00, 0x00, 0xf6, 0x00, 0xf2, 0xf1, 0xf0 },   /* VIA ATA133 */
  470: 		{ 0x00, 0x00, 0xc0, 0x00, 0xc5, 0xc6, 0xc7 }};  /* AMD/NVIDIA */
  471: 	    int *reg_val = NULL;
  472: 	    int reg_off = 0x53;
  473: 	    char *chip = "VIA";
  474: 
  475: 	    if (ata_find_dev(parent, 0x31471106, 0) ||		/* 8233a */
  476: 		ata_find_dev(parent, 0x31771106, 0) ||		/* 8235 */
  477: 		ata_find_dev(parent, 0x31491106, 0)) {		/* 8237 */
  478: 		udmamode = imin(udmamode, 6);
  479: 		reg_val = via_modes[3];
  480: 	    }
  481: 	    else if (ata_find_dev(parent, 0x06861106, 0x40) ||	/* 82C686b */
  482: 		ata_find_dev(parent, 0x82311106, 0) ||		/* 8231 */
  483: 		ata_find_dev(parent, 0x30741106, 0) ||		/* 8233 */
  484: 		ata_find_dev(parent, 0x31091106, 0)) {		/* 8233c */
  485: 		udmamode = imin(udmamode, 5);
  486: 		reg_val = via_modes[2];
  487: 	    }
  488: 	    else if (ata_find_dev(parent, 0x06861106, 0x10) ||	/* 82C686a */
  489: 		     ata_find_dev(parent, 0x05961106, 0x12)) {	/* 82C596b */
  490: 		udmamode = imin(udmamode, 4);
  491: 		reg_val = via_modes[1];
  492: 	    }
  493: 	    else if (ata_find_dev(parent, 0x06861106, 0)) {	/* 82C686 */
  494: 		udmamode = imin(udmamode, 2);
  495: 		reg_val = via_modes[1];
  496: 	    }
  497: 	    else if (ata_find_dev(parent, 0x05961106, 0) ||	/* 82C596a */
  498: 		     ata_find_dev(parent, 0x05861106, 0x03)) {	/* 82C586b */
  499: 		udmamode = imin(udmamode, 2);
  500: 		reg_val = via_modes[0];
  501: 	    }
  502: 	    else if (chiptype == 0x74691022 ||		/* AMD 8111 */
  503: 		     chiptype == 0x74411022 ||		/* AMD 768 */
  504: 		     chiptype == 0x74111022) {		/* AMD 766 */
  505: 		udmamode = imin(udmamode, 5);
  506: 		reg_val = via_modes[4];
  507: 		chip = "AMD";
  508: 	    }
  509: 	    else if (chiptype == 0x74091022) {		/* AMD 756 */
  510: 		udmamode = imin(udmamode, 4);
  511: 		reg_val = via_modes[4];
  512: 		chip = "AMD";
  513: 	    }
  514: 	    else if (chiptype == 0x01bc10de) {		/* nForce */
  515: 		udmamode = imin(udmamode, 5);
  516: 		reg_val = via_modes[4];
  517: #if !defined(NO_ATANG)
  518: 		reg_off += 0x10;
  519: #endif
  520: 		chip = "nVIDIA";
  521: 	    }
  522: 	    else if (chiptype == 0x006510de) {		/* nForce2 */
  523: 		udmamode = imin(udmamode, 6);
  524: 		reg_val = via_modes[4];
  525: #if !defined(NO_ATANG)
  526: 		reg_off += 0x10;
  527: #endif
  528: 		chip = "nVIDIA";
  529: 	    }
  530: 	    else 
  531: 		udmamode = 0;
  532: 
  533: 	    if (udmamode >= 6) {
  534: 		error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  535: 				    ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY);
  536: 		if (bootverbose)
  537: 		    ata_prtdev(atadev, "%s setting UDMA6 on %s chip\n",
  538: 			       (error) ? "failed" : "success", chip);
  539: 		if (!error) {
  540: 		    pci_write_config(parent, reg_off - devno, reg_val[6], 1);
  541: 		    ata_dmacreate(atadev, apiomode, ATA_UDMA6);
  542: 		    return;
  543: 		}
  544: 	    }
  545: 	    if (udmamode >= 5) {
  546: 		error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  547: 				    ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
  548: 		if (bootverbose)
  549: 		    ata_prtdev(atadev, "%s setting UDMA5 on %s chip\n",
  550: 			       (error) ? "failed" : "success", chip);
  551: 		if (!error) {
  552: 		    pci_write_config(parent, reg_off - devno, reg_val[5], 1);
  553: 		    ata_dmacreate(atadev, apiomode, ATA_UDMA5);
  554: 		    return;
  555: 		}
  556: 	    }
  557: 	    if (udmamode >= 4) {
  558: 		error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  559: 				    ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
  560: 		if (bootverbose)
  561: 		    ata_prtdev(atadev, "%s setting UDMA4 on %s chip\n",
  562: 			       (error) ? "failed" : "success", chip);
  563: 		if (!error) {
  564: 		    pci_write_config(parent, reg_off - devno, reg_val[4], 1);
  565: 		    ata_dmacreate(atadev, apiomode, ATA_UDMA4);
  566: 		    return;
  567: 		}
  568: 	    }
  569: 	    if (udmamode >= 2) {
  570: 		error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  571: 				    ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
  572: 		if (bootverbose)
  573: 		    ata_prtdev(atadev, "%s setting UDMA2 on %s chip\n",
  574: 			       (error) ? "failed" : "success", chip);
  575: 		if (!error) {
  576: 		    pci_write_config(parent, reg_off - devno, reg_val[2], 1);
  577: 		    ata_dmacreate(atadev, apiomode, ATA_UDMA2);
  578: 		    return;
  579: 		}
  580: 	    }
  581: 	    if (wdmamode >= 2 && apiomode >= 4) {
  582: 		error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  583: 				    ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
  584: 		if (bootverbose)
  585: 		    ata_prtdev(atadev, "%s setting WDMA2 on %s chip\n",
  586: 			       (error) ? "failed" : "success", chip);
  587: 		if (!error) {
  588: 		    pci_write_config(parent, reg_off - devno, 0x0b, 1);
  589: 		    pci_write_config(parent, (reg_off - 8) - devno, 0x31, 1);
  590: 		    ata_dmacreate(atadev, apiomode, ATA_WDMA2);
  591: 		    return;
  592: 		}
  593: 	    }
  594: 	}
  595: 	/* we could set PIO mode timings, but we assume the BIOS did that */
  596: 	break;
  597: 
  598:     case 0x55131039:	/* SiS 5591 */
  599: 	if (ata_find_dev(parent, 0x06301039, 0x30) ||	/* SiS 630 */
  600: 	    ata_find_dev(parent, 0x06331039, 0) ||	/* SiS 633 */
  601: 	    ata_find_dev(parent, 0x06351039, 0) ||	/* SiS 635 */
  602: 	    ata_find_dev(parent, 0x06401039, 0) ||	/* SiS 640 */
  603: 	    ata_find_dev(parent, 0x06451039, 0) ||	/* SiS 645 */
  604: 	    ata_find_dev(parent, 0x06461039, 0) ||	/* SiS 645DX */
  605: 	    ata_find_dev(parent, 0x06481039, 0) ||      /* SiS 648 */
  606: 	    ata_find_dev(parent, 0x06501039, 0) ||	/* SiS 650 */
  607: 	    ata_find_dev(parent, 0x07301039, 0) ||	/* SiS 730 */
  608: 	    ata_find_dev(parent, 0x07331039, 0) ||	/* SiS 733 */
  609: 	    ata_find_dev(parent, 0x07351039, 0) ||	/* SiS 735 */
  610: 	    ata_find_dev(parent, 0x07401039, 0) ||	/* SiS 740 */
  611: 	    ata_find_dev(parent, 0x07451039, 0) ||	/* SiS 745 */
  612: 	    ata_find_dev(parent, 0x07461039, 0) ||	/* SiS 746 */
  613: 	    ata_find_dev(parent, 0x07501039, 0)) {	/* SiS 750 */
  614: 	    int8_t reg = 0x40 + (devno << 1);
  615: 	    int16_t val = pci_read_config(parent, reg, 2) & 0x0fff;
  616: 
  617: 	    if (udmamode >= 5) {
  618: 		error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  619: 				    ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
  620: 		if (bootverbose)
  621: 		    ata_prtdev(atadev, "%s setting UDMA5 on SiS chip\n",
  622: 			       (error) ? "failed" : "success");
  623: 		if (!error) {
  624: 		    pci_write_config(parent, reg, val | 0x8000, 2);
  625: 		    ata_dmacreate(atadev, apiomode, ATA_UDMA5);
  626: 		    return;
  627: 		}
  628: 	    }
  629: 	    if (udmamode >= 4) {
  630: 		error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  631: 				    ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
  632: 		if (bootverbose)
  633: 		    ata_prtdev(atadev, "%s setting UDMA4 on SiS chip\n",
  634: 			       (error) ? "failed" : "success");
  635: 		if (!error) {
  636: 		    pci_write_config(parent, reg, val | 0x9000, 2);
  637: 		    ata_dmacreate(atadev, apiomode, ATA_UDMA4);
  638: 		    return;
  639: 		}
  640: 	    }
  641: 	    if (udmamode >= 2) {
  642: 		error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  643: 				    ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
  644: 		if (bootverbose)
  645: 		    ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n",
  646: 			       (error) ? "failed" : "success");
  647: 		if (!error) {
  648: 		    pci_write_config(parent, reg, val | 0xb000, 2);
  649: 		    ata_dmacreate(atadev, apiomode, ATA_UDMA2);
  650: 		    return;
  651: 		}
  652: 	    }
  653: 	} else if (ata_find_dev(parent, 0x05301039, 0) || /* SiS 530 */
  654: 		   ata_find_dev(parent, 0x05401039, 0) || /* SiS 540 */
  655: 		   ata_find_dev(parent, 0x06201039, 0) || /* SiS 620 */
  656: 		   ata_find_dev(parent, 0x06301039, 0)) { /* SiS 630 */
  657: 	    int8_t reg = 0x40 + (devno << 1);
  658: 	    int16_t val = pci_read_config(parent, reg, 2) & 0x0fff;
  659: 
  660: 	    if (udmamode >= 4) {
  661: 		error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  662: 				    ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
  663: 		if (bootverbose)
  664: 		    ata_prtdev(atadev, "%s setting UDMA4 on SiS chip\n",
  665: 			       (error) ? "failed" : "success");
  666: 		if (!error) {
  667: 		    pci_write_config(parent, reg, val | 0x9000, 2);
  668: 		    ata_dmacreate(atadev, apiomode, ATA_UDMA4);
  669: 		    return;
  670: 		}
  671: 	    }
  672: 	    if (udmamode >= 2) {
  673: 		error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  674: 				    ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
  675: 		if (bootverbose)
  676: 		    ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n",
  677: 			       (error) ? "failed" : "success");
  678: 		if (!error) {
  679: 		    pci_write_config(parent, reg, val | 0xa000, 2);
  680: 		    ata_dmacreate(atadev, apiomode, ATA_UDMA2);
  681: 		    return;
  682: 		}
  683: 	    }
  684: 	} else if (udmamode >= 2 && chiprev > 0xc1) {
  685: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  686: 				ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
  687: 	    if (bootverbose)
  688: 		ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n",
  689: 			   (error) ? "failed" : "success");
  690: 	    if (!error) {
  691: 		pci_write_config(parent, 0x40 + (devno << 1), 0xa301, 2);
  692: 		ata_dmacreate(atadev, apiomode, ATA_UDMA2);
  693: 		return;
  694: 	    }
  695: 	}
  696: 	if (wdmamode >=2 && apiomode >= 4) {
  697: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  698: 				ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
  699: 	    if (bootverbose)
  700: 		ata_prtdev(atadev, "%s setting WDMA2 on SiS chip\n",
  701: 			   (error) ? "failed" : "success");
  702: 	    if (!error) {
  703: 		pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2);
  704: 		ata_dmacreate(atadev, apiomode, ATA_WDMA2);
  705: 		return;
  706: 	    }
  707: 	}
  708: 	/* we could set PIO mode timings, but we assume the BIOS did that */
  709: 	break;
  710: 
  711:     case 0x35121095:	/* SiI 3512 SATA controller */
  712: 	/* EXPERIMENTAL!  Works with FN85 AMD 64 3200+ motherboard */
  713: 	/* FALLTHROUGH */
  714:     case 0x31141095:	/* SiI 3114 SATA controller */
  715:     case 0x06801095:	/* SiI 0680 ATA133 controller */
  716: 	{
  717: 	    u_int8_t ureg = 0xac + (device * 0x02) + (channel * 0x10);
  718: 	    u_int8_t uval = pci_read_config(parent, ureg, 1);
  719: 	    u_int8_t mreg = channel ? 0x84 : 0x80;
  720: 	    u_int8_t mask = device ? 0x30 : 0x03;
  721: 	    u_int8_t mode = pci_read_config(parent, mreg, 1);
  722: 
  723: 	    /* enable UDMA mode */
  724: 	    pci_write_config(parent, mreg,
  725: 			     (mode & ~mask) | (device ? 0x30 : 0x03), 1);
  726:     	    if (udmamode >= 6) {
  727: 		error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  728: 				    ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY);
  729: 		if (bootverbose)
  730: 		    ata_prtdev(atadev, "%s setting UDMA6 on SiI chip\n",
  731: 			       (error) ? "failed" : "success");
  732: 		if (!error) {
  733: 		    pci_write_config(parent, ureg, (uval & ~0x3f) | 0x01, 1);
  734: 		    ata_dmacreate(atadev, apiomode, ATA_UDMA6);
  735: 		    return;
  736: 		}
  737: 	    }
  738:     	    if (udmamode >= 5) {
  739: 		error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  740: 				    ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
  741: 		if (bootverbose)
  742: 		    ata_prtdev(atadev, "%s setting UDMA5 on SiI chip\n",
  743: 			       (error) ? "failed" : "success");
  744: 		if (!error) {
  745: 		    pci_write_config(parent, ureg, (uval & ~0x3f) | 0x02, 1);
  746: 		    ata_dmacreate(atadev, apiomode, ATA_UDMA5);
  747: 		    return;
  748: 		}
  749: 	    }
  750:     	    if (udmamode >= 4) {
  751: 		error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  752: 				    ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
  753: 		if (bootverbose)
  754: 		    ata_prtdev(atadev, "%s setting UDMA4 on SiI chip\n",
  755: 			       (error) ? "failed" : "success");
  756: 		if (!error) {
  757: 		    pci_write_config(parent, ureg, (uval & ~0x3f) | 0x03, 1);
  758: 		    ata_dmacreate(atadev, apiomode, ATA_UDMA4);
  759: 		    return;
  760: 		}
  761: 	    }
  762:     	    if (udmamode >= 2) {
  763: 		error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  764: 				    ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
  765: 		if (bootverbose)
  766: 		    ata_prtdev(atadev, "%s setting UDMA2 on SiI chip\n",
  767: 			       (error) ? "failed" : "success");
  768: 		if (!error) {
  769: 		    pci_write_config(parent, ureg, (uval & ~0x3f) | 0x07, 1);
  770: 		    ata_dmacreate(atadev, apiomode, ATA_UDMA2);
  771: 		    return;
  772: 		}
  773: 	    }
  774: 
  775: 	    /* disable UDMA mode and enable WDMA mode */
  776: 	    pci_write_config(parent, mreg,
  777: 			     (mode & ~mask) | (device ? 0x20 : 0x02), 1);
  778: 	    if (wdmamode >= 2 && apiomode >= 4) {
  779: 		error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  780: 				    ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
  781: 		if (bootverbose)
  782: 		    ata_prtdev(atadev, "%s setting WDMA2 on SiI chip\n",
  783: 			       (error) ? "failed" : "success");
  784: 		if (!error) {
  785: 		    pci_write_config(parent, ureg - 0x4, 0x10c1, 2);
  786: 		    ata_dmacreate(atadev, apiomode, ATA_WDMA2);
  787: 		    return;
  788: 		}
  789: 	    }
  790: 
  791: 	    /* restore PIO mode */
  792: 	    pci_write_config(parent, mreg, mode, 1);
  793: 	}
  794: 	/* we could set PIO mode timings, but we assume the BIOS did that */
  795: 	break;
  796: 
  797:     case 0x06491095:	/* CMD 649 ATA100 controller */
  798: 	if (udmamode >= 5) {
  799: 	    u_int8_t umode;
  800: 
  801: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  802: 				ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
  803: 	    if (bootverbose)
  804: 		ata_prtdev(atadev, "%s setting UDMA5 on CMD chip\n",
  805: 			   (error) ? "failed" : "success");
  806: 	    if (!error) {
  807: 		umode = pci_read_config(parent, channel ? 0x7b : 0x73, 1);
  808: 		umode &= ~(device ? 0xca : 0x35);
  809: 		umode |= (device ? 0x0a : 0x05);
  810: 		pci_write_config(parent, channel ? 0x7b : 0x73, umode, 1);
  811: 		ata_dmacreate(atadev, apiomode, ATA_UDMA5);
  812: 		return;
  813: 	    }
  814: 	}
  815: 	/* FALLTHROUGH */
  816: 
  817:     case 0x06481095:	/* CMD 648 ATA66 controller */
  818: 	if (udmamode >= 4) {
  819: 	    u_int8_t umode;
  820: 
  821: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  822: 				ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
  823: 	    if (bootverbose)
  824: 		ata_prtdev(atadev, "%s setting UDMA4 on CMD chip\n",
  825: 			   (error) ? "failed" : "success");
  826: 	    if (!error) {
  827: 		umode = pci_read_config(parent, channel ? 0x7b : 0x73, 1);
  828: 		umode &= ~(device ? 0xca : 0x35);
  829: 		umode |= (device ? 0x4a : 0x15);
  830: 		pci_write_config(parent, channel ? 0x7b : 0x73, umode, 1);
  831: 		ata_dmacreate(atadev, apiomode, ATA_UDMA4);
  832: 		return;
  833: 	    }
  834: 	}
  835: 	if (udmamode >= 2) {
  836: 	    u_int8_t umode;
  837: 
  838: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  839: 				ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
  840: 	    if (bootverbose)
  841: 		ata_prtdev(atadev, "%s setting UDMA2 on CMD chip\n",
  842: 			   (error) ? "failed" : "success");
  843: 	    if (!error) {
  844: 		umode = pci_read_config(parent, channel ? 0x7b : 0x73, 1);
  845: 		umode &= ~(device ? 0xca : 0x35);
  846: 		umode |= (device ? 0x42 : 0x11);
  847: 		pci_write_config(parent, channel ? 0x7b : 0x73, umode, 1);
  848: 		ata_dmacreate(atadev, apiomode, ATA_UDMA2);
  849: 		return;
  850: 	    }
  851: 	}
  852: 	/* make sure eventual UDMA mode from the BIOS is disabled */
  853: 	pci_write_config(parent, channel ? 0x7b : 0x73, 
  854: 			 pci_read_config(parent, channel ? 0x7b : 0x73, 1)&
  855: #if !defined(NO_ATANG)
  856: 			 ~(device ? 0xca : 0x53), 1);
  857: #else
  858: 			 ~(device ? 0xca : 0x35), 1);
  859: #endif
  860: 	/* FALLTHROUGH */
  861: 
  862:     case 0x06461095:	/* CMD 646 ATA controller */
  863: 	if (wdmamode >= 2 && apiomode >= 4) {
  864: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  865: 				ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
  866: 	    if (bootverbose)
  867: 		ata_prtdev(atadev, "%s setting WDMA2 on CMD chip\n",
  868: 			   error ? "failed" : "success");
  869: 	    if (!error) {
  870: 		int32_t offset = (devno < 3) ? (devno << 1) : 7;
  871: 
  872: 		pci_write_config(parent, 0x54 + offset, 0x3f, 1);
  873: 		ata_dmacreate(atadev, apiomode, ATA_WDMA2);
  874: 		return;
  875: 	    }
  876: 	}
  877: 	/* we could set PIO mode timings, but we assume the BIOS did that */
  878: 	break;
  879: 
  880:     case 0xc6931080:	/* Cypress 82c693 ATA controller */
  881: 	if (wdmamode >= 2 && apiomode >= 4) {
  882: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  883: 				ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
  884: 	    if (bootverbose)
  885: 		ata_prtdev(atadev, "%s setting WDMA2 on Cypress chip\n",
  886: 			   error ? "failed" : "success");
  887: 	    if (!error) {
  888: 		pci_write_config(atadev->channel->dev,
  889: 				channel ? 0x4e:0x4c, 0x2020, 2);
  890: 		ata_dmacreate(atadev, apiomode, ATA_WDMA2);
  891: 		return;
  892: 	    }
  893: 	}
  894: 	/* we could set PIO mode timings, but we assume the BIOS did that */
  895: 	break;
  896: 
  897:     case 0x01021078:	/* Cyrix 5530 ATA33 controller */
  898: 	atadev->channel->alignment = 0xf;	/* DMA engine requires 16 byte alignment */
  899: 	if (udmamode >= 2) {
  900: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  901: 				ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
  902: 	    if (bootverbose)
  903: 		ata_prtdev(atadev, "%s setting UDMA2 on Cyrix chip\n",
  904: 			   (error) ? "failed" : "success");
  905: 	    if (!error) {
  906: 		cyrix_timing(atadev, devno, ATA_UDMA2);
  907: 		ata_dmacreate(atadev, apiomode, ATA_UDMA2);
  908: 		return;
  909: 	    }
  910: 	}
  911: 	if (wdmamode >= 2 && apiomode >= 4) {
  912: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  913: 				ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
  914: 	    if (bootverbose)
  915: 		ata_prtdev(atadev, "%s setting WDMA2 on Cyrix chip\n",
  916: 			   (error) ? "failed" : "success");
  917: 	    if (!error) {
  918: 		cyrix_timing(atadev, devno, ATA_WDMA2);
  919: 		ata_dmacreate(atadev, apiomode, ATA_WDMA2);
  920: 		return;
  921: 	    }
  922: 	}
  923: 	error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  924: 			    ATA_PIO0 + apiomode, ATA_C_F_SETXFER,
  925: 			    ATA_WAIT_READY);
  926: 	if (bootverbose)
  927: 	    ata_prtdev(atadev, "%s setting %s on Cyrix chip\n",
  928: 		       (error) ? "failed" : "success",
  929: 		       ata_mode2str(ATA_PIO0 + apiomode));
  930: 	cyrix_timing(atadev, devno, ATA_PIO0 + apiomode);
  931: 	atadev->mode = ATA_PIO0 + apiomode;
  932: 	return;
  933: 
  934: #if !defined(NO_ATANG)
  935:     case 0x02131166:	/* ServerWorks CSB6 ATA 100 controller (chan 0+1) */
  936: #endif
  937:     case 0x02121166:	/* ServerWorks CSB5 ATA66/100 controller */
  938: #if !defined(NO_ATANG)
  939: 	if (udmamode >= 5 && (chiptype == 0x02131166 ||
  940: 			      (chiptype == 0x02121166 &&
  941: 			      chiprev >= 0x92))) {
  942: #else
  943: 	if (udmamode >= 5 && chiprev >= 0x92) {
  944: #endif
  945: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  946: 				ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
  947: 	    if (bootverbose)
  948: 		ata_prtdev(atadev, "%s setting UDMA5 on ServerWorks chip\n",
  949: 			   (error) ? "failed" : "success");
  950: 	    if (!error) {
  951: 		u_int16_t reg56;
  952: 
  953: 		pci_write_config(parent, 0x54, 
  954: 				 pci_read_config(parent, 0x54, 1) |
  955: 				 (0x01 << devno), 1);
  956: 		reg56 = pci_read_config(parent, 0x56, 2);
  957: 		reg56 &= ~(0xf << (devno * 4));
  958: 		reg56 |= (0x5 << (devno * 4));
  959: 		pci_write_config(parent, 0x56, reg56, 2);
  960: 		ata_dmacreate(atadev, apiomode, ATA_UDMA5);
  961: 		return;
  962: 	    }
  963: 	}
  964: #if !defined(NO_ATANG)
  965: 	/* FALLTHROUGH */
  966:     case 0x02171166:	/* Server Works CSB6 ATA 66 controller chan 2 */
  967: #endif
  968: 	if (udmamode >= 4) {
  969: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  970: 				ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
  971: 	    if (bootverbose)
  972: 		ata_prtdev(atadev, "%s setting UDMA4 on ServerWorks chip\n",
  973: 			   (error) ? "failed" : "success");
  974: 	    if (!error) {
  975: 		u_int16_t reg56;
  976: 
  977: 		pci_write_config(parent, 0x54, 
  978: 				 pci_read_config(parent, 0x54, 1) |
  979: 				 (0x01 << devno), 1);
  980: 		reg56 = pci_read_config(parent, 0x56, 2);
  981: 		reg56 &= ~(0xf << (devno * 4));
  982: 		reg56 |= (0x4 << (devno * 4));
  983: 		pci_write_config(parent, 0x56, reg56, 2);
  984: 		ata_dmacreate(atadev, apiomode, ATA_UDMA4);
  985: 		return;
  986: 	    }
  987: 	}
  988: 	/* FALLTHROUGH */
  989: 
  990:     case 0x02111166:	/* ServerWorks ROSB4 ATA33 controller */
  991: 	if (udmamode >= 2) {
  992: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
  993: 				ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
  994: 	    if (bootverbose)
  995: 		ata_prtdev(atadev, "%s setting UDMA2 on ServerWorks chip\n",
  996: 			   (error) ? "failed" : "success");
  997: 	    if (!error) {
  998: 		u_int16_t reg56;
  999: 
 1000: 		pci_write_config(parent, 0x54, 
 1001: 				 pci_read_config(parent, 0x54, 1) |
 1002: 				 (0x01 << devno), 1);
 1003: 		reg56 = pci_read_config(parent, 0x56, 2);
 1004: 		reg56 &= ~(0xf << (devno * 4));
 1005: 		reg56 |= (0x2 << (devno * 4));
 1006: 		pci_write_config(parent, 0x56, reg56, 2);
 1007: 		ata_dmacreate(atadev, apiomode, ATA_UDMA2);
 1008: 		return;
 1009: 	    }
 1010: 	}
 1011: 	if (wdmamode >= 2 && apiomode >= 4) {
 1012: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
 1013: 				ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
 1014: 	    if (bootverbose)
 1015: 		ata_prtdev(atadev, "%s setting WDMA2 on ServerWorks chip\n",
 1016: 			   (error) ? "failed" : "success");
 1017: 	    if (!error) {
 1018: 		int offset = devno ^ 0x01; /* (chan*2) + (dev==ATA_MASTER)*/
 1019: 		int word44 = pci_read_config(parent, 0x44, 4);
 1020: 
 1021: 		pci_write_config(parent, 0x54,
 1022: 				 pci_read_config(parent, 0x54, 1) &
 1023: 				 ~(0x01 << devno), 1);
 1024: 		word44 &= ~(0xff << (offset << 8));
 1025: 		word44 |= (0x20 << (offset << 8));
 1026: 		pci_write_config(parent, 0x44, 0x20, 4);
 1027: 		ata_dmacreate(atadev, apiomode, ATA_UDMA2);
 1028: 		return;
 1029: 	    }
 1030: 	}
 1031: 	/* we could set PIO mode timings, but we assume the BIOS did that */
 1032: 	break;
 1033: 
 1034:     case 0x4d69105a:	/* Promise TX2 ATA133 controllers */
 1035:     case 0x5275105a:	/* Promise TX2 ATA133 controllers */
 1036:     case 0x6269105a:	/* Promise TX2 ATA133 controllers */
 1037:     case 0x7275105a:	/* Promise TX2 ATA133 controllers */
 1038: 	ATA_OUTB(atadev->channel->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
 1039: 	if (udmamode >= 6 &&
 1040: 	    !(ATA_INB(atadev->channel->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) {
 1041: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
 1042: 				ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY);
 1043: 	    if (bootverbose)
 1044: 		ata_prtdev(atadev, "%s setting UDMA6 on Promise chip\n",
 1045: 			   (error) ? "failed" : "success");
 1046: 	    if (!error) {
 1047: 		ata_dmacreate(atadev, apiomode, ATA_UDMA6);
 1048: 		return;
 1049: 	    }
 1050: 	}
 1051: 	/* FALLTHROUGH */
 1052: 
 1053:     case 0x4d68105a:	/* Promise TX2 ATA100 controllers */
 1054:     case 0x6268105a:	/* Promise TX2 ATA100 controllers */
 1055: 	ATA_OUTB(atadev->channel->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
 1056: 	if (udmamode >= 5 && 
 1057: 	    !(ATA_INB(atadev->channel->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) {
 1058: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
 1059: 				ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
 1060: 	    if (bootverbose)
 1061: 		ata_prtdev(atadev, "%s setting UDMA5 on Promise chip\n",
 1062: 			   (error) ? "failed" : "success");
 1063: 	    if (!error) {
 1064: 		ata_dmacreate(atadev, apiomode, ATA_UDMA5);
 1065: 		return;
 1066: 	    }
 1067: 	}
 1068: 	ATA_OUTB(atadev->channel->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
 1069: 	if (udmamode >= 4 && 
 1070: 	    !(ATA_INB(atadev->channel->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) {
 1071: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
 1072: 				ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
 1073: 	    if (bootverbose)
 1074: 		ata_prtdev(atadev, "%s setting UDMA4 on Promise chip\n",
 1075: 			   (error) ? "failed" : "success");
 1076: 	    if (!error) {
 1077: 		ata_dmacreate(atadev, apiomode, ATA_UDMA4);
 1078: 		return;
 1079: 	    }
 1080: 	}
 1081: 	if (udmamode >= 2) {
 1082: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
 1083: 				ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
 1084: 	    if (bootverbose)
 1085: 		ata_prtdev(atadev, "%s setting UDMA on Promise chip\n",
 1086: 			   (error) ? "failed" : "success");
 1087: 	    if (!error) {
 1088: 		ata_dmacreate(atadev, apiomode, ATA_UDMA2);
 1089: 		return;
 1090: 	    }
 1091: 	}
 1092: 	if (wdmamode >= 2 && apiomode >= 4) {
 1093: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
 1094: 				ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
 1095: 	    if (bootverbose)
 1096: 		ata_prtdev(atadev, "%s setting WDMA2 on Promise chip\n",
 1097: 			   (error) ? "failed" : "success");
 1098: 	    if (!error) {
 1099: 		ata_dmacreate(atadev, apiomode, ATA_WDMA2);
 1100: 		return;
 1101: 	    }
 1102: 	}
 1103: 	break;
 1104: 
 1105:     case 0x0d30105a:	/* Promise OEM ATA100 controllers */
 1106:     case 0x4d30105a:	/* Promise Ultra/FastTrak 100 controllers */
 1107: 	if (!ATAPI_DEVICE(atadev) && udmamode >= 5 && 
 1108: 	    !(pci_read_config(parent, 0x50, 2)&(channel ? 1<<11 : 1<<10))){
 1109: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
 1110: 				ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
 1111: 	    if (bootverbose)
 1112: 		ata_prtdev(atadev, "%s setting UDMA5 on Promise chip\n",
 1113: 			   (error) ? "failed" : "success");
 1114: 	    if (!error) {
 1115: 		promise_timing(atadev, devno, ATA_UDMA5);
 1116: 		ata_dmacreate(atadev, apiomode, ATA_UDMA5);
 1117: 		return;
 1118: 	    }
 1119: 	}
 1120: 	/* FALLTHROUGH */
 1121: 
 1122:     case 0x0d38105a:	/* Promise FastTrak 66 controllers */
 1123:     case 0x4d38105a:	/* Promise Ultra/FastTrak 66 controllers */
 1124: 	if (!ATAPI_DEVICE(atadev) && udmamode >= 4 && 
 1125: 	    !(pci_read_config(parent, 0x50, 2)&(channel ? 1<<11 : 1<<10))){
 1126: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
 1127: 				ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
 1128: 	    if (bootverbose)
 1129: 		ata_prtdev(atadev, "%s setting UDMA4 on Promise chip\n",
 1130: 			   (error) ? "failed" : "success");
 1131: 	    if (!error) {
 1132: 		promise_timing(atadev, devno, ATA_UDMA4);
 1133: 		ata_dmacreate(atadev, apiomode, ATA_UDMA4);
 1134: 		return;
 1135: 	    }
 1136: 	}
 1137: 	/* FALLTHROUGH */
 1138: 
 1139:     case 0x4d33105a:	/* Promise Ultra/FastTrak 33 controllers */
 1140: 	if (!ATAPI_DEVICE(atadev) && udmamode >= 2) {
 1141: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
 1142: 				ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
 1143: 	    if (bootverbose)
 1144: 		ata_prtdev(atadev, "%s setting UDMA2 on Promise chip\n",
 1145: 			   (error) ? "failed" : "success");
 1146: 	    if (!error) {
 1147: 		promise_timing(atadev, devno, ATA_UDMA2);
 1148: 		ata_dmacreate(atadev, apiomode, ATA_UDMA2);
 1149: 		return;
 1150: 	    }
 1151: 	}
 1152: 	if (!ATAPI_DEVICE(atadev) && wdmamode >= 2 && apiomode >= 4) {
 1153: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
 1154: 				ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
 1155: 	    if (bootverbose)
 1156: 		ata_prtdev(atadev, "%s setting WDMA2 on Promise chip\n",
 1157: 			   (error) ? "failed" : "success");
 1158: 	    if (!error) {
 1159: 		promise_timing(atadev, devno, ATA_WDMA2);
 1160: 		ata_dmacreate(atadev, apiomode, ATA_WDMA2);
 1161: 		return;
 1162: 	    }
 1163: 	}
 1164: 	error = ata_command(atadev, ATA_C_SETFEATURES, 0,
 1165: 			    ATA_PIO0 + apiomode, 
 1166: 			    ATA_C_F_SETXFER, ATA_WAIT_READY);
 1167: 	if (bootverbose)
 1168: 	    ata_prtdev(atadev, "%s setting PIO%d on Promise chip\n",
 1169: 		       (error) ? "failed" : "success",
 1170: 		       (apiomode >= 0) ? apiomode : 0);
 1171: 	promise_timing(atadev, devno, ATA_PIO0 + apiomode);
 1172: 	atadev->mode = ATA_PIO0 + apiomode;
 1173: 	return;
 1174:     
 1175:     case 0x00041103:	/* HighPoint HPT366/368/370/372 controllers */
 1176:     case 0x00051103:	/* HighPoint HPT372 controllers */
 1177:     case 0x00081103:	/* HighPoint HPT374 controllers */
 1178: 	if (!ATAPI_DEVICE(atadev) && udmamode >= 6 && hpt_cable80(atadev) &&
 1179: 	    ((chiptype == 0x00041103 && chiprev >= 0x05) ||
 1180: 	     (chiptype == 0x00051103 && chiprev >= 0x01) ||
 1181: 	     (chiptype == 0x00081103 && chiprev >= 0x07))) {
 1182: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
 1183: 				ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY);
 1184: 	    if (bootverbose)
 1185: 		ata_prtdev(atadev, "%s setting UDMA6 on HighPoint chip\n",
 1186: 			   (error) ? "failed" : "success");
 1187: 	    if (!error) {
 1188: 		hpt_timing(atadev, devno, ATA_UDMA6);
 1189: 		ata_dmacreate(atadev, apiomode, ATA_UDMA6);
 1190: 		return;
 1191: 	    }
 1192: 	}
 1193: 	if (!ATAPI_DEVICE(atadev) && udmamode >= 5 && hpt_cable80(atadev) &&
 1194: 	    ((chiptype == 0x00041103 && chiprev >= 0x03) ||
 1195: 	     (chiptype == 0x00051103 && chiprev >= 0x01) ||
 1196: 	     (chiptype == 0x00081103 && chiprev >= 0x07))) {
 1197: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
 1198: 				ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
 1199: 	    if (bootverbose)
 1200: 		ata_prtdev(atadev, "%s setting UDMA5 on HighPoint chip\n",
 1201: 			   (error) ? "failed" : "success");
 1202: 	    if (!error) {
 1203: 		hpt_timing(atadev, devno, ATA_UDMA5);
 1204: 		ata_dmacreate(atadev, apiomode, ATA_UDMA5);
 1205: 		return;
 1206: 	    }
 1207: 	}
 1208: 	if (!ATAPI_DEVICE(atadev) && udmamode >= 4 && hpt_cable80(atadev)) {
 1209: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
 1210: 				ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
 1211: 	    if (bootverbose)
 1212: 		ata_prtdev(atadev, "%s setting UDMA4 on HighPoint chip\n",
 1213: 			   (error) ? "failed" : "success");
 1214: 	    if (!error) {
 1215: 		hpt_timing(atadev, devno, ATA_UDMA4);
 1216: 		ata_dmacreate(atadev, apiomode, ATA_UDMA4);
 1217: 		return;
 1218: 	    }
 1219: 	}
 1220: 	if (!ATAPI_DEVICE(atadev) && udmamode >= 2) {
 1221: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
 1222: 				ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
 1223: 	    if (bootverbose)
 1224: 		ata_prtdev(atadev, "%s setting UDMA2 on HighPoint chip\n",
 1225: 			   (error) ? "failed" : "success");
 1226: 	    if (!error) {
 1227: 		hpt_timing(atadev, devno, ATA_UDMA2);
 1228: 		ata_dmacreate(atadev, apiomode, ATA_UDMA2);
 1229: 		return;
 1230: 	    }
 1231: 	}
 1232: 	if (!ATAPI_DEVICE(atadev) && wdmamode >= 2 && apiomode >= 4) {
 1233: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
 1234: 				ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
 1235: 	    if (bootverbose)
 1236: 		ata_prtdev(atadev, "%s setting WDMA2 on HighPoint chip\n",
 1237: 			   (error) ? "failed" : "success");
 1238: 	    if (!error) {
 1239: 		hpt_timing(atadev, devno, ATA_WDMA2);
 1240: 		ata_dmacreate(atadev, apiomode, ATA_WDMA2);
 1241: 		return;
 1242: 	    }
 1243: 	}
 1244: 	error = ata_command(atadev, ATA_C_SETFEATURES, 0,
 1245: 			    ATA_PIO0 + apiomode, 
 1246: 			    ATA_C_F_SETXFER, ATA_WAIT_READY);
 1247: 	if (bootverbose)
 1248: 	    ata_prtdev(atadev, "%s setting PIO%d on HighPoint chip\n",
 1249: 		       (error) ? "failed" : "success",
 1250: 		       (apiomode >= 0) ? apiomode : 0);
 1251: 	hpt_timing(atadev, devno, ATA_PIO0 + apiomode);
 1252: 	atadev->mode = ATA_PIO0 + apiomode;
 1253: 	return;
 1254: 
 1255:     case 0x000116ca:	/* Cenatek Rocket Drive controller */
 1256: 	if (wdmamode >= 0 &&
 1257: 	    (ATA_INB(atadev->channel->r_bmio, ATA_BMSTAT_PORT) & 
 1258: 	     (device ? ATA_BMSTAT_DMA_SLAVE : ATA_BMSTAT_DMA_MASTER)))
 1259: 	    ata_dmacreate(atadev, apiomode, ATA_DMA);
 1260: 	else
 1261: 	    atadev->mode = ATA_PIO;
 1262: 	return;
 1263: 
 1264:     default:		/* unknown controller chip */
 1265: 	/* better not try generic DMA on ATAPI devices it almost never works */
 1266: 	if (ATAPI_DEVICE(atadev))
 1267: 	    break;
 1268: 
 1269: 	/* if controller says its setup for DMA take the easy way out */
 1270: 	/* the downside is we dont know what DMA mode we are in */
 1271: 	if ((udmamode >= 0 || wdmamode >= 2) &&
 1272: 	    (ATA_INB(atadev->channel->r_bmio, ATA_BMSTAT_PORT) &
 1273: 	     (device ? ATA_BMSTAT_DMA_SLAVE : ATA_BMSTAT_DMA_MASTER))) {
 1274: 	    ata_dmacreate(atadev, apiomode, ATA_DMA);
 1275: 	    return;
 1276: 	}
 1277: 
 1278: 	/* well, we have no support for this, but try anyways */
 1279: 	if ((wdmamode >= 2 && apiomode >= 4) && atadev->channel->r_bmio) {
 1280: 	    error = ata_command(atadev, ATA_C_SETFEATURES, 0,
 1281: 				ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
 1282: 	    if (bootverbose)
 1283: 		ata_prtdev(atadev, "%s setting WDMA2 on generic chip\n",
 1284: 			   (error) ? "failed" : "success");
 1285: 	    if (!error) {
 1286: 		ata_dmacreate(atadev, apiomode, ATA_WDMA2);
 1287: 		return;
 1288: 	    }
 1289: 	}
 1290:     }
 1291:     error = ata_command(atadev, ATA_C_SETFEATURES, 0, ATA_PIO0 + apiomode,
 1292: 			ATA_C_F_SETXFER, ATA_WAIT_READY);
 1293:     if (bootverbose)
 1294: 	ata_prtdev(atadev, "%s setting PIO%d on generic chip\n",
 1295: 		   (error) ? "failed" : "success", apiomode < 0 ? 0 : apiomode);
 1296:     if (!error)
 1297: 	atadev->mode = ATA_PIO0 + apiomode;
 1298:     else {
 1299: 	if (bootverbose)
 1300: 	    ata_prtdev(atadev, "using PIO mode set by BIOS\n");
 1301: 	atadev->mode = ATA_PIO;
 1302:     }
 1303: }
 1304: 
 1305: int
 1306: ata_dmasetup(struct ata_device *atadev, caddr_t data, int32_t count)
 1307: {
 1308:     struct ata_channel *ch = atadev->channel;
 1309:     struct ata_dmastate *ds = &atadev->dmastate;
 1310:     u_int32_t dma_count, dma_base;
 1311:     int i = 0;
 1312: 
 1313:     if (((uintptr_t)data & ch->alignment) || (count & ch->alignment)) {
 1314: 	ata_prtdev(atadev, "non aligned DMA transfer attempted\n");
 1315: 	return -1;
 1316:     }
 1317: 
 1318:     if (!count) {
 1319: 	ata_prtdev(atadev, "zero length DMA transfer attempted\n");
 1320: 	return -1;
 1321:     }
 1322:     
 1323:     dma_base = vtophys(data);
 1324:     dma_count = imin(count, (PAGE_SIZE - ((uintptr_t)data & PAGE_MASK)));
 1325:     data += dma_count;
 1326:     count -= dma_count;
 1327: 
 1328:     while (count) {
 1329: 	ds->dmatab[i].base = dma_base;
 1330: 	ds->dmatab[i].count = (dma_count & 0xffff);
 1331: 	i++; 
 1332: 	if (i >= ATA_DMA_ENTRIES) {
 1333: 	    ata_prtdev(atadev, "too many segments in DMA table\n");
 1334: 	    return -1;
 1335: 	}
 1336: 	dma_base = vtophys(data);
 1337: 	dma_count = imin(count, PAGE_SIZE);
 1338: 	data += imin(count, PAGE_SIZE);
 1339: 	count -= imin(count, PAGE_SIZE);
 1340:     }
 1341:     ds->dmatab[i].base = dma_base;
 1342:     ds->dmatab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT;
 1343:     return 0;
 1344: }
 1345: 
 1346: int
 1347: ata_dmastart(struct ata_device *atadev, caddr_t data, int32_t count, int dir)
 1348: {
 1349:     struct ata_channel *ch = atadev->channel;
 1350:     struct ata_dmastate *ds = &atadev->dmastate;
 1351: 
 1352:     ch->flags |= ATA_DMA_ACTIVE;
 1353:     ATA_OUTL(ch->r_bmio, ATA_BMDTP_PORT, vtophys(ds->dmatab));
 1354:     ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT, dir ? ATA_BMCMD_WRITE_READ : 0);
 1355:     ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, 
 1356: 	 (ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) | 
 1357: 	  (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR)));
 1358:     ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT, 
 1359: 	 ATA_INB(ch->r_bmio, ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP);
 1360:     return(0);
 1361: }
 1362: 
 1363: int
 1364: ata_dmadone(struct ata_device *atadev)
 1365: {
 1366:     struct ata_channel *ch;
 1367:     struct ata_dmastate *ds;
 1368:     int error;
 1369: 
 1370:     ch = atadev->channel;
 1371:     ds = &atadev->dmastate;
 1372: 
 1373:     ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT, 
 1374: 		ATA_INB(ch->r_bmio, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
 1375:     error = ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT);
 1376:     ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, 
 1377: 	     error | ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR);
 1378:     ch->flags &= ~ATA_DMA_ACTIVE;
 1379:     ds->flags = 0;
 1380:     return error & ATA_BMSTAT_MASK;
 1381: }
 1382: 
 1383: int
 1384: ata_dmastatus(struct ata_channel *ch)
 1385: {
 1386:     return ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
 1387: }
 1388: 
 1389: static void
 1390: cyrix_timing(struct ata_device *atadev, int devno, int mode)
 1391: {
 1392:     u_int32_t reg20 = 0x0000e132;
 1393:     u_int32_t reg24 = 0x00017771;
 1394: 
 1395:     switch (mode) {
 1396:     case ATA_PIO0:	reg20 = 0x0000e132; break;
 1397:     case ATA_PIO1:	reg20 = 0x00018121; break;
 1398:     case ATA_PIO2:	reg20 = 0x00024020; break;
 1399:     case ATA_PIO3:	reg20 = 0x00032010; break;
 1400:     case ATA_PIO4:	reg20 = 0x00040010; break;
 1401:     case ATA_WDMA2:	reg24 = 0x00002020; break;
 1402:     case ATA_UDMA2:	reg24 = 0x00911030; break;
 1403:     }
 1404:     ATA_OUTL(atadev->channel->r_bmio, (devno << 3) + 0x20, reg20);
 1405:     ATA_OUTL(atadev->channel->r_bmio, (devno << 3) + 0x24, reg24);
 1406: }
 1407: 
 1408: static void
 1409: promise_timing(struct ata_device *atadev, int devno, int mode)
 1410: {
 1411:     u_int32_t timing = 0;
 1412:     /* XXX: Endianess */
 1413:     struct promise_timing {
 1414: 	u_int8_t  pa:4;
 1415: 	u_int8_t  prefetch:1;
 1416: 	u_int8_t  iordy:1;
 1417: 	u_int8_t  errdy:1;
 1418: 	u_int8_t  syncin:1;
 1419: 	u_int8_t  pb:5;
 1420: 	u_int8_t  mb:3;
 1421: 	u_int8_t  mc:4;
 1422: 	u_int8_t  dmaw:1;
 1423: 	u_int8_t  dmar:1;
 1424: 	u_int8_t  iordyp:1;
 1425: 	u_int8_t  dmarqp:1;
 1426: 	u_int8_t  reserved:8;
 1427:     } *t = (struct promise_timing*)&timing;
 1428: 
 1429:     t->iordy = 1; t->iordyp = 1;
 1430:     if (mode >= ATA_DMA) {
 1431: 	t->prefetch = 1; t->errdy = 1; t->syncin = 1;
 1432:     }
 1433: 
 1434:     switch (atadev->channel->chiptype) {
 1435:     case 0x4d33105a:  /* Promise Ultra/Fasttrak 33 */
 1436: 	switch (mode) {
 1437: 	default:
 1438: 	case ATA_PIO0:	t->pa =	 9; t->pb = 19; t->mb = 7; t->mc = 15; break;
 1439: 	case ATA_PIO1:	t->pa =	 5; t->pb = 12; t->mb = 7; t->mc = 15; break;
 1440: 	case ATA_PIO2:	t->pa =	 3; t->pb =  8; t->mb = 7; t->mc = 15; break;
 1441: 	case ATA_PIO3:	t->pa =	 2; t->pb =  6; t->mb = 7; t->mc = 15; break;
 1442: 	case ATA_PIO4:	t->pa =	 1; t->pb =  4; t->mb = 7; t->mc = 15; break;
 1443: 	case ATA_WDMA2: t->pa =	 3; t->pb =  7; t->mb = 3; t->mc =  3; break;
 1444: 	case ATA_UDMA2: t->pa =	 3; t->pb =  7; t->mb = 1; t->mc =  1; break;
 1445: 	}
 1446: 	break;
 1447: 
 1448:     case 0x4d38105a:  /* Promise Ultra/Fasttrak 66 */
 1449:     case 0x4d30105a:  /* Promise Ultra/Fasttrak 100 */
 1450:     case 0x0d30105a:  /* Promise OEM ATA 100 */
 1451: 	switch (mode) {
 1452: 	default:
 1453: 	case ATA_PIO0:	t->pa = 15; t->pb = 31; t->mb = 7; t->mc = 15; break;
 1454: 	case ATA_PIO1:	t->pa = 10; t->pb = 24; t->mb = 7; t->mc = 15; break;
 1455: 	case ATA_PIO2:	t->pa =	 6; t->pb = 16; t->mb = 7; t->mc = 15; break;
 1456: 	case ATA_PIO3:	t->pa =	 4; t->pb = 12; t->mb = 7; t->mc = 15; break;
 1457: 	case ATA_PIO4:	t->pa =	 2; t->pb =  8; t->mb = 7; t->mc = 15; break;
 1458: 	case ATA_WDMA2: t->pa =	 6; t->pb = 14; t->mb = 6; t->mc =  6; break;
 1459: 	case ATA_UDMA2: t->pa =	 6; t->pb = 14; t->mb = 2; t->mc =  2; break;
 1460: 	case ATA_UDMA4: t->pa =	 3; t->pb =  7; t->mb = 1; t->mc =  1; break;
 1461: 	case ATA_UDMA5: t->pa =	 3; t->pb =  7; t->mb = 1; t->mc =  1; break;
 1462: 	}
 1463: 	break;
 1464:     }
 1465:     pci_write_config(device_get_parent(atadev->channel->dev), 
 1466: 		    0x60 + (devno<<2), timing, 4);
 1467: }
 1468: 
 1469: static void
 1470: hpt_timing(struct ata_device *atadev, int devno, int mode)
 1471: {
 1472:     device_t parent = device_get_parent(atadev->channel->dev);
 1473:     u_int32_t chiptype = atadev->channel->chiptype;
 1474:     int chiprev = pci_get_revid(parent);
 1475:     u_int32_t timing;
 1476: 
 1477:     if (chiptype == 0x00081103 && chiprev >= 0x07) {
 1478: 	switch (mode) {						/* HPT374 */
 1479: 	case ATA_PIO0:	timing = 0x0ac1f48a; break;
 1480: 	case ATA_PIO1:	timing = 0x0ac1f465; break;
 1481: 	case ATA_PIO2:	timing = 0x0a81f454; break;
 1482: 	case ATA_PIO3:	timing = 0x0a81f443; break;
 1483: 	case ATA_PIO4:	timing = 0x0a81f442; break;
 1484: 	case ATA_WDMA2: timing = 0x22808242; break;
 1485: 	case ATA_UDMA2: timing = 0x120c8242; break;
 1486: 	case ATA_UDMA4: timing = 0x12ac8242; break;
 1487: 	case ATA_UDMA5: timing = 0x12848242; break;
 1488: 	case ATA_UDMA6: timing = 0x12808242; break;
 1489: 	default:	timing = 0x0d029d5e;
 1490: 	}
 1491:     }
 1492:     else if ((chiptype == 0x00041103 && chiprev >= 0x05) ||
 1493: 	     (chiptype == 0x00051103 && chiprev >= 0x01)) {
 1494: 	switch (mode) {						/* HPT372 */
 1495: 	case ATA_PIO0:	timing = 0x0d029d5e; break;
 1496: 	case ATA_PIO1:	timing = 0x0d029d26; break;
 1497: 	case ATA_PIO2:	timing = 0x0c829ca6; break;
 1498: 	case ATA_PIO3:	timing = 0x0c829c84; break;
 1499: 	case ATA_PIO4:	timing = 0x0c829c62; break;
 1500: 	case ATA_WDMA2: timing = 0x2c829262; break;
 1501: 	case ATA_UDMA2: timing = 0x1c91dc62; break;
 1502: 	case ATA_UDMA4: timing = 0x1c8ddc62; break;
 1503: 	case ATA_UDMA5: timing = 0x1c6ddc62; break;
 1504: 	case ATA_UDMA6: timing = 0x1c81dc62; break;
 1505: 	default:	timing = 0x0d029d5e;
 1506: 	}
 1507:     }
 1508:     else if (chiptype == 0x00041103 && chiprev >= 0x03) {
 1509: 	switch (mode) {						/* HPT370 */
 1510: 	case ATA_PIO0:	timing = 0x06914e57; break;
 1511: 	case ATA_PIO1:	timing = 0x06914e43; break;
 1512: 	case ATA_PIO2:	timing = 0x06514e33; break;
 1513: 	case ATA_PIO3:	timing = 0x06514e22; break;
 1514: 	case ATA_PIO4:	timing = 0x06514e21; break;
 1515: 	case ATA_WDMA2: timing = 0x26514e21; break;
 1516: 	case ATA_UDMA2: timing = 0x16494e31; break;
 1517: 	case ATA_UDMA4: timing = 0x16454e31; break;
 1518: 	case ATA_UDMA5: timing = 0x16454e31; break;
 1519: 	default:	timing = 0x06514e57;
 1520: 	}
 1521: 	pci_write_config(parent, 0x40 + (devno << 2) , timing, 4);
 1522:     }
 1523:     else {							/* HPT36[68] */
 1524: 	switch (pci_read_config(parent, 0x41 + (devno << 2), 1)) {
 1525: 	case 0x85:	/* 25Mhz */
 1526: 	    switch (mode) {
 1527: 	    case ATA_PIO0:	timing = 0x40d08585; break;
 1528: 	    case ATA_PIO1:	timing = 0x40d08572; break;
 1529: 	    case ATA_PIO2:	timing = 0x40ca8542; break;
 1530: 	    case ATA_PIO3:	timing = 0x40ca8532; break;
 1531: 	    case ATA_PIO4:	timing = 0x40ca8521; break;
 1532: 	    case ATA_WDMA2:	timing = 0x20ca8521; break;
 1533: 	    case ATA_UDMA2:	timing = 0x10cf8521; break;
 1534: 	    case ATA_UDMA4:	timing = 0x10c98521; break;
 1535: 	    default:		timing = 0x01208585;
 1536: 	    }
 1537: 	    break;
 1538: 	default:
 1539: 	case 0xa7:	/* 33MHz */
 1540: 	    switch (mode) {
 1541: 	    case ATA_PIO0:	timing = 0x40d0a7aa; break;
 1542: 	    case ATA_PIO1:	timing = 0x40d0a7a3; break;
 1543: 	    case ATA_PIO2:	timing = 0x40d0a753; break;
 1544: 	    case ATA_PIO3:	timing = 0x40c8a742; break;
 1545: 	    case ATA_PIO4:	timing = 0x40c8a731; break;
 1546: 	    case ATA_WDMA2:	timing = 0x20c8a731; break;
 1547: 	    case ATA_UDMA2:	timing = 0x10caa731; break;
 1548: 	    case ATA_UDMA4:	timing = 0x10c9a731; break;
 1549: 	    default:		timing = 0x0120a7a7;
 1550: 	    }
 1551: 	    break;
 1552: 	case 0xd9:	/* 40Mhz */
 1553: 	    switch (mode) {
 1554: 	    case ATA_PIO0:	timing = 0x4018d9d9; break;
 1555: 	    case ATA_PIO1:	timing = 0x4010d9c7; break;
 1556: 	    case ATA_PIO2:	timing = 0x4010d997; break;
 1557: 	    case ATA_PIO3:	timing = 0x4010d974; break;
 1558: 	    case ATA_PIO4:	timing = 0x4008d963; break;
 1559: 	    case ATA_WDMA2:	timing = 0x2008d943; break;
 1560: 	    case ATA_UDMA2:	timing = 0x100bd943; break;
 1561: 	    case ATA_UDMA4:	timing = 0x100fd943; break;
 1562: 	    default:		timing = 0x0120d9d9;
 1563: 	    }
 1564: 	}
 1565:     }
 1566:     pci_write_config(parent, 0x40 + (devno << 2) , timing, 4);
 1567: }
 1568: 
 1569: static int
 1570: hpt_cable80(struct ata_device *atadev)
 1571: {
 1572:     device_t parent = device_get_parent(atadev->channel->dev);
 1573:     u_int8_t reg, val, res;
 1574: 
 1575:     if (atadev->channel->chiptype == 0x00081103 && pci_get_function(parent) == 1) {
 1576: 	reg = atadev->channel->unit ? 0x57 : 0x53;
 1577: 	val = pci_read_config(parent, reg, 1);
 1578: 	pci_write_config(parent, reg, val | 0x80, 1);
 1579:     }
 1580:     else {
 1581: 	reg = 0x5b;
 1582: 	val = pci_read_config(parent, reg, 1);
 1583: 	pci_write_config(parent, reg, val & 0xfe, 1);
 1584:     }
 1585:     res = pci_read_config(parent, 0x5a, 1) & (atadev->channel->unit ? 0x01 : 0x02);
 1586:     pci_write_config(parent, reg, val, 1);
 1587:     return !res;
 1588: }