File:  [DragonFly] / src / sys / dev / disk / ata / ata-pci.c
Revision 1.8: download - view: text, annotated - select for diffs
Fri Jan 23 15:35:13 2004 UTC (10 years, 6 months ago) by asmodai
Branches: MAIN
CVS tags: HEAD
Add detection code for the SiS 746 ATA133 controller.
This does not, for all I can quickly see, enable ATA133 on the controller.

    1: /*-
    2:  * Copyright (c) 1998,1999,2000,2001,2002 Søren Schmidt <sos@FreeBSD.org>
    3:  * All rights reserved.
    4:  *
    5:  * Redistribution and use in source and binary forms, with or without
    6:  * modification, are permitted provided that the following conditions
    7:  * are met:
    8:  * 1. Redistributions of source code must retain the above copyright
    9:  *    notice, this list of conditions and the following disclaimer,
   10:  *    without modification, immediately at the beginning of the file.
   11:  * 2. Redistributions in binary form must reproduce the above copyright
   12:  *    notice, this list of conditions and the following disclaimer in the
   13:  *    documentation and/or other materials provided with the distribution.
   14:  * 3. The name of the author may not be used to endorse or promote products
   15:  *    derived from this software without specific prior written permission.
   16:  *
   17:  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   18:  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   19:  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   20:  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   21:  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
   22:  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   23:  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   24:  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   25:  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
   26:  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   27:  *
   28:  * $FreeBSD: src/sys/dev/ata/ata-pci.c,v 1.32.2.15 2003/06/06 13:27:05 fjoe Exp $
   29:  * $DragonFly: src/sys/dev/disk/ata/ata-pci.c,v 1.8 2004/01/23 15:35:13 asmodai Exp $
   30:  */
   31: 
   32: #include <sys/param.h>
   33: #include <sys/systm.h>
   34: #include <sys/kernel.h>
   35: #include <sys/disk.h>
   36: #include <sys/module.h>
   37: #include <sys/bus.h>
   38: #include <sys/buf.h>
   39: #include <sys/malloc.h>
   40: #include <sys/devicestat.h>
   41: #include <sys/sysctl.h>
   42: #include <machine/stdarg.h>
   43: #include <machine/resource.h>
   44: #include <machine/bus.h>
   45: #include <machine/clock.h>
   46: #ifdef __alpha__
   47: #include <machine/md_var.h>
   48: #endif
   49: #include <sys/rman.h>
   50: #include <bus/pci/pcivar.h>
   51: #include <bus/pci/pcireg.h>
   52: #include "ata-all.h"
   53: 
   54: /* device structures */
   55: struct ata_pci_controller {
   56:     struct resource *bmio;
   57:     int bmaddr;
   58:     struct resource *irq;
   59:     int irqcnt;
   60: };
   61: 
   62: /* misc defines */
   63: #define IOMASK			0xfffffffc
   64: #define GRANDPARENT(dev)	device_get_parent(device_get_parent(dev))
   65: #define ATA_MASTERDEV(dev)	((pci_get_progif(dev) & 0x80) && \
   66: 				 (pci_get_progif(dev) & 0x05) != 0x05)
   67: 
   68: int
   69: ata_find_dev(device_t dev, u_int32_t devid, u_int32_t revid)
   70: {
   71:     device_t *children;
   72:     int nchildren, i;
   73: 
   74:     if (device_get_children(device_get_parent(dev), &children, &nchildren))
   75: 	return 0;
   76: 
   77:     for (i = 0; i < nchildren; i++) {
   78: 	if (pci_get_devid(children[i]) == devid &&
   79: 	    pci_get_revid(children[i]) >= revid) {
   80: 	    free(children, M_TEMP);
   81: 	    return 1;
   82: 	}
   83:     }
   84:     free(children, M_TEMP);
   85:     return 0;
   86: }
   87: 
   88: static void
   89: ata_via_southbridge_fixup(device_t dev)
   90: {
   91:     device_t *children;
   92:     int nchildren, i;
   93: 
   94:     if (device_get_children(device_get_parent(dev), &children, &nchildren))
   95: 	return;
   96: 
   97:     for (i = 0; i < nchildren; i++) {
   98: 	if (pci_get_devid(children[i]) == 0x03051106 ||		/* VIA VT8363 */
   99: 	    pci_get_devid(children[i]) == 0x03911106 ||		/* VIA VT8371 */
  100: 	    pci_get_devid(children[i]) == 0x31021106 ||		/* VIA VT8662 */
  101: 	    pci_get_devid(children[i]) == 0x31121106) {		/* VIA VT8361 */
  102: 	    u_int8_t reg76 = pci_read_config(children[i], 0x76, 1);
  103: 
  104: 	    if ((reg76 & 0xf0) != 0xd0) {
  105: 		device_printf(dev,
  106: 		"Correcting VIA config for southbridge data corruption bug\n");
  107: 		pci_write_config(children[i], 0x75, 0x80, 1);
  108: 		pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1);
  109: 	    }
  110: 	    break;
  111: 	}
  112:     }
  113:     free(children, M_TEMP);
  114: }
  115: 
  116: static const char *
  117: ata_pci_match(device_t dev)
  118: {
  119:     if (pci_get_class(dev) != PCIC_STORAGE)
  120: 	return NULL;
  121: 
  122:     switch (pci_get_devid(dev)) {
  123:     /* supported chipsets */
  124:     case 0x12308086:
  125: 	return "Intel PIIX ATA controller";
  126: 
  127:     case 0x70108086:
  128: 	return "Intel PIIX3 ATA controller";
  129: 
  130:     case 0x71118086:
  131:     case 0x71998086:
  132:     case 0x84ca8086:
  133: 	return "Intel PIIX4 ATA33 controller";
  134: 
  135:     case 0x24218086:
  136: 	return "Intel ICH0 ATA33 controller";
  137: 
  138:     case 0x24118086:
  139:     case 0x76018086:
  140: 	return "Intel ICH ATA66 controller";
  141: 
  142:     case 0x244a8086:
  143:     case 0x244b8086:
  144: 	return "Intel ICH2 ATA100 controller";
  145: 
  146:     case 0x248a8086:
  147:     case 0x248b8086:
  148: 	return "Intel ICH3 ATA100 controller";
  149: 
  150:     case 0x24ca8086:
  151:     case 0x24cb8086:
  152: 	return "Intel ICH4 ATA100 controller";
  153: 
  154:     case 0x24db8086:
  155: 	return "Intel ICH5 ATA100 controller";
  156: 
  157:     case 0x522910b9:
  158: 	if (pci_get_revid(dev) >= 0xc4)
  159: 	    return "AcerLabs Aladdin ATA100 controller";
  160: 	else if (pci_get_revid(dev) >= 0xc2)
  161: 	    return "AcerLabs Aladdin ATA66 controller";
  162: 	else if (pci_get_revid(dev) >= 0x20)
  163: 	    return "AcerLabs Aladdin ATA33 controller";
  164: 	else
  165: 	    return "AcerLabs Aladdin ATA controller";
  166: 
  167:     case 0x05711106: 
  168: 	if (ata_find_dev(dev, 0x05861106, 0x02))
  169: 	    return "VIA 82C586 ATA33 controller";
  170: 	if (ata_find_dev(dev, 0x05861106, 0))
  171: 	    return "VIA 82C586 ATA controller";
  172: 	if (ata_find_dev(dev, 0x05961106, 0x12))
  173: 	    return "VIA 82C596 ATA66 controller";
  174: 	if (ata_find_dev(dev, 0x05961106, 0))
  175: 	    return "VIA 82C596 ATA33 controller";
  176: 	if (ata_find_dev(dev, 0x06861106, 0x40))
  177: 	    return "VIA 82C686 ATA100 controller";
  178: 	if (ata_find_dev(dev, 0x06861106, 0x10))
  179: 	    return "VIA 82C686 ATA66 controller";
  180: 	if (ata_find_dev(dev, 0x06861106, 0))
  181: 	    return "VIA 82C686 ATA33 controller";
  182: 	if (ata_find_dev(dev, 0x82311106, 0))
  183: 	    return "VIA 8231 ATA100 controller";
  184: 	if (ata_find_dev(dev, 0x30741106, 0) ||
  185: 	    ata_find_dev(dev, 0x31091106, 0))
  186: 	    return "VIA 8233 ATA100 controller";
  187: 	if (ata_find_dev(dev, 0x31471106, 0))
  188: 	    return "VIA 8233 ATA133 controller";
  189: 	if (ata_find_dev(dev, 0x31771106, 0))
  190: 	    return "VIA 8235 ATA133 controller";
  191: 	return "VIA Apollo ATA controller";
  192: 
  193:     case 0x55131039:
  194: 	if (ata_find_dev(dev, 0x07461039, 0))
  195: 	    return "SiS 5591 ATA133 controller";
  196: 	if (ata_find_dev(dev, 0x06301039, 0x30) ||
  197: 	    ata_find_dev(dev, 0x06331039, 0) ||
  198: 	    ata_find_dev(dev, 0x06351039, 0) ||
  199: 	    ata_find_dev(dev, 0x06401039, 0) ||
  200: 	    ata_find_dev(dev, 0x06451039, 0) ||
  201: 	    ata_find_dev(dev, 0x06461039, 0) ||
  202: 	    ata_find_dev(dev, 0x06481039, 0) ||
  203: 	    ata_find_dev(dev, 0x06501039, 0) ||
  204: 	    ata_find_dev(dev, 0x07301039, 0) ||
  205: 	    ata_find_dev(dev, 0x07331039, 0) ||
  206: 	    ata_find_dev(dev, 0x07351039, 0) ||
  207: 	    ata_find_dev(dev, 0x07401039, 0) ||
  208: 	    ata_find_dev(dev, 0x07451039, 0) ||
  209: 	    ata_find_dev(dev, 0x07501039, 0))
  210: 	    return "SiS 5591 ATA100 controller";
  211: 	else if (ata_find_dev(dev, 0x05301039, 0) ||
  212: 	    ata_find_dev(dev, 0x05401039, 0) ||
  213: 	    ata_find_dev(dev, 0x06201039, 0) ||
  214: 	    ata_find_dev(dev, 0x06301039, 0))
  215: 	    return "SiS 5591 ATA66 controller";
  216: 	else
  217: 	    return "SiS 5591 ATA33 controller";
  218: 
  219:     case 0x06801095:
  220: 	return "SiI 0680 ATA133 controller";
  221: 
  222:     case 0x06491095:
  223: 	return "CMD 649 ATA100 controller";
  224: 
  225:     case 0x06481095:
  226: 	return "CMD 648 ATA66 controller";
  227: 
  228:     case 0x06461095:
  229: 	return "CMD 646 ATA controller";
  230: 
  231:     case 0xc6931080:
  232: 	if (pci_get_subclass(dev) == PCIS_STORAGE_IDE)
  233: 	    return "Cypress 82C693 ATA controller";
  234: 	return NULL;
  235: 
  236:     case 0x01021078:
  237: 	return "Cyrix 5530 ATA33 controller";
  238: 
  239:     case 0x74091022:
  240: 	return "AMD 756 ATA66 controller";
  241: 
  242:     case 0x74111022:
  243: 	return "AMD 766 ATA100 controller";
  244: 
  245:     case 0x74411022:
  246: 	return "AMD 768 ATA100 controller";
  247: 
  248:     case 0x01bc10de:
  249: 	return "NVIDIA nForce ATA100 controller";
  250: 
  251:     case 0x006510de:
  252: 	return "NVIDIA nForce ATA133 controller";
  253: 
  254:     case 0x02111166:
  255: 	return "ServerWorks ROSB4 ATA33 controller";
  256: 
  257:     case 0x02121166:
  258: 	if (pci_get_revid(dev) >= 0x92)
  259: 	    return "ServerWorks CSB5 ATA100 controller";
  260: 	else
  261: 	    return "ServerWorks CSB5 ATA66 controller";
  262: 
  263:     case 0x4d33105a:
  264: 	return "Promise ATA33 controller";
  265: 
  266:     case 0x0d38105a:
  267:     case 0x4d38105a:
  268: 	return "Promise ATA66 controller";
  269: 
  270:     case 0x0d30105a:
  271:     case 0x4d30105a:
  272: 	return "Promise ATA100 controller";
  273: 
  274:     case 0x4d68105a:
  275:     case 0x6268105a: 
  276: 	if (pci_get_devid(GRANDPARENT(dev)) == 0x00221011 &&
  277: 	    pci_get_class(GRANDPARENT(dev)) == PCIC_BRIDGE) {
  278: 	    static long start = 0, end = 0;
  279: 
  280: 	    /* we belive we are on a TX4, now do our (simple) magic */
  281: 	    if (pci_get_slot(dev) == 1) {
  282: 		bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end);
  283: 		return "Promise TX4 ATA100 controller (channel 0+1)";
  284: 	    }
  285: 	    else if (pci_get_slot(dev) == 2 && start && end) {
  286: 		bus_set_resource(dev, SYS_RES_IRQ, 0, start, end);
  287: 		start = end = 0;
  288: 		return "Promise TX4 ATA100 controller (channel 2+3)";
  289: 	    }
  290: 	    else
  291: 		start = end = 0;
  292: 	}
  293: 	return "Promise TX2 ATA100 controller";
  294: 
  295:     case 0x4d69105a:
  296:     case 0x5275105a:
  297:     case 0x6269105a: 
  298:     case 0x7275105a: 
  299: 	return "Promise TX2 ATA133 controller";
  300: 
  301:     case 0x00041103:
  302: 	switch (pci_get_revid(dev)) {
  303: 	case 0x00:
  304: 	case 0x01:
  305: 	    return "HighPoint HPT366 ATA66 controller";
  306: 	case 0x02:
  307: 	    return "HighPoint HPT368 ATA66 controller";
  308: 	case 0x03:
  309: 	case 0x04:
  310: 	    return "HighPoint HPT370 ATA100 controller";
  311: 	case 0x05:
  312: 	    return "HighPoint HPT372 ATA133 controller";
  313: 	}
  314: 	return NULL;
  315: 
  316:     case 0x00051103:
  317: 	switch (pci_get_revid(dev)) {
  318: 	case 0x01:
  319: 	case 0x02:
  320: 	    return "HighPoint HPT372 ATA133 controller";
  321: 	}
  322: 	return NULL;
  323: 
  324:     case 0x00081103:
  325: 	switch (pci_get_revid(dev)) {
  326: 	case 0x07:
  327: 	    return "HighPoint HPT374 ATA133 controller";
  328: 	}
  329: 	return NULL;
  330: 
  331:     case 0x000116ca:
  332: 	return "Cenatek Rocket Drive controller";
  333: 
  334:    /* unsupported but known chipsets, generic DMA only */
  335:     case 0x10001042:
  336:     case 0x10011042:
  337: 	return "RZ 100? ATA controller !WARNING! buggy chip data loss possible";
  338: 
  339:     case 0x06401095:
  340: 	return "CMD 640 ATA controller !WARNING! buggy chip data loss possible";
  341: 
  342:     /* unknown chipsets, try generic DMA if it seems possible */
  343:     default:
  344: 	if (pci_get_class(dev) == PCIC_STORAGE &&
  345: 	    (pci_get_subclass(dev) == PCIS_STORAGE_IDE))
  346: 	    return "Generic PCI ATA controller";
  347:     }
  348:     return NULL;
  349: }
  350: 
  351: static int
  352: ata_pci_probe(device_t dev)
  353: {
  354:     const char *desc = ata_pci_match(dev);
  355:     
  356:     if (desc) {
  357: 	device_set_desc(dev, desc);
  358: 	return 0;
  359:     } 
  360:     else
  361: 	return ENXIO;
  362: }
  363: 
  364: static int
  365: ata_pci_add_child(device_t dev, int unit)
  366: {
  367:     device_t child;
  368: 
  369:     /* check if this is located at one of the std addresses */
  370:     if (ATA_MASTERDEV(dev)) {
  371: 	if (!(child = device_add_child(dev, "ata", unit)))
  372: 	    return ENOMEM;
  373:     }
  374:     else {
  375: 	if (!(child = device_add_child(dev, "ata", 2)))
  376: 	    return ENOMEM;
  377:     }
  378:     return 0;
  379: }
  380: 
  381: static int
  382: ata_pci_attach(device_t dev)
  383: {
  384:     struct ata_pci_controller *controller = device_get_softc(dev);
  385:     u_int8_t class, subclass;
  386:     u_int32_t type, cmd;
  387:     int rid;
  388: 
  389:     /* set up vendor-specific stuff */
  390:     type = pci_get_devid(dev);
  391:     class = pci_get_class(dev);
  392:     subclass = pci_get_subclass(dev);
  393:     cmd = pci_read_config(dev, PCIR_COMMAND, 4);
  394: 
  395:     if (!(cmd & PCIM_CMD_PORTEN)) {
  396: 	device_printf(dev, "ATA channel disabled by BIOS\n");
  397: 	return 0;
  398:     }
  399: 
  400:     /* is busmastering supported ? */
  401:     if ((cmd & (PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN)) == 
  402: 	(PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN)) {
  403: 
  404: 	/* is there a valid port range to connect to ? */
  405: 	rid = 0x20;
  406: 	controller->bmio = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
  407: 					      0, ~0, 1, RF_ACTIVE);
  408: 	if (!controller->bmio)
  409: 	    device_printf(dev, "Busmastering DMA not configured\n");
  410:     }
  411:     else
  412: 	device_printf(dev, "Busmastering DMA not supported\n");
  413: 
  414:     /* do extra chipset specific setups */
  415:     switch (type) {
  416:     case 0x522910b9: /* Aladdin need to activate the ATAPI FIFO */
  417: 	pci_write_config(dev, 0x53, 
  418: 			 (pci_read_config(dev, 0x53, 1) & ~0x01) | 0x02, 1);
  419: 	break;
  420: 
  421:     case 0x4d38105a: /* Promise 66 & 100 (before TX2) need the clock changed */
  422:     case 0x4d30105a:
  423:     case 0x0d30105a:
  424: 	ATA_OUTB(controller->bmio, 0x11, ATA_INB(controller->bmio, 0x11)|0x0a);
  425: 	/* FALLTHROUGH */
  426: 
  427:     case 0x4d33105a: /* Promise (before TX2) need burst mode turned on */
  428: 	ATA_OUTB(controller->bmio, 0x1f, ATA_INB(controller->bmio, 0x1f)|0x01);
  429: 	break;
  430: 
  431:     case 0x00041103:	/* HighPoint HPT366/368/370/372 */
  432: 	if (pci_get_revid(dev) < 2) {	/* HPT 366 */
  433: 	    /* turn off interrupt prediction */
  434: 	    pci_write_config(dev, 0x51, 
  435: 			     (pci_read_config(dev, 0x51, 1) & ~0x80), 1);
  436: 	    break;
  437: 	}
  438: 	if (pci_get_revid(dev) < 5) {   /* HPT368/370 */
  439: 	    /* turn off interrupt prediction */
  440: 	    pci_write_config(dev, 0x51,
  441: 			     (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
  442: 	    pci_write_config(dev, 0x55,
  443: 			     (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
  444: 
  445: 	    /* turn on interrupts */
  446: 	    pci_write_config(dev, 0x5a,
  447: 			     (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
  448: 
  449: 	    /* set clocks etc */
  450: 	    pci_write_config(dev, 0x5b, 0x22, 1);
  451: 	    break;
  452: 	}
  453: 	/* FALLTHROUGH */
  454: 
  455:     case 0x00051103:	/* HighPoint HPT372 */
  456:     case 0x00081103:	/* HighPoint HPT374 */
  457: 	/* turn off interrupt prediction */
  458: 	pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
  459: 	pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
  460: 
  461: 	/* turn on interrupts */
  462: 	pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
  463: 
  464: 	/* set clocks etc */
  465: 	pci_write_config(dev, 0x5b,
  466: 			 (pci_read_config(dev, 0x5b, 1) & 0x01) | 0x20, 1);
  467: 	break;
  468: 
  469:     case 0x05711106: /* VIA 82C586, '596, '686 default setup */
  470: 	/* prepare for ATA-66 on the 82C686a and 82C596b */
  471: 	if ((ata_find_dev(dev, 0x06861106, 0x10) && 
  472: 	     !ata_find_dev(dev, 0x06861106, 0x40)) || 
  473: 	    ata_find_dev(dev, 0x05961106, 0x12))
  474: 	    pci_write_config(dev, 0x50, 0x030b030b, 4);	  
  475: 
  476: 	/* the southbridge might need the data corruption fix */
  477: 	if (ata_find_dev(dev, 0x06861106, 0x40) ||
  478: 	    ata_find_dev(dev, 0x82311106, 0x10))
  479: 	    ata_via_southbridge_fixup(dev);
  480: 	/* FALLTHROUGH */
  481: 
  482:     case 0x74091022: /* AMD 756 default setup */
  483:     case 0x74111022: /* AMD 766 default setup */
  484:     case 0x74411022: /* AMD 768 default setup */
  485:     case 0x01bc10de: /* NVIDIA nForce default setup */
  486:     case 0x006510de: /* NVIDIA nForce2 default setup */
  487: 	/* set prefetch, postwrite */
  488: 	pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) | 0xf0, 1);
  489: 
  490: 	/* set fifo configuration half'n'half */
  491: 	pci_write_config(dev, 0x43, 
  492: 			 (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1);
  493: 
  494: 	/* set status register read retry */
  495: 	pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1);
  496: 
  497: 	/* set DMA read & end-of-sector fifo flush */
  498: 	pci_write_config(dev, 0x46, 
  499: 			 (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1);
  500: 
  501: 	/* set sector size */
  502: 	pci_write_config(dev, 0x60, DEV_BSIZE, 2);
  503: 	pci_write_config(dev, 0x68, DEV_BSIZE, 2);
  504: 	break;
  505: 
  506:     case 0x02111166: /* ServerWorks ROSB4 enable UDMA33 */
  507: 	pci_write_config(dev, 0x64,   
  508: 			 (pci_read_config(dev, 0x64, 4) & ~0x00002000) |
  509: 			 0x00004000, 4);
  510: 	break;
  511: 	
  512:     case 0x02121166: /* ServerWorks CSB5 enable UDMA66/100 depending on rev */
  513: 	pci_write_config(dev, 0x5a,   
  514: 			 (pci_read_config(dev, 0x5a, 1) & ~0x40) |
  515: 			 (pci_get_revid(dev) >= 0x92) ? 0x03 : 0x02, 1);
  516: 	break;
  517: 
  518:     case 0x06801095: /* SiI 0680 set ATA reference clock speed */
  519: 	if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
  520: 	    pci_write_config(dev, 0x8a, 
  521: 			     (pci_read_config(dev, 0x8a, 1) & 0x0F) | 0x10, 1);
  522: 	if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
  523: 	    device_printf(dev, "SiI 0680 could not set clock\n");
  524: 	break;
  525: 
  526:     case 0x06491095:
  527:     case 0x06481095:
  528:     case 0x06461095: /* CMD 646 enable interrupts, set DMA read mode */
  529: 	pci_write_config(dev, 0x71, 0x01, 1);
  530: 	break;
  531: 
  532:     case 0x10001042:   /* RZ 100? known bad, no DMA */
  533:     case 0x10011042:
  534:     case 0x06401095:   /* CMD 640 known bad, no DMA */
  535: 	controller->bmio = NULL;
  536: 	device_printf(dev, "Busmastering DMA disabled\n");
  537:     }
  538: 
  539:     if (controller->bmio) {
  540: 	controller->bmaddr = rman_get_start(controller->bmio);
  541: 	BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
  542: 			     SYS_RES_IOPORT, rid, controller->bmio);
  543: 	controller->bmio = NULL;
  544:     }
  545: 
  546:     /*
  547:      * the Cypress chip is a mess, it contains two ATA functions, but 
  548:      * both channels are visible on the first one.
  549:      * simply ignore the second function for now, as the right
  550:      * solution (ignoring the second channel on the first function)
  551:      * doesn't work with the crappy ATA interrupt setup on the alpha.
  552:      */
  553:     if (pci_get_devid(dev) == 0xc6931080 && pci_get_function(dev) > 1)
  554: 	return 0;
  555: 
  556:     ata_pci_add_child(dev, 0);
  557: 
  558:     if (ATA_MASTERDEV(dev) || pci_read_config(dev, 0x18, 4) & IOMASK)
  559: 	ata_pci_add_child(dev, 1);
  560: 
  561:     return bus_generic_attach(dev);
  562: }
  563: 
  564: static int
  565: ata_pci_intr(struct ata_channel *ch)
  566: {
  567:     u_int8_t dmastat;
  568: 
  569:     /* 
  570:      * since we might share the IRQ with another device, and in some
  571:      * cases with our twin channel, we only want to process interrupts
  572:      * that we know this channel generated.
  573:      */
  574:     switch (ch->chiptype) {
  575:     case 0x00041103:	/* HighPoint HPT366/368/370/372 */
  576:     case 0x00051103:	/* HighPoint HPT372 */
  577:     case 0x00081103:	/* HighPoint HPT374 */
  578: 	if (((dmastat = ata_dmastatus(ch)) &
  579: 	    (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) != ATA_BMSTAT_INTERRUPT)
  580: 	    return 1;
  581: 	ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, dmastat | ATA_BMSTAT_INTERRUPT);
  582: 	DELAY(1);
  583: 	return 0;
  584: 
  585:     case 0x06481095:	/* CMD 648 */
  586:     case 0x06491095:	/* CMD 649 */
  587: 	if (!(pci_read_config(device_get_parent(ch->dev), 0x71, 1) &
  588: 	      (ch->unit ? 0x08 : 0x04)))
  589: 	    return 1;
  590: 	break;
  591: 
  592:     case 0x4d33105a:	/* Promise Ultra/Fasttrak 33 */
  593:     case 0x0d38105a:	/* Promise Fasttrak 66 */
  594:     case 0x4d38105a:	/* Promise Ultra/Fasttrak 66 */
  595:     case 0x0d30105a:	/* Promise OEM ATA100 */
  596:     case 0x4d30105a:	/* Promise Ultra/Fasttrak 100 */
  597: 	if (!(ATA_INL(ch->r_bmio, (ch->unit ? 0x14 : 0x1c)) &
  598: 	      (ch->unit ? 0x00004000 : 0x00000400)))
  599: 	    return 1;
  600: 	break;
  601: 
  602:     case 0x4d68105a:	/* Promise TX2 ATA100 */
  603:     case 0x6268105a:	/* Promise TX2 ATA100 */
  604:     case 0x4d69105a:	/* Promise TX2 ATA133 */
  605:     case 0x5275105a:	/* Promise TX2 ATA133 */
  606:     case 0x6269105a:	/* Promise TX2 ATA133 */
  607:     case 0x7275105a:	/* Promise TX2 ATA133 */
  608: 	ATA_OUTB(ch->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
  609: 	if (!(ATA_INB(ch->r_bmio, ATA_BMDEVSPEC_1) & 0x20))
  610: 	    return 1;
  611: 	break;
  612:     }
  613: 
  614:     if (ch->flags & ATA_DMA_ACTIVE) {
  615: 	if (!((dmastat = ata_dmastatus(ch)) & ATA_BMSTAT_INTERRUPT))
  616: 	    return 1;
  617: 	ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, dmastat | ATA_BMSTAT_INTERRUPT);
  618: 	DELAY(1);
  619:     }
  620:     return 0;
  621: }
  622: 
  623: static int
  624: ata_pci_print_child(device_t dev, device_t child)
  625: {
  626:     struct ata_channel *ch = device_get_softc(child);
  627:     int retval = 0;
  628: 
  629:     retval += bus_print_child_header(dev, child);
  630:     retval += printf(": at 0x%lx", rman_get_start(ch->r_io));
  631: 
  632:     if (ATA_MASTERDEV(dev))
  633: 	retval += printf(" irq %d", 14 + ch->unit);
  634:     
  635:     retval += bus_print_child_footer(dev, child);
  636: 
  637:     return retval;
  638: }
  639: 
  640: static struct resource *
  641: ata_pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
  642: 		       u_long start, u_long end, u_long count, u_int flags)
  643: {
  644:     struct ata_pci_controller *controller = device_get_softc(dev);
  645:     struct resource *res = NULL;
  646:     int unit = ((struct ata_channel *)device_get_softc(child))->unit;
  647:     int myrid;
  648: 
  649:     if (type == SYS_RES_IOPORT) {
  650: 	switch (*rid) {
  651: 	case ATA_IOADDR_RID:
  652: 	    if (ATA_MASTERDEV(dev)) {
  653: 		myrid = 0;
  654: 		start = (unit ? ATA_SECONDARY : ATA_PRIMARY);
  655: 		end = start + ATA_IOSIZE - 1;
  656: 		count = ATA_IOSIZE;
  657: 		res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
  658: 					 SYS_RES_IOPORT, &myrid,
  659: 					 start, end, count, flags);
  660: 	    }
  661: 	    else {
  662: 		myrid = 0x10 + 8 * unit;
  663: 		res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
  664: 					 SYS_RES_IOPORT, &myrid,
  665: 					 start, end, count, flags);
  666: 	    }
  667: 	    break;
  668: 
  669: 	case ATA_ALTADDR_RID:
  670: 	    if (ATA_MASTERDEV(dev)) {
  671: 		myrid = 0;
  672: 		start = (unit ? ATA_SECONDARY : ATA_PRIMARY) + ATA_ALTOFFSET;
  673: 		end = start + ATA_ALTIOSIZE - 1;
  674: 		count = ATA_ALTIOSIZE;
  675: 		res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
  676: 					 SYS_RES_IOPORT, &myrid,
  677: 					 start, end, count, flags);
  678: 	    }
  679: 	    else {
  680: 		myrid = 0x14 + 8 * unit;
  681: 		res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
  682: 					 SYS_RES_IOPORT, &myrid,
  683: 					 start, end, count, flags);
  684: 		if (res) {
  685: 			start = rman_get_start(res) + 2;
  686: 			end = rman_get_start(res) + ATA_ALTIOSIZE - 1;
  687: 			count = ATA_ALTIOSIZE;
  688: 			BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
  689: 					     SYS_RES_IOPORT, myrid, res);
  690: 			res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
  691: 						 SYS_RES_IOPORT, &myrid,
  692: 						 start, end, count, flags);
  693: 		}
  694: 	    }
  695: 	    break;
  696: 
  697: 	case ATA_BMADDR_RID:
  698: 	    if (controller->bmaddr) {
  699: 		myrid = 0x20;
  700: 		start = (unit == 0 ? 
  701: 			 controller->bmaddr : controller->bmaddr+ATA_BMIOSIZE);
  702: 		end = start + ATA_BMIOSIZE - 1;
  703: 		count = ATA_BMIOSIZE;
  704: 		res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
  705: 					 SYS_RES_IOPORT, &myrid,
  706: 					 start, end, count, flags);
  707: 	    }
  708: 	}
  709: 	return res;
  710:     }
  711: 
  712:     if (type == SYS_RES_IRQ && *rid == ATA_IRQ_RID) {
  713: 	if (ATA_MASTERDEV(dev)) {
  714: #ifdef __alpha__
  715: 	    return alpha_platform_alloc_ide_intr(unit);
  716: #else
  717: 	    int irq = (unit == 0 ? 14 : 15);
  718: 
  719: 	    return BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
  720: 				      SYS_RES_IRQ, rid, irq, irq, 1, flags);
  721: #endif
  722: 	}
  723: 	else {
  724: 	    /* primary and secondary channels share interrupt, keep track */
  725: 	    if (!controller->irq)
  726: 		controller->irq = BUS_ALLOC_RESOURCE(device_get_parent(dev), 
  727: 						     dev, SYS_RES_IRQ,
  728: 						     rid, 0, ~0, 1, flags);
  729: 	    controller->irqcnt++;
  730: 	    return controller->irq;
  731: 	}
  732:     }
  733:     return 0;
  734: }
  735: 
  736: static int
  737: ata_pci_release_resource(device_t dev, device_t child, int type, int rid,
  738: 			 struct resource *r)
  739: {
  740:     struct ata_pci_controller *controller = device_get_softc(dev);
  741:     int unit = ((struct ata_channel *)device_get_softc(child))->unit;
  742: 
  743:     if (type == SYS_RES_IOPORT) {
  744: 	switch (rid) {
  745: 	case ATA_IOADDR_RID:
  746: 	    if (ATA_MASTERDEV(dev))
  747: 		return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
  748: 					    SYS_RES_IOPORT, 0x0, r);
  749: 	    else
  750: 		return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
  751: 					    SYS_RES_IOPORT, 0x10 + 8 * unit, r);
  752: 	    break;
  753: 
  754: 	case ATA_ALTADDR_RID:
  755: 	    if (ATA_MASTERDEV(dev))
  756: 		return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
  757: 					    SYS_RES_IOPORT, 0x0, r);
  758: 	    else
  759: 		return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
  760: 					    SYS_RES_IOPORT, 0x14 + 8 * unit, r);
  761: 	    break;
  762: 
  763: 	case ATA_BMADDR_RID:
  764: 	    return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
  765: 					SYS_RES_IOPORT, 0x20, r);
  766: 	default:
  767: 	    return ENOENT;
  768: 	}
  769:     }
  770:     if (type == SYS_RES_IRQ) {
  771: 	if (rid != ATA_IRQ_RID)
  772: 	    return ENOENT;
  773: 
  774: 	if (ATA_MASTERDEV(dev)) {
  775: #ifdef __alpha__
  776: 	    return alpha_platform_release_ide_intr(unit, r);
  777: #else
  778: 	    return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
  779: 					SYS_RES_IRQ, rid, r);
  780: #endif
  781: 	}
  782: 	else {
  783: 	    /* primary and secondary channels share interrupt, keep track */
  784: 	    if (--controller->irqcnt)
  785: 		return 0;
  786: 	    controller->irq = NULL;
  787: 	    return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
  788: 					SYS_RES_IRQ, rid, r);
  789: 	}
  790:     }
  791:     return EINVAL;
  792: }
  793: 
  794: static int
  795: ata_pci_setup_intr(device_t dev, device_t child, struct resource *irq, 
  796: 		   int flags, driver_intr_t *intr, void *arg,
  797: 		   void **cookiep)
  798: {
  799:     if (ATA_MASTERDEV(dev)) {
  800: #ifdef __alpha__
  801: 	return alpha_platform_setup_ide_intr(irq, intr, arg, cookiep);
  802: #else
  803: 	return BUS_SETUP_INTR(device_get_parent(dev), child, irq,
  804: 			      flags, intr, arg, cookiep);
  805: #endif
  806:     }
  807:     else
  808: 	return BUS_SETUP_INTR(device_get_parent(dev), dev, irq,
  809: 			      flags, intr, arg, cookiep);
  810: }
  811: 
  812: static int
  813: ata_pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
  814: 		      void *cookie)
  815: {
  816:     if (ATA_MASTERDEV(dev)) {
  817: #ifdef __alpha__
  818: 	return alpha_platform_teardown_ide_intr(irq, cookie);
  819: #else
  820: 	return BUS_TEARDOWN_INTR(device_get_parent(dev), child, irq, cookie);
  821: #endif
  822:     }
  823:     else
  824: 	return BUS_TEARDOWN_INTR(device_get_parent(dev), dev, irq, cookie);
  825: }
  826: 
  827: static device_method_t ata_pci_methods[] = {
  828:     /* device interface */
  829:     DEVMETHOD(device_probe,		ata_pci_probe),
  830:     DEVMETHOD(device_attach,		ata_pci_attach),
  831:     DEVMETHOD(device_shutdown,		bus_generic_shutdown),
  832:     DEVMETHOD(device_suspend,		bus_generic_suspend),
  833:     DEVMETHOD(device_resume,		bus_generic_resume),
  834: 
  835:     /* bus methods */
  836:     DEVMETHOD(bus_print_child,		ata_pci_print_child),
  837:     DEVMETHOD(bus_alloc_resource,	ata_pci_alloc_resource),
  838:     DEVMETHOD(bus_release_resource,	ata_pci_release_resource),
  839:     DEVMETHOD(bus_activate_resource,	bus_generic_activate_resource),
  840:     DEVMETHOD(bus_deactivate_resource,	bus_generic_deactivate_resource),
  841:     DEVMETHOD(bus_setup_intr,		ata_pci_setup_intr),
  842:     DEVMETHOD(bus_teardown_intr,	ata_pci_teardown_intr),
  843:     { 0, 0 }
  844: };
  845: 
  846: static driver_t ata_pci_driver = {
  847:     "atapci",
  848:     ata_pci_methods,
  849:     sizeof(struct ata_pci_controller),
  850: };
  851: 
  852: static devclass_t ata_pci_devclass;
  853: 
  854: DRIVER_MODULE(atapci, pci, ata_pci_driver, ata_pci_devclass, 0, 0);
  855: 
  856: static int
  857: ata_pcisub_probe(device_t dev)
  858: {
  859:     struct ata_channel *ch = device_get_softc(dev);
  860:     device_t *children;
  861:     int count, i;
  862: 
  863:     /* find channel number on this controller */
  864:     device_get_children(device_get_parent(dev), &children, &count);
  865:     for (i = 0; i < count; i++) {
  866: 	if (children[i] == dev)
  867: 	    ch->unit = i;
  868:     }
  869:     free(children, M_TEMP);
  870:     ch->chiptype = pci_get_devid(device_get_parent(dev));
  871:     ch->intr_func = ata_pci_intr;
  872:     return ata_probe(dev);
  873: }
  874: 
  875: static device_method_t ata_pcisub_methods[] = {
  876:     /* device interface */
  877:     DEVMETHOD(device_probe,	ata_pcisub_probe),
  878:     DEVMETHOD(device_attach,	ata_attach),
  879:     DEVMETHOD(device_detach,	ata_detach),
  880:     DEVMETHOD(device_resume,	ata_resume),
  881:     { 0, 0 }
  882: };
  883: 
  884: static driver_t ata_pcisub_driver = {
  885:     "ata",
  886:     ata_pcisub_methods,
  887:     sizeof(struct ata_channel),
  888: };
  889: 
  890: DRIVER_MODULE(ata, atapci, ata_pcisub_driver, ata_devclass, 0, 0);