File:  [DragonFly] / src / sys / dev / disk / ata / ata-pci.c
Revision 1.9: download - view: text, annotated - select for diffs
Wed Jan 28 12:48:49 2004 UTC (10 years, 2 months ago) by joerg
Branches: MAIN
CVS tags: HEAD
Add support for the AMD 8111 chipset

    1: /*-
    2:  * Copyright (c) 1998,1999,2000,2001,2002 Søren Schmidt <sos@FreeBSD.org>
    3:  * All rights reserved.
    4:  *
    5:  * Redistribution and use in source and binary forms, with or without
    6:  * modification, are permitted provided that the following conditions
    7:  * are met:
    8:  * 1. Redistributions of source code must retain the above copyright
    9:  *    notice, this list of conditions and the following disclaimer,
   10:  *    without modification, immediately at the beginning of the file.
   11:  * 2. Redistributions in binary form must reproduce the above copyright
   12:  *    notice, this list of conditions and the following disclaimer in the
   13:  *    documentation and/or other materials provided with the distribution.
   14:  * 3. The name of the author may not be used to endorse or promote products
   15:  *    derived from this software without specific prior written permission.
   16:  *
   17:  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   18:  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   19:  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   20:  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   21:  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
   22:  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   23:  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   24:  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   25:  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
   26:  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   27:  *
   28:  * $FreeBSD: src/sys/dev/ata/ata-pci.c,v 1.32.2.15 2003/06/06 13:27:05 fjoe Exp $
   29:  * $DragonFly: src/sys/dev/disk/ata/ata-pci.c,v 1.9 2004/01/28 12:48:49 joerg Exp $
   30:  */
   31: 
   32: #include <sys/param.h>
   33: #include <sys/systm.h>
   34: #include <sys/kernel.h>
   35: #include <sys/disk.h>
   36: #include <sys/module.h>
   37: #include <sys/bus.h>
   38: #include <sys/buf.h>
   39: #include <sys/malloc.h>
   40: #include <sys/devicestat.h>
   41: #include <sys/sysctl.h>
   42: #include <machine/stdarg.h>
   43: #include <machine/resource.h>
   44: #include <machine/bus.h>
   45: #include <machine/clock.h>
   46: #ifdef __alpha__
   47: #include <machine/md_var.h>
   48: #endif
   49: #include <sys/rman.h>
   50: #include <bus/pci/pcivar.h>
   51: #include <bus/pci/pcireg.h>
   52: #include "ata-all.h"
   53: 
   54: /* device structures */
   55: struct ata_pci_controller {
   56:     struct resource *bmio;
   57:     int bmaddr;
   58:     struct resource *irq;
   59:     int irqcnt;
   60: };
   61: 
   62: /* misc defines */
   63: #define IOMASK			0xfffffffc
   64: #define GRANDPARENT(dev)	device_get_parent(device_get_parent(dev))
   65: #define ATA_MASTERDEV(dev)	((pci_get_progif(dev) & 0x80) && \
   66: 				 (pci_get_progif(dev) & 0x05) != 0x05)
   67: 
   68: int
   69: ata_find_dev(device_t dev, u_int32_t devid, u_int32_t revid)
   70: {
   71:     device_t *children;
   72:     int nchildren, i;
   73: 
   74:     if (device_get_children(device_get_parent(dev), &children, &nchildren))
   75: 	return 0;
   76: 
   77:     for (i = 0; i < nchildren; i++) {
   78: 	if (pci_get_devid(children[i]) == devid &&
   79: 	    pci_get_revid(children[i]) >= revid) {
   80: 	    free(children, M_TEMP);
   81: 	    return 1;
   82: 	}
   83:     }
   84:     free(children, M_TEMP);
   85:     return 0;
   86: }
   87: 
   88: static void
   89: ata_via_southbridge_fixup(device_t dev)
   90: {
   91:     device_t *children;
   92:     int nchildren, i;
   93: 
   94:     if (device_get_children(device_get_parent(dev), &children, &nchildren))
   95: 	return;
   96: 
   97:     for (i = 0; i < nchildren; i++) {
   98: 	if (pci_get_devid(children[i]) == 0x03051106 ||		/* VIA VT8363 */
   99: 	    pci_get_devid(children[i]) == 0x03911106 ||		/* VIA VT8371 */
  100: 	    pci_get_devid(children[i]) == 0x31021106 ||		/* VIA VT8662 */
  101: 	    pci_get_devid(children[i]) == 0x31121106) {		/* VIA VT8361 */
  102: 	    u_int8_t reg76 = pci_read_config(children[i], 0x76, 1);
  103: 
  104: 	    if ((reg76 & 0xf0) != 0xd0) {
  105: 		device_printf(dev,
  106: 		"Correcting VIA config for southbridge data corruption bug\n");
  107: 		pci_write_config(children[i], 0x75, 0x80, 1);
  108: 		pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1);
  109: 	    }
  110: 	    break;
  111: 	}
  112:     }
  113:     free(children, M_TEMP);
  114: }
  115: 
  116: static const char *
  117: ata_pci_match(device_t dev)
  118: {
  119:     if (pci_get_class(dev) != PCIC_STORAGE)
  120: 	return NULL;
  121: 
  122:     switch (pci_get_devid(dev)) {
  123:     /* supported chipsets */
  124:     case 0x12308086:
  125: 	return "Intel PIIX ATA controller";
  126: 
  127:     case 0x70108086:
  128: 	return "Intel PIIX3 ATA controller";
  129: 
  130:     case 0x71118086:
  131:     case 0x71998086:
  132:     case 0x84ca8086:
  133: 	return "Intel PIIX4 ATA33 controller";
  134: 
  135:     case 0x24218086:
  136: 	return "Intel ICH0 ATA33 controller";
  137: 
  138:     case 0x24118086:
  139:     case 0x76018086:
  140: 	return "Intel ICH ATA66 controller";
  141: 
  142:     case 0x244a8086:
  143:     case 0x244b8086:
  144: 	return "Intel ICH2 ATA100 controller";
  145: 
  146:     case 0x248a8086:
  147:     case 0x248b8086:
  148: 	return "Intel ICH3 ATA100 controller";
  149: 
  150:     case 0x24ca8086:
  151:     case 0x24cb8086:
  152: 	return "Intel ICH4 ATA100 controller";
  153: 
  154:     case 0x24db8086:
  155: 	return "Intel ICH5 ATA100 controller";
  156: 
  157:     case 0x522910b9:
  158: 	if (pci_get_revid(dev) >= 0xc4)
  159: 	    return "AcerLabs Aladdin ATA100 controller";
  160: 	else if (pci_get_revid(dev) >= 0xc2)
  161: 	    return "AcerLabs Aladdin ATA66 controller";
  162: 	else if (pci_get_revid(dev) >= 0x20)
  163: 	    return "AcerLabs Aladdin ATA33 controller";
  164: 	else
  165: 	    return "AcerLabs Aladdin ATA controller";
  166: 
  167:     case 0x05711106: 
  168: 	if (ata_find_dev(dev, 0x05861106, 0x02))
  169: 	    return "VIA 82C586 ATA33 controller";
  170: 	if (ata_find_dev(dev, 0x05861106, 0))
  171: 	    return "VIA 82C586 ATA controller";
  172: 	if (ata_find_dev(dev, 0x05961106, 0x12))
  173: 	    return "VIA 82C596 ATA66 controller";
  174: 	if (ata_find_dev(dev, 0x05961106, 0))
  175: 	    return "VIA 82C596 ATA33 controller";
  176: 	if (ata_find_dev(dev, 0x06861106, 0x40))
  177: 	    return "VIA 82C686 ATA100 controller";
  178: 	if (ata_find_dev(dev, 0x06861106, 0x10))
  179: 	    return "VIA 82C686 ATA66 controller";
  180: 	if (ata_find_dev(dev, 0x06861106, 0))
  181: 	    return "VIA 82C686 ATA33 controller";
  182: 	if (ata_find_dev(dev, 0x82311106, 0))
  183: 	    return "VIA 8231 ATA100 controller";
  184: 	if (ata_find_dev(dev, 0x30741106, 0) ||
  185: 	    ata_find_dev(dev, 0x31091106, 0))
  186: 	    return "VIA 8233 ATA100 controller";
  187: 	if (ata_find_dev(dev, 0x31471106, 0))
  188: 	    return "VIA 8233 ATA133 controller";
  189: 	if (ata_find_dev(dev, 0x31771106, 0))
  190: 	    return "VIA 8235 ATA133 controller";
  191: 	return "VIA Apollo ATA controller";
  192: 
  193:     case 0x55131039:
  194: 	if (ata_find_dev(dev, 0x07461039, 0))
  195: 	    return "SiS 5591 ATA133 controller";
  196: 	if (ata_find_dev(dev, 0x06301039, 0x30) ||
  197: 	    ata_find_dev(dev, 0x06331039, 0) ||
  198: 	    ata_find_dev(dev, 0x06351039, 0) ||
  199: 	    ata_find_dev(dev, 0x06401039, 0) ||
  200: 	    ata_find_dev(dev, 0x06451039, 0) ||
  201: 	    ata_find_dev(dev, 0x06461039, 0) ||
  202: 	    ata_find_dev(dev, 0x06481039, 0) ||
  203: 	    ata_find_dev(dev, 0x06501039, 0) ||
  204: 	    ata_find_dev(dev, 0x07301039, 0) ||
  205: 	    ata_find_dev(dev, 0x07331039, 0) ||
  206: 	    ata_find_dev(dev, 0x07351039, 0) ||
  207: 	    ata_find_dev(dev, 0x07401039, 0) ||
  208: 	    ata_find_dev(dev, 0x07451039, 0) ||
  209: 	    ata_find_dev(dev, 0x07501039, 0))
  210: 	    return "SiS 5591 ATA100 controller";
  211: 	else if (ata_find_dev(dev, 0x05301039, 0) ||
  212: 	    ata_find_dev(dev, 0x05401039, 0) ||
  213: 	    ata_find_dev(dev, 0x06201039, 0) ||
  214: 	    ata_find_dev(dev, 0x06301039, 0))
  215: 	    return "SiS 5591 ATA66 controller";
  216: 	else
  217: 	    return "SiS 5591 ATA33 controller";
  218: 
  219:     case 0x06801095:
  220: 	return "SiI 0680 ATA133 controller";
  221: 
  222:     case 0x06491095:
  223: 	return "CMD 649 ATA100 controller";
  224: 
  225:     case 0x06481095:
  226: 	return "CMD 648 ATA66 controller";
  227: 
  228:     case 0x06461095:
  229: 	return "CMD 646 ATA controller";
  230: 
  231:     case 0xc6931080:
  232: 	if (pci_get_subclass(dev) == PCIS_STORAGE_IDE)
  233: 	    return "Cypress 82C693 ATA controller";
  234: 	return NULL;
  235: 
  236:     case 0x01021078:
  237: 	return "Cyrix 5530 ATA33 controller";
  238: 
  239:     case 0x74091022:
  240: 	return "AMD 756 ATA66 controller";
  241: 
  242:     case 0x74111022:
  243: 	return "AMD 766 ATA100 controller";
  244: 
  245:     case 0x74411022:
  246: 	return "AMD 768 ATA100 controller";
  247: 
  248:     case 0x74691022:
  249:     	return "AMD 8111 UltraATA/133 controller";
  250: 
  251:     case 0x01bc10de:
  252: 	return "NVIDIA nForce ATA100 controller";
  253: 
  254:     case 0x006510de:
  255: 	return "NVIDIA nForce ATA133 controller";
  256: 
  257:     case 0x02111166:
  258: 	return "ServerWorks ROSB4 ATA33 controller";
  259: 
  260:     case 0x02121166:
  261: 	if (pci_get_revid(dev) >= 0x92)
  262: 	    return "ServerWorks CSB5 ATA100 controller";
  263: 	else
  264: 	    return "ServerWorks CSB5 ATA66 controller";
  265: 
  266:     case 0x4d33105a:
  267: 	return "Promise ATA33 controller";
  268: 
  269:     case 0x0d38105a:
  270:     case 0x4d38105a:
  271: 	return "Promise ATA66 controller";
  272: 
  273:     case 0x0d30105a:
  274:     case 0x4d30105a:
  275: 	return "Promise ATA100 controller";
  276: 
  277:     case 0x4d68105a:
  278:     case 0x6268105a: 
  279: 	if (pci_get_devid(GRANDPARENT(dev)) == 0x00221011 &&
  280: 	    pci_get_class(GRANDPARENT(dev)) == PCIC_BRIDGE) {
  281: 	    static long start = 0, end = 0;
  282: 
  283: 	    /* we belive we are on a TX4, now do our (simple) magic */
  284: 	    if (pci_get_slot(dev) == 1) {
  285: 		bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end);
  286: 		return "Promise TX4 ATA100 controller (channel 0+1)";
  287: 	    }
  288: 	    else if (pci_get_slot(dev) == 2 && start && end) {
  289: 		bus_set_resource(dev, SYS_RES_IRQ, 0, start, end);
  290: 		start = end = 0;
  291: 		return "Promise TX4 ATA100 controller (channel 2+3)";
  292: 	    }
  293: 	    else
  294: 		start = end = 0;
  295: 	}
  296: 	return "Promise TX2 ATA100 controller";
  297: 
  298:     case 0x4d69105a:
  299:     case 0x5275105a:
  300:     case 0x6269105a: 
  301:     case 0x7275105a: 
  302: 	return "Promise TX2 ATA133 controller";
  303: 
  304:     case 0x00041103:
  305: 	switch (pci_get_revid(dev)) {
  306: 	case 0x00:
  307: 	case 0x01:
  308: 	    return "HighPoint HPT366 ATA66 controller";
  309: 	case 0x02:
  310: 	    return "HighPoint HPT368 ATA66 controller";
  311: 	case 0x03:
  312: 	case 0x04:
  313: 	    return "HighPoint HPT370 ATA100 controller";
  314: 	case 0x05:
  315: 	    return "HighPoint HPT372 ATA133 controller";
  316: 	}
  317: 	return NULL;
  318: 
  319:     case 0x00051103:
  320: 	switch (pci_get_revid(dev)) {
  321: 	case 0x01:
  322: 	case 0x02:
  323: 	    return "HighPoint HPT372 ATA133 controller";
  324: 	}
  325: 	return NULL;
  326: 
  327:     case 0x00081103:
  328: 	switch (pci_get_revid(dev)) {
  329: 	case 0x07:
  330: 	    return "HighPoint HPT374 ATA133 controller";
  331: 	}
  332: 	return NULL;
  333: 
  334:     case 0x000116ca:
  335: 	return "Cenatek Rocket Drive controller";
  336: 
  337:    /* unsupported but known chipsets, generic DMA only */
  338:     case 0x10001042:
  339:     case 0x10011042:
  340: 	return "RZ 100? ATA controller !WARNING! buggy chip data loss possible";
  341: 
  342:     case 0x06401095:
  343: 	return "CMD 640 ATA controller !WARNING! buggy chip data loss possible";
  344: 
  345:     /* unknown chipsets, try generic DMA if it seems possible */
  346:     default:
  347: 	if (pci_get_class(dev) == PCIC_STORAGE &&
  348: 	    (pci_get_subclass(dev) == PCIS_STORAGE_IDE))
  349: 	    return "Generic PCI ATA controller";
  350:     }
  351:     return NULL;
  352: }
  353: 
  354: static int
  355: ata_pci_probe(device_t dev)
  356: {
  357:     const char *desc = ata_pci_match(dev);
  358:     
  359:     if (desc) {
  360: 	device_set_desc(dev, desc);
  361: 	return 0;
  362:     } 
  363:     else
  364: 	return ENXIO;
  365: }
  366: 
  367: static int
  368: ata_pci_add_child(device_t dev, int unit)
  369: {
  370:     device_t child;
  371: 
  372:     /* check if this is located at one of the std addresses */
  373:     if (ATA_MASTERDEV(dev)) {
  374: 	if (!(child = device_add_child(dev, "ata", unit)))
  375: 	    return ENOMEM;
  376:     }
  377:     else {
  378: 	if (!(child = device_add_child(dev, "ata", 2)))
  379: 	    return ENOMEM;
  380:     }
  381:     return 0;
  382: }
  383: 
  384: static int
  385: ata_pci_attach(device_t dev)
  386: {
  387:     struct ata_pci_controller *controller = device_get_softc(dev);
  388:     u_int8_t class, subclass;
  389:     u_int32_t type, cmd;
  390:     int rid;
  391: 
  392:     /* set up vendor-specific stuff */
  393:     type = pci_get_devid(dev);
  394:     class = pci_get_class(dev);
  395:     subclass = pci_get_subclass(dev);
  396:     cmd = pci_read_config(dev, PCIR_COMMAND, 4);
  397: 
  398:     if (!(cmd & PCIM_CMD_PORTEN)) {
  399: 	device_printf(dev, "ATA channel disabled by BIOS\n");
  400: 	return 0;
  401:     }
  402: 
  403:     /* is busmastering supported ? */
  404:     if ((cmd & (PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN)) == 
  405: 	(PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN)) {
  406: 
  407: 	/* is there a valid port range to connect to ? */
  408: 	rid = 0x20;
  409: 	controller->bmio = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
  410: 					      0, ~0, 1, RF_ACTIVE);
  411: 	if (!controller->bmio)
  412: 	    device_printf(dev, "Busmastering DMA not configured\n");
  413:     }
  414:     else
  415: 	device_printf(dev, "Busmastering DMA not supported\n");
  416: 
  417:     /* do extra chipset specific setups */
  418:     switch (type) {
  419:     case 0x522910b9: /* Aladdin need to activate the ATAPI FIFO */
  420: 	pci_write_config(dev, 0x53, 
  421: 			 (pci_read_config(dev, 0x53, 1) & ~0x01) | 0x02, 1);
  422: 	break;
  423: 
  424:     case 0x4d38105a: /* Promise 66 & 100 (before TX2) need the clock changed */
  425:     case 0x4d30105a:
  426:     case 0x0d30105a:
  427: 	ATA_OUTB(controller->bmio, 0x11, ATA_INB(controller->bmio, 0x11)|0x0a);
  428: 	/* FALLTHROUGH */
  429: 
  430:     case 0x4d33105a: /* Promise (before TX2) need burst mode turned on */
  431: 	ATA_OUTB(controller->bmio, 0x1f, ATA_INB(controller->bmio, 0x1f)|0x01);
  432: 	break;
  433: 
  434:     case 0x00041103:	/* HighPoint HPT366/368/370/372 */
  435: 	if (pci_get_revid(dev) < 2) {	/* HPT 366 */
  436: 	    /* turn off interrupt prediction */
  437: 	    pci_write_config(dev, 0x51, 
  438: 			     (pci_read_config(dev, 0x51, 1) & ~0x80), 1);
  439: 	    break;
  440: 	}
  441: 	if (pci_get_revid(dev) < 5) {   /* HPT368/370 */
  442: 	    /* turn off interrupt prediction */
  443: 	    pci_write_config(dev, 0x51,
  444: 			     (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
  445: 	    pci_write_config(dev, 0x55,
  446: 			     (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
  447: 
  448: 	    /* turn on interrupts */
  449: 	    pci_write_config(dev, 0x5a,
  450: 			     (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
  451: 
  452: 	    /* set clocks etc */
  453: 	    pci_write_config(dev, 0x5b, 0x22, 1);
  454: 	    break;
  455: 	}
  456: 	/* FALLTHROUGH */
  457: 
  458:     case 0x00051103:	/* HighPoint HPT372 */
  459:     case 0x00081103:	/* HighPoint HPT374 */
  460: 	/* turn off interrupt prediction */
  461: 	pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
  462: 	pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
  463: 
  464: 	/* turn on interrupts */
  465: 	pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
  466: 
  467: 	/* set clocks etc */
  468: 	pci_write_config(dev, 0x5b,
  469: 			 (pci_read_config(dev, 0x5b, 1) & 0x01) | 0x20, 1);
  470: 	break;
  471: 
  472:     case 0x05711106: /* VIA 82C586, '596, '686 default setup */
  473: 	/* prepare for ATA-66 on the 82C686a and 82C596b */
  474: 	if ((ata_find_dev(dev, 0x06861106, 0x10) && 
  475: 	     !ata_find_dev(dev, 0x06861106, 0x40)) || 
  476: 	    ata_find_dev(dev, 0x05961106, 0x12))
  477: 	    pci_write_config(dev, 0x50, 0x030b030b, 4);	  
  478: 
  479: 	/* the southbridge might need the data corruption fix */
  480: 	if (ata_find_dev(dev, 0x06861106, 0x40) ||
  481: 	    ata_find_dev(dev, 0x82311106, 0x10))
  482: 	    ata_via_southbridge_fixup(dev);
  483: 	/* FALLTHROUGH */
  484: 
  485:     case 0x74091022: /* AMD 756 default setup */
  486:     case 0x74111022: /* AMD 766 default setup */
  487:     case 0x74411022: /* AMD 768 default setup */
  488:     case 0x746d1022: /* AMD 8111 default setup */
  489:     case 0x01bc10de: /* NVIDIA nForce default setup */
  490:     case 0x006510de: /* NVIDIA nForce2 default setup */
  491: 	/* set prefetch, postwrite */
  492: 	pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) | 0xf0, 1);
  493: 
  494: 	/* set fifo configuration half'n'half */
  495: 	pci_write_config(dev, 0x43, 
  496: 			 (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1);
  497: 
  498: 	/* set status register read retry */
  499: 	pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1);
  500: 
  501: 	/* set DMA read & end-of-sector fifo flush */
  502: 	pci_write_config(dev, 0x46, 
  503: 			 (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1);
  504: 
  505: 	/* set sector size */
  506: 	pci_write_config(dev, 0x60, DEV_BSIZE, 2);
  507: 	pci_write_config(dev, 0x68, DEV_BSIZE, 2);
  508: 	break;
  509: 
  510:     case 0x02111166: /* ServerWorks ROSB4 enable UDMA33 */
  511: 	pci_write_config(dev, 0x64,   
  512: 			 (pci_read_config(dev, 0x64, 4) & ~0x00002000) |
  513: 			 0x00004000, 4);
  514: 	break;
  515: 	
  516:     case 0x02121166: /* ServerWorks CSB5 enable UDMA66/100 depending on rev */
  517: 	pci_write_config(dev, 0x5a,   
  518: 			 (pci_read_config(dev, 0x5a, 1) & ~0x40) |
  519: 			 (pci_get_revid(dev) >= 0x92) ? 0x03 : 0x02, 1);
  520: 	break;
  521: 
  522:     case 0x06801095: /* SiI 0680 set ATA reference clock speed */
  523: 	if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
  524: 	    pci_write_config(dev, 0x8a, 
  525: 			     (pci_read_config(dev, 0x8a, 1) & 0x0F) | 0x10, 1);
  526: 	if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
  527: 	    device_printf(dev, "SiI 0680 could not set clock\n");
  528: 	break;
  529: 
  530:     case 0x06491095:
  531:     case 0x06481095:
  532:     case 0x06461095: /* CMD 646 enable interrupts, set DMA read mode */
  533: 	pci_write_config(dev, 0x71, 0x01, 1);
  534: 	break;
  535: 
  536:     case 0x10001042:   /* RZ 100? known bad, no DMA */
  537:     case 0x10011042:
  538:     case 0x06401095:   /* CMD 640 known bad, no DMA */
  539: 	controller->bmio = NULL;
  540: 	device_printf(dev, "Busmastering DMA disabled\n");
  541:     }
  542: 
  543:     if (controller->bmio) {
  544: 	controller->bmaddr = rman_get_start(controller->bmio);
  545: 	BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
  546: 			     SYS_RES_IOPORT, rid, controller->bmio);
  547: 	controller->bmio = NULL;
  548:     }
  549: 
  550:     /*
  551:      * the Cypress chip is a mess, it contains two ATA functions, but 
  552:      * both channels are visible on the first one.
  553:      * simply ignore the second function for now, as the right
  554:      * solution (ignoring the second channel on the first function)
  555:      * doesn't work with the crappy ATA interrupt setup on the alpha.
  556:      */
  557:     if (pci_get_devid(dev) == 0xc6931080 && pci_get_function(dev) > 1)
  558: 	return 0;
  559: 
  560:     ata_pci_add_child(dev, 0);
  561: 
  562:     if (ATA_MASTERDEV(dev) || pci_read_config(dev, 0x18, 4) & IOMASK)
  563: 	ata_pci_add_child(dev, 1);
  564: 
  565:     return bus_generic_attach(dev);
  566: }
  567: 
  568: static int
  569: ata_pci_intr(struct ata_channel *ch)
  570: {
  571:     u_int8_t dmastat;
  572: 
  573:     /* 
  574:      * since we might share the IRQ with another device, and in some
  575:      * cases with our twin channel, we only want to process interrupts
  576:      * that we know this channel generated.
  577:      */
  578:     switch (ch->chiptype) {
  579:     case 0x00041103:	/* HighPoint HPT366/368/370/372 */
  580:     case 0x00051103:	/* HighPoint HPT372 */
  581:     case 0x00081103:	/* HighPoint HPT374 */
  582: 	if (((dmastat = ata_dmastatus(ch)) &
  583: 	    (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) != ATA_BMSTAT_INTERRUPT)
  584: 	    return 1;
  585: 	ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, dmastat | ATA_BMSTAT_INTERRUPT);
  586: 	DELAY(1);
  587: 	return 0;
  588: 
  589:     case 0x06481095:	/* CMD 648 */
  590:     case 0x06491095:	/* CMD 649 */
  591: 	if (!(pci_read_config(device_get_parent(ch->dev), 0x71, 1) &
  592: 	      (ch->unit ? 0x08 : 0x04)))
  593: 	    return 1;
  594: 	break;
  595: 
  596:     case 0x4d33105a:	/* Promise Ultra/Fasttrak 33 */
  597:     case 0x0d38105a:	/* Promise Fasttrak 66 */
  598:     case 0x4d38105a:	/* Promise Ultra/Fasttrak 66 */
  599:     case 0x0d30105a:	/* Promise OEM ATA100 */
  600:     case 0x4d30105a:	/* Promise Ultra/Fasttrak 100 */
  601: 	if (!(ATA_INL(ch->r_bmio, (ch->unit ? 0x14 : 0x1c)) &
  602: 	      (ch->unit ? 0x00004000 : 0x00000400)))
  603: 	    return 1;
  604: 	break;
  605: 
  606:     case 0x4d68105a:	/* Promise TX2 ATA100 */
  607:     case 0x6268105a:	/* Promise TX2 ATA100 */
  608:     case 0x4d69105a:	/* Promise TX2 ATA133 */
  609:     case 0x5275105a:	/* Promise TX2 ATA133 */
  610:     case 0x6269105a:	/* Promise TX2 ATA133 */
  611:     case 0x7275105a:	/* Promise TX2 ATA133 */
  612: 	ATA_OUTB(ch->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
  613: 	if (!(ATA_INB(ch->r_bmio, ATA_BMDEVSPEC_1) & 0x20))
  614: 	    return 1;
  615: 	break;
  616:     }
  617: 
  618:     if (ch->flags & ATA_DMA_ACTIVE) {
  619: 	if (!((dmastat = ata_dmastatus(ch)) & ATA_BMSTAT_INTERRUPT))
  620: 	    return 1;
  621: 	ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, dmastat | ATA_BMSTAT_INTERRUPT);
  622: 	DELAY(1);
  623:     }
  624:     return 0;
  625: }
  626: 
  627: static int
  628: ata_pci_print_child(device_t dev, device_t child)
  629: {
  630:     struct ata_channel *ch = device_get_softc(child);
  631:     int retval = 0;
  632: 
  633:     retval += bus_print_child_header(dev, child);
  634:     retval += printf(": at 0x%lx", rman_get_start(ch->r_io));
  635: 
  636:     if (ATA_MASTERDEV(dev))
  637: 	retval += printf(" irq %d", 14 + ch->unit);
  638:     
  639:     retval += bus_print_child_footer(dev, child);
  640: 
  641:     return retval;
  642: }
  643: 
  644: static struct resource *
  645: ata_pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
  646: 		       u_long start, u_long end, u_long count, u_int flags)
  647: {
  648:     struct ata_pci_controller *controller = device_get_softc(dev);
  649:     struct resource *res = NULL;
  650:     int unit = ((struct ata_channel *)device_get_softc(child))->unit;
  651:     int myrid;
  652: 
  653:     if (type == SYS_RES_IOPORT) {
  654: 	switch (*rid) {
  655: 	case ATA_IOADDR_RID:
  656: 	    if (ATA_MASTERDEV(dev)) {
  657: 		myrid = 0;
  658: 		start = (unit ? ATA_SECONDARY : ATA_PRIMARY);
  659: 		end = start + ATA_IOSIZE - 1;
  660: 		count = ATA_IOSIZE;
  661: 		res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
  662: 					 SYS_RES_IOPORT, &myrid,
  663: 					 start, end, count, flags);
  664: 	    }
  665: 	    else {
  666: 		myrid = 0x10 + 8 * unit;
  667: 		res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
  668: 					 SYS_RES_IOPORT, &myrid,
  669: 					 start, end, count, flags);
  670: 	    }
  671: 	    break;
  672: 
  673: 	case ATA_ALTADDR_RID:
  674: 	    if (ATA_MASTERDEV(dev)) {
  675: 		myrid = 0;
  676: 		start = (unit ? ATA_SECONDARY : ATA_PRIMARY) + ATA_ALTOFFSET;
  677: 		end = start + ATA_ALTIOSIZE - 1;
  678: 		count = ATA_ALTIOSIZE;
  679: 		res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
  680: 					 SYS_RES_IOPORT, &myrid,
  681: 					 start, end, count, flags);
  682: 	    }
  683: 	    else {
  684: 		myrid = 0x14 + 8 * unit;
  685: 		res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
  686: 					 SYS_RES_IOPORT, &myrid,
  687: 					 start, end, count, flags);
  688: 		if (res) {
  689: 			start = rman_get_start(res) + 2;
  690: 			end = rman_get_start(res) + ATA_ALTIOSIZE - 1;
  691: 			count = ATA_ALTIOSIZE;
  692: 			BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
  693: 					     SYS_RES_IOPORT, myrid, res);
  694: 			res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
  695: 						 SYS_RES_IOPORT, &myrid,
  696: 						 start, end, count, flags);
  697: 		}
  698: 	    }
  699: 	    break;
  700: 
  701: 	case ATA_BMADDR_RID:
  702: 	    if (controller->bmaddr) {
  703: 		myrid = 0x20;
  704: 		start = (unit == 0 ? 
  705: 			 controller->bmaddr : controller->bmaddr+ATA_BMIOSIZE);
  706: 		end = start + ATA_BMIOSIZE - 1;
  707: 		count = ATA_BMIOSIZE;
  708: 		res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
  709: 					 SYS_RES_IOPORT, &myrid,
  710: 					 start, end, count, flags);
  711: 	    }
  712: 	}
  713: 	return res;
  714:     }
  715: 
  716:     if (type == SYS_RES_IRQ && *rid == ATA_IRQ_RID) {
  717: 	if (ATA_MASTERDEV(dev)) {
  718: #ifdef __alpha__
  719: 	    return alpha_platform_alloc_ide_intr(unit);
  720: #else
  721: 	    int irq = (unit == 0 ? 14 : 15);
  722: 
  723: 	    return BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
  724: 				      SYS_RES_IRQ, rid, irq, irq, 1, flags);
  725: #endif
  726: 	}
  727: 	else {
  728: 	    /* primary and secondary channels share interrupt, keep track */
  729: 	    if (!controller->irq)
  730: 		controller->irq = BUS_ALLOC_RESOURCE(device_get_parent(dev), 
  731: 						     dev, SYS_RES_IRQ,
  732: 						     rid, 0, ~0, 1, flags);
  733: 	    controller->irqcnt++;
  734: 	    return controller->irq;
  735: 	}
  736:     }
  737:     return 0;
  738: }
  739: 
  740: static int
  741: ata_pci_release_resource(device_t dev, device_t child, int type, int rid,
  742: 			 struct resource *r)
  743: {
  744:     struct ata_pci_controller *controller = device_get_softc(dev);
  745:     int unit = ((struct ata_channel *)device_get_softc(child))->unit;
  746: 
  747:     if (type == SYS_RES_IOPORT) {
  748: 	switch (rid) {
  749: 	case ATA_IOADDR_RID:
  750: 	    if (ATA_MASTERDEV(dev))
  751: 		return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
  752: 					    SYS_RES_IOPORT, 0x0, r);
  753: 	    else
  754: 		return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
  755: 					    SYS_RES_IOPORT, 0x10 + 8 * unit, r);
  756: 	    break;
  757: 
  758: 	case ATA_ALTADDR_RID:
  759: 	    if (ATA_MASTERDEV(dev))
  760: 		return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
  761: 					    SYS_RES_IOPORT, 0x0, r);
  762: 	    else
  763: 		return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
  764: 					    SYS_RES_IOPORT, 0x14 + 8 * unit, r);
  765: 	    break;
  766: 
  767: 	case ATA_BMADDR_RID:
  768: 	    return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
  769: 					SYS_RES_IOPORT, 0x20, r);
  770: 	default:
  771: 	    return ENOENT;
  772: 	}
  773:     }
  774:     if (type == SYS_RES_IRQ) {
  775: 	if (rid != ATA_IRQ_RID)
  776: 	    return ENOENT;
  777: 
  778: 	if (ATA_MASTERDEV(dev)) {
  779: #ifdef __alpha__
  780: 	    return alpha_platform_release_ide_intr(unit, r);
  781: #else
  782: 	    return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
  783: 					SYS_RES_IRQ, rid, r);
  784: #endif
  785: 	}
  786: 	else {
  787: 	    /* primary and secondary channels share interrupt, keep track */
  788: 	    if (--controller->irqcnt)
  789: 		return 0;
  790: 	    controller->irq = NULL;
  791: 	    return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
  792: 					SYS_RES_IRQ, rid, r);
  793: 	}
  794:     }
  795:     return EINVAL;
  796: }
  797: 
  798: static int
  799: ata_pci_setup_intr(device_t dev, device_t child, struct resource *irq, 
  800: 		   int flags, driver_intr_t *intr, void *arg,
  801: 		   void **cookiep)
  802: {
  803:     if (ATA_MASTERDEV(dev)) {
  804: #ifdef __alpha__
  805: 	return alpha_platform_setup_ide_intr(irq, intr, arg, cookiep);
  806: #else
  807: 	return BUS_SETUP_INTR(device_get_parent(dev), child, irq,
  808: 			      flags, intr, arg, cookiep);
  809: #endif
  810:     }
  811:     else
  812: 	return BUS_SETUP_INTR(device_get_parent(dev), dev, irq,
  813: 			      flags, intr, arg, cookiep);
  814: }
  815: 
  816: static int
  817: ata_pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
  818: 		      void *cookie)
  819: {
  820:     if (ATA_MASTERDEV(dev)) {
  821: #ifdef __alpha__
  822: 	return alpha_platform_teardown_ide_intr(irq, cookie);
  823: #else
  824: 	return BUS_TEARDOWN_INTR(device_get_parent(dev), child, irq, cookie);
  825: #endif
  826:     }
  827:     else
  828: 	return BUS_TEARDOWN_INTR(device_get_parent(dev), dev, irq, cookie);
  829: }
  830: 
  831: static device_method_t ata_pci_methods[] = {
  832:     /* device interface */
  833:     DEVMETHOD(device_probe,		ata_pci_probe),
  834:     DEVMETHOD(device_attach,		ata_pci_attach),
  835:     DEVMETHOD(device_shutdown,		bus_generic_shutdown),
  836:     DEVMETHOD(device_suspend,		bus_generic_suspend),
  837:     DEVMETHOD(device_resume,		bus_generic_resume),
  838: 
  839:     /* bus methods */
  840:     DEVMETHOD(bus_print_child,		ata_pci_print_child),
  841:     DEVMETHOD(bus_alloc_resource,	ata_pci_alloc_resource),
  842:     DEVMETHOD(bus_release_resource,	ata_pci_release_resource),
  843:     DEVMETHOD(bus_activate_resource,	bus_generic_activate_resource),
  844:     DEVMETHOD(bus_deactivate_resource,	bus_generic_deactivate_resource),
  845:     DEVMETHOD(bus_setup_intr,		ata_pci_setup_intr),
  846:     DEVMETHOD(bus_teardown_intr,	ata_pci_teardown_intr),
  847:     { 0, 0 }
  848: };
  849: 
  850: static driver_t ata_pci_driver = {
  851:     "atapci",
  852:     ata_pci_methods,
  853:     sizeof(struct ata_pci_controller),
  854: };
  855: 
  856: static devclass_t ata_pci_devclass;
  857: 
  858: DRIVER_MODULE(atapci, pci, ata_pci_driver, ata_pci_devclass, 0, 0);
  859: 
  860: static int
  861: ata_pcisub_probe(device_t dev)
  862: {
  863:     struct ata_channel *ch = device_get_softc(dev);
  864:     device_t *children;
  865:     int count, i;
  866: 
  867:     /* find channel number on this controller */
  868:     device_get_children(device_get_parent(dev), &children, &count);
  869:     for (i = 0; i < count; i++) {
  870: 	if (children[i] == dev)
  871: 	    ch->unit = i;
  872:     }
  873:     free(children, M_TEMP);
  874:     ch->chiptype = pci_get_devid(device_get_parent(dev));
  875:     ch->intr_func = ata_pci_intr;
  876:     return ata_probe(dev);
  877: }
  878: 
  879: static device_method_t ata_pcisub_methods[] = {
  880:     /* device interface */
  881:     DEVMETHOD(device_probe,	ata_pcisub_probe),
  882:     DEVMETHOD(device_attach,	ata_attach),
  883:     DEVMETHOD(device_detach,	ata_detach),
  884:     DEVMETHOD(device_resume,	ata_resume),
  885:     { 0, 0 }
  886: };
  887: 
  888: static driver_t ata_pcisub_driver = {
  889:     "ata",
  890:     ata_pcisub_methods,
  891:     sizeof(struct ata_channel),
  892: };
  893: 
  894: DRIVER_MODULE(ata, atapci, ata_pcisub_driver, ata_devclass, 0, 0);