File:  [DragonFly] / src / sys / dev / serial / rp / rp.c
Revision 1.11: download - view: text, annotated - select for diffs
Wed May 19 22:52:49 2004 UTC (10 years, 5 months ago) by dillon
Branches: MAIN
CVS tags: HEAD, DragonFly_Snap13Sep2004, DragonFly_1_0_REL, DragonFly_1_0_RC1, DragonFly_1_0A_REL
Device layer rollup commit.

* cdevsw_add() is now required.  cdevsw_add() and cdevsw_remove() may specify
  a mask/match indicating the range of supported minor numbers.  Multiple
  cdevsw_add()'s using the same major number, but distinctly different
  ranges, may be issued.  All devices that failed to call cdevsw_add() before
  now do.

* cdevsw_remove() now automatically marks all devices within its supported
  range as being destroyed.

* vnode->v_rdev is no longer resolved when the vnode is created.  Instead,
  only v_udev (a newly added field) is resolved.  v_rdev is resolved when
  the vnode is opened and cleared on the last close.

* A great deal of code was making rather dubious assumptions with regards
  to the validity of devices associated with vnodes, primarily due to
  the persistence of a device structure due to being indexed by (major, minor)
  instead of by (cdevsw, major, minor).  In particular, if you run a program
  which connects to a USB device and then you pull the USB device and plug
  it back in, the vnode subsystem will continue to believe that the device
  is open when, in fact, it isn't (because it was destroyed and recreated).

  In particular, note that all the VFS mount procedures now check devices
  via v_udev instead of v_rdev prior to calling VOP_OPEN(), since v_rdev
  is NULL prior to the first open.

* The disk layer's device interaction has been rewritten.  The disk layer
  (i.e. the slice and disklabel management layer) no longer overloads
  its data onto the device structure representing the underlying physical
  disk.  Instead, the disk layer uses the new cdevsw_add() functionality
  to register its own cdevsw using the underlying device's major number,
  and simply does NOT register the underlying device's cdevsw.  No
  confusion is created because the device hash is now based on
  (cdevsw,major,minor) rather then (major,minor).

  NOTE: This also means that underlying raw disk devices may use the entire
  device minor number instead of having to reserve the bits used by the disk
  layer, and also means that can we (theoretically) stack a fully
  disklabel-supported 'disk' on top of any block device.

* The new reference counting scheme prevents this by associating a device
  with a cdevsw and disconnecting the device from its cdevsw when the cdevsw
  is removed.  Additionally, all udev2dev() lookups run through the cdevsw
  mask/match and only successfully find devices still associated with an
  active cdevsw.

* Major work on MFS:  MFS no longer shortcuts vnode and device creation.  It
  now creates a real vnode and a real device and implements real open and
  close VOPs.  Additionally, due to the disk layer changes, MFS is no longer
  limited to 255 mounts.  The new limit is 16 million.  Since MFS creates a
  real device node, mount_mfs will now create a real /dev/mfs<PID> device
  that can be read from userland (e.g. so you can dump an MFS filesystem).

* BUF AND DEVICE STRATEGY changes.  The struct buf contains a b_dev field.
  In order to properly handle stacked devices we now require that the b_dev
  field be initialized before the device strategy routine is called.  This
  required some additional work in various VFS implementations.  To enforce
  this requirement, biodone() now sets b_dev to NODEV.  The new disk layer
  will adjust b_dev before forwarding a request to the actual physical
  device.

* A bug in the ISO CD boot sequence which resulted in a panic has been fixed.

Testing by: lots of people, but David Rhodus found the most aggregious bugs.

    1: /* 
    2:  * Copyright (c) Comtrol Corporation <support@comtrol.com>
    3:  * All rights reserved.
    4:  *
    5:  * Redistribution and use in source and binary forms, with or without
    6:  * modification, are permitted prodived that the follwoing conditions
    7:  * are met.
    8:  * 1. Redistributions of source code must retain the above copyright 
    9:  *    notive, this list of conditions and the following disclainer.
   10:  * 2. Redistributions in binary form must reproduce the above copyright
   11:  *    notice, this list of conditions and the following disclaimer in the
   12:  *    documentation and/or other materials prodided with the distribution.
   13:  * 3. All advertising materials mentioning features or use of this software
   14:  *    must display the following acknowledgement:
   15:  *       This product includes software developed by Comtrol Corporation.
   16:  * 4. The name of Comtrol Corporation may not be used to endorse or 
   17:  *    promote products derived from this software without specific 
   18:  *    prior written permission.
   19:  *
   20:  * THIS SOFTWARE IS PROVIDED BY COMTROL CORPORATION ``AS IS'' AND ANY
   21:  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   22:  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   23:  * ARE DISCLAIMED.  IN NO EVENT SHALL COMTROL CORPORATION BE LIABLE FOR
   24:  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   25:  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   26:  * OR SERVICES; LOSS OF USE, DATA, LIFE OR PROFITS; OR BUSINESS INTERRUPTION)
   27:  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   28:  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   29:  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   30:  * SUCH DAMAGE.
   31:  *
   32:  * $FreeBSD: src/sys/dev/rp/rp.c,v 1.45.2.2 2002/11/07 22:26:59 tegge Exp $
   33:  * $DragonFly: src/sys/dev/serial/rp/rp.c,v 1.11 2004/05/19 22:52:49 dillon Exp $
   34:  */
   35: 
   36: /* 
   37:  * rp.c - for RocketPort FreeBSD
   38:  */
   39: 
   40: #include <sys/param.h>
   41: #include <sys/systm.h>
   42: #include <sys/fcntl.h>
   43: #include <sys/malloc.h>
   44: #include <sys/tty.h>
   45: #include <sys/proc.h>
   46: #include <sys/dkstat.h>
   47: #include <sys/conf.h>
   48: #include <sys/kernel.h>
   49: #include <machine/resource.h>
   50: #include <machine/bus.h>
   51: #include <sys/bus.h>
   52: #include <sys/rman.h>
   53: 
   54: #define ROCKET_C
   55: #include "rpreg.h"
   56: #include "rpvar.h"
   57: 
   58: static const char RocketPortVersion[] = "3.02";
   59: 
   60: static Byte_t RData[RDATASIZE] =
   61: {
   62:    0x00, 0x09, 0xf6, 0x82,
   63:    0x02, 0x09, 0x86, 0xfb,
   64:    0x04, 0x09, 0x00, 0x0a,
   65:    0x06, 0x09, 0x01, 0x0a,
   66:    0x08, 0x09, 0x8a, 0x13,
   67:    0x0a, 0x09, 0xc5, 0x11,
   68:    0x0c, 0x09, 0x86, 0x85,
   69:    0x0e, 0x09, 0x20, 0x0a,
   70:    0x10, 0x09, 0x21, 0x0a,
   71:    0x12, 0x09, 0x41, 0xff,
   72:    0x14, 0x09, 0x82, 0x00,
   73:    0x16, 0x09, 0x82, 0x7b,
   74:    0x18, 0x09, 0x8a, 0x7d,
   75:    0x1a, 0x09, 0x88, 0x81,
   76:    0x1c, 0x09, 0x86, 0x7a,
   77:    0x1e, 0x09, 0x84, 0x81,
   78:    0x20, 0x09, 0x82, 0x7c,
   79:    0x22, 0x09, 0x0a, 0x0a
   80: };
   81: 
   82: static Byte_t RRegData[RREGDATASIZE]=
   83: {
   84:    0x00, 0x09, 0xf6, 0x82,	       /* 00: Stop Rx processor */
   85:    0x08, 0x09, 0x8a, 0x13,	       /* 04: Tx software flow control */
   86:    0x0a, 0x09, 0xc5, 0x11,	       /* 08: XON char */
   87:    0x0c, 0x09, 0x86, 0x85,	       /* 0c: XANY */
   88:    0x12, 0x09, 0x41, 0xff,	       /* 10: Rx mask char */
   89:    0x14, 0x09, 0x82, 0x00,	       /* 14: Compare/Ignore #0 */
   90:    0x16, 0x09, 0x82, 0x7b,	       /* 18: Compare #1 */
   91:    0x18, 0x09, 0x8a, 0x7d,	       /* 1c: Compare #2 */
   92:    0x1a, 0x09, 0x88, 0x81,	       /* 20: Interrupt #1 */
   93:    0x1c, 0x09, 0x86, 0x7a,	       /* 24: Ignore/Replace #1 */
   94:    0x1e, 0x09, 0x84, 0x81,	       /* 28: Interrupt #2 */
   95:    0x20, 0x09, 0x82, 0x7c,	       /* 2c: Ignore/Replace #2 */
   96:    0x22, 0x09, 0x0a, 0x0a	       /* 30: Rx FIFO Enable */
   97: };
   98: 
   99: #if 0
  100: /* IRQ number to MUDBAC register 2 mapping */
  101: Byte_t sIRQMap[16] =
  102: {
  103:    0,0,0,0x10,0x20,0x30,0,0,0,0x40,0x50,0x60,0x70,0,0,0x80
  104: };
  105: #endif
  106: 
  107: Byte_t rp_sBitMapClrTbl[8] =
  108: {
  109:    0xfe,0xfd,0xfb,0xf7,0xef,0xdf,0xbf,0x7f
  110: };
  111: 
  112: Byte_t rp_sBitMapSetTbl[8] =
  113: {
  114:    0x01,0x02,0x04,0x08,0x10,0x20,0x40,0x80
  115: };
  116: 
  117: /* Actually not used */
  118: #if notdef
  119: struct termios deftermios = {
  120: 	TTYDEF_IFLAG,
  121: 	TTYDEF_OFLAG,
  122: 	TTYDEF_CFLAG,
  123: 	TTYDEF_LFLAG,
  124: 	{ CEOF, CEOL, CEOL, CERASE, CWERASE, CKILL, CREPRINT,
  125: 	_POSIX_VDISABLE, CINTR, CQUIT, CSUSP, CDSUSP, CSTART, CSTOP, CLNEXT,
  126: 	CDISCARD, CMIN, CTIME, CSTATUS, _POSIX_VDISABLE },
  127: 	TTYDEF_SPEED,
  128: 	TTYDEF_SPEED
  129: };
  130: #endif
  131: 
  132: /***************************************************************************
  133: Function: sReadAiopID
  134: Purpose:  Read the AIOP idenfication number directly from an AIOP.
  135: Call:	  sReadAiopID(CtlP, aiop)
  136: 	  CONTROLLER_T *CtlP; Ptr to controller structure
  137: 	  int aiop: AIOP index
  138: Return:   int: Flag AIOPID_XXXX if a valid AIOP is found, where X
  139: 		 is replace by an identifying number.
  140: 	  Flag AIOPID_NULL if no valid AIOP is found
  141: Warnings: No context switches are allowed while executing this function.
  142: 
  143: */
  144: int sReadAiopID(CONTROLLER_T *CtlP, int aiop)
  145: {
  146:    Byte_t AiopID;		/* ID byte from AIOP */
  147: 
  148:    rp_writeaiop1(CtlP, aiop, _CMD_REG, RESET_ALL);     /* reset AIOP */
  149:    rp_writeaiop1(CtlP, aiop, _CMD_REG, 0x0);
  150:    AiopID = rp_readaiop1(CtlP, aiop, _CHN_STAT0) & 0x07;
  151:    if(AiopID == 0x06)
  152:       return(1);
  153:    else 			       /* AIOP does not exist */
  154:       return(-1);
  155: }
  156: 
  157: /***************************************************************************
  158: Function: sReadAiopNumChan
  159: Purpose:  Read the number of channels available in an AIOP directly from
  160: 	  an AIOP.
  161: Call:	  sReadAiopNumChan(CtlP, aiop)
  162: 	  CONTROLLER_T *CtlP; Ptr to controller structure
  163: 	  int aiop: AIOP index
  164: Return:   int: The number of channels available
  165: Comments: The number of channels is determined by write/reads from identical
  166: 	  offsets within the SRAM address spaces for channels 0 and 4.
  167: 	  If the channel 4 space is mirrored to channel 0 it is a 4 channel
  168: 	  AIOP, otherwise it is an 8 channel.
  169: Warnings: No context switches are allowed while executing this function.
  170: */
  171: int sReadAiopNumChan(CONTROLLER_T *CtlP, int aiop)
  172: {
  173:    Word_t x, y;
  174: 
  175:    rp_writeaiop4(CtlP, aiop, _INDX_ADDR,0x12340000L); /* write to chan 0 SRAM */
  176:    rp_writeaiop2(CtlP, aiop, _INDX_ADDR,0);	   /* read from SRAM, chan 0 */
  177:    x = rp_readaiop2(CtlP, aiop, _INDX_DATA);
  178:    rp_writeaiop2(CtlP, aiop, _INDX_ADDR,0x4000);  /* read from SRAM, chan 4 */
  179:    y = rp_readaiop2(CtlP, aiop, _INDX_DATA);
  180:    if(x != y)  /* if different must be 8 chan */
  181:       return(8);
  182:    else
  183:       return(4);
  184: }
  185: 
  186: /***************************************************************************
  187: Function: sInitChan
  188: Purpose:  Initialization of a channel and channel structure
  189: Call:	  sInitChan(CtlP,ChP,AiopNum,ChanNum)
  190: 	  CONTROLLER_T *CtlP; Ptr to controller structure
  191: 	  CHANNEL_T *ChP; Ptr to channel structure
  192: 	  int AiopNum; AIOP number within controller
  193: 	  int ChanNum; Channel number within AIOP
  194: Return:   int: TRUE if initialization succeeded, FALSE if it fails because channel
  195: 	       number exceeds number of channels available in AIOP.
  196: Comments: This function must be called before a channel can be used.
  197: Warnings: No range checking on any of the parameters is done.
  198: 
  199: 	  No context switches are allowed while executing this function.
  200: */
  201: int sInitChan(	CONTROLLER_T *CtlP,
  202: 		CHANNEL_T *ChP,
  203: 		int AiopNum,
  204: 		int ChanNum)
  205: {
  206:    int i, ChOff;
  207:    Byte_t *ChR;
  208:    static Byte_t R[4];
  209: 
  210:    if(ChanNum >= CtlP->AiopNumChan[AiopNum])
  211:       return(FALSE);		       /* exceeds num chans in AIOP */
  212: 
  213:    /* Channel, AIOP, and controller identifiers */
  214:    ChP->CtlP = CtlP;
  215:    ChP->ChanID = CtlP->AiopID[AiopNum];
  216:    ChP->AiopNum = AiopNum;
  217:    ChP->ChanNum = ChanNum;
  218: 
  219:    /* Initialize the channel from the RData array */
  220:    for(i=0; i < RDATASIZE; i+=4)
  221:    {
  222:       R[0] = RData[i];
  223:       R[1] = RData[i+1] + 0x10 * ChanNum;
  224:       R[2] = RData[i+2];
  225:       R[3] = RData[i+3];
  226:       rp_writech4(ChP,_INDX_ADDR,*((DWord_t *)&R[0]));
  227:    }
  228: 
  229:    ChR = ChP->R;
  230:    for(i=0; i < RREGDATASIZE; i+=4)
  231:    {
  232:       ChR[i] = RRegData[i];
  233:       ChR[i+1] = RRegData[i+1] + 0x10 * ChanNum;
  234:       ChR[i+2] = RRegData[i+2];
  235:       ChR[i+3] = RRegData[i+3];
  236:    }
  237: 
  238:    /* Indexed registers */
  239:    ChOff = (Word_t)ChanNum * 0x1000;
  240: 
  241:    ChP->BaudDiv[0] = (Byte_t)(ChOff + _BAUD);
  242:    ChP->BaudDiv[1] = (Byte_t)((ChOff + _BAUD) >> 8);
  243:    ChP->BaudDiv[2] = (Byte_t)BRD9600;
  244:    ChP->BaudDiv[3] = (Byte_t)(BRD9600 >> 8);
  245:    rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&ChP->BaudDiv[0]);
  246: 
  247:    ChP->TxControl[0] = (Byte_t)(ChOff + _TX_CTRL);
  248:    ChP->TxControl[1] = (Byte_t)((ChOff + _TX_CTRL) >> 8);
  249:    ChP->TxControl[2] = 0;
  250:    ChP->TxControl[3] = 0;
  251:    rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&ChP->TxControl[0]);
  252: 
  253:    ChP->RxControl[0] = (Byte_t)(ChOff + _RX_CTRL);
  254:    ChP->RxControl[1] = (Byte_t)((ChOff + _RX_CTRL) >> 8);
  255:    ChP->RxControl[2] = 0;
  256:    ChP->RxControl[3] = 0;
  257:    rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&ChP->RxControl[0]);
  258: 
  259:    ChP->TxEnables[0] = (Byte_t)(ChOff + _TX_ENBLS);
  260:    ChP->TxEnables[1] = (Byte_t)((ChOff + _TX_ENBLS) >> 8);
  261:    ChP->TxEnables[2] = 0;
  262:    ChP->TxEnables[3] = 0;
  263:    rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&ChP->TxEnables[0]);
  264: 
  265:    ChP->TxCompare[0] = (Byte_t)(ChOff + _TXCMP1);
  266:    ChP->TxCompare[1] = (Byte_t)((ChOff + _TXCMP1) >> 8);
  267:    ChP->TxCompare[2] = 0;
  268:    ChP->TxCompare[3] = 0;
  269:    rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&ChP->TxCompare[0]);
  270: 
  271:    ChP->TxReplace1[0] = (Byte_t)(ChOff + _TXREP1B1);
  272:    ChP->TxReplace1[1] = (Byte_t)((ChOff + _TXREP1B1) >> 8);
  273:    ChP->TxReplace1[2] = 0;
  274:    ChP->TxReplace1[3] = 0;
  275:    rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&ChP->TxReplace1[0]);
  276: 
  277:    ChP->TxReplace2[0] = (Byte_t)(ChOff + _TXREP2);
  278:    ChP->TxReplace2[1] = (Byte_t)((ChOff + _TXREP2) >> 8);
  279:    ChP->TxReplace2[2] = 0;
  280:    ChP->TxReplace2[3] = 0;
  281:    rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&ChP->TxReplace2[0]);
  282: 
  283:    ChP->TxFIFOPtrs = ChOff + _TXF_OUTP;
  284:    ChP->TxFIFO = ChOff + _TX_FIFO;
  285: 
  286:    rp_writech1(ChP,_CMD_REG,(Byte_t)ChanNum | RESTXFCNT); /* apply reset Tx FIFO count */
  287:    rp_writech1(ChP,_CMD_REG,(Byte_t)ChanNum);  /* remove reset Tx FIFO count */
  288:    rp_writech2(ChP,_INDX_ADDR,ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
  289:    rp_writech2(ChP,_INDX_DATA,0);
  290:    ChP->RxFIFOPtrs = ChOff + _RXF_OUTP;
  291:    ChP->RxFIFO = ChOff + _RX_FIFO;
  292: 
  293:    rp_writech1(ChP,_CMD_REG,(Byte_t)ChanNum | RESRXFCNT); /* apply reset Rx FIFO count */
  294:    rp_writech1(ChP,_CMD_REG,(Byte_t)ChanNum);  /* remove reset Rx FIFO count */
  295:    rp_writech2(ChP,_INDX_ADDR,ChP->RxFIFOPtrs); /* clear Rx out ptr */
  296:    rp_writech2(ChP,_INDX_DATA,0);
  297:    rp_writech2(ChP,_INDX_ADDR,ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
  298:    rp_writech2(ChP,_INDX_DATA,0);
  299:    ChP->TxPrioCnt = ChOff + _TXP_CNT;
  300:    rp_writech2(ChP,_INDX_ADDR,ChP->TxPrioCnt);
  301:    rp_writech1(ChP,_INDX_DATA,0);
  302:    ChP->TxPrioPtr = ChOff + _TXP_PNTR;
  303:    rp_writech2(ChP,_INDX_ADDR,ChP->TxPrioPtr);
  304:    rp_writech1(ChP,_INDX_DATA,0);
  305:    ChP->TxPrioBuf = ChOff + _TXP_BUF;
  306:    sEnRxProcessor(ChP); 	       /* start the Rx processor */
  307: 
  308:    return(TRUE);
  309: }
  310: 
  311: /***************************************************************************
  312: Function: sStopRxProcessor
  313: Purpose:  Stop the receive processor from processing a channel.
  314: Call:	  sStopRxProcessor(ChP)
  315: 	  CHANNEL_T *ChP; Ptr to channel structure
  316: 
  317: Comments: The receive processor can be started again with sStartRxProcessor().
  318: 	  This function causes the receive processor to skip over the
  319: 	  stopped channel.  It does not stop it from processing other channels.
  320: 
  321: Warnings: No context switches are allowed while executing this function.
  322: 
  323: 	  Do not leave the receive processor stopped for more than one
  324: 	  character time.
  325: 
  326: 	  After calling this function a delay of 4 uS is required to ensure
  327: 	  that the receive processor is no longer processing this channel.
  328: */
  329: void sStopRxProcessor(CHANNEL_T *ChP)
  330: {
  331:    Byte_t R[4];
  332: 
  333:    R[0] = ChP->R[0];
  334:    R[1] = ChP->R[1];
  335:    R[2] = 0x0a;
  336:    R[3] = ChP->R[3];
  337:    rp_writech4(ChP, _INDX_ADDR,*(DWord_t *)&R[0]);
  338: }
  339: 
  340: /***************************************************************************
  341: Function: sFlushRxFIFO
  342: Purpose:  Flush the Rx FIFO
  343: Call:	  sFlushRxFIFO(ChP)
  344: 	  CHANNEL_T *ChP; Ptr to channel structure
  345: Return:   void
  346: Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
  347: 	  while it is being flushed the receive processor is stopped
  348: 	  and the transmitter is disabled.  After these operations a
  349: 	  4 uS delay is done before clearing the pointers to allow
  350: 	  the receive processor to stop.  These items are handled inside
  351: 	  this function.
  352: Warnings: No context switches are allowed while executing this function.
  353: */
  354: void sFlushRxFIFO(CHANNEL_T *ChP)
  355: {
  356:    int i;
  357:    Byte_t Ch;			/* channel number within AIOP */
  358:    int RxFIFOEnabled;		       /* TRUE if Rx FIFO enabled */
  359: 
  360:    if(sGetRxCnt(ChP) == 0)	       /* Rx FIFO empty */
  361:       return;			       /* don't need to flush */
  362: 
  363:    RxFIFOEnabled = FALSE;
  364:    if(ChP->R[0x32] == 0x08) /* Rx FIFO is enabled */
  365:    {
  366:       RxFIFOEnabled = TRUE;
  367:       sDisRxFIFO(ChP);		       /* disable it */
  368:       for(i=0; i < 2000/200; i++)	/* delay 2 uS to allow proc to disable FIFO*/
  369: 	 rp_readch1(ChP,_INT_CHAN);		/* depends on bus i/o timing */
  370:    }
  371:    sGetChanStatus(ChP); 	 /* clear any pending Rx errors in chan stat */
  372:    Ch = (Byte_t)sGetChanNum(ChP);
  373:    rp_writech1(ChP,_CMD_REG,Ch | RESRXFCNT);     /* apply reset Rx FIFO count */
  374:    rp_writech1(ChP,_CMD_REG,Ch);		       /* remove reset Rx FIFO count */
  375:    rp_writech2(ChP,_INDX_ADDR,ChP->RxFIFOPtrs); /* clear Rx out ptr */
  376:    rp_writech2(ChP,_INDX_DATA,0);
  377:    rp_writech2(ChP,_INDX_ADDR,ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
  378:    rp_writech2(ChP,_INDX_DATA,0);
  379:    if(RxFIFOEnabled)
  380:       sEnRxFIFO(ChP);		       /* enable Rx FIFO */
  381: }
  382: 
  383: /***************************************************************************
  384: Function: sFlushTxFIFO
  385: Purpose:  Flush the Tx FIFO
  386: Call:	  sFlushTxFIFO(ChP)
  387: 	  CHANNEL_T *ChP; Ptr to channel structure
  388: Return:   void
  389: Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
  390: 	  while it is being flushed the receive processor is stopped
  391: 	  and the transmitter is disabled.  After these operations a
  392: 	  4 uS delay is done before clearing the pointers to allow
  393: 	  the receive processor to stop.  These items are handled inside
  394: 	  this function.
  395: Warnings: No context switches are allowed while executing this function.
  396: */
  397: void sFlushTxFIFO(CHANNEL_T *ChP)
  398: {
  399:    int i;
  400:    Byte_t Ch;			/* channel number within AIOP */
  401:    int TxEnabled;		       /* TRUE if transmitter enabled */
  402: 
  403:    if(sGetTxCnt(ChP) == 0)	       /* Tx FIFO empty */
  404:       return;			       /* don't need to flush */
  405: 
  406:    TxEnabled = FALSE;
  407:    if(ChP->TxControl[3] & TX_ENABLE)
  408:    {
  409:       TxEnabled = TRUE;
  410:       sDisTransmit(ChP);	       /* disable transmitter */
  411:    }
  412:    sStopRxProcessor(ChP);	       /* stop Rx processor */
  413:    for(i = 0; i < 4000/200; i++)	 /* delay 4 uS to allow proc to stop */
  414:       rp_readch1(ChP,_INT_CHAN);	/* depends on bus i/o timing */
  415:    Ch = (Byte_t)sGetChanNum(ChP);
  416:    rp_writech1(ChP,_CMD_REG,Ch | RESTXFCNT);     /* apply reset Tx FIFO count */
  417:    rp_writech1(ChP,_CMD_REG,Ch);		       /* remove reset Tx FIFO count */
  418:    rp_writech2(ChP,_INDX_ADDR,ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
  419:    rp_writech2(ChP,_INDX_DATA,0);
  420:    if(TxEnabled)
  421:       sEnTransmit(ChP); 	       /* enable transmitter */
  422:    sStartRxProcessor(ChP);	       /* restart Rx processor */
  423: }
  424: 
  425: /***************************************************************************
  426: Function: sWriteTxPrioByte
  427: Purpose:  Write a byte of priority transmit data to a channel
  428: Call:	  sWriteTxPrioByte(ChP,Data)
  429: 	  CHANNEL_T *ChP; Ptr to channel structure
  430: 	  Byte_t Data; The transmit data byte
  431: 
  432: Return:   int: 1 if the bytes is successfully written, otherwise 0.
  433: 
  434: Comments: The priority byte is transmitted before any data in the Tx FIFO.
  435: 
  436: Warnings: No context switches are allowed while executing this function.
  437: */
  438: int sWriteTxPrioByte(CHANNEL_T *ChP, Byte_t Data)
  439: {
  440:    Byte_t DWBuf[4];		/* buffer for double word writes */
  441:    Word_t *WordPtr;	     /* must be far because Win SS != DS */
  442: 
  443:    if(sGetTxCnt(ChP) > 1)	       /* write it to Tx priority buffer */
  444:    {
  445:       rp_writech2(ChP,_INDX_ADDR,ChP->TxPrioCnt); /* get priority buffer status */
  446:       if(rp_readch1(ChP,_INDX_DATA) & PRI_PEND) /* priority buffer busy */
  447: 	 return(0);		       /* nothing sent */
  448: 
  449:       WordPtr = (Word_t *)(&DWBuf[0]);
  450:       *WordPtr = ChP->TxPrioBuf;       /* data byte address */
  451: 
  452:       DWBuf[2] = Data;		       /* data byte value */
  453:       rp_writech4(ChP,_INDX_ADDR,*((DWord_t *)(&DWBuf[0]))); /* write it out */
  454: 
  455:       *WordPtr = ChP->TxPrioCnt;       /* Tx priority count address */
  456: 
  457:       DWBuf[2] = PRI_PEND + 1;	       /* indicate 1 byte pending */
  458:       DWBuf[3] = 0;		       /* priority buffer pointer */
  459:       rp_writech4(ChP,_INDX_ADDR,*((DWord_t *)(&DWBuf[0]))); /* write it out */
  460:    }
  461:    else 			       /* write it to Tx FIFO */
  462:    {
  463:       sWriteTxByte(ChP,sGetTxRxDataIO(ChP),Data);
  464:    }
  465:    return(1);			       /* 1 byte sent */
  466: }
  467: 
  468: /***************************************************************************
  469: Function: sEnInterrupts
  470: Purpose:  Enable one or more interrupts for a channel
  471: Call:	  sEnInterrupts(ChP,Flags)
  472: 	  CHANNEL_T *ChP; Ptr to channel structure
  473: 	  Word_t Flags: Interrupt enable flags, can be any combination
  474: 	     of the following flags:
  475: 		TXINT_EN:   Interrupt on Tx FIFO empty
  476: 		RXINT_EN:   Interrupt on Rx FIFO at trigger level (see
  477: 			    sSetRxTrigger())
  478: 		SRCINT_EN:  Interrupt on SRC (Special Rx Condition)
  479: 		MCINT_EN:   Interrupt on modem input change
  480: 		CHANINT_EN: Allow channel interrupt signal to the AIOP's
  481: 			    Interrupt Channel Register.
  482: Return:   void
  483: Comments: If an interrupt enable flag is set in Flags, that interrupt will be
  484: 	  enabled.  If an interrupt enable flag is not set in Flags, that
  485: 	  interrupt will not be changed.  Interrupts can be disabled with
  486: 	  function sDisInterrupts().
  487: 
  488: 	  This function sets the appropriate bit for the channel in the AIOP's
  489: 	  Interrupt Mask Register if the CHANINT_EN flag is set.  This allows
  490: 	  this channel's bit to be set in the AIOP's Interrupt Channel Register.
  491: 
  492: 	  Interrupts must also be globally enabled before channel interrupts
  493: 	  will be passed on to the host.  This is done with function
  494: 	  sEnGlobalInt().
  495: 
  496: 	  In some cases it may be desirable to disable interrupts globally but
  497: 	  enable channel interrupts.  This would allow the global interrupt
  498: 	  status register to be used to determine which AIOPs need service.
  499: */
  500: void sEnInterrupts(CHANNEL_T *ChP,Word_t Flags)
  501: {
  502:    Byte_t Mask; 		/* Interrupt Mask Register */
  503: 
  504:    ChP->RxControl[2] |=
  505:       ((Byte_t)Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
  506: 
  507:    rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&ChP->RxControl[0]);
  508: 
  509:    ChP->TxControl[2] |= ((Byte_t)Flags & TXINT_EN);
  510: 
  511:    rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&ChP->TxControl[0]);
  512: 
  513:    if(Flags & CHANINT_EN)
  514:    {
  515:       Mask = rp_readch1(ChP,_INT_MASK) | rp_sBitMapSetTbl[ChP->ChanNum];
  516:       rp_writech1(ChP,_INT_MASK,Mask);
  517:    }
  518: }
  519: 
  520: /***************************************************************************
  521: Function: sDisInterrupts
  522: Purpose:  Disable one or more interrupts for a channel
  523: Call:	  sDisInterrupts(ChP,Flags)
  524: 	  CHANNEL_T *ChP; Ptr to channel structure
  525: 	  Word_t Flags: Interrupt flags, can be any combination
  526: 	     of the following flags:
  527: 		TXINT_EN:   Interrupt on Tx FIFO empty
  528: 		RXINT_EN:   Interrupt on Rx FIFO at trigger level (see
  529: 			    sSetRxTrigger())
  530: 		SRCINT_EN:  Interrupt on SRC (Special Rx Condition)
  531: 		MCINT_EN:   Interrupt on modem input change
  532: 		CHANINT_EN: Disable channel interrupt signal to the
  533: 			    AIOP's Interrupt Channel Register.
  534: Return:   void
  535: Comments: If an interrupt flag is set in Flags, that interrupt will be
  536: 	  disabled.  If an interrupt flag is not set in Flags, that
  537: 	  interrupt will not be changed.  Interrupts can be enabled with
  538: 	  function sEnInterrupts().
  539: 
  540: 	  This function clears the appropriate bit for the channel in the AIOP's
  541: 	  Interrupt Mask Register if the CHANINT_EN flag is set.  This blocks
  542: 	  this channel's bit from being set in the AIOP's Interrupt Channel
  543: 	  Register.
  544: */
  545: void sDisInterrupts(CHANNEL_T *ChP,Word_t Flags)
  546: {
  547:    Byte_t Mask; 		/* Interrupt Mask Register */
  548: 
  549:    ChP->RxControl[2] &=
  550: 	 ~((Byte_t)Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
  551:    rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&ChP->RxControl[0]);
  552:    ChP->TxControl[2] &= ~((Byte_t)Flags & TXINT_EN);
  553:    rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&ChP->TxControl[0]);
  554: 
  555:    if(Flags & CHANINT_EN)
  556:    {
  557:       Mask = rp_readch1(ChP,_INT_MASK) & rp_sBitMapClrTbl[ChP->ChanNum];
  558:       rp_writech1(ChP,_INT_MASK,Mask);
  559:    }
  560: }
  561: 
  562: /*********************************************************************
  563:   Begin FreeBsd-specific driver code
  564: **********************************************************************/
  565: 
  566: static timeout_t rpdtrwakeup;
  567: 
  568: static	d_open_t	rpopen;
  569: static	d_close_t	rpclose;
  570: static	d_write_t	rpwrite;
  571: static	d_ioctl_t	rpioctl;
  572: 
  573: #define	CDEV_MAJOR	81
  574: struct cdevsw rp_cdevsw = {
  575: 	/* name */	"rp",
  576: 	/* maj */	CDEV_MAJOR,
  577: 	/* flags */	D_TTY,
  578: 	/* port */	NULL,
  579: 	/* clone */	NULL,
  580: 
  581: 	/* open */	rpopen,
  582: 	/* close */	rpclose,
  583: 	/* read */	ttyread,
  584: 	/* write */	rpwrite,
  585: 	/* ioctl */	rpioctl,
  586: 	/* poll */	ttypoll,
  587: 	/* mmap */	nommap,
  588: 	/* strategy */	nostrategy,
  589: 	/* dump */	nodump,
  590: 	/* psize */	nopsize
  591: };
  592: 
  593: static int	rp_num_ports_open = 0;
  594: static int	rp_ndevs = 0;
  595: static int	minor_to_unit[128];
  596: 
  597: static int rp_num_ports[4];	/* Number of ports on each controller */
  598: 
  599: #define _INLINE_ __inline
  600: #define POLL_INTERVAL 1
  601: 
  602: #define CALLOUT_MASK		0x80
  603: #define CONTROL_MASK		0x60
  604: #define CONTROL_INIT_STATE	0x20
  605: #define CONTROL_LOCK_STATE	0x40
  606: #define DEV_UNIT(dev)	(MINOR_TO_UNIT(minor(dev))
  607: #define MINOR_MAGIC_MASK	(CALLOUT_MASK | CONTROL_MASK)
  608: #define MINOR_MAGIC(dev)	((minor(dev)) & ~MINOR_MAGIC_MASK)
  609: #define IS_CALLOUT(dev) 	(minor(dev) & CALLOUT_MASK)
  610: #define IS_CONTROL(dev) 	(minor(dev) & CONTROL_MASK)
  611: 
  612: #define RP_ISMULTIPORT(dev)	((dev)->id_flags & 0x1)
  613: #define RP_MPMASTER(dev)	(((dev)->id_flags >> 8) & 0xff)
  614: #define RP_NOTAST4(dev) 	((dev)->id_flags & 0x04)
  615: 
  616: static	struct	rp_port *p_rp_addr[4];
  617: static	struct	rp_port *p_rp_table[MAX_RP_PORTS];
  618: #define rp_addr(unit)	(p_rp_addr[unit])
  619: #define rp_table(port)	(p_rp_table[port])
  620: 
  621: /*
  622:  * The top-level routines begin here
  623:  */
  624: 
  625: static	int	rpparam (struct tty *, struct termios *);
  626: static	void	rpstart (struct tty *);
  627: static	void	rpstop (struct tty *, int);
  628: static	void	rphardclose	(struct rp_port *);
  629: static	void	rp_disc_optim	(struct tty *tp, struct termios *t);
  630: 
  631: static _INLINE_ void rp_do_receive(struct rp_port *rp, struct tty *tp,
  632: 			CHANNEL_t *cp, unsigned int ChanStatus)
  633: {
  634: 	int	spl;
  635: 	unsigned	int	CharNStat;
  636: 	int	ToRecv, wRecv, ch, ttynocopy;
  637: 
  638: 	ToRecv = sGetRxCnt(cp);
  639: 	if(ToRecv == 0)
  640: 		return;
  641: 
  642: /*	If status indicates there are errored characters in the
  643: 	FIFO, then enter status mode (a word in FIFO holds
  644: 	characters and status)
  645: */
  646: 
  647: 	if(ChanStatus & (RXFOVERFL | RXBREAK | RXFRAME | RXPARITY)) {
  648: 		if(!(ChanStatus & STATMODE)) {
  649: 			ChanStatus |= STATMODE;
  650: 			sEnRxStatusMode(cp);
  651: 		}
  652: 	}
  653: /*
  654: 	if we previously entered status mode then read down the
  655: 	FIFO one word at a time, pulling apart the character and
  656: 	the status. Update error counters depending on status.
  657: */
  658: 	if(ChanStatus & STATMODE) {
  659: 		while(ToRecv) {
  660: 			if(tp->t_state & TS_TBLOCK) {
  661: 				break;
  662: 			}
  663: 			CharNStat = rp_readch2(cp,sGetTxRxDataIO(cp));
  664: 			ch = CharNStat & 0xff;
  665: 
  666: 			if((CharNStat & STMBREAK) || (CharNStat & STMFRAMEH))
  667: 				ch |= TTY_FE;
  668: 			else if (CharNStat & STMPARITYH)
  669: 				ch |= TTY_PE;
  670: 			else if (CharNStat & STMRCVROVRH)
  671: 				rp->rp_overflows++;
  672: 
  673: 			(*linesw[tp->t_line].l_rint)(ch, tp);
  674: 			ToRecv--;
  675: 		}
  676: /*
  677: 	After emtying FIFO in status mode, turn off status mode
  678: */
  679: 
  680: 		if(sGetRxCnt(cp) == 0) {
  681: 			sDisRxStatusMode(cp);
  682: 		}
  683: 	} else {
  684: 		/*
  685: 		 * Avoid the grotesquely inefficient lineswitch routine
  686: 		 * (ttyinput) in "raw" mode.  It usually takes about 450
  687: 		 * instructions (that's without canonical processing or echo!).
  688: 		 * slinput is reasonably fast (usually 40 instructions plus
  689: 		 * call overhead).
  690: 		 */
  691: 		ToRecv = sGetRxCnt(cp);
  692: 		if ( tp->t_state & TS_CAN_BYPASS_L_RINT ) {
  693: 			if ( ToRecv > RXFIFO_SIZE ) {
  694: 				ToRecv = RXFIFO_SIZE;
  695: 			}
  696: 			wRecv = ToRecv >> 1;
  697: 			if ( wRecv ) {
  698: 				rp_readmultich2(cp,sGetTxRxDataIO(cp),(u_int16_t *)rp->RxBuf,wRecv);
  699: 			}
  700: 			if ( ToRecv & 1 ) {
  701: 				((unsigned char *)rp->RxBuf)[(ToRecv-1)] = (u_char) rp_readch1(cp,sGetTxRxDataIO(cp));
  702: 			}
  703: 			tk_nin += ToRecv;
  704: 			tk_rawcc += ToRecv;
  705: 			tp->t_rawcc += ToRecv;
  706: 			ttynocopy = b_to_q((char *)rp->RxBuf, ToRecv, &tp->t_rawq);
  707: 			ttwakeup(tp);
  708: 		} else {
  709: 			while (ToRecv) {
  710: 				if(tp->t_state & TS_TBLOCK) {
  711: 					break;
  712: 				}
  713: 				ch = (u_char) rp_readch1(cp,sGetTxRxDataIO(cp));
  714: 				spl = spltty();
  715: 				(*linesw[tp->t_line].l_rint)(ch, tp);
  716: 				splx(spl);
  717: 				ToRecv--;
  718: 			}
  719: 		}
  720: 	}
  721: }
  722: 
  723: static _INLINE_ void rp_handle_port(struct rp_port *rp)
  724: {
  725: 	CHANNEL_t	*cp;
  726: 	struct	tty	*tp;
  727: 	unsigned	int	IntMask, ChanStatus;
  728: 
  729: 	if(!rp)
  730: 		return;
  731: 
  732: 	cp = &rp->rp_channel;
  733: 	tp = rp->rp_tty;
  734: 	IntMask = sGetChanIntID(cp);
  735: 	IntMask = IntMask & rp->rp_intmask;
  736: 	ChanStatus = sGetChanStatus(cp);
  737: 	if(IntMask & RXF_TRIG)
  738: 		if(!(tp->t_state & TS_TBLOCK) && (tp->t_state & TS_CARR_ON) && (tp->t_state & TS_ISOPEN)) {
  739: 			rp_do_receive(rp, tp, cp, ChanStatus);
  740: 		}
  741: 	if(IntMask & DELTA_CD) {
  742: 		if(ChanStatus & CD_ACT) {
  743: 			if(!(tp->t_state & TS_CARR_ON) ) {
  744: 				(void)(*linesw[tp->t_line].l_modem)(tp, 1);
  745: 			}
  746: 		} else {
  747: 			if((tp->t_state & TS_CARR_ON)) {
  748: 				(void)(*linesw[tp->t_line].l_modem)(tp, 0);
  749: 				if((*linesw[tp->t_line].l_modem)(tp, 0) == 0) {
  750: 					rphardclose(rp);
  751: 				}
  752: 			}
  753: 		}
  754: 	}
  755: /*	oldcts = rp->rp_cts;
  756: 	rp->rp_cts = ((ChanStatus & CTS_ACT) != 0);
  757: 	if(oldcts != rp->rp_cts) {
  758: 		printf("CTS change (now %s)... on port %d\n", rp->rp_cts ? "on" : "off", rp->rp_port);
  759: 	}
  760: */
  761: }
  762: 
  763: static void rp_do_poll(void *not_used)
  764: {
  765: 	CONTROLLER_t	*ctl;
  766: 	struct rp_port	*rp;
  767: 	struct tty	*tp;
  768: 	int	unit, aiop, ch, line, count;
  769: 	unsigned char	CtlMask, AiopMask;
  770: 
  771: 	for(unit = 0; unit < rp_ndevs; unit++) {
  772: 	rp = rp_addr(unit);
  773: 	ctl = rp->rp_ctlp;
  774: 	CtlMask = ctl->ctlmask(ctl);
  775: 	for(aiop=0; CtlMask; CtlMask >>=1, aiop++) {
  776: 		if(CtlMask & 1) {
  777: 			AiopMask = sGetAiopIntStatus(ctl, aiop);
  778: 			for(ch = 0; AiopMask; AiopMask >>=1, ch++) {
  779: 				if(AiopMask & 1) {
  780: 					line = (unit << 5) | (aiop << 3) | ch;
  781: 					rp = rp_table(line);
  782: 					rp_handle_port(rp);
  783: 				}
  784: 			}
  785: 		}
  786: 	}
  787: 
  788: 	for(line = 0, rp = rp_addr(unit); line < rp_num_ports[unit];
  789: 			line++, rp++) {
  790: 		tp = rp->rp_tty;
  791: 		if((tp->t_state & TS_BUSY) && (tp->t_state & TS_ISOPEN)) {
  792: 			count = sGetTxCnt(&rp->rp_channel);
  793: 			if(count == 0)
  794: 				tp->t_state &= ~(TS_BUSY);
  795: 			if(!(tp->t_state & TS_TTSTOP) &&
  796: 				(count <= rp->rp_restart)) {
  797: 				(*linesw[tp->t_line].l_start)(tp);
  798: 			}
  799: 		}
  800: 	}
  801: 	}
  802: 	if(rp_num_ports_open)
  803: 		timeout(rp_do_poll, (void *)NULL, POLL_INTERVAL);
  804: }
  805: 
  806: int
  807: rp_attachcommon(CONTROLLER_T *ctlp, int num_aiops, int num_ports)
  808: {
  809: 	int	oldspl, unit;
  810: 	int	num_chan;
  811: 	int	aiop, chan, port;
  812: 	int	ChanStatus, line, i, count;
  813: 	int	retval;
  814: 	struct	rp_port *rp;
  815: 	struct	tty	*tty;
  816: 
  817: 	unit = device_get_unit(ctlp->dev);
  818: 
  819: 	printf("RocketPort%d (Version %s) %d ports.\n", unit,
  820: 		RocketPortVersion, num_ports);
  821: 	rp_num_ports[unit] = num_ports;
  822: 
  823: 	ctlp->rp = rp = (struct rp_port *)
  824: 		malloc(sizeof(struct rp_port) * num_ports, M_TTYS, M_NOWAIT);
  825: 	if (rp == NULL) {
  826: 		device_printf(ctlp->dev, "rp_attachcommon: Could not malloc rp_ports structures.\n");
  827: 		retval = ENOMEM;
  828: 		goto nogo;
  829: 	}
  830: 
  831: 	count = unit * 32;      /* board times max ports per card SG */
  832: 	for(i=count;i < (count + rp_num_ports[unit]);i++)
  833: 		minor_to_unit[i] = unit;
  834: 
  835: 	bzero(rp, sizeof(struct rp_port) * num_ports);
  836: 	ctlp->tty = tty = (struct tty *)
  837: 		malloc(sizeof(struct tty) * num_ports, M_TTYS,
  838: 			M_NOWAIT | M_ZERO);
  839: 	if(tty == NULL) {
  840: 		device_printf(ctlp->dev, "rp_attachcommon: Could not malloc tty structures.\n");
  841: 		retval = ENOMEM;
  842: 		goto nogo;
  843: 	}
  844: 
  845: 	oldspl = spltty();
  846: 	rp_addr(unit) = rp;
  847: 	splx(oldspl);
  848: 
  849: 	cdevsw_add(&rp_cdevsw, 0xffff0000, (unit + 1) << 16);
  850: 	for (i = 0 ; i < rp_num_ports[unit] ; i++) {
  851: 		make_dev(&rp_cdevsw, ((unit + 1) << 16) | i,
  852: 			  UID_ROOT, GID_WHEEL, 0666, "ttyR%c",
  853: 			  i <= 9 ? '0' + i : 'a' + i - 10);
  854: 		make_dev(&rp_cdevsw, ((unit + 1) << 16) | i | 0x20,
  855: 			  UID_ROOT, GID_WHEEL, 0666, "ttyiR%c",
  856: 			  i <= 9 ? '0' + i : 'a' + i - 10);
  857: 		make_dev(&rp_cdevsw, ((unit + 1) << 16) | i | 0x40,
  858: 			  UID_ROOT, GID_WHEEL, 0666, "ttylR%c",
  859: 			  i <= 9 ? '0' + i : 'a' + i - 10);
  860: 		make_dev(&rp_cdevsw, ((unit + 1) << 16) | i | 0x80,
  861: 			  UID_ROOT, GID_WHEEL, 0666, "cuaR%c",
  862: 			  i <= 9 ? '0' + i : 'a' + i - 10);
  863: 		make_dev(&rp_cdevsw, ((unit + 1) << 16) | i | 0xa0,
  864: 			  UID_ROOT, GID_WHEEL, 0666, "cuaiR%c",
  865: 			  i <= 9 ? '0' + i : 'a' + i - 10);
  866: 		make_dev(&rp_cdevsw, ((unit + 1) << 16) | i | 0xc0,
  867: 			  UID_ROOT, GID_WHEEL, 0666, "cualR%c",
  868: 			  i <= 9 ? '0' + i : 'a' + i - 10);
  869: 	}
  870: 
  871: 	port = 0;
  872: 	for(aiop=0; aiop < num_aiops; aiop++) {
  873: 		num_chan = sGetAiopNumChan(ctlp, aiop);
  874: 		for(chan=0; chan < num_chan; chan++, port++, rp++, tty++) {
  875: 			rp->rp_tty = tty;
  876: 			rp->rp_port = port;
  877: 			rp->rp_ctlp = ctlp;
  878: 			rp->rp_unit = unit;
  879: 			rp->rp_chan = chan;
  880: 			rp->rp_aiop = aiop;
  881: 
  882: 			tty->t_line = 0;
  883: 	/*		tty->t_termios = deftermios;
  884: 	*/
  885: 			rp->dtr_wait = 3 * hz;
  886: 			rp->it_in.c_iflag = 0;
  887: 			rp->it_in.c_oflag = 0;
  888: 			rp->it_in.c_cflag = TTYDEF_CFLAG;
  889: 			rp->it_in.c_lflag = 0;
  890: 			termioschars(&rp->it_in);
  891: 	/*		termioschars(&tty->t_termios);
  892: 	*/
  893: 			rp->it_in.c_ispeed = rp->it_in.c_ospeed = TTYDEF_SPEED;
  894: 			rp->it_out = rp->it_in;
  895: 
  896: 			rp->rp_intmask = RXF_TRIG | TXFIFO_MT | SRC_INT |
  897: 				DELTA_CD | DELTA_CTS | DELTA_DSR;
  898: #if notdef
  899: 			ChanStatus = sGetChanStatus(&rp->rp_channel);
  900: #endif /* notdef */
  901: 			if(sInitChan(ctlp, &rp->rp_channel, aiop, chan) == 0) {
  902: 				device_printf(ctlp->dev, "RocketPort sInitChan(%d, %d, %d) failed.\n",
  903: 					      unit, aiop, chan);
  904: 				retval = ENXIO;
  905: 				goto nogo;
  906: 			}
  907: 			ChanStatus = sGetChanStatus(&rp->rp_channel);
  908: 			rp->rp_cts = (ChanStatus & CTS_ACT) != 0;
  909: 			line = (unit << 5) | (aiop << 3) | chan;
  910: 			rp_table(line) = rp;
  911: 		}
  912: 	}
  913: 
  914: 	rp_ndevs++;
  915: 	return (0);
  916: 
  917: nogo:
  918: 	rp_releaseresource(ctlp);
  919: 
  920: 	return (retval);
  921: }
  922: 
  923: void
  924: rp_releaseresource(CONTROLLER_t *ctlp)
  925: {
  926: 	int i, s, unit;
  927: 
  928: 	unit = device_get_unit(ctlp->dev);
  929: 
  930: 	if (ctlp->rp != NULL) {
  931: 		s = spltty();
  932: 		for (i = 0 ; i < sizeof(p_rp_addr) / sizeof(*p_rp_addr) ; i++)
  933: 			if (p_rp_addr[i] == ctlp->rp)
  934: 				p_rp_addr[i] = NULL;
  935: 		for (i = 0 ; i < sizeof(p_rp_table) / sizeof(*p_rp_table) ; i++)
  936: 			if (p_rp_table[i] == ctlp->rp)
  937: 				p_rp_table[i] = NULL;
  938: 		splx(s);
  939: 		free(ctlp->rp, M_DEVBUF);
  940: 		ctlp->rp = NULL;
  941: 	}
  942: 	if (ctlp->tty != NULL) {
  943: 		free(ctlp->tty, M_DEVBUF);
  944: 		ctlp->tty = NULL;
  945: 	}
  946: 	if (ctlp->dev != NULL)
  947: 		ctlp->dev = NULL;
  948: 	cdevsw_remove(&rp_cdevsw, 0xffff0000, (unit + 1) << 16);
  949: }
  950: 
  951: int
  952: rpopen(dev_t dev, int flag, int mode, d_thread_t *td)
  953: {
  954: 	struct	rp_port *rp;
  955: 	int	unit, port, mynor, umynor, flags;  /* SG */
  956: 	struct	tty	*tp;
  957: 	int	oldspl, error;
  958: 	unsigned int	IntMask, ChanStatus;
  959: 
  960:    umynor = (((minor(dev) >> 16) -1) * 32);    /* SG */
  961: 	port  = (minor(dev) & 0x1f);                /* SG */
  962: 	mynor = (port + umynor);                    /* SG */
  963: 	unit = minor_to_unit[mynor];
  964: 	if (rp_addr(unit) == NULL)
  965: 		return (ENXIO);
  966: 	if(IS_CONTROL(dev))
  967: 		return(0);
  968: 	rp = rp_addr(unit) + port;
  969: /*	rp->rp_tty = &rp_tty[rp->rp_port];
  970: */
  971: 	tp = rp->rp_tty;
  972: 	dev->si_tty = tp;
  973: 
  974: 	oldspl = spltty();
  975: 
  976: open_top:
  977: 	while(rp->state & ~SET_DTR) {
  978: 		error = tsleep(&rp->dtr_wait, PCATCH, "rpdtr", 0);
  979: 		if(error != 0)
  980: 			goto out;
  981: 	}
  982: 
  983: 	if(tp->t_state & TS_ISOPEN) {
  984: 		if(IS_CALLOUT(dev)) {
  985: 			if(!rp->active_out) {
  986: 				error = EBUSY;
  987: 				goto out;
  988: 			}
  989: 		} else {
  990: 			if(rp->active_out) {
  991: 				if(flag & O_NONBLOCK) {
  992: 					error = EBUSY;
  993: 					goto out;
  994: 				}
  995: 				error = tsleep(&rp->active_out,
  996: 					    PCATCH, "rpbi", 0);
  997: 				if(error != 0)
  998: 					goto out;
  999: 				goto open_top;
 1000: 			}
 1001: 		}
 1002: 		if(tp->t_state & TS_XCLUDE && suser(td) != 0) {
 1003: 			splx(oldspl);
 1004: 			error = EBUSY;
 1005: 			goto out2;
 1006: 		}
 1007: 	}
 1008: 	else {
 1009: 		tp->t_dev = dev;
 1010: 		tp->t_param = rpparam;
 1011: 		tp->t_oproc = rpstart;
 1012: 		tp->t_stop = rpstop;
 1013: 		tp->t_line = 0;
 1014: 		tp->t_termios = IS_CALLOUT(dev) ? rp->it_out : rp->it_in;
 1015: 		tp->t_ififosize = 512;
 1016: 		tp->t_ispeedwat = (speed_t)-1;
 1017: 		tp->t_ospeedwat = (speed_t)-1;
 1018: 		flags = 0;
 1019: 		flags |= SET_RTS;
 1020: 		flags |= SET_DTR;
 1021: 		rp->rp_channel.TxControl[3] =
 1022: 			((rp->rp_channel.TxControl[3]
 1023: 			& ~(SET_RTS | SET_DTR)) | flags);
 1024: 		rp_writech4(&rp->rp_channel,_INDX_ADDR,
 1025: 			*(DWord_t *) &(rp->rp_channel.TxControl[0]));
 1026: 		sSetRxTrigger(&rp->rp_channel, TRIG_1);
 1027: 		sDisRxStatusMode(&rp->rp_channel);
 1028: 		sFlushRxFIFO(&rp->rp_channel);
 1029: 		sFlushTxFIFO(&rp->rp_channel);
 1030: 
 1031: 		sEnInterrupts(&rp->rp_channel,
 1032: 			(TXINT_EN|MCINT_EN|RXINT_EN|SRCINT_EN|CHANINT_EN));
 1033: 		sSetRxTrigger(&rp->rp_channel, TRIG_1);
 1034: 
 1035: 		sDisRxStatusMode(&rp->rp_channel);
 1036: 		sClrTxXOFF(&rp->rp_channel);
 1037: 
 1038: /*		sDisRTSFlowCtl(&rp->rp_channel);
 1039: 		sDisCTSFlowCtl(&rp->rp_channel);
 1040: */
 1041: 		sDisTxSoftFlowCtl(&rp->rp_channel);
 1042: 
 1043: 		sStartRxProcessor(&rp->rp_channel);
 1044: 
 1045: 		sEnRxFIFO(&rp->rp_channel);
 1046: 		sEnTransmit(&rp->rp_channel);
 1047: 
 1048: /*		sSetDTR(&rp->rp_channel);
 1049: 		sSetRTS(&rp->rp_channel);
 1050: */
 1051: 
 1052: 		++rp->wopeners;
 1053: 		error = rpparam(tp, &tp->t_termios);
 1054: 		--rp->wopeners;
 1055: 		if(error != 0) {
 1056: 			splx(oldspl);
 1057: 			return(error);
 1058: 		}
 1059: 
 1060: 		rp_num_ports_open++;
 1061: 
 1062: 		IntMask = sGetChanIntID(&rp->rp_channel);
 1063: 		IntMask = IntMask & rp->rp_intmask;
 1064: 		ChanStatus = sGetChanStatus(&rp->rp_channel);
 1065: 		if((IntMask & DELTA_CD) || IS_CALLOUT(dev)) {
 1066: 			if((ChanStatus & CD_ACT) || IS_CALLOUT(dev)) {
 1067: 					(void)(*linesw[tp->t_line].l_modem)(tp, 1);
 1068: 			}
 1069: 		}
 1070: 
 1071: 	if(rp_num_ports_open == 1)
 1072: 		timeout(rp_do_poll, (void *)NULL, POLL_INTERVAL);
 1073: 
 1074: 	}
 1075: 
 1076: 	if(!(flag&O_NONBLOCK) && !(tp->t_cflag&CLOCAL) &&
 1077: 		!(tp->t_state & TS_CARR_ON) && !(IS_CALLOUT(dev))) {
 1078: 		++rp->wopeners;
 1079: 		error = tsleep(TSA_CARR_ON(tp), PCATCH, "rpdcd", 0);
 1080: 		--rp->wopeners;
 1081: 		if(error != 0)
 1082: 			goto out;
 1083: 		goto open_top;
 1084: 	}
 1085: 	error = (*linesw[tp->t_line].l_open)(dev, tp);
 1086: 
 1087: 	rp_disc_optim(tp, &tp->t_termios);
 1088: 	if(tp->t_state & TS_ISOPEN && IS_CALLOUT(dev))
 1089: 		rp->active_out = TRUE;
 1090: 
 1091: /*	if(rp_num_ports_open == 1)
 1092: 		timeout(rp_do_poll, (void *)NULL, POLL_INTERVAL);
 1093: */
 1094: out:
 1095: 	splx(oldspl);
 1096: 	if(!(tp->t_state & TS_ISOPEN) && rp->wopeners == 0) {
 1097: 		rphardclose(rp);
 1098: 	}
 1099: out2:
 1100: 	if (error == 0)
 1101: 		device_busy(rp->rp_ctlp->dev);
 1102: 	return(error);
 1103: }
 1104: 
 1105: int
 1106: rpclose(dev_t dev, int flag, int mode, d_thread_t *td)
 1107: {
 1108: 	int	oldspl, unit, mynor, umynor, port; /* SG */
 1109: 	struct	rp_port *rp;
 1110: 	struct	tty	*tp;
 1111: 	CHANNEL_t	*cp;
 1112: 
 1113:    umynor = (((minor(dev) >> 16) -1) * 32);    /* SG */
 1114: 	port  = (minor(dev) & 0x1f);                /* SG */
 1115: 	mynor = (port + umynor);                    /* SG */
 1116:    unit = minor_to_unit[mynor];                /* SG */
 1117: 
 1118: 	if(IS_CONTROL(dev))
 1119: 		return(0);
 1120: 	rp = rp_addr(unit) + port;
 1121: 	cp = &rp->rp_channel;
 1122: 	tp = rp->rp_tty;
 1123: 
 1124: 	oldspl = spltty();
 1125: 	(*linesw[tp->t_line].l_close)(tp, flag);
 1126: 	rp_disc_optim(tp, &tp->t_termios);
 1127: 	rpstop(tp, FREAD | FWRITE);
 1128: 	rphardclose(rp);
 1129: 
 1130: 	tp->t_state &= ~TS_BUSY;
 1131: 	ttyclose(tp);
 1132: 
 1133: 	splx(oldspl);
 1134: 
 1135: 	device_unbusy(rp->rp_ctlp->dev);
 1136: 
 1137: 	return(0);
 1138: }
 1139: 
 1140: static void
 1141: rphardclose(struct rp_port *rp)
 1142: {
 1143: 	int	mynor;
 1144: 	struct	tty	*tp;
 1145: 	CHANNEL_t	*cp;
 1146: 
 1147: 	cp = &rp->rp_channel;
 1148: 	tp = rp->rp_tty;
 1149: 	mynor = MINOR_MAGIC(tp->t_dev);
 1150: 
 1151: 	sFlushRxFIFO(cp);
 1152: 	sFlushTxFIFO(cp);
 1153: 	sDisTransmit(cp);
 1154: 	sDisInterrupts(cp, TXINT_EN|MCINT_EN|RXINT_EN|SRCINT_EN|CHANINT_EN);
 1155: 	sDisRTSFlowCtl(cp);
 1156: 	sDisCTSFlowCtl(cp);
 1157: 	sDisTxSoftFlowCtl(cp);
 1158: 	sClrTxXOFF(cp);
 1159: 
 1160: 	if(tp->t_cflag&HUPCL || !(tp->t_state&TS_ISOPEN) || !rp->active_out) {
 1161: 		sClrDTR(cp);
 1162: 	}
 1163: 	if(IS_CALLOUT(tp->t_dev)) {
 1164: 		sClrDTR(cp);
 1165: 	}
 1166: 	if(rp->dtr_wait != 0) {
 1167: 		timeout(rpdtrwakeup, rp, rp->dtr_wait);
 1168: 		rp->state |= ~SET_DTR;
 1169: 	}
 1170: 
 1171: 	rp->active_out = FALSE;
 1172: 	wakeup(&rp->active_out);
 1173: 	wakeup(TSA_CARR_ON(tp));
 1174: }
 1175: 
 1176: static
 1177: int
 1178: rpwrite(dev, uio, flag)
 1179: 	dev_t	dev;
 1180: 	struct	uio	*uio;
 1181: 	int	flag;
 1182: {
 1183: 	struct	rp_port *rp;
 1184: 	struct	tty	*tp;
 1185: 	int	unit, mynor, port, umynor, error = 0; /* SG */
 1186: 
 1187:    umynor = (((minor(dev) >> 16) -1) * 32);    /* SG */
 1188: 	port  = (minor(dev) & 0x1f);                /* SG */
 1189: 	mynor = (port + umynor);                    /* SG */
 1190:    unit = minor_to_unit[mynor];                /* SG */
 1191: 
 1192: 	if(IS_CONTROL(dev))
 1193: 		return(ENODEV);
 1194: 	rp = rp_addr(unit) + port;
 1195: 	tp = rp->rp_tty;
 1196: 	while(rp->rp_disable_writes) {
 1197: 		rp->rp_waiting = 1;
 1198: 		error = ttysleep(tp, (caddr_t)rp, PCATCH, "rp_write", 0);
 1199: 		if (error)
 1200: 			return(error);
 1201: 	}
 1202: 
 1203: 	error = (*linesw[tp->t_line].l_write)(tp, uio, flag);
 1204: 	return error;
 1205: }
 1206: 
 1207: static void
 1208: rpdtrwakeup(void *chan)
 1209: {
 1210: 	struct	rp_port *rp;
 1211: 
 1212: 	rp = (struct rp_port *)chan;
 1213: 	rp->state &= SET_DTR;
 1214: 	wakeup(&rp->dtr_wait);
 1215: }
 1216: 
 1217: int
 1218: rpioctl(dev_t dev, u_long cmd, caddr_t data, int flag, d_thread_t *td)
 1219: {
 1220: 	struct rp_port	*rp;
 1221: 	CHANNEL_t	*cp;
 1222: 	struct tty	*tp;
 1223: 	int	unit, mynor, port, umynor;            /* SG */
 1224: 	int	oldspl;
 1225: 	int	error = 0;
 1226: 	int	arg, flags, result, ChanStatus;
 1227: 	struct	termios *t;
 1228: 
 1229:    umynor = (((minor(dev) >> 16) -1) * 32);    /* SG */
 1230: 	port  = (minor(dev) & 0x1f);                /* SG */
 1231: 	mynor = (port + umynor);                    /* SG */
 1232: 	unit = minor_to_unit[mynor];
 1233: 	rp = rp_addr(unit) + port;
 1234: 
 1235: 	if(IS_CONTROL(dev)) {
 1236: 		struct	termios *ct;
 1237: 
 1238: 		switch (IS_CONTROL(dev)) {
 1239: 		case CONTROL_INIT_STATE:
 1240: 			ct =  IS_CALLOUT(dev) ? &rp->it_out : &rp->it_in;
 1241: 			break;
 1242: 		case CONTROL_LOCK_STATE:
 1243: 			ct =  IS_CALLOUT(dev) ? &rp->lt_out : &rp->lt_in;
 1244: 			break;
 1245: 		default:
 1246: 			return(ENODEV); 	/* /dev/nodev */
 1247: 		}
 1248: 		switch (cmd) {
 1249: 		case TIOCSETA:
 1250: 			error = suser(td);
 1251: 			if(error != 0)
 1252: 				return(error);
 1253: 			*ct = *(struct termios *)data;
 1254: 			return(0);
 1255: 		case TIOCGETA:
 1256: 			*(struct termios *)data = *ct;
 1257: 			return(0);
 1258: 		case TIOCGETD:
 1259: 			*(int *)data = TTYDISC;
 1260: 			return(0);
 1261: 		case TIOCGWINSZ:
 1262: 			bzero(data, sizeof(struct winsize));
 1263: 			return(0);
 1264: 		default:
 1265: 			return(ENOTTY);
 1266: 		}
 1267: 	}
 1268: 
 1269: 	tp = rp->rp_tty;
 1270: 	cp = &rp->rp_channel;
 1271: 
 1272: #if defined(COMPAT_43) || defined(COMPAT_SUNOS)
 1273: 	term = tp->t_termios;
 1274: 	oldcmd = cmd;
 1275: 	error = ttsetcompat(tp, &cmd, data, &term);
 1276: 	if(error != 0)
 1277: 		return(error);
 1278: 	if(cmd != oldcmd) {
 1279: 		data = (caddr_t)&term;
 1280: 	}
 1281: #endif
 1282: 	if((cmd == TIOCSETA) || (cmd == TIOCSETAW) || (cmd == TIOCSETAF)) {
 1283: 		int	cc;
 1284: 		struct	termios *dt = (struct termios *)data;
 1285: 		struct	termios *lt = IS_CALLOUT(dev)
 1286: 					? &rp->lt_out : &rp->lt_in;
 1287: 
 1288: 		dt->c_iflag = (tp->t_iflag & lt->c_iflag)
 1289: 				| (dt->c_iflag & ~lt->c_iflag);
 1290: 		dt->c_oflag = (tp->t_oflag & lt->c_oflag)
 1291: 				| (dt->c_oflag & ~lt->c_oflag);
 1292: 		dt->c_cflag = (tp->t_cflag & lt->c_cflag)
 1293: 				| (dt->c_cflag & ~lt->c_cflag);
 1294: 		dt->c_lflag = (tp->t_lflag & lt->c_lflag)
 1295: 				| (dt->c_lflag & ~lt->c_lflag);
 1296: 		for(cc = 0; cc < NCCS; ++cc)
 1297: 			if(lt->c_cc[cc] != 0)
 1298: 				dt->c_cc[cc] = tp->t_cc[cc];
 1299: 		if(lt->c_ispeed != 0)
 1300: 			dt->c_ispeed = tp->t_ispeed;
 1301: 		if(lt->c_ospeed != 0)
 1302: 			dt->c_ospeed = tp->t_ospeed;
 1303: 	}
 1304: 
 1305: 	t = &tp->t_termios;
 1306: 
 1307: 	error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, td);
 1308: 	if(error != ENOIOCTL) {
 1309: 		return(error);
 1310: 	}
 1311: 	oldspl = spltty();
 1312: 
 1313: 	flags = rp->rp_channel.TxControl[3];
 1314: 
 1315: 	error = ttioctl(tp, cmd, data, flag);
 1316: 	flags = rp->rp_channel.TxControl[3];
 1317: 	rp_disc_optim(tp, &tp->t_termios);
 1318: 	if(error != ENOIOCTL) {
 1319: 		splx(oldspl);
 1320: 		return(error);
 1321: 	}
 1322: 	switch(cmd) {
 1323: 	case TIOCSBRK:
 1324: 		sSendBreak(&rp->rp_channel);
 1325: 		break;
 1326: 
 1327: 	case TIOCCBRK:
 1328: 		sClrBreak(&rp->rp_channel);
 1329: 		break;
 1330: 
 1331: 	case TIOCSDTR:
 1332: 		sSetDTR(&rp->rp_channel);
 1333: 		sSetRTS(&rp->rp_channel);
 1334: 		break;
 1335: 
 1336: 	case TIOCCDTR:
 1337: 		sClrDTR(&rp->rp_channel);
 1338: 		break;
 1339: 
 1340: 	case TIOCMSET:
 1341: 		arg = *(int *) data;
 1342: 		flags = 0;
 1343: 		if(arg & TIOCM_RTS)
 1344: 			flags |= SET_RTS;
 1345: 		if(arg & TIOCM_DTR)
 1346: 			flags |= SET_DTR;
 1347: 		rp->rp_channel.TxControl[3] =
 1348: 			((rp->rp_channel.TxControl[3]
 1349: 			& ~(SET_RTS | SET_DTR)) | flags);
 1350: 		rp_writech4(&rp->rp_channel,_INDX_ADDR,
 1351: 			*(DWord_t *) &(rp->rp_channel.TxControl[0]));
 1352: 		break;
 1353: 	case TIOCMBIS:
 1354: 		arg = *(int *) data;
 1355: 		flags = 0;
 1356: 		if(arg & TIOCM_RTS)
 1357: 			flags |= SET_RTS;
 1358: 		if(arg & TIOCM_DTR)
 1359: 			flags |= SET_DTR;
 1360: 			rp->rp_channel.TxControl[3] |= flags;
 1361: 		rp_writech4(&rp->rp_channel,_INDX_ADDR,
 1362: 			*(DWord_t *) &(rp->rp_channel.TxControl[0]));
 1363: 		break;
 1364: 	case TIOCMBIC:
 1365: 		arg = *(int *) data;
 1366: 		flags = 0;
 1367: 		if(arg & TIOCM_RTS)
 1368: 			flags |= SET_RTS;
 1369: 		if(arg & TIOCM_DTR)
 1370: 			flags |= SET_DTR;
 1371: 		rp->rp_channel.TxControl[3] &= ~flags;
 1372: 		rp_writech4(&rp->rp_channel,_INDX_ADDR,
 1373: 			*(DWord_t *) &(rp->rp_channel.TxControl[0]));
 1374: 		break;
 1375: 
 1376: 
 1377: 	case TIOCMGET:
 1378: 		ChanStatus = sGetChanStatusLo(&rp->rp_channel);
 1379: 		flags = rp->rp_channel.TxControl[3];
 1380: 		result = TIOCM_LE; /* always on while open for some reason */
 1381: 		result |= (((flags & SET_DTR) ? TIOCM_DTR : 0)
 1382: 			| ((flags & SET_RTS) ? TIOCM_RTS : 0)
 1383: 			| ((ChanStatus & CD_ACT) ? TIOCM_CAR : 0)
 1384: 			| ((ChanStatus & DSR_ACT) ? TIOCM_DSR : 0)
 1385: 			| ((ChanStatus & CTS_ACT) ? TIOCM_CTS : 0));
 1386: 
 1387: 		if(rp->rp_channel.RxControl[2] & RTSFC_EN)
 1388: 		{
 1389: 			result |= TIOCM_RTS;
 1390: 		}
 1391: 
 1392: 		*(int *)data = result;
 1393: 		break;
 1394: 	case TIOCMSDTRWAIT:
 1395: 		error = suser(td);
 1396: 		if(error != 0) {
 1397: 			splx(oldspl);
 1398: 			return(error);
 1399: 		}
 1400: 		rp->dtr_wait = *(int *)data * hz/100;
 1401: 		break;
 1402: 	case TIOCMGDTRWAIT:
 1403: 		*(int *)data = rp->dtr_wait * 100/hz;
 1404: 		break;
 1405: 	default:
 1406: 		splx(oldspl);
 1407: 		return ENOTTY;
 1408: 	}
 1409: 	splx(oldspl);
 1410: 	return(0);
 1411: }
 1412: 
 1413: static struct speedtab baud_table[] = {
 1414: 	{B0,	0},		{B50,	BRD50},		{B75,	BRD75},
 1415: 	{B110,	BRD110}, 	{B134,	BRD134}, 	{B150,	BRD150},
 1416: 	{B200,	BRD200}, 	{B300,	BRD300}, 	{B600,	BRD600},
 1417: 	{B1200,	BRD1200},	{B1800,	BRD1800},	{B2400,	BRD2400},
 1418: 	{B4800,	BRD4800},	{B9600,	BRD9600},	{B19200, BRD19200},
 1419: 	{B38400, BRD38400},	{B7200,	BRD7200},	{B14400, BRD14400},
 1420: 				{B57600, BRD57600},	{B76800, BRD76800},
 1421: 	{B115200, BRD115200},	{B230400, BRD230400},
 1422: 	{-1,	-1}
 1423: };
 1424: 
 1425: static int
 1426: rpparam(tp, t)
 1427: 	struct tty *tp;
 1428: 	struct termios *t;
 1429: {
 1430: 	struct rp_port	*rp;
 1431: 	CHANNEL_t	*cp;
 1432: 	int	unit, mynor, port, umynor;               /* SG */
 1433: 	int	oldspl, cflag, iflag, oflag, lflag;
 1434: 	int	ospeed;
 1435: #ifdef RPCLOCAL
 1436: 	int	devshift;
 1437: #endif
 1438: 
 1439: 
 1440:    umynor = (((minor(tp->t_dev) >> 16) -1) * 32);    /* SG */
 1441: 	port  = (minor(tp->t_dev) & 0x1f);                /* SG */
 1442: 	mynor = (port + umynor);                          /* SG */
 1443: 
 1444: 	unit = minor_to_unit[mynor];
 1445: 	rp = rp_addr(unit) + port;
 1446: 	cp = &rp->rp_channel;
 1447: 	oldspl = spltty();
 1448: 
 1449: 	cflag = t->c_cflag;
 1450: #ifdef RPCLOCAL
 1451: 	devshift = umynor / 32;
 1452: 	devshift = 1 << devshift;
 1453: 	if ( devshift & RPCLOCAL ) {
 1454: 		cflag |= CLOCAL;
 1455: 	}
 1456: #endif
 1457: 	iflag = t->c_iflag;
 1458: 	oflag = t->c_oflag;
 1459: 	lflag = t->c_lflag;
 1460: 
 1461: 	ospeed = ttspeedtab(t->c_ispeed, baud_table);
 1462: 	if(ospeed < 0 || t->c_ispeed != t->c_ospeed)
 1463: 		return(EINVAL);
 1464: 
 1465: 	tp->t_ispeed = t->c_ispeed;
 1466: 	tp->t_ospeed = t->c_ospeed;
 1467: 	tp->t_cflag = cflag;
 1468: 	tp->t_iflag = iflag;
 1469: 	tp->t_oflag = oflag;
 1470: 	tp->t_lflag = lflag;
 1471: 
 1472: 	if(t->c_ospeed == 0) {
 1473: 		sClrDTR(cp);
 1474: 		return(0);
 1475: 	}
 1476: 	rp->rp_fifo_lw = ((t->c_ospeed*2) / 1000) +1;
 1477: 
 1478: 	/* Set baud rate ----- we only pay attention to ispeed */
 1479: 	sSetDTR(cp);
 1480: 	sSetRTS(cp);
 1481: 	sSetBaud(cp, ospeed);
 1482: 
 1483: 	if(cflag & CSTOPB) {
 1484: 		sSetStop2(cp);
 1485: 	} else {
 1486: 		sSetStop1(cp);
 1487: 	}
 1488: 
 1489: 	if(cflag & PARENB) {
 1490: 		sEnParity(cp);
 1491: 		if(cflag & PARODD) {
 1492: 			sSetOddParity(cp);
 1493: 		} else {
 1494: 			sSetEvenParity(cp);
 1495: 		}
 1496: 	}
 1497: 	else {
 1498: 		sDisParity(cp);
 1499: 	}
 1500: 	if((cflag & CSIZE) == CS8) {
 1501: 		sSetData8(cp);
 1502: 		rp->rp_imask = 0xFF;
 1503: 	} else {
 1504: 		sSetData7(cp);
 1505: 		rp->rp_imask = 0x7F;
 1506: 	}
 1507: 
 1508: 	if(iflag & ISTRIP) {
 1509: 		rp->rp_imask &= 0x7F;
 1510: 	}
 1511: 
 1512: 	if(cflag & CLOCAL) {
 1513: 		rp->rp_intmask &= ~DELTA_CD;
 1514: 	} else {
 1515: 		rp->rp_intmask |= DELTA_CD;
 1516: 	}
 1517: 
 1518: 	/* Put flow control stuff here */
 1519: 
 1520: 	if(cflag & CCTS_OFLOW) {
 1521: 		sEnCTSFlowCtl(cp);
 1522: 	} else {
 1523: 		sDisCTSFlowCtl(cp);
 1524: 	}
 1525: 
 1526: 	if(cflag & CRTS_IFLOW) {
 1527: 		rp->rp_rts_iflow = 1;
 1528: 	} else {
 1529: 		rp->rp_rts_iflow = 0;
 1530: 	}
 1531: 
 1532: 	if(cflag & CRTS_IFLOW) {
 1533: 		sEnRTSFlowCtl(cp);
 1534: 	} else {
 1535: 		sDisRTSFlowCtl(cp);
 1536: 	}
 1537: 	rp_disc_optim(tp, t);
 1538: 
 1539: 	if((cflag & CLOCAL) || (sGetChanStatusLo(cp) & CD_ACT)) {
 1540: 		tp->t_state |= TS_CARR_ON;
 1541: 		wakeup(TSA_CARR_ON(tp));
 1542: 	}
 1543: 
 1544: /*	tp->t_state |= TS_CAN_BYPASS_L_RINT;
 1545: 	flags = rp->rp_channel.TxControl[3];
 1546: 	if(flags & SET_DTR)
 1547: 	else
 1548: 	if(flags & SET_RTS)
 1549: 	else
 1550: */
 1551: 	splx(oldspl);
 1552: 
 1553: 	return(0);
 1554: }
 1555: 
 1556: static void
 1557: rp_disc_optim(tp, t)
 1558: struct	tty	*tp;
 1559: struct	termios *t;
 1560: {
 1561: 	if(!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON))
 1562: 		&&(!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK))
 1563: 		&&(!(t->c_iflag & PARMRK)
 1564: 		  ||(t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK))
 1565: 		&& !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN))
 1566: 		&& linesw[tp->t_line].l_rint == ttyinput)
 1567: 		tp->t_state |= TS_CAN_BYPASS_L_RINT;
 1568: 	else
 1569: 		tp->t_state &= ~TS_CAN_BYPASS_L_RINT;
 1570: }
 1571: 
 1572: static void
 1573: rpstart(tp)
 1574: 	struct tty *tp;
 1575: {
 1576: 	struct rp_port	*rp;
 1577: 	CHANNEL_t	*cp;
 1578: 	struct	clist	*qp;
 1579: 	int	unit, mynor, port, umynor;               /* SG */
 1580: 	char	flags;
 1581: 	int	spl, xmit_fifo_room;
 1582: 	int	count, wcount;
 1583: 
 1584: 
 1585:    umynor = (((minor(tp->t_dev) >> 16) -1) * 32);    /* SG */
 1586: 	port  = (minor(tp->t_dev) & 0x1f);                /* SG */
 1587: 	mynor = (port + umynor);                          /* SG */
 1588: 	unit = minor_to_unit[mynor];
 1589: 	rp = rp_addr(unit) + port;
 1590: 	cp = &rp->rp_channel;
 1591: 	flags = rp->rp_channel.TxControl[3];
 1592: 	spl = spltty();
 1593: 
 1594: 	if(tp->t_state & (TS_TIMEOUT | TS_TTSTOP)) {
 1595: 		ttwwakeup(tp);
 1596: 		splx(spl);
 1597: 		return;
 1598: 	}
 1599: 	if(rp->rp_xmit_stopped) {
 1600: 		sEnTransmit(cp);
 1601: 		rp->rp_xmit_stopped = 0;
 1602: 	}
 1603: 	count = sGetTxCnt(cp);
 1604: 
 1605: 	if(tp->t_outq.c_cc == 0) {
 1606: 		if((tp->t_state & TS_BUSY) && (count == 0)) {
 1607: 			tp->t_state &= ~TS_BUSY;
 1608: 		}
 1609: 		ttwwakeup(tp);
 1610: 		splx(spl);
 1611: 		return;
 1612: 	}
 1613: 	xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
 1614: 	qp = &tp->t_outq;
 1615: 	if(xmit_fifo_room > 0 && qp->c_cc > 0) {
 1616: 		tp->t_state |= TS_BUSY;
 1617: 		count = q_to_b( qp, (char *)rp->TxBuf, xmit_fifo_room );
 1618: 		wcount = count >> 1;
 1619: 		if ( wcount ) {
 1620: 			rp_writemultich2(cp, sGetTxRxDataIO(cp), (u_int16_t *)rp->TxBuf, wcount);
 1621: 		}
 1622: 		if ( count & 1 ) {
 1623: 			rp_writech1(cp, sGetTxRxDataIO(cp),
 1624: 				    ((unsigned char *)(rp->TxBuf))[(count-1)]);
 1625: 		}
 1626: 	}
 1627: 	rp->rp_restart = (qp->c_cc > 0) ? rp->rp_fifo_lw : 0;
 1628: 
 1629: 	ttwwakeup(tp);
 1630: 	splx(spl);
 1631: }
 1632: 
 1633: static
 1634: void
 1635: rpstop(tp, flag)
 1636: 	struct tty *tp;
 1637: 	int	flag;
 1638: {
 1639: 	struct rp_port	*rp;
 1640: 	CHANNEL_t	*cp;
 1641: 	int	unit, mynor, port, umynor;                  /* SG */
 1642: 	int	spl;
 1643: 
 1644:    umynor = (((minor(tp->t_dev) >> 16) -1) * 32);    /* SG */
 1645: 	port  = (minor(tp->t_dev) & 0x1f);                /* SG */
 1646: 	mynor = (port + umynor);                          /* SG */
 1647: 	unit = minor_to_unit[mynor];
 1648: 	rp = rp_addr(unit) + port;
 1649: 	cp = &rp->rp_channel;
 1650: 
 1651: 	spl = spltty();
 1652: 
 1653: 	if(tp->t_state & TS_BUSY) {
 1654: 		if((tp->t_state&TS_TTSTOP) == 0) {
 1655: 			sFlushTxFIFO(cp);
 1656: 		} else {
 1657: 			if(rp->rp_xmit_stopped == 0) {
 1658: 				sDisTransmit(cp);
 1659: 				rp->rp_xmit_stopped = 1;
 1660: 			}
 1661: 		}
 1662: 	}
 1663: 	splx(spl);
 1664: 	rpstart(tp);
 1665: }