Up to [DragonFly] / src / sys / i386 / i386
Request diff between arbitrary revisions
Keyword substitution: kv
Default branch: MAIN
Reorganize the way machine architectures are handled. Consolidate the kernel configurations into a single generic directory. Move machine-specific Makefile's and loader scripts into the appropriate architecture directory. Kernel and module builds also generally add sys/arch to the include path so source files that include architecture-specific headers do not have to be adjusted. sys/<ARCH> -> sys/arch/<ARCH> sys/conf/*.<ARCH> -> sys/arch/<ARCH>/conf/*.<ARCH> sys/<ARCH>/conf/<KERNEL> -> sys/config/<KERNEL>
Add two KTR (kernel trace) options: KTR_GIANT_CONTENTION and KTR_SPIN_CONTENTION. These will cause MP lock contention and spin lock contention to be KTR-logged.
Clean up some minor typos in comments. Submitted-by: Michal Belczyk <firstname.lastname@example.org>
ICU/APIC cleanup part 9/many. Get rid of machine/smptests.h, remove or implement the related #defines. Distinguish between boot-time vector initialization and interrupt setup and teardown in MACHINTR ABI. Get rid of the ISR test for APIC-generated interrupts and all related support code. Just generate the EOI and pray. Document more of the IO APIC redirection register(s). Intel sure screwed up the LAPIC and IO APIC royally. There is no simple way to poll the actual signal level on a pin, no simple way to manually EOI interrupts or EOI them in the order we desire, no simple way to poll the LAPIC for the vector that will be EOI'd when we send the EOI. We can't mask the interrupt on the IO APIC without triggering stupid legacy code on some machines. We can't even program the IO APIC linearly, it uses a stupid register/data sequence that makes it impossible for access on an SMP system without serialization. It's a goddamn mess, and it is all Intel's fault.
ICU/APIC cleanup part 1/many. Move ICU and APIC support files into their own subdirectory, bump the required config version for the build since this move also requires the use of the new arch/ symlink.
Fix a number of SMP issues. * Add required pause instructions in code paths that skip running "HLT". This occurs when e.g. cpu #1 is running code with the BGL while cpu #2's only runnable thread requires the BGL. cpu #2's LWKT scheduler spins in that case. Similar situations can occur when the only runnable threads on a cpu are waiting for a token. * Add required pause instructions to spin loops. DragonFly has very few spin locks (e.g. things like com_lock()) but its a good idea anyway to avoid known livelock issues on Intel cpus. * Fix a pending interrupt / HLT race. We were not atomically retiring pending interrupts prior to potentially HLTing the cpu. This could result in an SMP machine's network locking up until a key is hit on the console, then magically resuming. Lockups-reported-by: Peter Avalos <email@example.com>
Update all my personal copyrights to the Dragonfly Standard Copyright.
Fix spelling in comment.
Synchronize a bunch of things from FreeBSD-5 in preparation for the new ACPICA driver support. * Bring in a lot of new bus and pci DEV_METHODs from FreeBSD-5 * split apic.h into apicreg.h and apicio.h * rename INTR_TYPE_FAST -> INTR_FAST and move the #define * rename INTR_TYPE_EXCL -> INTR_EXCL and move the #define * rename some PCIR_ registers and add additional macros from FreeBSD-5 * note: new pcib bus call, host_pcib_get_busno() imported. * kern/subr_power.c no longer optional. Other changes: * machine/smp.h machine smp/smptests.h can now be #included unconditionally, and some APIC_IO vs SMP separation has been done as well. * gd_acpi_id and gd_apic_id added to machine/globaldata.h prep for new ACPI code. Despite all the changes, the generated code should be virtually the same. These were mostly additions which the pre-existing code does not (yet) use.
General cleanups as part of the libcaps userland threading work.
Fix a number of mp_lock issues. I had outsmarted myself trying to deal with td->td_mpcount / mp_lock races. The new rule is: you first modify td->td_mpcount, then you deal with mp_lock assuming that an interrupt might have already dealt with it for you, and various other pieces of code deal with the race if an interrupt occurs in the middle of the above two data accesses.
Fix a minor compile-time errors when INVARIANTS is not defined.
MP Implmentation 3A/4: Fix stupid bug introduced in last commit.
MP Implmentation 3A/4: Cleanup MP lock operations to allow the MP lock to occassionally be out of synch from td_mpcount, so we don't have to disable interrupts and so we can call try_mplock() from the middle of a switch function.
MP Implmentation 3/4: MAJOR progress on SMP, full userland MP is now working! A number of issues relating to MP lock operation have been fixed, primarily that we have to read %cr2 before get_mplock() since get_mplock() may switch away. Idlethreads can now safely HLT without any performance detriment. The userland scheduler has been almost completely rewritten and is now using an extremely flexible abstraction with a lot of room to grow. pgeflag has been removed from mapdev (without per-page invalidation it isn't safe to use PG_G even on UP). Necessary locked bus cycles have been added for the pmap->pm_active field in swtch.s. CR3 has been unoptimized for the moment (see comment in swtch.s). Since the switch code runs without the MP lock we have to adjust pm_active PRIOR to loading %cr3. Additional sanity checks have been added to the code (see PARANOID_INVLTLB and ONLY_ONE_USER_CPU in the code), plus many more in kern_switch.c. A passive release mechanism has been implemented to optimize P_CURPROC/lwkt priority shifting when going from user->kernel and kernel->user. Note: preemptive interrupts don't care due to the way preemption works so no additional complexity there. non-locking atomic functions to protect only against local interrupts have been added. astpending now uses non-locking atomic functions to set and clear bits. private_tss has been moved to a per-cpu variable. The LWKT thread module has been considerably enhanced and cleaned up, including some fixes to handle MPLOCKED vs td_mpcount races (so eventually we can do MP locking without a pushfl/cli/popfl combo). stopevent() needs critical section protection, maybe.
MP Implementation 2/4: Implement a poor-man's IPI messaging subsystem, get both cpus arbitrating the BGL for interrupts, IPIing foreign cpu LWKT scheduling requests without crashing, and dealing with the cpl. The APs are in a slightly less degenerate state now, but hardclock and statclock distribution is broken, only one user process is being scheduled at a time, and priorities are all messed up.
MP Implementation 1/2: Get the APIC code working again, sweetly integrate the MP lock into the LWKT scheduler, replace the old simplelock code with tokens or spin locks as appropriate. In particular, the vnode interlock (and most other interlocks) are now tokens. Also clean up a few curproc/cred sequences that are no longer needed. The APs are left in degenerate state with non IPI interrupts disabled as additional LWKT work must be done before we can really make use of them, and FAST interrupts are not managed by the MP lock yet. The main thing for this stage was to get the system working with an APIC again. buildworld tested on UP and 2xCPU/MP (Dell 2550)
Remove pre-ELF underscore prefix and asnames macro hacks.
Add the DragonFly cvs id and perform general cleanups on cvs/rcs/sccs ids. Most ids have been removed from !lint sections and moved into comment sections.
import from FreeBSD RELENG_4 18.104.22.168