File:  [DragonFly] / src / sys / net / i4b / capi / iavc / iavc.h
Revision 1.2: download - view: text, annotated - select for diffs
Tue Jun 17 04:28:39 2003 UTC (11 years, 2 months ago) by dillon
Branches: MAIN
CVS tags: PRE_MP, HEAD
Add the DragonFly cvs id and perform general cleanups on cvs/rcs/sccs ids.  Most
ids have been removed from !lint sections and moved into comment sections.

    1: /*
    2:  * Copyright (c) 2001 Cubical Solutions Ltd. All rights reserved.
    3:  *
    4:  * Redistribution and use in source and binary forms, with or without
    5:  * modification, are permitted provided that the following conditions
    6:  * are met:
    7:  * 1. Redistributions of source code must retain the above copyright
    8:  *    notice, this list of conditions and the following disclaimer.
    9:  * 2. Redistributions in binary form must reproduce the above copyright
   10:  *    notice, this list of conditions and the following disclaimer in the
   11:  *    documentation and/or other materials provided with the distribution.
   12:  *
   13:  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   14:  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   15:  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   16:  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   17:  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   18:  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   19:  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   20:  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   21:  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   22:  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   23:  * SUCH DAMAGE.
   24:  *
   25:  * capi/iavc/iavc.h	The AVM ISDN controllers' common declarations.
   26:  *
   27:  * $FreeBSD: src/sys/i4b/capi/iavc/iavc.h,v 1.1.2.1 2001/08/10 14:08:34 obrien Exp $
   28:  * $DragonFly: src/sys/net/i4b/capi/iavc/iavc.h,v 1.2 2003/06/17 04:28:39 dillon Exp $
   29:  */
   30: 
   31: #ifndef _CAPI_IAVC_H_
   32: #define _CAPI_IAVC_H_
   33: 
   34: /* max 4 units supported per machine */
   35: 
   36: #define IAVC_MAXUNIT 4
   37: 
   38: /*
   39: //  iavc_softc_t
   40: //      The software context of one AVM T1 controller.
   41: */
   42: 
   43: #define IAVC_IO_BASES 1
   44: 
   45: typedef struct i4b_info {
   46:     struct resource * io_base[IAVC_IO_BASES];
   47:     int               io_rid [IAVC_IO_BASES];
   48:     struct resource * irq;
   49:     int               irq_rid;
   50:     struct resource * mem;
   51:     int               mem_rid;
   52: } i4b_info_t;
   53: 
   54: typedef struct iavc_softc {
   55:     capi_softc_t        sc_capi;
   56:     int		        sc_unit;
   57:     int		        sc_cardtyp;
   58: 
   59:     u_int32_t           sc_membase;
   60:     bus_space_handle_t  sc_mem_bh;
   61:     bus_space_tag_t     sc_mem_bt;
   62:     u_int32_t	        sc_iobase;
   63:     bus_space_handle_t  sc_io_bh;
   64:     bus_space_tag_t     sc_io_bt;
   65: 
   66:     int                 sc_state;
   67: #define IAVC_DOWN       0
   68: #define IAVC_POLL       1
   69: #define IAVC_INIT       2
   70: #define IAVC_UP         3
   71:     int                 sc_blocked;
   72:     int                 sc_dma;
   73:     int                 sc_t1;
   74:     int                 sc_intr;
   75: 
   76:     u_int32_t           sc_csr;
   77: 
   78:     char                sc_sendbuf[128+2048];
   79:     char                sc_recvbuf[128+2048];
   80:     int                 sc_recvlen;
   81: 
   82:     struct ifqueue      sc_txq;
   83: 
   84:     i4b_info_t	        sc_resources;
   85: } iavc_softc_t;
   86: 
   87: extern iavc_softc_t iavc_sc[];
   88: 
   89: #define iavc_find_sc(unit)	(&iavc_sc[(unit)])
   90: 
   91: /*
   92: //  {b1,b1dma,t1}_{detect,reset}
   93: //      Routines to detect and manage the specific type of card.
   94: */
   95: 
   96: extern int      b1_detect(iavc_softc_t *sc);
   97: extern void     b1_disable_irq(iavc_softc_t *sc);
   98: extern void     b1_reset(iavc_softc_t *sc);
   99: 
  100: extern int      b1dma_detect(iavc_softc_t *sc);
  101: extern void     b1dma_reset(iavc_softc_t *sc);
  102: 
  103: extern int      t1_detect(iavc_softc_t *sc);
  104: extern void     t1_disable_irq(iavc_softc_t *sc);
  105: extern void     t1_reset(iavc_softc_t *sc);
  106: 
  107: /*
  108: //  AMCC_{READ,WRITE}
  109: //      Routines to access the memory mapped registers of the
  110: //      S5933 DMA controller.
  111: */
  112: 
  113: static __inline u_int32_t AMCC_READ(iavc_softc_t *sc, int off)
  114: {
  115:     return bus_space_read_4(sc->sc_mem_bt, sc->sc_mem_bh, off);
  116: }
  117: 
  118: static __inline void AMCC_WRITE(iavc_softc_t *sc, int off, u_int32_t value)
  119: {
  120:     bus_space_write_4(sc->sc_mem_bt, sc->sc_mem_bh, off, value);
  121: }
  122: 
  123: /*
  124: //  amcc_{put,get}_{byte,word}
  125: //      Routines to access the DMA buffers byte- or wordwise.
  126: */
  127: 
  128: static __inline u_int8_t* amcc_put_byte(u_int8_t *buf, u_int8_t value)
  129: {
  130:     *buf++ = value;
  131:     return buf;
  132: }
  133: 
  134: static __inline u_int8_t* amcc_get_byte(u_int8_t *buf, u_int8_t *value)
  135: {
  136:     *value = *buf++;
  137:     return buf;
  138: }
  139: 
  140: static __inline u_int8_t* amcc_put_word(u_int8_t *buf, u_int32_t value)
  141: {
  142:     *buf++ = (value & 0xff);
  143:     *buf++ = (value >> 8) & 0xff;
  144:     *buf++ = (value >> 16) & 0xff;
  145:     *buf++ = (value >> 24) & 0xff;
  146:     return buf;
  147: }
  148: 
  149: static __inline u_int8_t* amcc_get_word(u_int8_t *buf, u_int32_t *value)
  150: {
  151:     *value = *buf++;
  152:     *value |= (*buf++ << 8);
  153:     *value |= (*buf++ << 16);
  154:     *value |= (*buf++ << 24);
  155:     return buf;
  156: }
  157: 
  158: /*
  159: //  Controller LLI message numbers.
  160: */
  161: 
  162: #define SEND_POLL           0x72
  163: #define SEND_INIT           0x11
  164: #define SEND_REGISTER       0x12
  165: #define SEND_DATA_B3_REQ    0x13
  166: #define SEND_RELEASE        0x14
  167: #define SEND_MESSAGE        0x15
  168: #define SEND_CONFIG         0x71
  169: #define SEND_POLLACK        0x73
  170: 
  171: #define RECEIVE_POLL        0x32
  172: #define RECEIVE_INIT        0x27
  173: #define RECEIVE_MESSAGE     0x21
  174: #define RECEIVE_DATA_B3_IND 0x22
  175: #define RECEIVE_START       0x23
  176: #define RECEIVE_STOP        0x24
  177: #define RECEIVE_NEW_NCCI    0x25
  178: #define RECEIVE_FREE_NCCI   0x26
  179: #define RECEIVE_RELEASE     0x26
  180: #define RECEIVE_TASK_READY  0x31
  181: #define RECEIVE_DEBUGMSG    0x71
  182: #define RECEIVE_POLLDWORD   0x75
  183: 
  184: /* Operation constants */
  185: 
  186: #define WRITE_REGISTER      0x00
  187: #define READ_REGISTER       0x01
  188: 
  189: /* Port offsets in I/O space */
  190: 
  191: #define B1_READ             0x00
  192: #define B1_WRITE            0x01
  193: #define B1_INSTAT           0x02
  194: #define B1_OUTSTAT          0x03
  195: #define B1_ANALYSE          0x04
  196: #define B1_REVISION         0x05
  197: #define B1_RESET            0x10
  198: 
  199: #define T1_FASTLINK         0x00
  200: #define T1_SLOWLINK         0x08
  201: 
  202: #define T1_READ             B1_READ
  203: #define T1_WRITE            B1_WRITE
  204: #define T1_INSTAT           B1_INSTAT
  205: #define T1_OUTSTAT          B1_OUTSTAT
  206: #define T1_IRQENABLE        0x05
  207: #define T1_FIFOSTAT         0x06
  208: #define T1_RESETLINK        0x10
  209: #define T1_ANALYSE          0x11
  210: #define T1_IRQMASTER        0x12
  211: #define T1_IDENT            0x17
  212: #define T1_RESETBOARD       0x1f
  213: 
  214: #define T1F_IREADY          0x01
  215: #define T1F_IHALF           0x02
  216: #define T1F_IFULL           0x04
  217: #define T1F_IEMPTY          0x08
  218: #define T1F_IFLAGS          0xf0
  219: 
  220: #define T1F_OREADY          0x10
  221: #define T1F_OHALF           0x20
  222: #define T1F_OEMPTY          0x40
  223: #define T1F_OFULL           0x80
  224: #define T1F_OFLAGS          0xf0
  225: 
  226: #define FIFO_OUTBSIZE       256
  227: #define FIFO_INPBSIZE       512
  228: 
  229: #define HEMA_VERSION_ID     0
  230: #define HEMA_PAL_ID         0
  231: 
  232: /*
  233: //  S5933 DMA controller register offsets in memory, and bitmasks.
  234: */
  235: 
  236: #define AMCC_RXPTR       0x24
  237: #define AMCC_RXLEN       0x28
  238: #define AMCC_TXPTR       0x2c
  239: #define AMCC_TXLEN       0x30
  240: 
  241: #define AMCC_INTCSR      0x38
  242: #define EN_READ_TC_INT   0x00008000
  243: #define EN_WRITE_TC_INT  0x00004000
  244: #define EN_TX_TC_INT     EN_READ_TC_INT
  245: #define EN_RX_TC_INT     EN_WRITE_TC_INT
  246: #define AVM_FLAG         0x30000000
  247: 
  248: #define ANY_S5933_INT    0x00800000
  249: #define READ_TC_INT      0x00080000
  250: #define WRITE_TC_INT     0x00040000
  251: #define TX_TC_INT        READ_TC_INT
  252: #define RX_TC_INT        WRITE_TC_INT
  253: #define MASTER_ABORT_INT 0x00100000
  254: #define TARGET_ABORT_INT 0x00200000
  255: #define BUS_MASTER_INT   0x00200000
  256: #define ALL_INT          0x000c0000
  257: 
  258: #define AMCC_MCSR        0x3c
  259: #define A2P_HI_PRIORITY  0x00000100
  260: #define EN_A2P_TRANSFERS 0x00000400
  261: #define P2A_HI_PRIORITY  0x00001000
  262: #define EN_P2A_TRANSFERS 0x00004000
  263: #define RESET_A2P_FLAGS  0x04000000
  264: #define RESET_P2A_FLAGS  0x02000000
  265: 
  266: /*
  267: //  (B1IO_WAIT_MAX * B1IO_WAIT_DLY) is the max wait in us for the card
  268: //  to become ready after an I/O operation. The default is 1 ms.
  269: */
  270: 
  271: #define B1IO_WAIT_MAX    1000
  272: #define B1IO_WAIT_DLY    1
  273: 
  274: /*
  275: //  b1io_outp
  276: //      Diagnostic output routine, returns the written value via
  277: //      the device's analysis register.
  278: //
  279: //  b1io_rx_full
  280: //      Returns nonzero if data is readable from the card via the
  281: //      I/O ports.
  282: //
  283: //  b1io_tx_empty
  284: //      Returns nonzero if data can be written to the card via the
  285: //      I/O ports.
  286: */
  287: 
  288: static __inline u_int8_t b1io_outp(iavc_softc_t *sc, int off, u_int8_t val)
  289: {
  290:     bus_space_write_1(sc->sc_io_bt, sc->sc_io_bh, off, val);
  291:     DELAY(1);
  292:     return bus_space_read_1(sc->sc_io_bt, sc->sc_io_bh, B1_ANALYSE);
  293: }
  294: 
  295: static __inline int b1io_rx_full(iavc_softc_t *sc)
  296: {
  297:     u_int8_t val = bus_space_read_1(sc->sc_io_bt, sc->sc_io_bh, B1_INSTAT);
  298:     return (val & 0x01);
  299: }
  300: 
  301: static __inline int b1io_tx_empty(iavc_softc_t *sc)
  302: {
  303:     u_int8_t val = bus_space_read_1(sc->sc_io_bt, sc->sc_io_bh, B1_OUTSTAT);
  304:     return  (val & 0x01);
  305: }
  306: 
  307: /*
  308: //  b1io_{get,put}_{byte,word}
  309: //      Routines to read and write the device I/O registers byte- or
  310: //      wordwise.
  311: //
  312: //  b1io_{get,put}_slice
  313: //      Routines to read and write sequential bytes to the device
  314: //      I/O registers.
  315: */
  316: 
  317: static __inline u_int8_t b1io_get_byte(iavc_softc_t *sc)
  318: {
  319:     int spin = 0;
  320:     while (!b1io_rx_full(sc) && spin < B1IO_WAIT_MAX) {
  321: 	spin++; DELAY(B1IO_WAIT_DLY);
  322:     }
  323:     if (b1io_rx_full(sc))
  324: 	return bus_space_read_1(sc->sc_io_bt, sc->sc_io_bh, B1_READ);
  325:     printf("iavc%d: rx not completed\n", sc->sc_unit);
  326:     return 0xff;
  327: }
  328: 
  329: static __inline int b1io_put_byte(iavc_softc_t *sc, u_int8_t val)
  330: {
  331:     int spin = 0;
  332:     while (!b1io_tx_empty(sc) && spin < B1IO_WAIT_MAX) {
  333: 	spin++; DELAY(B1IO_WAIT_DLY);
  334:     }
  335:     if (b1io_tx_empty(sc)) {
  336: 	bus_space_write_1(sc->sc_io_bt, sc->sc_io_bh, B1_WRITE, val);
  337: 	return 0;
  338:     }
  339:     printf("iavc%d: tx not emptied\n", sc->sc_unit);
  340:     return -1;
  341: }
  342: 
  343: static __inline int b1io_save_put_byte(iavc_softc_t *sc, u_int8_t val)
  344: {
  345:     int spin = 0;
  346:     while (!b1io_tx_empty(sc) && spin < B1IO_WAIT_MAX) {
  347: 	spin++; DELAY(B1IO_WAIT_DLY);
  348:     }
  349:     if (b1io_tx_empty(sc)) {
  350: 	b1io_outp(sc, B1_WRITE, val);
  351: 	return 0;
  352:     }
  353:     printf("iavc%d: tx not emptied\n", sc->sc_unit);
  354:     return -1;
  355: }
  356: 
  357: static __inline u_int32_t b1io_get_word(iavc_softc_t *sc)
  358: {
  359:     u_int32_t val = 0;
  360:     val |= b1io_get_byte(sc);
  361:     val |= (b1io_get_byte(sc) << 8);
  362:     val |= (b1io_get_byte(sc) << 16);
  363:     val |= (b1io_get_byte(sc) << 24);
  364:     return val;
  365: }
  366: 
  367: static __inline void b1io_put_word(iavc_softc_t *sc, u_int32_t val)
  368: {
  369:     b1io_put_byte(sc, (val & 0xff));
  370:     b1io_put_byte(sc, (val >> 8) & 0xff);
  371:     b1io_put_byte(sc, (val >> 16) & 0xff);
  372:     b1io_put_byte(sc, (val >> 24) & 0xff);
  373: }
  374: 
  375: static __inline int b1io_get_slice(iavc_softc_t *sc, u_int8_t *dp)
  376: {
  377:     int len, i;
  378:     len = i = b1io_get_word(sc);
  379:     while (i--) *dp++ = b1io_get_byte(sc);
  380:     return len;
  381: }
  382: 
  383: static __inline void b1io_put_slice(iavc_softc_t *sc, u_int8_t *dp, int len)
  384: {
  385:     b1io_put_word(sc, len);
  386:     while (len--) b1io_put_byte(sc, *dp++);
  387: }
  388: 
  389: /*
  390: //  b1io_{read,write}_reg
  391: //      Routines to read and write the device registers via the I/O
  392: //      ports.
  393: */
  394: 
  395: static __inline u_int32_t b1io_read_reg(iavc_softc_t *sc, int reg)
  396: {
  397:     b1io_put_byte(sc, READ_REGISTER);
  398:     b1io_put_word(sc, reg);
  399:     return b1io_get_word(sc);
  400: }
  401: 
  402: static __inline u_int32_t b1io_write_reg(iavc_softc_t *sc, int reg, u_int32_t val)
  403: {
  404:     b1io_put_byte(sc, WRITE_REGISTER);
  405:     b1io_put_word(sc, reg);
  406:     b1io_put_word(sc, val);
  407:     return b1io_get_word(sc);
  408: }
  409: 
  410: /*
  411: //  t1io_outp
  412: //      I/O port write operation for the T1, which does not seem
  413: //      to have the analysis port.
  414: */
  415: 
  416: static __inline void t1io_outp(iavc_softc_t *sc, int off, u_int8_t val)
  417: {
  418:     bus_space_write_1(sc->sc_io_bt, sc->sc_io_bh, off, val);
  419: }
  420: 
  421: static __inline u_int8_t t1io_inp(iavc_softc_t *sc, int off)
  422: {
  423:     return bus_space_read_1(sc->sc_io_bt, sc->sc_io_bh, off);
  424: }
  425: 
  426: static __inline int t1io_isfastlink(iavc_softc_t *sc)
  427: {
  428:     return ((bus_space_read_1(sc->sc_io_bt, sc->sc_io_bh, T1_IDENT) & ~0x82) == 1);
  429: }
  430: 
  431: static __inline u_int8_t t1io_fifostatus(iavc_softc_t *sc)
  432: {
  433:     return bus_space_read_1(sc->sc_io_bt, sc->sc_io_bh, T1_FIFOSTAT);
  434: }
  435: 
  436: static __inline int t1io_get_slice(iavc_softc_t *sc, u_int8_t *dp)
  437: {
  438:     int len, i;
  439:     len = i = b1io_get_word(sc);
  440:     if (t1io_isfastlink(sc)) {
  441: 	int status;
  442: 	while (i) {
  443: 	    status = t1io_fifostatus(sc) & (T1F_IREADY|T1F_IHALF);
  444: 	    if (i >= FIFO_INPBSIZE) status |= T1F_IFULL;
  445: 
  446: 	    switch (status) {
  447: 	    case T1F_IREADY|T1F_IHALF|T1F_IFULL:
  448: 		bus_space_read_multi_1(sc->sc_io_bt, sc->sc_io_bh,
  449: 				       T1_READ, dp, FIFO_INPBSIZE);
  450: 		dp += FIFO_INPBSIZE;
  451: 		i -= FIFO_INPBSIZE;
  452: 		break;
  453: 
  454: 	    case T1F_IREADY|T1F_IHALF:
  455: 		bus_space_read_multi_1(sc->sc_io_bt, sc->sc_io_bh,
  456: 				       T1_READ, dp, i);
  457: 		dp += i;
  458: 		i = 0;
  459: 		break;
  460: 
  461: 	    default:
  462: 		*dp++ = b1io_get_byte(sc);
  463: 		i--;
  464: 	    }
  465: 	}
  466:     } else { /* not fastlink */
  467: 	if (i--) *dp++ = b1io_get_byte(sc);
  468:     }
  469:     return len;
  470: }
  471: 
  472: static __inline void t1io_put_slice(iavc_softc_t *sc, u_int8_t *dp, int len)
  473: {
  474:     int i = len;
  475:     b1io_put_word(sc, i);
  476:     if (t1io_isfastlink(sc)) {
  477: 	int status;
  478: 	while (i) {
  479: 	    status = t1io_fifostatus(sc) & (T1F_OREADY|T1F_OHALF);
  480: 	    if (i >= FIFO_OUTBSIZE) status |= T1F_OFULL;
  481: 
  482: 	    switch (status) {
  483: 	    case T1F_OREADY|T1F_OHALF|T1F_OFULL:
  484: 		bus_space_write_multi_1(sc->sc_io_bt, sc->sc_io_bh,
  485: 					T1_WRITE, dp, FIFO_OUTBSIZE);
  486: 		dp += FIFO_OUTBSIZE;
  487: 		i -= FIFO_OUTBSIZE;
  488: 		break;
  489: 
  490: 	    case T1F_OREADY|T1F_OHALF:
  491: 		bus_space_write_multi_1(sc->sc_io_bt, sc->sc_io_bh,
  492: 					T1_WRITE, dp, i);
  493: 		dp += i;
  494: 		i = 0;
  495: 		break;
  496: 
  497: 	    default:
  498: 		b1io_put_byte(sc, *dp++);
  499: 		i--;
  500: 	    }
  501: 	}
  502:     } else {
  503: 	while (i--) b1io_put_byte(sc, *dp++);
  504:     }
  505: }
  506: 
  507: /*
  508: //  An attempt to bring it all together:
  509: //  ------------------------------------
  510: //
  511: //  iavc_{read,write}_reg
  512: //      Routines to access the device registers via the I/O port.
  513: //
  514: //  iavc_{read,write}_port
  515: //      Routines to access the device I/O ports.
  516: //
  517: //  iavc_tx_empty, iavc_rx_full
  518: //      Routines to check when the device has drained the last written
  519: //      byte, or produced a full byte to read.
  520: //
  521: //  iavc_{get,put}_byte
  522: //      Routines to read/write byte values to the device via the I/O port.
  523: //
  524: //  iavc_{get,put}_word
  525: //      Routines to read/write 32-bit words to the device via the I/O port.
  526: //
  527: //  iavc_{get,put}_slice
  528: //      Routines to read/write {length, data} pairs to the device via the
  529: //      ubiquituous I/O port. Uses the HEMA FIFO on a T1.
  530: */
  531: 
  532: #define iavc_read_reg(sc, reg) b1io_read_reg(sc, reg)
  533: #define iavc_write_reg(sc, reg, val) b1io_write_reg(sc, reg, val)
  534: 
  535: #define iavc_read_port(sc, port) \
  536:         bus_space_read_1(sc->sc_io_bt, sc->sc_io_bh, (port))
  537: #define iavc_write_port(sc, port, val) \
  538:         bus_space_write_1(sc->sc_io_bt, sc->sc_io_bh, (port), (val))
  539: 
  540: #define iavc_tx_empty(sc)      b1io_tx_empty(sc)
  541: #define iavc_rx_full(sc)       b1io_rx_full(sc)
  542: 
  543: #define iavc_get_byte(sc)      b1io_get_byte(sc)
  544: #define iavc_put_byte(sc, val) b1io_put_byte(sc, val)
  545: #define iavc_get_word(sc)      b1io_get_word(sc)
  546: #define iavc_put_word(sc, val) b1io_put_word(sc, val)
  547: 
  548: static __inline u_int32_t iavc_get_slice(iavc_softc_t *sc, u_int8_t *dp)
  549: {
  550:     if (sc->sc_t1) return t1io_get_slice(sc, dp);
  551:     else return b1io_get_slice(sc, dp);
  552: }
  553: 
  554: static __inline void iavc_put_slice(iavc_softc_t *sc, u_int8_t *dp, int len)
  555: {
  556:     if (sc->sc_t1) t1io_put_slice(sc, dp, len);
  557:     else b1io_put_slice(sc, dp, len);
  558: }
  559: 
  560: /*
  561: //  iavc_handle_intr
  562: //      Interrupt handler, called by the bus specific interrupt routine
  563: //      in iavc_<bustype>.c module.
  564: //
  565: //  iavc_load
  566: //      CAPI callback. Resets device and loads firmware.
  567: //
  568: //  iavc_register
  569: //      CAPI callback. Registers an application id.
  570: //
  571: //  iavc_release
  572: //      CAPI callback. Releases an application id.
  573: //
  574: //  iavc_send
  575: //      CAPI callback. Sends a CAPI message. A B3_DATA_REQ message has
  576: //      m_next point to a data mbuf.
  577: */
  578: 
  579: extern void iavc_handle_intr(iavc_softc_t *);
  580: extern int iavc_load(capi_softc_t *, int, u_int8_t *);
  581: extern int iavc_register(capi_softc_t *, int, int);
  582: extern int iavc_release(capi_softc_t *, int);
  583: extern int iavc_send(capi_softc_t *, struct mbuf *);
  584: 
  585: extern void b1isa_setup_irq(struct iavc_softc *sc);
  586: 
  587: #endif /* _CAPI_IAVC_H_ */