File:  [DragonFly] / src / sys / net / i4b / capi / iavc / iavc.h
Revision 1.3: download - view: text, annotated - select for diffs
Fri Apr 16 15:40:21 2004 UTC (10 years, 8 months ago) by joerg
Branches: MAIN
CVS tags: HEAD, DragonFly_Stable, DragonFly_Snap29Sep2004, DragonFly_Snap13Sep2004, DragonFly_RELEASE_1_4_Slip, DragonFly_RELEASE_1_4, DragonFly_RELEASE_1_2_Slip, DragonFly_RELEASE_1_2, DragonFly_1_0_REL, DragonFly_1_0_RC1, DragonFly_1_0A_REL
Merge changes from FreeBSD 5:
- remove dependency on device counting
- undo massive inlining on iavc

    1: /*
    2:  * Copyright (c) 2001 Cubical Solutions Ltd. All rights reserved.
    3:  *
    4:  * Redistribution and use in source and binary forms, with or without
    5:  * modification, are permitted provided that the following conditions
    6:  * are met:
    7:  * 1. Redistributions of source code must retain the above copyright
    8:  *    notice, this list of conditions and the following disclaimer.
    9:  * 2. Redistributions in binary form must reproduce the above copyright
   10:  *    notice, this list of conditions and the following disclaimer in the
   11:  *    documentation and/or other materials provided with the distribution.
   12:  *
   13:  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   14:  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   15:  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   16:  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   17:  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   18:  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   19:  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   20:  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   21:  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   22:  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   23:  * SUCH DAMAGE.
   24:  *
   25:  * capi/iavc/iavc.h	The AVM ISDN controllers' common declarations.
   26:  *
   27:  * $FreeBSD: src/sys/i4b/capi/iavc/iavc.h,v 1.2 2003/07/23 17:58:41 phk Exp $
   28:  * $DragonFly: src/sys/net/i4b/capi/iavc/iavc.h,v 1.3 2004/04/16 15:40:21 joerg Exp $
   29:  */
   30: 
   31: #ifndef _CAPI_IAVC_H_
   32: #define _CAPI_IAVC_H_
   33: 
   34: /* max 4 units supported per machine */
   35: 
   36: #define IAVC_MAXUNIT 4
   37: 
   38: /*
   39: //  iavc_softc_t
   40: //      The software context of one AVM T1 controller.
   41: */
   42: 
   43: #define IAVC_IO_BASES 1
   44: 
   45: typedef struct i4b_info {
   46:     struct resource * io_base[IAVC_IO_BASES];
   47:     int               io_rid [IAVC_IO_BASES];
   48:     struct resource * irq;
   49:     int               irq_rid;
   50:     struct resource * mem;
   51:     int               mem_rid;
   52: } i4b_info_t;
   53: 
   54: typedef struct iavc_softc {
   55:     capi_softc_t        sc_capi;
   56:     int		        sc_unit;
   57:     int		        sc_cardtyp;
   58: 
   59:     u_int32_t           sc_membase;
   60:     bus_space_handle_t  sc_mem_bh;
   61:     bus_space_tag_t     sc_mem_bt;
   62:     u_int32_t	        sc_iobase;
   63:     bus_space_handle_t  sc_io_bh;
   64:     bus_space_tag_t     sc_io_bt;
   65: 
   66:     int                 sc_state;
   67: #define IAVC_DOWN       0
   68: #define IAVC_POLL       1
   69: #define IAVC_INIT       2
   70: #define IAVC_UP         3
   71:     int                 sc_blocked;
   72:     int                 sc_dma;
   73:     int                 sc_t1;
   74:     int                 sc_intr;
   75: 
   76:     u_int32_t           sc_csr;
   77: 
   78:     char                sc_sendbuf[128+2048];
   79:     char                sc_recvbuf[128+2048];
   80:     int                 sc_recvlen;
   81: 
   82:     struct ifqueue      sc_txq;
   83: 
   84:     i4b_info_t	        sc_resources;
   85: } iavc_softc_t;
   86: 
   87: extern iavc_softc_t iavc_sc[];
   88: 
   89: #define iavc_find_sc(unit)	(&iavc_sc[(unit)])
   90: 
   91: /*
   92: //  {b1,b1dma,t1}_{detect,reset}
   93: //      Routines to detect and manage the specific type of card.
   94: */
   95: 
   96: extern int      b1_detect(iavc_softc_t *sc);
   97: extern void     b1_disable_irq(iavc_softc_t *sc);
   98: extern void     b1_reset(iavc_softc_t *sc);
   99: 
  100: extern int      b1dma_detect(iavc_softc_t *sc);
  101: extern void     b1dma_reset(iavc_softc_t *sc);
  102: 
  103: extern int      t1_detect(iavc_softc_t *sc);
  104: extern void     t1_disable_irq(iavc_softc_t *sc);
  105: extern void     t1_reset(iavc_softc_t *sc);
  106: 
  107: /*
  108: //  AMCC_{READ,WRITE}
  109: //      Routines to access the memory mapped registers of the
  110: //      S5933 DMA controller.
  111: */
  112: 
  113: static __inline u_int32_t AMCC_READ(iavc_softc_t *sc, int off)
  114: {
  115:     return bus_space_read_4(sc->sc_mem_bt, sc->sc_mem_bh, off);
  116: }
  117: 
  118: static __inline void AMCC_WRITE(iavc_softc_t *sc, int off, u_int32_t value)
  119: {
  120:     bus_space_write_4(sc->sc_mem_bt, sc->sc_mem_bh, off, value);
  121: }
  122: 
  123: /*
  124: //  amcc_{put,get}_{byte,word}
  125: //      Routines to access the DMA buffers byte- or wordwise.
  126: */
  127: 
  128: static __inline u_int8_t* amcc_put_byte(u_int8_t *buf, u_int8_t value)
  129: {
  130:     *buf++ = value;
  131:     return buf;
  132: }
  133: 
  134: static __inline u_int8_t* amcc_get_byte(u_int8_t *buf, u_int8_t *value)
  135: {
  136:     *value = *buf++;
  137:     return buf;
  138: }
  139: 
  140: static __inline u_int8_t* amcc_put_word(u_int8_t *buf, u_int32_t value)
  141: {
  142:     *buf++ = (value & 0xff);
  143:     *buf++ = (value >> 8) & 0xff;
  144:     *buf++ = (value >> 16) & 0xff;
  145:     *buf++ = (value >> 24) & 0xff;
  146:     return buf;
  147: }
  148: 
  149: static __inline u_int8_t* amcc_get_word(u_int8_t *buf, u_int32_t *value)
  150: {
  151:     *value = *buf++;
  152:     *value |= (*buf++ << 8);
  153:     *value |= (*buf++ << 16);
  154:     *value |= (*buf++ << 24);
  155:     return buf;
  156: }
  157: 
  158: /*
  159: //  Controller LLI message numbers.
  160: */
  161: 
  162: #define SEND_POLL           0x72
  163: #define SEND_INIT           0x11
  164: #define SEND_REGISTER       0x12
  165: #define SEND_DATA_B3_REQ    0x13
  166: #define SEND_RELEASE        0x14
  167: #define SEND_MESSAGE        0x15
  168: #define SEND_CONFIG         0x71
  169: #define SEND_POLLACK        0x73
  170: 
  171: #define RECEIVE_POLL        0x32
  172: #define RECEIVE_INIT        0x27
  173: #define RECEIVE_MESSAGE     0x21
  174: #define RECEIVE_DATA_B3_IND 0x22
  175: #define RECEIVE_START       0x23
  176: #define RECEIVE_STOP        0x24
  177: #define RECEIVE_NEW_NCCI    0x25
  178: #define RECEIVE_FREE_NCCI   0x26
  179: #define RECEIVE_RELEASE     0x26
  180: #define RECEIVE_TASK_READY  0x31
  181: #define RECEIVE_DEBUGMSG    0x71
  182: #define RECEIVE_POLLDWORD   0x75
  183: 
  184: /* Operation constants */
  185: 
  186: #define WRITE_REGISTER      0x00
  187: #define READ_REGISTER       0x01
  188: 
  189: /* Port offsets in I/O space */
  190: 
  191: #define B1_READ             0x00
  192: #define B1_WRITE            0x01
  193: #define B1_INSTAT           0x02
  194: #define B1_OUTSTAT          0x03
  195: #define B1_ANALYSE          0x04
  196: #define B1_REVISION         0x05
  197: #define B1_RESET            0x10
  198: 
  199: #define T1_FASTLINK         0x00
  200: #define T1_SLOWLINK         0x08
  201: 
  202: #define T1_READ             B1_READ
  203: #define T1_WRITE            B1_WRITE
  204: #define T1_INSTAT           B1_INSTAT
  205: #define T1_OUTSTAT          B1_OUTSTAT
  206: #define T1_IRQENABLE        0x05
  207: #define T1_FIFOSTAT         0x06
  208: #define T1_RESETLINK        0x10
  209: #define T1_ANALYSE          0x11
  210: #define T1_IRQMASTER        0x12
  211: #define T1_IDENT            0x17
  212: #define T1_RESETBOARD       0x1f
  213: 
  214: #define T1F_IREADY          0x01
  215: #define T1F_IHALF           0x02
  216: #define T1F_IFULL           0x04
  217: #define T1F_IEMPTY          0x08
  218: #define T1F_IFLAGS          0xf0
  219: 
  220: #define T1F_OREADY          0x10
  221: #define T1F_OHALF           0x20
  222: #define T1F_OEMPTY          0x40
  223: #define T1F_OFULL           0x80
  224: #define T1F_OFLAGS          0xf0
  225: 
  226: #define FIFO_OUTBSIZE       256
  227: #define FIFO_INPBSIZE       512
  228: 
  229: #define HEMA_VERSION_ID     0
  230: #define HEMA_PAL_ID         0
  231: 
  232: /*
  233: //  S5933 DMA controller register offsets in memory, and bitmasks.
  234: */
  235: 
  236: #define AMCC_RXPTR       0x24
  237: #define AMCC_RXLEN       0x28
  238: #define AMCC_TXPTR       0x2c
  239: #define AMCC_TXLEN       0x30
  240: 
  241: #define AMCC_INTCSR      0x38
  242: #define EN_READ_TC_INT   0x00008000
  243: #define EN_WRITE_TC_INT  0x00004000
  244: #define EN_TX_TC_INT     EN_READ_TC_INT
  245: #define EN_RX_TC_INT     EN_WRITE_TC_INT
  246: #define AVM_FLAG         0x30000000
  247: 
  248: #define ANY_S5933_INT    0x00800000
  249: #define READ_TC_INT      0x00080000
  250: #define WRITE_TC_INT     0x00040000
  251: #define TX_TC_INT        READ_TC_INT
  252: #define RX_TC_INT        WRITE_TC_INT
  253: #define MASTER_ABORT_INT 0x00100000
  254: #define TARGET_ABORT_INT 0x00200000
  255: #define BUS_MASTER_INT   0x00200000
  256: #define ALL_INT          0x000c0000
  257: 
  258: #define AMCC_MCSR        0x3c
  259: #define A2P_HI_PRIORITY  0x00000100
  260: #define EN_A2P_TRANSFERS 0x00000400
  261: #define P2A_HI_PRIORITY  0x00001000
  262: #define EN_P2A_TRANSFERS 0x00004000
  263: #define RESET_A2P_FLAGS  0x04000000
  264: #define RESET_P2A_FLAGS  0x02000000
  265: 
  266: /*
  267: //  (B1IO_WAIT_MAX * B1IO_WAIT_DLY) is the max wait in us for the card
  268: //  to become ready after an I/O operation. The default is 1 ms.
  269: */
  270: 
  271: #define B1IO_WAIT_MAX    1000
  272: #define B1IO_WAIT_DLY    1
  273: 
  274: /*
  275: //  b1io_outp
  276: //      Diagnostic output routine, returns the written value via
  277: //      the device's analysis register.
  278: //
  279: //  b1io_rx_full
  280: //      Returns nonzero if data is readable from the card via the
  281: //      I/O ports.
  282: //
  283: //  b1io_tx_empty
  284: //      Returns nonzero if data can be written to the card via the
  285: //      I/O ports.
  286: */
  287: 
  288: static __inline u_int8_t b1io_outp(iavc_softc_t *sc, int off, u_int8_t val)
  289: {
  290:     bus_space_write_1(sc->sc_io_bt, sc->sc_io_bh, off, val);
  291:     DELAY(1);
  292:     return bus_space_read_1(sc->sc_io_bt, sc->sc_io_bh, B1_ANALYSE);
  293: }
  294: 
  295: static __inline int b1io_rx_full(iavc_softc_t *sc)
  296: {
  297:     u_int8_t val = bus_space_read_1(sc->sc_io_bt, sc->sc_io_bh, B1_INSTAT);
  298:     return (val & 0x01);
  299: }
  300: 
  301: static __inline int b1io_tx_empty(iavc_softc_t *sc)
  302: {
  303:     u_int8_t val = bus_space_read_1(sc->sc_io_bt, sc->sc_io_bh, B1_OUTSTAT);
  304:     return  (val & 0x01);
  305: }
  306: 
  307: /*
  308: //  b1io_{get,put}_{byte,word}
  309: //      Routines to read and write the device I/O registers byte- or
  310: //      wordwise.
  311: //
  312: //  b1io_{get,put}_slice
  313: //      Routines to read and write sequential bytes to the device
  314: //      I/O registers.
  315: */
  316: 
  317: u_int8_t b1io_get_byte(iavc_softc_t *sc);
  318: int b1io_put_byte(iavc_softc_t *sc, u_int8_t val);
  319: 
  320: int b1io_save_put_byte(iavc_softc_t *sc, u_int8_t val);
  321: 
  322: u_int32_t b1io_get_word(iavc_softc_t *sc);
  323: void b1io_put_word(iavc_softc_t *sc, u_int32_t val);
  324: 
  325: int b1io_get_slice(iavc_softc_t *sc, u_int8_t *dp);
  326: void b1io_put_slice(iavc_softc_t *sc, u_int8_t *dp, int len);
  327: 
  328: /*
  329: //  b1io_{read,write}_reg
  330: //      Routines to read and write the device registers via the I/O
  331: //      ports.
  332: */
  333: 
  334: u_int32_t b1io_read_reg(iavc_softc_t *sc, int reg);
  335: u_int32_t b1io_write_reg(iavc_softc_t *sc, int reg, u_int32_t val);
  336: 
  337: /*
  338: //  t1io_outp
  339: //      I/O port write operation for the T1, which does not seem
  340: //      to have the analysis port.
  341: */
  342: 
  343: static __inline void t1io_outp(iavc_softc_t *sc, int off, u_int8_t val)
  344: {
  345:     bus_space_write_1(sc->sc_io_bt, sc->sc_io_bh, off, val);
  346: }
  347: 
  348: static __inline u_int8_t t1io_inp(iavc_softc_t *sc, int off)
  349: {
  350:     return bus_space_read_1(sc->sc_io_bt, sc->sc_io_bh, off);
  351: }
  352: 
  353: static __inline int t1io_isfastlink(iavc_softc_t *sc)
  354: {
  355:     return ((bus_space_read_1(sc->sc_io_bt, sc->sc_io_bh, T1_IDENT) & ~0x82) == 1);
  356: }
  357: 
  358: static __inline u_int8_t t1io_fifostatus(iavc_softc_t *sc)
  359: {
  360:     return bus_space_read_1(sc->sc_io_bt, sc->sc_io_bh, T1_FIFOSTAT);
  361: }
  362: 
  363: int t1io_get_slice(iavc_softc_t *sc, u_int8_t *dp);
  364: void t1io_put_slice(iavc_softc_t *sc, u_int8_t *dp, int len);
  365: 
  366: /*
  367: //  An attempt to bring it all together:
  368: //  ------------------------------------
  369: //
  370: //  iavc_{read,write}_reg
  371: //      Routines to access the device registers via the I/O port.
  372: //
  373: //  iavc_{read,write}_port
  374: //      Routines to access the device I/O ports.
  375: //
  376: //  iavc_tx_empty, iavc_rx_full
  377: //      Routines to check when the device has drained the last written
  378: //      byte, or produced a full byte to read.
  379: //
  380: //  iavc_{get,put}_byte
  381: //      Routines to read/write byte values to the device via the I/O port.
  382: //
  383: //  iavc_{get,put}_word
  384: //      Routines to read/write 32-bit words to the device via the I/O port.
  385: //
  386: //  iavc_{get,put}_slice
  387: //      Routines to read/write {length, data} pairs to the device via the
  388: //      ubiquituous I/O port. Uses the HEMA FIFO on a T1.
  389: */
  390: 
  391: #define iavc_read_reg(sc, reg) b1io_read_reg(sc, reg)
  392: #define iavc_write_reg(sc, reg, val) b1io_write_reg(sc, reg, val)
  393: 
  394: #define iavc_read_port(sc, port) \
  395:         bus_space_read_1(sc->sc_io_bt, sc->sc_io_bh, (port))
  396: #define iavc_write_port(sc, port, val) \
  397:         bus_space_write_1(sc->sc_io_bt, sc->sc_io_bh, (port), (val))
  398: 
  399: #define iavc_tx_empty(sc)      b1io_tx_empty(sc)
  400: #define iavc_rx_full(sc)       b1io_rx_full(sc)
  401: 
  402: #define iavc_get_byte(sc)      b1io_get_byte(sc)
  403: #define iavc_put_byte(sc, val) b1io_put_byte(sc, val)
  404: #define iavc_get_word(sc)      b1io_get_word(sc)
  405: #define iavc_put_word(sc, val) b1io_put_word(sc, val)
  406: 
  407: static __inline u_int32_t iavc_get_slice(iavc_softc_t *sc, u_int8_t *dp)
  408: {
  409:     if (sc->sc_t1) return t1io_get_slice(sc, dp);
  410:     else return b1io_get_slice(sc, dp);
  411: }
  412: 
  413: static __inline void iavc_put_slice(iavc_softc_t *sc, u_int8_t *dp, int len)
  414: {
  415:     if (sc->sc_t1) t1io_put_slice(sc, dp, len);
  416:     else b1io_put_slice(sc, dp, len);
  417: }
  418: 
  419: /*
  420: //  iavc_handle_intr
  421: //      Interrupt handler, called by the bus specific interrupt routine
  422: //      in iavc_<bustype>.c module.
  423: //
  424: //  iavc_load
  425: //      CAPI callback. Resets device and loads firmware.
  426: //
  427: //  iavc_register
  428: //      CAPI callback. Registers an application id.
  429: //
  430: //  iavc_release
  431: //      CAPI callback. Releases an application id.
  432: //
  433: //  iavc_send
  434: //      CAPI callback. Sends a CAPI message. A B3_DATA_REQ message has
  435: //      m_next point to a data mbuf.
  436: */
  437: 
  438: extern void iavc_handle_intr(iavc_softc_t *);
  439: extern int iavc_load(capi_softc_t *, int, u_int8_t *);
  440: extern int iavc_register(capi_softc_t *, int, int);
  441: extern int iavc_release(capi_softc_t *, int);
  442: extern int iavc_send(capi_softc_t *, struct mbuf *);
  443: 
  444: extern void b1isa_setup_irq(struct iavc_softc *sc);
  445: 
  446: #endif /* _CAPI_IAVC_H_ */