DragonFly commits List (threaded) for 2005-11
cvs commit: src/sys/conf options.i386 src/sys/i386/i386 initcpu.c
dillon 2005/11/04 15:20:35 PST
DragonFly src repository
Solve the continuous stream of spurious IRQ 7's that occur on machines
with AMDX2 (dual core) cpus. It's a BIOS bug. If a BIOS running this cpu
does not set the LINTEN bit in the Hyper Transport Transaction Control
Register, incoming interrupts from the 8259 will go the INTR/NMI pins for
BOTH cpus, causing *TWO* interrupt ack cycles (one from each cpu). The
second cycle usually results in a spurious interrupt vector (typically IRQ 7)
getting hit. The spurious interrupt vector is not subject to the 8259's
At the moment the fix requires specifying a cpu option in your kernel config:
This problem can occur when the kernel is operating in ICU (8259) mode,
in an SMP configuration, or if you are attempting to route
one or more ISA interrupts, such as the 8254 clock, through the 8259 in
an SMP configuration.
When the bit is set, the incoming INTR/NMI is routed to both LAPIC's
LINT0/LINT1, which is what we expect. When the bit is not set, INTR/NMI
goes to both cpus simultaniously, which is bad. In addition, having both
the LAPIC and the 8259 responding to the INTA bus cycle can create serious
general interrupt routing issues.
Symptoms of the problem:
* The 8259 never gets routed through to LINT0/LINT1, no matter how the
IMCR is set or what the MPTable reports.
* Every 8259 interrupt causes an additional spurious interrupt to occur.
* Interrupt routing in general is more severely broken then usual.
* The kernel is unable to get the 8254 clock interrupt routed.
PS: This took 30 man hours to locate, so give me credit if you transplant
Revision Changes Path
1.13 +1 -0 src/sys/conf/options.i386
1.7 +26 -0 src/sys/i386/i386/initcpu.c