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git: kernel - Adjust AHCI driver to deal with AMD braindamage / 880G chipset

From: Matthew Dillon <dillon@xxxxxxxxxxxxxxxxxxxxxxx>
Date: Thu, 16 Sep 2010 19:56:18 -0700 (PDT)

commit 492bffafd6e93f1740fdb67ebe789de127625782
Author: Matthew Dillon <dillon@apollo.backplane.com>
Date:   Thu Sep 16 14:57:27 2010 -0700

    kernel - Adjust AHCI driver to deal with AMD braindamage / 880G chipset
    * As of this writing AMD has some new chipsets out for AM3 MBs which
      supports AHCI on 5 SATA + 1 E-SATA connector.  My testing was done
      on a MB with the 880G chipset.
      The AHCI firmware for this chipset is a bit on the rough side.  It
      seems a bit slow on the INIT/device-detection sequencing (possibly due
      to longer PHY training time?  It's supposed to be a 6GBit PHY), and it
      generates a stream of PCS interrupts for some devices.
      My assumption is that the PCS interrupts are not being masked by the
      chipset during the INIT phase.  Both IFS and PCS interrupts seem to
      occur during INIT/RESET and PM probing stages.
      In addition, at least one drive... an Intel SSD, caused a large number
      of PCS interrupts during the INIT phase even when connected to an
      internal SATA port at power-on.  This is clearly a bug in the AMD
      AHCI chipset, again related to their firmware not internally masking
      communications glitches during INIT, and/or taking an extra long time
      to train the PHY.
    * Adjust the AHCI driver to deal with this situation.  Limit the interrupt
      rate for PCS errors and do harsh reinitialization of the port when we get
      a PCS error, along with allowing extra time for the device detect to
    * As a side benefit the AHCI driver should be able to deal with device
      connection and disconnection on non-hot-swap-capable ports, at least
      up to a point.
    * Silence some of the console output during probe.
    * Try harder to clear the CI/SACT registers when stopping a port.  Some
      chipsets appear to not clear the registers when we cycle ST when they
      have already stopped the command processor, possibly as part of the IFS
      or PCS interrupt paths.
    * Fix a bug where an IFS or PCS interrupt marks a probe command (software
      reset sequence) as complete when it actually errored-out.
    * Sleep longer between retries if a command fails due to an IFS error.
      When testing with the WD Green drives a drive inserted into a PM
      enclosure cold seems to take longer to start up during the COMRESET
      sequence.  This only seems to occur with the AMD chipset and does
      not occur with the older NVidia chipset.  IFS errors occur for several
      seconds beyond what I would consider a reasonable sleep interval.

Summary of changes:
 sys/dev/disk/ahci/ahci.c    |  351 ++++++++++++++++++++++++++++++++++---------
 sys/dev/disk/ahci/ahci.h    |    3 +-
 sys/dev/disk/ahci/ahci_pm.c |   89 +++++++----
 sys/dev/disk/ahci/atascsi.h |    2 +
 4 files changed, 338 insertions(+), 107 deletions(-)


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