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Re: PCI Express

From: Chuck Tuffli <chuck_tuffli@xxxxxxxxxxx>
Date: Wed, 25 Aug 2004 10:00:17 -0700

On Wed, Aug 25, 2004 at 03:13:15PM +0200, Jeroen Ruigrok/asmodai wrote:
. ..
> I doubt any drivers or lowlevel routines need to be rewritten to accomodate
> for the shared -> point-to-point change in the specification.

Correct. The mandate for PCIe was backwards compatibility for
software. For example, I was able to use a new express device with
relatively few changes compared to the PCI-X driver. At this point, my
belief is that the bigest changes are for

- there are a handful of express registers that allow the kernel or
  drivers to tune the size of requests going across the links, detect
  link errors, retrain the links, etc. none of these are mandatory to
  use but can be quite useful.
- config space is now 4096 bytes as opposed to 256. most of the
  express control and status structures are located above offset
  0x100. to access these registers, there is a memory range that
  decodes memory access to config packets with the extra register

- MSI is now mandatory for devices, although legacy INTx support
  exists to help with the transition to express.

- Active State Power Management (ASPM). I haven't played with this and
  don't know how many first generation devices are going to support it.

Chuck Tuffli
Agilent Technologies, Storage Area Networking

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