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DragonFly kernel List (threaded) for 2005-06
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Re: PAE with dragonfly

From: Craig Dooley <xlnxminusx@xxxxxxxxx>
Date: Wed, 8 Jun 2005 15:36:21 -0400

PAE lets you address 36 bits (although like you said, only 32 at a
time), but it makes the paging structures 64bits long, and AMD64 long
mode is built off the same structures.  The AMD64 manuals say you need
to enable PAE before enabling long mode.  Granted this would probably
mean only setting up a small page table before jumping to long mode,
but wouldn't the infrastructure for PAE on x86 make it easier to
implement AMD64?


On 6/8/05, David Rhodus <sdrhodus@xxxxxxxxx> wrote:
> On 6/8/05, Craig Dooley <xlnxminusx@xxxxxxxxx> wrote:
> > Doesn't AMD64 use PAE for large address spaces?  I thought the Page
> > Table structures were the same for both.
> >
> > -Craig
> No, on AMD64 when operating in long mode the address space is 64bit.
> PAE is a 32bit hack that lets you access a few more bits.  34, 37 ?  I
> don't recall exactly off the top of my head.
> There are some interesting uses for PAE on the regular ia32
> architecture such as allowing the kernel a full 4Gig memory and the
> userland a full 4Gig of memory.  This actually makes the kernels life
> a lot easier, though almost no one has this type of setup so its
> mostly a moot development point.  About a year ago I had a working
> implementation of PAE working on DragonFly, though I only had one test
> machine with 4.5 Gigs of memory.  I also only had access to the
> machine for a few days so I never had time to go through and optimize
> the code.
> I can look around for the old patch if someone has access to some
> machines with more than 4 gigs of memory and someone that also has
> time to revive it.
> -DR

Craig Dooley <xlnxminusx@xxxxxxxxx>

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