From 1a361eba58f899b55978d500a6be8f55bdb005b0 Mon Sep 17 00:00:00 2001
From: Sascha Wildner <saw@online.de>
Date: Tue, 18 Mar 2014 21:37:17 +0100
Subject: [PATCH] usb4bsd: Sync run(4) with FreeBSD.

---
 etc/devd/usb.conf            |   34 +-
 share/man/man4/run.4         |   30 +-
 sys/bus/u4b/wlan/if_run.c    | 1826 ++++++++++++++++++++++++++++++++------
 sys/bus/u4b/wlan/if_runreg.h | 1998 +++++++++++++++++++++++++-----------------
 sys/bus/u4b/wlan/if_runvar.h |   62 +-
 5 files changed, 2868 insertions(+), 1082 deletions(-)

diff --git a/etc/devd/usb.conf b/etc/devd/usb.conf
index 3a43c1f..10c5038 100644
--- a/etc/devd/usb.conf
+++ b/etc/devd/usb.conf
@@ -487,6 +487,14 @@ nomatch 32 {
 	match "bus" "uhub[0-9]+";
 	match "mode" "host";
 	match "vendor" "0x050d";
+	match "product" "0x1103";
+	action "kldload -n if_run";
+};
+
+nomatch 32 {
+	match "bus" "uhub[0-9]+";
+	match "mode" "host";
+	match "vendor" "0x050d";
 	match "product" "0x1203";
 	action "kldload -n ubsa";
 };
@@ -535,7 +543,7 @@ nomatch 32 {
 	match "bus" "uhub[0-9]+";
 	match "mode" "host";
 	match "vendor" "0x050d";
-	match "product" "0x935a";
+	match "product" "(0x935a|0x935b)";
 	action "kldload -n if_run";
 };
 
@@ -662,6 +670,14 @@ nomatch 32 {
 nomatch 32 {
 	match "bus" "uhub[0-9]+";
 	match "mode" "host";
+	match "vendor" "0x0586";
+	match "product" "0x3421";
+	action "kldload -n if_run";
+};
+
+nomatch 32 {
+	match "bus" "uhub[0-9]+";
+	match "mode" "host";
 	match "vendor" "0x058f";
 	match "product" "0x9720";
 	action "kldload -n uplcom";
@@ -1167,6 +1183,14 @@ nomatch 32 {
 	match "bus" "uhub[0-9]+";
 	match "mode" "host";
 	match "vendor" "0x0b05";
+	match "product" "0x17ad";
+	action "kldload -n if_run";
+};
+
+nomatch 32 {
+	match "bus" "uhub[0-9]+";
+	match "mode" "host";
+	match "vendor" "0x0b05";
 	match "product" "(0x4200|0x4201|0x4202|0x420f|0x9200|0x9202)";
 	action "kldload -n uipaq";
 };
@@ -1903,7 +1927,7 @@ nomatch 32 {
 	match "bus" "uhub[0-9]+";
 	match "mode" "host";
 	match "vendor" "0x148f";
-	match "product" "(0x2770|0x2870|0x3070|0x3071|0x3072|0x3370|0x3572|0x8070)";
+	match "product" "(0x2770|0x2870|0x2878|0x3070|0x3071|0x3072|0x3370|0x3572|0x3573|0x5370|0x5572|0x8070)";
 	action "kldload -n if_run";
 };
 
@@ -2391,7 +2415,7 @@ nomatch 32 {
 	match "bus" "uhub[0-9]+";
 	match "mode" "host";
 	match "vendor" "0x2001";
-	match "product" "(0x3c09|0x3c0a)";
+	match "product" "(0x3c09|0x3c0a|0x3c15|0x3c1a|0x3c1b|0x3c1f)";
 	action "kldload -n if_run";
 };
 
@@ -2639,7 +2663,7 @@ nomatch 32 {
 	match "bus" "uhub[0-9]+";
 	match "mode" "host";
 	match "vendor" "0x7392";
-	match "product" "(0x7711|0x7717|0x7718)";
+	match "product" "(0x7711|0x7717|0x7718|0x7733)";
 	action "kldload -n if_run";
 };
 
@@ -2793,5 +2817,5 @@ nomatch 32 {
 	action "kldload -n umass";
 };
 
-# 1401 USB entries processed
+# 1414 USB entries processed
 
diff --git a/share/man/man4/run.4 b/share/man/man4/run.4
index 4823206..aa3ad95 100644
--- a/share/man/man4/run.4
+++ b/share/man/man4/run.4
@@ -14,9 +14,9 @@
 .\" ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 .\" OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 .\"
-.\" $FreeBSD: src/share/man/man4/run.4,v 1.12 2013/02/14 01:11:38 svnexp Exp $
+.\" $FreeBSD: head/share/man/man4/run.4 260219 2014-01-03 06:01:05Z kevlo $
 .\"
-.Dd August 18, 2013
+.Dd March 17, 2014
 .Dt RUN 4
 .Os
 .Sh NAME
@@ -52,7 +52,7 @@ runfw_load="YES"
 The
 .Nm
 driver supports USB 2.0 wireless adapters based on the Ralink RT2700U,
-RT2800U and RT3000U chipsets.
+RT2800U, RT3000U and RT3900E chipsets.
 .Pp
 The RT2700U chipset consists of two integrated chips, an RT2770 MAC/BBP and
 an RT2720 (1T2R) or RT2750 (dual-band 1T2R) radio transceiver.
@@ -64,6 +64,18 @@ The RT3000U is a single-chip solution based on an RT3070 MAC/BBP and
 an RT3020 (1T1R), RT3021 (1T2R) or RT3022 (2T2R) single-band radio
 transceiver.
 .Pp
+The RT3900E is a single-chip USB 2.0 802.11n solution.
+The MAC/Baseband Processor can be an RT3593, RT5390, RT5392 or an RT5592.
+The radio can be an RT3053, RT5370, RT5372 or an RT5572.
+The RT3053 chip operates in the 2GHz and 5GHz spectra and supports up to
+3 transmit paths and 3 receiver paths (3T3R).
+The RT5370 chip operates in the 2GHz spectrum and supports 1 transmit path
+and 1 receiver path (1T1R).
+The RT5372 chip operates in the 2GHz spectrum and supports up to 2 transmit
+paths and 2 receiver paths (2T2R).
+The RT5572 chip operates in the 2GHz and 5GHz spectra and supports up to
+2 transmit paths and 2 receiver paths (2T2R).
+.Pp
 These are the modes the
 .Nm
 driver can operate in:
@@ -113,11 +125,13 @@ driver supports the following wireless adapters:
 .It Airlink101 AWLL6090
 .It ASUS USB-N11
 .It ASUS USB-N13 ver. A1
+.It ASUS USB-N66
 .It ASUS WL-160N
 .It Belkin F5D8051 ver 3000
 .It Belkin F5D8053
 .It Belkin F5D8055
 .It Belkin F6D4050 ver 1
+.It Belkin F9L1103
 .It Buffalo WLI-UC-AG300N
 .It Buffalo WLI-UC-G300N
 .It Buffalo WLI-UC-G301N
@@ -129,12 +143,15 @@ driver supports the following wireless adapters:
 .It Corega CG-WLUSB300AGN
 .It Corega CG-WLUSB300GNM
 .It D-Link DWA-130 rev B1
-.It D-Link DWA-140 rev B1, B2
+.It D-Link DWA-140 rev B1, B2, B3, D1
+.It D-Link DWA-160 rev B2
+.It D-Link DWA-162
 .It DrayTek Vigor N61
 .It Edimax EW-7711UAn
 .It Edimax EW-7711UTn
 .It Edimax EW-7717Un
 .It Edimax EW-7718Un
+.It Edimax EW-7733UnD
 .It Gigabyte GN-WB30N
 .It Gigabyte GN-WB31N
 .It Gigabyte GN-WB32L
@@ -156,8 +173,11 @@ driver supports the following wireless adapters:
 .It SMC SMCWUSBS-N2
 .It Sweex LW303
 .It Sweex LW313
+.It TP-LINK TL-WDN3200
+.It TP-LINK TL-WN727N v3
 .It Unex DNUR-81
 .It Unex DNUR-82
+.It ZyXEL NWD2705
 .It ZyXEL NWD210N
 .It ZyXEL NWD270N
 .El
@@ -230,4 +250,4 @@ driver was written by
 The
 .Nm
 driver does not support any of the 802.11n capabilities offered by the
-RT2800 and RT3000 chipsets.
+RT2800, RT3000 and RT3900 chipsets.
diff --git a/sys/bus/u4b/wlan/if_run.c b/sys/bus/u4b/wlan/if_run.c
index f52ddd2..d588c6f 100644
--- a/sys/bus/u4b/wlan/if_run.c
+++ b/sys/bus/u4b/wlan/if_run.c
@@ -2,6 +2,7 @@
  * Copyright (c) 2008,2010 Damien Bergamini <damien.bergamini@free.fr>
  * ported to FreeBSD by Akinori Furukoshi <moonlightakkiy@yahoo.ca>
  * USB Consulting, Hans Petter Selasky <hselasky@freebsd.org>
+ * Copyright (c) 2013-2014 Kevin Lo
  *
  * Permission to use, copy, modify, and distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -15,11 +16,11 @@
  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  *
- * $FreeBSD: src/sys/dev/usb/wlan/if_run.c,v 1.40 2013/03/19 02:17:34 svnexp Exp $
+ * $FreeBSD: head/sys/dev/usb/wlan/if_run.c 262795 2014-03-05 18:39:27Z hselasky $
  */
 
 /*-
- * Ralink Technology RT2700U/RT2800U/RT3000U chipset driver.
+ * Ralink Technology RT2700U/RT2800U/RT3000U/RT3900E chipset driver.
  * http://www.ralinktech.com/
  */
 
@@ -42,6 +43,7 @@
 
 #include <net/bpf.h>
 #include <net/if.h>
+#include <net/if_var.h>
 #include <net/if_arp.h>
 #include <net/ethernet.h>
 #include <net/if_dl.h>
@@ -64,14 +66,15 @@
 #include <bus/u4b/usbdi.h>
 #include "usbdevs.h"
 
-#define USB_DEBUG_VAR run_debug
+#define	USB_DEBUG_VAR	run_debug
 #include <bus/u4b/usb_debug.h>
+#include <bus/u4b/usb_msctest.h>
 
 #include <bus/u4b/wlan/if_runreg.h>
 #include <bus/u4b/wlan/if_runvar.h>
 
 #ifdef	USB_DEBUG
-#define RUN_DEBUG
+#define	RUN_DEBUG
 #endif
 
 #ifdef	RUN_DEBUG
@@ -81,17 +84,20 @@ SYSCTL_INT(_hw_usb_run, OID_AUTO, debug, CTLFLAG_RW, &run_debug, 0,
     "run debug level");
 #endif
 
-#define IEEE80211_HAS_ADDR4(wh) \
+#define	IEEE80211_HAS_ADDR4(wh)	\
 	(((wh)->i_fc[1] & IEEE80211_FC1_DIR_MASK) == IEEE80211_FC1_DIR_DSTODS)
 
 /*
  * Because of LOR in run_key_delete(), use atomic instead.
  * '& RUN_CMDQ_MASQ' is to loop cmdq[].
  */
-#define RUN_CMDQ_GET(c)	(atomic_fetchadd_32((c), 1) & RUN_CMDQ_MASQ)
+#define	RUN_CMDQ_GET(c)	(atomic_fetchadd_32((c), 1) & RUN_CMDQ_MASQ)
 
 static const STRUCT_USB_HOST_ID run_devs[] = {
-#define RUN_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) }
+#define	RUN_DEV(v,p)	{ USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) }
+#define	RUN_DEV_EJECT(v,p)	\
+	{ USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, RUN_EJECT) }
+#define	RUN_EJECT	1
     RUN_DEV(ABOCOM,		RT2770),
     RUN_DEV(ABOCOM,		RT2870),
     RUN_DEV(ABOCOM,		RT3070),
@@ -130,6 +136,7 @@ static const STRUCT_USB_HOST_ID run_devs[] = {
     RUN_DEV(ASUS,		RT2870_5),
     RUN_DEV(ASUS,		USBN13),
     RUN_DEV(ASUS,		RT3070_1),
+    RUN_DEV(ASUS,		USBN66),
     RUN_DEV(ASUS,		USB_N53),
     RUN_DEV(ASUS2,		USBN11),
     RUN_DEV(AZUREWAVE,		RT2870_1),
@@ -137,10 +144,12 @@ static const STRUCT_USB_HOST_ID run_devs[] = {
     RUN_DEV(AZUREWAVE,		RT3070_1),
     RUN_DEV(AZUREWAVE,		RT3070_2),
     RUN_DEV(AZUREWAVE,		RT3070_3),
+    RUN_DEV(BELKIN,		F9L1103),
     RUN_DEV(BELKIN,		F5D8053V3),
     RUN_DEV(BELKIN,		F5D8055),
     RUN_DEV(BELKIN,		F5D8055V2),
     RUN_DEV(BELKIN,		F6D4050V1),
+    RUN_DEV(BELKIN,		F6D4050V2),
     RUN_DEV(BELKIN,		RT2870_1),
     RUN_DEV(BELKIN,		RT2870_2),
     RUN_DEV(CISCOLINKSYS,	AE1000),
@@ -165,6 +174,10 @@ static const STRUCT_USB_HOST_ID run_devs[] = {
     RUN_DEV(CYBERTAN,		RT2870),
     RUN_DEV(DLINK,		RT2870),
     RUN_DEV(DLINK,		RT3072),
+    RUN_DEV(DLINK,		DWA127),
+    RUN_DEV(DLINK,		DWA140B3),
+    RUN_DEV(DLINK,		DWA160B2),
+    RUN_DEV(DLINK,		DWA162),
     RUN_DEV(DLINK2,		DWA130),
     RUN_DEV(DLINK2,		RT2870_1),
     RUN_DEV(DLINK2,		RT2870_2),
@@ -177,6 +190,7 @@ static const STRUCT_USB_HOST_ID run_devs[] = {
     RUN_DEV(DLINK2,		RT3072_1),
     RUN_DEV(EDIMAX,		EW7717),
     RUN_DEV(EDIMAX,		EW7718),
+    RUN_DEV(EDIMAX,		EW7733UND),
     RUN_DEV(EDIMAX,		RT2870_1),
     RUN_DEV(ENCORE,		RT3070_1),
     RUN_DEV(ENCORE,		RT3070_2),
@@ -248,6 +262,9 @@ static const STRUCT_USB_HOST_ID run_devs[] = {
     RUN_DEV(RALINK,		RT3072),
     RUN_DEV(RALINK,		RT3370),
     RUN_DEV(RALINK,		RT3572),
+    RUN_DEV(RALINK,		RT3573),
+    RUN_DEV(RALINK,		RT5370),
+    RUN_DEV(RALINK,		RT5572),
     RUN_DEV(RALINK,		RT8070),
     RUN_DEV(SAMSUNG,		WIS09ABGN),
     RUN_DEV(SAMSUNG2,		RT2870_1),
@@ -295,6 +312,9 @@ static const STRUCT_USB_HOST_ID run_devs[] = {
     RUN_DEV(ZINWELL,		RT3072_2),
     RUN_DEV(ZYXEL,		RT2870_1),
     RUN_DEV(ZYXEL,		RT2870_2),
+    RUN_DEV_EJECT(ZYXEL,	NWD2705),
+    RUN_DEV_EJECT(RALINK,	RT_STOR),
+#undef RUN_DEV_EJECT
 #undef RUN_DEV
 };
 
@@ -310,8 +330,11 @@ static usb_callback_t	run_bulk_tx_callback3;
 static usb_callback_t	run_bulk_tx_callback4;
 static usb_callback_t	run_bulk_tx_callback5;
 
+static void	run_autoinst(void *, struct usb_device *,
+		    struct usb_attach_arg *);
+static int	run_driver_loaded(struct module *, int, void *);
 static void	run_bulk_tx_callbackN(struct usb_xfer *xfer,
-		    usb_error_t error, unsigned int index);
+		    usb_error_t error, u_int index);
 static struct ieee80211vap *run_vap_create(struct ieee80211com *,
 		    const char [IFNAMSIZ], int, enum ieee80211_opmode, int,
 		    const uint8_t [IEEE80211_ADDR_LEN],
@@ -333,15 +356,18 @@ static int	run_write(struct run_softc *, uint16_t, uint32_t);
 static int	run_write_region_1(struct run_softc *, uint16_t,
 		    const uint8_t *, int);
 static int	run_set_region_4(struct run_softc *, uint16_t, uint32_t, int);
+static int	run_efuse_read(struct run_softc *, uint16_t, uint16_t *, int);
 static int	run_efuse_read_2(struct run_softc *, uint16_t, uint16_t *);
 static int	run_eeprom_read_2(struct run_softc *, uint16_t, uint16_t *);
-static int	run_rt2870_rf_write(struct run_softc *, uint8_t, uint32_t);
+static int	run_rt2870_rf_write(struct run_softc *, uint32_t);
 static int	run_rt3070_rf_read(struct run_softc *, uint8_t, uint8_t *);
 static int	run_rt3070_rf_write(struct run_softc *, uint8_t, uint8_t);
 static int	run_bbp_read(struct run_softc *, uint8_t, uint8_t *);
 static int	run_bbp_write(struct run_softc *, uint8_t, uint8_t);
 static int	run_mcu_cmd(struct run_softc *, uint8_t, uint16_t);
-static const char *run_get_rf(int);
+static const char *run_get_rf(uint16_t);
+static void	run_rt3593_get_txpower(struct run_softc *);
+static void	run_get_txpower(struct run_softc *);
 static int	run_read_eeprom(struct run_softc *);
 static struct ieee80211_node *run_node_alloc(struct ieee80211vap *,
 			    const uint8_t mac[IEEE80211_ADDR_LEN]);
@@ -353,7 +379,7 @@ static void	run_key_update_begin(struct ieee80211vap *);
 static void	run_key_update_end(struct ieee80211vap *);
 static void	run_key_set_cb(void *);
 static int	run_key_set(struct ieee80211vap *, struct ieee80211_key *,
-			    const uint8_t mac[IEEE80211_ADDR_LEN]);
+		    const uint8_t mac[IEEE80211_ADDR_LEN]);
 static void	run_key_delete_cb(void *);
 static int	run_key_delete(struct ieee80211vap *, struct ieee80211_key *);
 static void	run_ratectl_to(void *);
@@ -380,12 +406,16 @@ static int	run_raw_xmit(struct ieee80211_node *, struct mbuf *,
 static void	run_start_locked(struct ifnet *);
 static void	run_start(struct ifnet *, struct ifaltq_subque *);
 static int	run_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
+static void	run_iq_calib(struct run_softc *, u_int);
 static void	run_set_agc(struct run_softc *, uint8_t);
 static void	run_select_chan_group(struct run_softc *, int);
 static void	run_set_rx_antenna(struct run_softc *, int);
 static void	run_rt2870_set_chan(struct run_softc *, u_int);
 static void	run_rt3070_set_chan(struct run_softc *, u_int);
 static void	run_rt3572_set_chan(struct run_softc *, u_int);
+static void	run_rt3593_set_chan(struct run_softc *, u_int);
+static void	run_rt5390_set_chan(struct run_softc *, u_int);
+static void	run_rt5592_set_chan(struct run_softc *, u_int);
 static int	run_set_chan(struct run_softc *, struct ieee80211_channel *);
 static void	run_set_channel(struct ieee80211com *);
 static void	run_scan_start(struct ieee80211com *);
@@ -409,16 +439,46 @@ static void	run_update_mcast(struct ifnet *);
 static int8_t	run_rssi2dbm(struct run_softc *, uint8_t, uint8_t);
 static void	run_update_promisc_locked(struct ifnet *);
 static void	run_update_promisc(struct ifnet *);
+static void	run_rt5390_bbp_init(struct run_softc *);
 static int	run_bbp_init(struct run_softc *);
 static int	run_rt3070_rf_init(struct run_softc *);
+static void	run_rt3593_rf_init(struct run_softc *);
+static void	run_rt5390_rf_init(struct run_softc *);
 static int	run_rt3070_filter_calib(struct run_softc *, uint8_t, uint8_t,
 		    uint8_t *);
 static void	run_rt3070_rf_setup(struct run_softc *);
+static void	run_rt3593_rf_setup(struct run_softc *);
+static void	run_rt5390_rf_setup(struct run_softc *);
 static int	run_txrx_enable(struct run_softc *);
+static void	run_adjust_freq_offset(struct run_softc *);
 static void	run_init(void *);
 static void	run_init_locked(struct run_softc *);
 static void	run_stop(void *);
-static void	run_delay(struct run_softc *, unsigned int);
+static void	run_delay(struct run_softc *, u_int);
+
+static eventhandler_tag run_etag;
+
+static const struct rt2860_rate {
+	uint8_t		rate;
+	uint8_t		mcs;
+	enum		ieee80211_phytype phy;
+	uint8_t		ctl_ridx;
+	uint16_t	sp_ack_dur;
+	uint16_t	lp_ack_dur;
+} rt2860_rates[] = {
+	{   2, 0, IEEE80211_T_DS,   0, 314, 314 },
+	{   4, 1, IEEE80211_T_DS,   1, 258, 162 },
+	{  11, 2, IEEE80211_T_DS,   2, 223, 127 },
+	{  22, 3, IEEE80211_T_DS,   3, 213, 117 },
+	{  12, 0, IEEE80211_T_OFDM, 4,  60,  60 },
+	{  18, 1, IEEE80211_T_OFDM, 4,  52,  52 },
+	{  24, 2, IEEE80211_T_OFDM, 6,  48,  48 },
+	{  36, 3, IEEE80211_T_OFDM, 6,  44,  44 },
+	{  48, 4, IEEE80211_T_OFDM, 8,  44,  44 },
+	{  72, 5, IEEE80211_T_OFDM, 8,  40,  40 },
+	{  96, 6, IEEE80211_T_OFDM, 8,  40,  40 },
+	{ 108, 7, IEEE80211_T_OFDM, 8,  40,  40 }
+};
 
 static const struct {
 	uint16_t	reg;
@@ -432,6 +492,25 @@ static const struct {
 	uint8_t	val;
 } rt2860_def_bbp[] = {
 	RT2860_DEF_BBP
+},rt5390_def_bbp[] = {
+	RT5390_DEF_BBP
+},rt5592_def_bbp[] = {
+	RT5592_DEF_BBP
+};
+
+/* 
+ * Default values for BBP register R196 for RT5592.
+ */
+static const uint8_t rt5592_bbp_r196[] = {
+	0xe0, 0x1f, 0x38, 0x32, 0x08, 0x28, 0x19, 0x0a, 0xff, 0x00,
+	0x16, 0x10, 0x10, 0x0b, 0x36, 0x2c, 0x26, 0x24, 0x42, 0x36,
+	0x30, 0x2d, 0x4c, 0x46, 0x3d, 0x40, 0x3e, 0x42, 0x3d, 0x40,
+	0x3c, 0x34, 0x2c, 0x2f, 0x3c, 0x35, 0x2e, 0x2a, 0x49, 0x41,
+	0x36, 0x31, 0x30, 0x30, 0x0e, 0x0d, 0x28, 0x21, 0x1c, 0x16,
+	0x50, 0x4a, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x7d, 0x14, 0x32, 0x2c, 0x36, 0x4c, 0x43, 0x2c,
+	0x2e, 0x36, 0x30, 0x6e
 };
 
 static const struct rfprog {
@@ -447,6 +526,15 @@ struct {
 	RT3070_RF3052
 };
 
+static const struct rt5592_freqs {
+	uint16_t	n;
+	uint8_t		k, m, r;
+} rt5592_freqs_20mhz[] = {
+	RT5592_RF5592_20MHZ
+},rt5592_freqs_40mhz[] = {
+	RT5592_RF5592_40MHZ
+};
+
 static const struct {
 	uint8_t	reg;
 	uint8_t	val;
@@ -454,6 +542,27 @@ static const struct {
 	RT3070_DEF_RF
 },rt3572_def_rf[] = {
 	RT3572_DEF_RF
+},rt3593_def_rf[] = {
+	RT3593_DEF_RF
+},rt5390_def_rf[] = {
+	RT5390_DEF_RF
+},rt5392_def_rf[] = {
+	RT5392_DEF_RF
+},rt5592_def_rf[] = {
+	RT5592_DEF_RF
+},rt5592_2ghz_def_rf[] = {
+	RT5592_2GHZ_DEF_RF
+},rt5592_5ghz_def_rf[] = {
+	RT5592_5GHZ_DEF_RF
+};
+
+static const struct {
+	u_int	firstchan;
+	u_int	lastchan;
+	uint8_t	reg;
+	uint8_t	val;
+} rt5592_chan_5ghz[] = {
+	RT5592_CHAN_5GHZ
 };
 
 static const struct usb_config run_config[RUN_N_XFER] = {
@@ -527,6 +636,46 @@ static const struct usb_config run_config[RUN_N_XFER] = {
     }
 };
 
+static void
+run_autoinst(void *arg, struct usb_device *udev,
+    struct usb_attach_arg *uaa)
+{
+	struct usb_interface *iface;
+	struct usb_interface_descriptor *id;
+
+	if (uaa->dev_state != UAA_DEV_READY)
+		return;
+
+	iface = usbd_get_iface(udev, 0);
+	if (iface == NULL)
+		return;
+	id = iface->idesc;
+	if (id == NULL || id->bInterfaceClass != UICLASS_MASS)
+		return;
+	if (usbd_lookup_id_by_uaa(run_devs, sizeof(run_devs), uaa))
+		return;
+
+	if (usb_msc_eject(udev, 0, MSC_EJECT_STOPUNIT) == 0)
+		uaa->dev_state = UAA_DEV_EJECTING;
+}
+
+static int
+run_driver_loaded(struct module *mod, int what, void *arg)
+{
+	switch (what) {
+	case MOD_LOAD:
+		run_etag = EVENTHANDLER_REGISTER(usb_dev_configured,
+		    run_autoinst, NULL, EVENTHANDLER_PRI_ANY);
+		break;
+	case MOD_UNLOAD:
+		EVENTHANDLER_DEREGISTER(usb_dev_configured, run_etag);
+		break;
+	default:
+		return (EOPNOTSUPP);
+	}
+	return (0);
+}
+
 static int
 run_match(device_t self)
 {
@@ -550,7 +699,7 @@ run_attach(device_t self)
 	struct ieee80211com *ic;
 	struct ifnet *ifp;
 	uint32_t ver;
-	int i, ntries, error;
+	int ntries, error;
 	uint8_t iface_index, bands;
 	char ethstr[ETHER_ADDRSTRLEN + 1];
 
@@ -559,6 +708,8 @@ run_attach(device_t self)
 	device_set_usb_desc(self);
 	sc->sc_udev = uaa->device;
 	sc->sc_dev = self;
+	if (USB_GET_DRIVER_INFO(uaa) != RUN_EJECT)
+		sc->sc_flags |= RUN_FLAG_FWLOAD_NEEDED;
 
 	lockinit(&sc->sc_lock, device_get_nameunit(sc->sc_dev),
 	    0, LK_CANRECURSE);
@@ -651,27 +802,12 @@ run_attach(device_t self)
 	bands = 0;
 	setbit(&bands, IEEE80211_MODE_11B);
 	setbit(&bands, IEEE80211_MODE_11G);
+	if (sc->rf_rev == RT2860_RF_2750 || sc->rf_rev == RT2860_RF_2850 ||
+	    sc->rf_rev == RT3070_RF_3052 || sc->rf_rev == RT3593_RF_3053 ||
+	    sc->rf_rev == RT5592_RF_5592)
+		setbit(&bands, IEEE80211_MODE_11A);
 	ieee80211_init_channels(ic, NULL, &bands);
 
-	/*
-	 * Do this by own because h/w supports
-	 * more channels than ieee80211_init_channels()
-	 */
-	if (sc->rf_rev == RT2860_RF_2750 ||
-	    sc->rf_rev == RT2860_RF_2850 ||
-	    sc->rf_rev == RT3070_RF_3052) {
-		/* set supported .11a rates */
-		for (i = 14; i < NELEM(rt2860_rf2850); i++) {
-			uint8_t chan = rt2860_rf2850[i].chan;
-			ic->ic_channels[ic->ic_nchans].ic_freq =
-			    ieee80211_ieee2mhz(chan, IEEE80211_CHAN_A);
-			ic->ic_channels[ic->ic_nchans].ic_ieee = chan;
-			ic->ic_channels[ic->ic_nchans].ic_flags = IEEE80211_CHAN_A;
-			ic->ic_channels[ic->ic_nchans].ic_extieee = 0;
-			ic->ic_nchans++;
-		}
-	}
-
 	ieee80211_ifattach(ic, sc->sc_bssid);
 
 	ic->ic_scan_start = run_scan_start;
@@ -801,7 +937,13 @@ run_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit,
 	rvp = (struct run_vap *) kmalloc(sizeof(struct run_vap),
 	    M_80211_VAP, M_INTWAIT | M_ZERO);
 	vap = &rvp->vap;
-	ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid, mac);
+
+	if (ieee80211_vap_setup(ic, vap, name, unit,
+	    opmode, flags, bssid, mac) != 0) {
+		/* out of memory */
+		kfree(rvp, M_80211_VAP);
+		return (NULL);
+	}
 
 	vap->iv_key_update_begin = run_key_update_begin;
 	vap->iv_key_update_end = run_key_update_end;
@@ -1009,17 +1151,18 @@ run_load_microcode(struct run_softc *sc)
 	/* cheap sanity check */
 	temp = fw->data;
 	bytes = *temp;
-	if (bytes != be64toh(0xffffff0210280210)) {
+	if (bytes != be64toh(0xffffff0210280210ULL)) {
 		device_printf(sc->sc_dev, "firmware checksum failed\n");
 		error = EINVAL;
 		goto fail;
 	}
 
-	run_read(sc, RT2860_ASIC_VER_ID, &tmp);
 	/* write microcode image */
-	run_write_region_1(sc, RT2870_FW_BASE, base, 4096);
-	run_write(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff);
-	run_write(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff);
+	if (sc->sc_flags & RUN_FLAG_FWLOAD_NEEDED) {
+		run_write_region_1(sc, RT2870_FW_BASE, base, 4096);
+		run_write(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff);
+		run_write(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff);
+	}
 
 	req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
 	req.bRequest = RT2870_RESET;
@@ -1034,15 +1177,16 @@ run_load_microcode(struct run_softc *sc)
 
 	run_delay(sc, 10);
 
+	run_write(sc, RT2860_H2M_BBPAGENT, 0);
 	run_write(sc, RT2860_H2M_MAILBOX, 0);
+	run_write(sc, RT2860_H2M_INTSRC, 0);
 	if ((error = run_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0)) != 0)
 		goto fail;
 
 	/* wait until microcontroller is ready */
 	for (ntries = 0; ntries < 1000; ntries++) {
-		if ((error = run_read(sc, RT2860_SYS_CTRL, &tmp)) != 0) {
+		if ((error = run_read(sc, RT2860_SYS_CTRL, &tmp)) != 0)
 			goto fail;
-		}
 		if (tmp & RT2860_MCU_READY)
 			break;
 		run_delay(sc, 10);
@@ -1062,7 +1206,7 @@ fail:
 	return (error);
 }
 
-int
+static int
 run_reset(struct run_softc *sc)
 {
 	usb_device_request_t req;
@@ -1166,13 +1310,32 @@ run_write_region_1(struct run_softc *sc, uint16_t reg, const uint8_t *buf,
 	return (error);
 #else
 	usb_device_request_t req;
+	int error = 0;
 
-	req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
-	req.bRequest = RT2870_WRITE_REGION_1;
-	USETW(req.wValue, 0);
-	USETW(req.wIndex, reg);
-	USETW(req.wLength, len);
-	return (run_do_request(sc, &req, buf));
+	/*
+	 * NOTE: It appears the WRITE_REGION_1 command cannot be
+	 * passed a huge amount of data, which will crash the
+	 * firmware. Limit amount of data passed to 64-bytes at a
+	 * time.
+	 */
+	while (len > 0) {
+		int delta = 64;
+		if (delta > len)
+			delta = len;
+
+		req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
+		req.bRequest = RT2870_WRITE_REGION_1;
+		USETW(req.wValue, 0);
+		USETW(req.wIndex, reg);
+		USETW(req.wLength, delta);
+		error = run_do_request(sc, &req, __DECONST(uint8_t *, buf));
+		if (error != 0)
+			break;
+		reg += delta;
+		buf += delta;
+		len -= delta;
+	}
+	return (error);
 #endif
 }
 
@@ -1187,9 +1350,8 @@ run_set_region_4(struct run_softc *sc, uint16_t reg, uint32_t val, int len)
 	return (error);
 }
 
-/* Read 16-bit from eFUSE ROM (RT3070 only.) */
 static int
-run_efuse_read_2(struct run_softc *sc, uint16_t addr, uint16_t *val)
+run_efuse_read(struct run_softc *sc, uint16_t addr, uint16_t *val, int count)
 {
 	uint32_t tmp;
 	uint16_t reg;
@@ -1198,7 +1360,8 @@ run_efuse_read_2(struct run_softc *sc, uint16_t addr, uint16_t *val)
 	if ((error = run_read(sc, RT3070_EFUSE_CTRL, &tmp)) != 0)
 		return (error);
 
-	addr *= 2;
+	if (count == 2)
+		addr *= 2;
 	/*-
 	 * Read one 16-byte block into registers EFUSE_DATA[0-3]:
 	 * DATA0: F E D C
@@ -1228,10 +1391,19 @@ run_efuse_read_2(struct run_softc *sc, uint16_t addr, uint16_t *val)
 	if ((error = run_read(sc, reg, &tmp)) != 0)
 		return (error);
 
-	*val = (addr & 2) ? tmp >> 16 : tmp & 0xffff;
+	tmp >>= (8 * (addr & 0x3));
+	*val = (addr & 1) ? tmp >> 16 : tmp & 0xffff;
+
 	return (0);
 }
 
+/* Read 16-bit from eFUSE ROM for RT3xxx. */
+static int
+run_efuse_read_2(struct run_softc *sc, uint16_t addr, uint16_t *val)
+{
+	return (run_efuse_read(sc, addr, val, 2));
+}
+
 static int
 run_eeprom_read_2(struct run_softc *sc, uint16_t addr, uint16_t *val)
 {
@@ -1244,7 +1416,7 @@ run_eeprom_read_2(struct run_softc *sc, uint16_t addr, uint16_t *val)
 	req.bRequest = RT2870_EEPROM_READ;
 	USETW(req.wValue, 0);
 	USETW(req.wIndex, addr);
-	USETW(req.wLength, sizeof tmp);
+	USETW(req.wLength, sizeof(tmp));
 
 	error = usbd_do_request(sc->sc_udev, &sc->sc_lock, &req, &tmp);
 	if (error == 0)
@@ -1262,7 +1434,7 @@ run_srom_read(struct run_softc *sc, uint16_t addr, uint16_t *val)
 }
 
 static int
-run_rt2870_rf_write(struct run_softc *sc, uint8_t reg, uint32_t val)
+run_rt2870_rf_write(struct run_softc *sc, uint32_t val)
 {
 	uint32_t tmp;
 	int error, ntries;
@@ -1276,10 +1448,7 @@ run_rt2870_rf_write(struct run_softc *sc, uint8_t reg, uint32_t val)
 	if (ntries == 10)
 		return (ETIMEDOUT);
 
-	/* RF registers are 24-bit on the RT2860 */
-	tmp = RT2860_RF_REG_CTRL | 24 << RT2860_RF_REG_WIDTH_SHIFT |
-	    (val & 0x3fffff) << 2 | (reg & 3);
-	return (run_write(sc, RT2860_RF_CSR_CFG0, tmp));
+	return (run_write(sc, RT2860_RF_CSR_CFG0, val));
 }
 
 static int
@@ -1430,7 +1599,7 @@ b4inc(uint32_t b32, int8_t delta)
 }
 
 static const char *
-run_get_rf(int rev)
+run_get_rf(uint16_t rev)
 {
 	switch (rev) {
 	case RT2860_RF_2820:	return "RT2820";
@@ -1442,11 +1611,134 @@ run_get_rf(int rev)
 	case RT3070_RF_3021:	return "RT3021";
 	case RT3070_RF_3022:	return "RT3022";
 	case RT3070_RF_3052:	return "RT3052";
+	case RT3593_RF_3053:	return "RT3053";
+	case RT5592_RF_5592:	return "RT5592";
+	case RT5390_RF_5370:	return "RT5370";
+	case RT5390_RF_5372:	return "RT5372";
 	}
 	return ("unknown");
 }
 
-int
+static void
+run_rt3593_get_txpower(struct run_softc *sc)
+{
+	uint16_t addr, val;
+	int i;
+
+	/* Read power settings for 2GHz channels. */
+	for (i = 0; i < 14; i += 2) {
+		addr = (sc->ntxchains == 3) ? RT3593_EEPROM_PWR2GHZ_BASE1 :
+		    RT2860_EEPROM_PWR2GHZ_BASE1;
+		run_srom_read(sc, addr + i / 2, &val);
+		sc->txpow1[i + 0] = (int8_t)(val & 0xff);
+		sc->txpow1[i + 1] = (int8_t)(val >> 8);
+
+		addr = (sc->ntxchains == 3) ? RT3593_EEPROM_PWR2GHZ_BASE2 :
+		    RT2860_EEPROM_PWR2GHZ_BASE2;
+		run_srom_read(sc, addr + i / 2, &val);
+		sc->txpow2[i + 0] = (int8_t)(val & 0xff);
+		sc->txpow2[i + 1] = (int8_t)(val >> 8);
+
+		if (sc->ntxchains == 3) {
+			run_srom_read(sc, RT3593_EEPROM_PWR2GHZ_BASE3 + i / 2,
+			    &val);
+			sc->txpow3[i + 0] = (int8_t)(val & 0xff);
+			sc->txpow3[i + 1] = (int8_t)(val >> 8);
+		}
+	}
+	/* Fix broken Tx power entries. */
+	for (i = 0; i < 14; i++) {
+		if (sc->txpow1[i] > 31)
+			sc->txpow1[i] = 5;
+		if (sc->txpow2[i] > 31)
+			sc->txpow2[i] = 5;
+		if (sc->ntxchains == 3) {
+			if (sc->txpow3[i] > 31)
+				sc->txpow3[i] = 5;
+		}
+	}
+	/* Read power settings for 5GHz channels. */
+	for (i = 0; i < 40; i += 2) {
+		run_srom_read(sc, RT3593_EEPROM_PWR5GHZ_BASE1 + i / 2, &val);
+		sc->txpow1[i + 14] = (int8_t)(val & 0xff);
+		sc->txpow1[i + 15] = (int8_t)(val >> 8);
+
+		run_srom_read(sc, RT3593_EEPROM_PWR5GHZ_BASE2 + i / 2, &val);
+		sc->txpow2[i + 14] = (int8_t)(val & 0xff);
+		sc->txpow2[i + 15] = (int8_t)(val >> 8);
+
+		if (sc->ntxchains == 3) {
+			run_srom_read(sc, RT3593_EEPROM_PWR5GHZ_BASE3 + i / 2,
+			    &val);
+			sc->txpow3[i + 14] = (int8_t)(val & 0xff);
+			sc->txpow3[i + 15] = (int8_t)(val >> 8);
+		}
+	}
+}
+
+static void
+run_get_txpower(struct run_softc *sc)
+{
+	uint16_t val;
+	int i;
+
+	/* Read power settings for 2GHz channels. */
+	for (i = 0; i < 14; i += 2) {
+		run_srom_read(sc, RT2860_EEPROM_PWR2GHZ_BASE1 + i / 2, &val);
+		sc->txpow1[i + 0] = (int8_t)(val & 0xff);
+		sc->txpow1[i + 1] = (int8_t)(val >> 8);
+
+		if (sc->mac_ver != 0x5390) {
+			run_srom_read(sc,
+			    RT2860_EEPROM_PWR2GHZ_BASE2 + i / 2, &val);
+			sc->txpow2[i + 0] = (int8_t)(val & 0xff);
+			sc->txpow2[i + 1] = (int8_t)(val >> 8);
+		}
+	}
+	/* Fix broken Tx power entries. */
+	for (i = 0; i < 14; i++) {
+		if (sc->mac_ver >= 0x5390) {
+			if (sc->txpow1[i] < 0 || sc->txpow1[i] > 27)
+				sc->txpow1[i] = 5;
+		} else {
+			if (sc->txpow1[i] < 0 || sc->txpow1[i] > 31)
+				sc->txpow1[i] = 5;
+		}
+		if (sc->mac_ver > 0x5390) {
+			if (sc->txpow2[i] < 0 || sc->txpow2[i] > 27)
+				sc->txpow2[i] = 5;
+		} else if (sc->mac_ver < 0x5390) {
+			if (sc->txpow2[i] < 0 || sc->txpow2[i] > 31)
+				sc->txpow2[i] = 5;
+		}
+		DPRINTF("chan %d: power1=%d, power2=%d\n",
+		    rt2860_rf2850[i].chan, sc->txpow1[i], sc->txpow2[i]);
+	}
+	/* Read power settings for 5GHz channels. */
+	for (i = 0; i < 40; i += 2) {
+		run_srom_read(sc, RT2860_EEPROM_PWR5GHZ_BASE1 + i / 2, &val);
+		sc->txpow1[i + 14] = (int8_t)(val & 0xff);
+		sc->txpow1[i + 15] = (int8_t)(val >> 8);
+
+		run_srom_read(sc, RT2860_EEPROM_PWR5GHZ_BASE2 + i / 2, &val);
+		sc->txpow2[i + 14] = (int8_t)(val & 0xff);
+		sc->txpow2[i + 15] = (int8_t)(val >> 8);
+	}
+	/* Fix broken Tx power entries. */
+	for (i = 0; i < 40; i++ ) {
+		if (sc->mac_ver != 0x5592) {
+			if (sc->txpow1[14 + i] < -7 || sc->txpow1[14 + i] > 15)
+				sc->txpow1[14 + i] = 5;
+			if (sc->txpow2[14 + i] < -7 || sc->txpow2[14 + i] > 15)
+				sc->txpow2[14 + i] = 5;
+		}
+		DPRINTF("chan %d: power1=%d, power2=%d\n",
+		    rt2860_rf2850[14 + i].chan, sc->txpow1[14 + i],
+		    sc->txpow2[14 + i]);
+	}
+}
+
+static int
 run_read_eeprom(struct run_softc *sc)
 {
 	int8_t delta_2ghz, delta_5ghz;
@@ -1459,7 +1751,7 @@ run_read_eeprom(struct run_softc *sc)
 	if (sc->mac_ver >= 0x3070) {
 		run_read(sc, RT3070_EFUSE_CTRL, &tmp);
 		DPRINTF("EFUSE_CTRL=0x%08x\n", tmp);
-		if (tmp & RT3070_SEL_EFUSE)
+		if ((tmp & RT3070_SEL_EFUSE) || sc->mac_ver == 0x3593)
 			sc->sc_srom_read = run_efuse_read_2;
 	}
 
@@ -1478,35 +1770,45 @@ run_read_eeprom(struct run_softc *sc)
 	sc->sc_bssid[4] = val & 0xff;
 	sc->sc_bssid[5] = val >> 8;
 
-	/* read vender BBP settings */
-	for (i = 0; i < 10; i++) {
-		run_srom_read(sc, RT2860_EEPROM_BBP_BASE + i, &val);
-		sc->bbp[i].val = val & 0xff;
-		sc->bbp[i].reg = val >> 8;
-		DPRINTF("BBP%d=0x%02x\n", sc->bbp[i].reg, sc->bbp[i].val);
-	}
-	if (sc->mac_ver >= 0x3071) {
-		/* read vendor RF settings */
+	if (sc->mac_ver < 0x3593) {
+		/* read vender BBP settings */
 		for (i = 0; i < 10; i++) {
-			run_srom_read(sc, RT3071_EEPROM_RF_BASE + i, &val);
-			sc->rf[i].val = val & 0xff;
-			sc->rf[i].reg = val >> 8;
-			DPRINTF("RF%d=0x%02x\n", sc->rf[i].reg,
-			    sc->rf[i].val);
+			run_srom_read(sc, RT2860_EEPROM_BBP_BASE + i, &val);
+			sc->bbp[i].val = val & 0xff;
+			sc->bbp[i].reg = val >> 8;
+			DPRINTF("BBP%d=0x%02x\n", sc->bbp[i].reg,
+			    sc->bbp[i].val);
+		}
+		if (sc->mac_ver >= 0x3071) {
+			/* read vendor RF settings */
+			for (i = 0; i < 10; i++) {
+				run_srom_read(sc, RT3071_EEPROM_RF_BASE + i,
+				   &val);
+				sc->rf[i].val = val & 0xff;
+				sc->rf[i].reg = val >> 8;
+				DPRINTF("RF%d=0x%02x\n", sc->rf[i].reg,
+				    sc->rf[i].val);
+			}
 		}
 	}
 
 	/* read RF frequency offset from EEPROM */
-	run_srom_read(sc, RT2860_EEPROM_FREQ_LEDS, &val);
+	run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_FREQ_LEDS :
+	    RT3593_EEPROM_FREQ, &val);
 	sc->freq = ((val & 0xff) != 0xff) ? val & 0xff : 0;
 	DPRINTF("EEPROM freq offset %d\n", sc->freq & 0xff);
 
+	run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_FREQ_LEDS :
+	    RT3593_EEPROM_FREQ_LEDS, &val);
 	if (val >> 8 != 0xff) {
 		/* read LEDs operating mode */
 		sc->leds = val >> 8;
-		run_srom_read(sc, RT2860_EEPROM_LED1, &sc->led[0]);
-		run_srom_read(sc, RT2860_EEPROM_LED2, &sc->led[1]);
-		run_srom_read(sc, RT2860_EEPROM_LED3, &sc->led[2]);
+		run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_LED1 :
+		    RT3593_EEPROM_LED1, &sc->led[0]);
+		run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_LED2 :
+		    RT3593_EEPROM_LED2, &sc->led[1]);
+		run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_LED3 :
+		    RT3593_EEPROM_LED3, &sc->led[2]);
 	} else {
 		/* broken EEPROM, use default settings */
 		sc->leds = 0x01;
@@ -1518,8 +1820,14 @@ run_read_eeprom(struct run_softc *sc)
 	    sc->leds, sc->led[0], sc->led[1], sc->led[2]);
 
 	/* read RF information */
-	run_srom_read(sc, RT2860_EEPROM_ANTENNA, &val);
+	if (sc->mac_ver == 0x5390 || sc->mac_ver ==0x5392)
+		run_srom_read(sc, 0x00, &val);
+	else
+		run_srom_read(sc, RT2860_EEPROM_ANTENNA, &val);
+
 	if (val == 0xffff) {
+		device_printf(sc->sc_dev,
+		    "invalid EEPROM antenna info, using default\n");
 		DPRINTF("invalid EEPROM antenna info, using default\n");
 		if (sc->mac_ver == 0x3572) {
 			/* default to RF3052 2T2R */
@@ -1538,11 +1846,15 @@ run_read_eeprom(struct run_softc *sc)
 			sc->nrxchains = 2;
 		}
 	} else {
-		sc->rf_rev = (val >> 8) & 0xf;
+		if (sc->mac_ver == 0x5390 || sc->mac_ver ==0x5392) {
+			sc->rf_rev = val;
+			run_srom_read(sc, RT2860_EEPROM_ANTENNA, &val);
+		} else
+			sc->rf_rev = (val >> 8) & 0xf;
 		sc->ntxchains = (val >> 4) & 0xf;
 		sc->nrxchains = val & 0xf;
 	}
-	DPRINTF("EEPROM RF rev=0x%02x chains=%dT%dR\n",
+	DPRINTF("EEPROM RF rev=0x%04x chains=%dT%dR\n",
 	    sc->rf_rev, sc->ntxchains, sc->nrxchains);
 
 	/* check if RF supports automatic Tx access gain control */
@@ -1560,45 +1872,11 @@ run_read_eeprom(struct run_softc *sc)
 		sc->rfswitch = val & 1;
 	}
 
-	/* read power settings for 2GHz channels */
-	for (i = 0; i < 14; i += 2) {
-		run_srom_read(sc, RT2860_EEPROM_PWR2GHZ_BASE1 + i / 2, &val);
-		sc->txpow1[i + 0] = (int8_t)(val & 0xff);
-		sc->txpow1[i + 1] = (int8_t)(val >> 8);
-
-		run_srom_read(sc, RT2860_EEPROM_PWR2GHZ_BASE2 + i / 2, &val);
-		sc->txpow2[i + 0] = (int8_t)(val & 0xff);
-		sc->txpow2[i + 1] = (int8_t)(val >> 8);
-	}
-	/* fix broken Tx power entries */
-	for (i = 0; i < 14; i++) {
-		if (sc->txpow1[i] < 0 || sc->txpow1[i] > 31)
-			sc->txpow1[i] = 5;
-		if (sc->txpow2[i] < 0 || sc->txpow2[i] > 31)
-			sc->txpow2[i] = 5;
-		DPRINTF("chan %d: power1=%d, power2=%d\n",
-		    rt2860_rf2850[i].chan, sc->txpow1[i], sc->txpow2[i]);
-	}
-	/* read power settings for 5GHz channels */
-	for (i = 0; i < 40; i += 2) {
-		run_srom_read(sc, RT2860_EEPROM_PWR5GHZ_BASE1 + i / 2, &val);
-		sc->txpow1[i + 14] = (int8_t)(val & 0xff);
-		sc->txpow1[i + 15] = (int8_t)(val >> 8);
-
-		run_srom_read(sc, RT2860_EEPROM_PWR5GHZ_BASE2 + i / 2, &val);
-		sc->txpow2[i + 14] = (int8_t)(val & 0xff);
-		sc->txpow2[i + 15] = (int8_t)(val >> 8);
-	}
-	/* fix broken Tx power entries */
-	for (i = 0; i < 40; i++) {
-		if (sc->txpow1[14 + i] < -7 || sc->txpow1[14 + i] > 15)
-			sc->txpow1[14 + i] = 5;
-		if (sc->txpow2[14 + i] < -7 || sc->txpow2[14 + i] > 15)
-			sc->txpow2[14 + i] = 5;
-		DPRINTF("chan %d: power1=%d, power2=%d\n",
-		    rt2860_rf2850[14 + i].chan, sc->txpow1[14 + i],
-		    sc->txpow2[14 + i]);
-	}
+	/* Read Tx power settings. */
+	if (sc->mac_ver == 0x3593)
+		run_rt3593_get_txpower(sc);
+	else
+		run_get_txpower(sc);
 
 	/* read Tx power compensation for each Tx rate */
 	run_srom_read(sc, RT2860_EEPROM_DELTAPWR, &val);
@@ -1634,27 +1912,38 @@ run_read_eeprom(struct run_softc *sc)
 		    sc->txpow40mhz_2ghz[ridx], sc->txpow40mhz_5ghz[ridx]);
 	}
 
-	/* read RSSI offsets and LNA gains from EEPROM */
-	run_srom_read(sc, RT2860_EEPROM_RSSI1_2GHZ, &val);
+	/* Read RSSI offsets and LNA gains from EEPROM. */
+	run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_RSSI1_2GHZ :
+	    RT3593_EEPROM_RSSI1_2GHZ, &val);
 	sc->rssi_2ghz[0] = val & 0xff;	/* Ant A */
 	sc->rssi_2ghz[1] = val >> 8;	/* Ant B */
-	run_srom_read(sc, RT2860_EEPROM_RSSI2_2GHZ, &val);
+	run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_RSSI2_2GHZ :
+	    RT3593_EEPROM_RSSI2_2GHZ, &val);
 	if (sc->mac_ver >= 0x3070) {
-		/*
-		 * On RT3070 chips (limited to 2 Rx chains), this ROM
-		 * field contains the Tx mixer gain for the 2GHz band.
-		 */
-		if ((val & 0xff) != 0xff)
-			sc->txmixgain_2ghz = val & 0x7;
+		if (sc->mac_ver == 0x3593) {
+			sc->txmixgain_2ghz = 0;
+			sc->rssi_2ghz[2] = val & 0xff;	/* Ant C */
+		} else {
+			/*
+			 * On RT3070 chips (limited to 2 Rx chains), this ROM
+			 * field contains the Tx mixer gain for the 2GHz band.
+			 */
+			if ((val & 0xff) != 0xff)
+				sc->txmixgain_2ghz = val & 0x7;
+		}
 		DPRINTF("tx mixer gain=%u (2GHz)\n", sc->txmixgain_2ghz);
 	} else
 		sc->rssi_2ghz[2] = val & 0xff;	/* Ant C */
+	if (sc->mac_ver == 0x3593)
+		run_srom_read(sc, RT3593_EEPROM_LNA_5GHZ, &val);
 	sc->lna[2] = val >> 8;		/* channel group 2 */
 
-	run_srom_read(sc, RT2860_EEPROM_RSSI1_5GHZ, &val);
+	run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_RSSI1_5GHZ :
+	    RT3593_EEPROM_RSSI1_5GHZ, &val);
 	sc->rssi_5ghz[0] = val & 0xff;	/* Ant A */
 	sc->rssi_5ghz[1] = val >> 8;	/* Ant B */
-	run_srom_read(sc, RT2860_EEPROM_RSSI2_5GHZ, &val);
+	run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_RSSI2_5GHZ :
+	    RT3593_EEPROM_RSSI2_5GHZ, &val);
 	if (sc->mac_ver == 0x3572) {
 		/*
 		 * On RT3572 chips (limited to 2 Rx chains), this ROM
@@ -1665,9 +1954,14 @@ run_read_eeprom(struct run_softc *sc)
 		DPRINTF("tx mixer gain=%u (5GHz)\n", sc->txmixgain_5ghz);
 	} else
 		sc->rssi_5ghz[2] = val & 0xff;	/* Ant C */
+	if (sc->mac_ver == 0x3593) {
+		sc->txmixgain_5ghz = 0;
+		run_srom_read(sc, RT3593_EEPROM_LNA_5GHZ, &val);
+	}
 	sc->lna[3] = val >> 8;		/* channel group 3 */
 
-	run_srom_read(sc, RT2860_EEPROM_LNA, &val);
+	run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_LNA :
+	    RT3593_EEPROM_LNA, &val);
 	sc->lna[0] = val & 0xff;	/* channel group 0 */
 	sc->lna[1] = val >> 8;		/* channel group 1 */
 
@@ -2217,9 +2511,7 @@ run_ratectl_cb(void *arg, int pending)
 	if (vap == NULL)
 		return;
 
-	if (sc->rvp_cnt <= 1 && vap->iv_opmode == IEEE80211_M_STA)
-		run_iter_func(sc, vap->iv_bss);
-	else {
+	if (sc->rvp_cnt > 1 || vap->iv_opmode != IEEE80211_M_STA) {
 		/*
 		 * run_reset_livelock() doesn't do anything with AMRR,
 		 * but Ralink wants us to call it every 1 sec. So, we
@@ -2232,11 +2524,14 @@ run_ratectl_cb(void *arg, int pending)
 		/* just in case, there are some stats to drain */
 		run_drain_fifo(sc);
 		RUN_UNLOCK(sc);
-		ieee80211_iterate_nodes(&ic->ic_sta, run_iter_func, sc);
 	}
 
+	ieee80211_iterate_nodes(&ic->ic_sta, run_iter_func, sc);
+
+	RUN_LOCK(sc);
 	if(sc->ratectl_run != RUN_RATECTL_OFF)
 		usb_callout_reset(&sc->ratectl_ch, hz, run_ratectl_to, sc);
+	RUN_UNLOCK(sc);
 }
 
 static void
@@ -2312,6 +2607,11 @@ run_iter_func(void *arg, struct ieee80211_node *ni)
 
 	RUN_LOCK(sc);
 
+	/* Check for special case */
+	if (sc->rvp_cnt <= 1 && vap->iv_opmode == IEEE80211_M_STA &&
+	    ni != vap->iv_bss)
+		goto fail;
+
 	if (sc->rvp_cnt <= 1 && (vap->iv_opmode == IEEE80211_M_IBSS ||
 	    vap->iv_opmode == IEEE80211_M_STA)) {
 		/* read statistic counters (clear on read) and update AMRR state */
@@ -2443,7 +2743,10 @@ run_newassoc(struct ieee80211_node *ni, int isnew)
 	rn->mgt_ridx = ridx;
 	DPRINTF("rate=%d, mgmt_ridx=%d\n", rate, rn->mgt_ridx);
 
-	usb_callout_reset(&sc->ratectl_ch, hz, run_ratectl_to, sc);
+	RUN_LOCK(sc);
+	if(sc->ratectl_run != RUN_RATECTL_OFF)
+		usb_callout_reset(&sc->ratectl_ch, hz, run_ratectl_to, sc);
+	RUN_UNLOCK(sc);
 }
 
 /*
@@ -2474,12 +2777,17 @@ run_rx_frame(struct run_softc *sc, struct mbuf *m, uint32_t dmalen)
 	struct rt2870_rxd *rxd;
 	struct rt2860_rxwi *rxwi;
 	uint32_t flags;
-	uint16_t len, phy;
+	uint16_t len, rxwisize;
 	uint8_t ant, rssi;
 	int8_t nf;
 
 	rxwi = mtod(m, struct rt2860_rxwi *);
 	len = le16toh(rxwi->len) & 0xfff;
+	rxwisize = sizeof(struct rt2860_rxwi);
+	if (sc->mac_ver == 0x5592)
+		rxwisize += sizeof(uint64_t);
+	else if (sc->mac_ver == 0x3593)
+		rxwisize += sizeof(uint32_t);
 	if (__predict_false(len > dmalen)) {
 		m_freem(m);
 		ifp->if_ierrors++;
@@ -2497,8 +2805,8 @@ run_rx_frame(struct run_softc *sc, struct mbuf *m, uint32_t dmalen)
 		return;
 	}
 
-	m->m_data += sizeof(struct rt2860_rxwi);
-	m->m_pkthdr.len = m->m_len -= sizeof(struct rt2860_rxwi);
+	m->m_data += rxwisize;
+	m->m_pkthdr.len = m->m_len -= rxwisize;
 
 	wh = mtod(m, struct ieee80211_frame *);
 
@@ -2518,7 +2826,8 @@ run_rx_frame(struct run_softc *sc, struct mbuf *m, uint32_t dmalen)
 	if (__predict_false(flags & RT2860_RX_MICERR)) {
 		/* report MIC failures to net80211 for TKIP */
 		if (ni != NULL)
-			ieee80211_notify_michael_failure(ni->ni_vap, wh, rxwi->keyidx);
+			ieee80211_notify_michael_failure(ni->ni_vap, wh,
+			    rxwi->keyidx);
 		m_freem(m);
 		ifp->if_ierrors++;
 		DPRINTF("MIC error. Someone is lying.\n");
@@ -2541,6 +2850,7 @@ run_rx_frame(struct run_softc *sc, struct mbuf *m, uint32_t dmalen)
 
 	if (__predict_false(ieee80211_radiotap_active(ic))) {
 		struct run_rx_radiotap_header *tap = &sc->sc_rxtap;
+		uint16_t phy;
 
 		tap->wr_flags = 0;
 		tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq);
@@ -2585,8 +2895,15 @@ run_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error)
 	struct mbuf *m = NULL;
 	struct mbuf *m0;
 	uint32_t dmalen;
+	uint16_t rxwisize;
 	int xferlen;
 
+	rxwisize = sizeof(struct rt2860_rxwi);
+	if (sc->mac_ver == 0x5592)
+		rxwisize += sizeof(uint64_t);
+	else if (sc->mac_ver == 0x3593)
+		rxwisize += sizeof(uint32_t);
+
 	usbd_xfer_status(xfer, &xferlen, NULL, NULL, NULL);
 
 	switch (USB_GET_STATE(xfer)) {
@@ -2594,8 +2911,8 @@ run_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error)
 
 		DPRINTFN(15, "rx done, actlen=%d\n", xferlen);
 
-		if (xferlen < (int)(sizeof(uint32_t) +
-		    sizeof(struct rt2860_rxwi) + sizeof(struct rt2870_rxd))) {
+		if (xferlen < (int)(sizeof(uint32_t) + rxwisize +
+		    sizeof(struct rt2870_rxd))) {
 			DPRINTF("xfer too short %d\n", xferlen);
 			goto tr_setup;
 		}
@@ -2677,6 +2994,7 @@ tr_setup:
 			m->m_data += 4;
 			m->m_pkthdr.len = m->m_len -= 4;
 			run_rx_frame(sc, m, dmalen);
+			m = NULL;	/* don't free source buffer */
 			break;
 		}
 
@@ -2698,6 +3016,9 @@ tr_setup:
 		m->m_pkthdr.len = m->m_len -= dmalen + 8;
 	}
 
+	/* make sure we free the source buffer, if any */
+	m_freem(m);
+
 	RUN_LOCK(sc);
 }
 
@@ -2725,7 +3046,7 @@ run_tx_free(struct run_endpoint_queue *pq,
 }
 
 static void
-run_bulk_tx_callbackN(struct usb_xfer *xfer, usb_error_t error, unsigned int index)
+run_bulk_tx_callbackN(struct usb_xfer *xfer, usb_error_t error, u_int index)
 {
 	struct run_softc *sc = usbd_xfer_softc(xfer);
 	struct ifnet *ifp = sc->sc_ifp;
@@ -2765,8 +3086,10 @@ tr_setup:
 		STAILQ_REMOVE_HEAD(&pq->tx_qh, next);
 
 		m = data->m;
+		size = (sc->mac_ver == 0x5592) ?
+		    sizeof(data->desc) + sizeof(uint32_t) : sizeof(data->desc);
 		if ((m->m_pkthdr.len +
-		    sizeof(data->desc) + 3 + 8) > RUN_MAX_TXSZ) {
+		    size + 3 + 8) > RUN_MAX_TXSZ) {
 			DPRINTF("data overflow, %u bytes\n",
 			    m->m_pkthdr.len);
 
@@ -2778,7 +3101,6 @@ tr_setup:
 		}
 
 		pc = usbd_xfer_get_frame(xfer, 0);
-		size = sizeof(data->desc);
 		usbd_copy_in(pc, 0, &data->desc, size);
 		usbd_m_copy_in(pc, size, m, 0, m->m_pkthdr.len);
 		size += m->m_pkthdr.len;
@@ -2793,9 +3115,8 @@ tr_setup:
 		vap = data->ni->ni_vap;
 		if (ieee80211_radiotap_active_vap(vap)) {
 			struct run_tx_radiotap_header *tap = &sc->sc_txtap;
-			struct rt2860_txwi *txwi =
+			struct rt2860_txwi *txwi = 
 			    (struct rt2860_txwi *)(&data->desc + sizeof(struct rt2870_txd));
-
 			tap->wt_flags = 0;
 			tap->wt_rate = rt2860_rates[data->ridx].rate;
 			tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq);
@@ -2903,7 +3224,7 @@ run_set_tx_desc(struct run_softc *sc, struct run_tx_data *data)
 	struct ieee80211_frame *wh;
 	struct rt2870_txd *txd;
 	struct rt2860_txwi *txwi;
-	uint16_t xferlen;
+	uint16_t xferlen, txwisize;
 	uint16_t mcs;
 	uint8_t ridx = data->ridx;
 	uint8_t pad;
@@ -2911,7 +3232,9 @@ run_set_tx_desc(struct run_softc *sc, struct run_tx_data *data)
 	/* get MCS code from rate index */
 	mcs = rt2860_rates[ridx].mcs;
 
-	xferlen = sizeof(*txwi) + m->m_pkthdr.len;
+	txwisize = (sc->mac_ver == 0x5592) ?
+	    sizeof(*txwi) + sizeof(uint32_t) : sizeof(*txwi);
+	xferlen = txwisize + m->m_pkthdr.len;
 
 	/* roundup to 32-bit alignment */
 	xferlen = (xferlen + 3) & ~3;
@@ -3039,7 +3362,7 @@ run_tx(struct run_softc *sc, struct mbuf *m, struct ieee80211_node *ni)
 			dur = rt2860_rates[ctl_ridx].sp_ack_dur;
 		else
 			dur = rt2860_rates[ctl_ridx].lp_ack_dur;
-		*(uint16_t *)wh->i_dur = htole16(dur);
+		USETW(wh->i_dur, dur);
 	}
 
 	/* reserve slots for mgmt packets, just in case */
@@ -3056,12 +3379,12 @@ run_tx(struct run_softc *sc, struct mbuf *m, struct ieee80211_node *ni)
 	txd->flags = qflags;
 	txwi = (struct rt2860_txwi *)(txd + 1);
 	txwi->xflags = xflags;
-	if (IEEE80211_IS_MULTICAST(wh->i_addr1)) {
+	if (IEEE80211_IS_MULTICAST(wh->i_addr1))
 		txwi->wcid = 0;
-	} else {
+	else
 		txwi->wcid = (vap->iv_opmode == IEEE80211_M_STA) ?
 		    1 : RUN_AID2WCID(ni->ni_associd);
-	}
+
 	/* clear leftover garbage bits */
 	txwi->flags = 0;
 	txwi->txop = 0;
@@ -3121,9 +3444,9 @@ run_tx(struct run_softc *sc, struct mbuf *m, struct ieee80211_node *ni)
 	usbd_transfer_start(sc->sc_xfer[qid]);
 	RUN_UNLOCK(sc);
 
-	DPRINTFN(8, "sending data frame len=%d rate=%d qid=%d\n", m->m_pkthdr.len +
-	    (int)(sizeof (struct rt2870_txd) + sizeof (struct rt2860_rxwi)),
-	    rt2860_rates[ridx].rate, qid);
+	DPRINTFN(8, "sending data frame len=%d rate=%d qid=%d\n",
+	    m->m_pkthdr.len + (int)(sizeof(struct rt2870_txd) +
+	    sizeof(struct rt2860_txwi)), rt2860_rates[ridx].rate, qid);
 
 	return (0);
 }
@@ -3160,7 +3483,7 @@ run_tx_mgt(struct run_softc *sc, struct mbuf *m, struct ieee80211_node *ni)
 
 		dur = ieee80211_ack_duration(ic->ic_rt, rt2860_rates[ridx].rate, 
 		    ic->ic_flags & IEEE80211_F_SHPREAMBLE);
-		*(uint16_t *)wh->i_dur = htole16(dur);
+		USETW(wh->i_dur, dur);
 	}
 
 	if (sc->sc_epq[0].tx_nfree == 0) {
@@ -3187,7 +3510,7 @@ run_tx_mgt(struct run_softc *sc, struct mbuf *m, struct ieee80211_node *ni)
 	run_set_tx_desc(sc, data);
 
 	DPRINTFN(10, "sending mgt frame len=%d rate=%d\n", m->m_pkthdr.len +
-	    (int)(sizeof (struct rt2870_txd) + sizeof (struct rt2860_rxwi)),
+	    (int)(sizeof(struct rt2870_txd) + sizeof(struct rt2860_txwi)),
 	    rt2860_rates[ridx].rate);
 
 	STAILQ_INSERT_TAIL(&sc->sc_epq[0].tx_qh, data, next);
@@ -3494,6 +3817,107 @@ run_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
 }
 
 static void
+run_iq_calib(struct run_softc *sc, u_int chan)
+{
+	uint16_t val;
+
+	/* Tx0 IQ gain. */
+	run_bbp_write(sc, 158, 0x2c);
+	if (chan <= 14)
+		run_efuse_read(sc, RT5390_EEPROM_IQ_GAIN_CAL_TX0_2GHZ, &val, 1);
+	else if (chan <= 64) {
+		run_efuse_read(sc,
+		    RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5GHZ,
+		    &val, 1);
+	} else if (chan <= 138) {
+		run_efuse_read(sc,
+		    RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5GHZ,
+		    &val, 1);
+	} else if (chan <= 165) {
+		run_efuse_read(sc,
+	    RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5GHZ,
+		    &val, 1);
+	} else
+		val = 0;
+	run_bbp_write(sc, 159, val);
+
+	/* Tx0 IQ phase. */
+	run_bbp_write(sc, 158, 0x2d);
+	if (chan <= 14) {
+		run_efuse_read(sc, RT5390_EEPROM_IQ_PHASE_CAL_TX0_2GHZ,
+		    &val, 1);
+	} else if (chan <= 64) {
+		run_efuse_read(sc,
+		    RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5GHZ,
+		    &val, 1);
+	} else if (chan <= 138) {
+		run_efuse_read(sc,
+		    RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5GHZ,
+		    &val, 1);
+	} else if (chan <= 165) {
+		run_efuse_read(sc,
+		    RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5GHZ,
+		    &val, 1);
+	} else
+		val = 0;
+	run_bbp_write(sc, 159, val);
+
+	/* Tx1 IQ gain. */
+	run_bbp_write(sc, 158, 0x4a);
+	if (chan <= 14) {
+		run_efuse_read(sc, RT5390_EEPROM_IQ_GAIN_CAL_TX1_2GHZ,
+		    &val, 1);
+	} else if (chan <= 64) {
+		run_efuse_read(sc,
+		    RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5GHZ,
+		    &val, 1);
+	} else if (chan <= 138) {
+		run_efuse_read(sc,
+		    RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5GHZ,
+		    &val, 1);
+	} else if (chan <= 165) {
+		run_efuse_read(sc,
+		    RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5GHZ,
+		    &val, 1);
+	} else
+		val = 0;
+	run_bbp_write(sc, 159, val);
+
+	/* Tx1 IQ phase. */
+	run_bbp_write(sc, 158, 0x4b);
+	if (chan <= 14) {
+		run_efuse_read(sc, RT5390_EEPROM_IQ_PHASE_CAL_TX1_2GHZ,
+		    &val, 1);
+	} else if (chan <= 64) {
+		run_efuse_read(sc,
+		    RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5GHZ,
+		    &val, 1);
+	} else if (chan <= 138) {
+		run_efuse_read(sc,
+		    RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5GHZ,
+		    &val, 1);
+	} else if (chan <= 165) {
+		run_efuse_read(sc,
+		    RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5GHZ,
+		    &val, 1);
+	} else
+		val = 0;
+	run_bbp_write(sc, 159, val);
+
+	/* RF IQ compensation control. */
+	run_bbp_write(sc, 158, 0x04);
+	run_efuse_read(sc, RT5390_EEPROM_RF_IQ_COMPENSATION_CTL,
+	    &val, 1);
+	run_bbp_write(sc, 159, val);
+
+	/* RF IQ imbalance compensation control. */
+	run_bbp_write(sc, 158, 0x03);
+	run_efuse_read(sc,
+	    RT5390_EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CTL, &val, 1);
+	run_bbp_write(sc, 159, val);
+}
+
+static void
 run_set_agc(struct run_softc *sc, uint8_t agc)
 {
 	uint8_t bbp;
@@ -3518,21 +3942,73 @@ run_select_chan_group(struct run_softc *sc, int group)
 	run_bbp_write(sc, 62, 0x37 - sc->lna[group]);
 	run_bbp_write(sc, 63, 0x37 - sc->lna[group]);
 	run_bbp_write(sc, 64, 0x37 - sc->lna[group]);
-	run_bbp_write(sc, 86, 0x00);
+	if (sc->mac_ver < 0x3572)
+		run_bbp_write(sc, 86, 0x00);
+
+	if (sc->mac_ver == 0x3593) {
+		run_bbp_write(sc, 77, 0x98);
+		run_bbp_write(sc, 83, (group == 0) ? 0x8a : 0x9a);
+	}
 
 	if (group == 0) {
 		if (sc->ext_2ghz_lna) {
-			run_bbp_write(sc, 82, 0x62);
-			run_bbp_write(sc, 75, 0x46);
+			if (sc->mac_ver >= 0x5390)
+				run_bbp_write(sc, 75, 0x52);
+			else {
+				run_bbp_write(sc, 82, 0x62);
+				run_bbp_write(sc, 75, 0x46);
+			}
 		} else {
-			run_bbp_write(sc, 82, 0x84);
-			run_bbp_write(sc, 75, 0x50);
+			if (sc->mac_ver == 0x5592) {
+				run_bbp_write(sc, 79, 0x1c);
+				run_bbp_write(sc, 80, 0x0e);
+				run_bbp_write(sc, 81, 0x3a);
+				run_bbp_write(sc, 82, 0x62);
+
+				run_bbp_write(sc, 195, 0x80);
+				run_bbp_write(sc, 196, 0xe0);
+				run_bbp_write(sc, 195, 0x81);
+				run_bbp_write(sc, 196, 0x1f);
+				run_bbp_write(sc, 195, 0x82);
+				run_bbp_write(sc, 196, 0x38);
+				run_bbp_write(sc, 195, 0x83);
+				run_bbp_write(sc, 196, 0x32);
+				run_bbp_write(sc, 195, 0x85);
+				run_bbp_write(sc, 196, 0x28);
+				run_bbp_write(sc, 195, 0x86);
+				run_bbp_write(sc, 196, 0x19);
+			} else if (sc->mac_ver >= 0x5390)
+				run_bbp_write(sc, 75, 0x50);
+			else {
+				run_bbp_write(sc, 82,
+				    (sc->mac_ver == 0x3593) ? 0x62 : 0x84);
+				run_bbp_write(sc, 75, 0x50);
+			}
 		}
 	} else {
-		if (sc->mac_ver == 0x3572)
+		if (sc->mac_ver == 0x5592) {
+			run_bbp_write(sc, 79, 0x18);
+			run_bbp_write(sc, 80, 0x08);
+			run_bbp_write(sc, 81, 0x38);
+			run_bbp_write(sc, 82, 0x92);
+
+			run_bbp_write(sc, 195, 0x80);
+			run_bbp_write(sc, 196, 0xf0);
+			run_bbp_write(sc, 195, 0x81);
+			run_bbp_write(sc, 196, 0x1e);
+			run_bbp_write(sc, 195, 0x82);
+			run_bbp_write(sc, 196, 0x28);
+			run_bbp_write(sc, 195, 0x83);
+			run_bbp_write(sc, 196, 0x20);
+			run_bbp_write(sc, 195, 0x85);
+			run_bbp_write(sc, 196, 0x7f);
+			run_bbp_write(sc, 195, 0x86);
+			run_bbp_write(sc, 196, 0x7f);
+		} else if (sc->mac_ver == 0x3572)
 			run_bbp_write(sc, 82, 0x94);
 		else
-			run_bbp_write(sc, 82, 0xf2);
+			run_bbp_write(sc, 82,
+			    (sc->mac_ver == 0x3593) ? 0x82 : 0xf2);
 		if (sc->ext_5ghz_lna)
 			run_bbp_write(sc, 75, 0x46);
 		else 
@@ -3546,12 +4022,18 @@ run_select_chan_group(struct run_softc *sc, int group)
 
 	/* enable appropriate Power Amplifiers and Low Noise Amplifiers */
 	tmp = RT2860_RFTR_EN | RT2860_TRSW_EN | RT2860_LNA_PE0_EN;
+	if (sc->mac_ver == 0x3593)
+		tmp |= 1 << 29 | 1 << 28;
 	if (sc->nrxchains > 1)
 		tmp |= RT2860_LNA_PE1_EN;
 	if (group == 0) {	/* 2GHz */
 		tmp |= RT2860_PA_PE_G0_EN;
 		if (sc->ntxchains > 1)
 			tmp |= RT2860_PA_PE_G1_EN;
+		if (sc->mac_ver == 0x3593) {
+			if (sc->ntxchains > 2)
+				tmp |= 1 << 25;
+		}
 	} else {		/* 5GHz */
 		tmp |= RT2860_PA_PE_A0_EN;
 		if (sc->ntxchains > 1)
@@ -3564,6 +4046,20 @@ run_select_chan_group(struct run_softc *sc, int group)
 	} else
 		run_write(sc, RT2860_TX_PIN_CFG, tmp);
 
+	if (sc->mac_ver == 0x5592) {
+		run_bbp_write(sc, 195, 0x8d);
+		run_bbp_write(sc, 196, 0x1a);
+	}
+
+	if (sc->mac_ver == 0x3593) {
+		run_read(sc, RT2860_GPIO_CTRL, &tmp);
+		tmp &= ~0x01010000;
+		if (group == 0)
+			tmp |= 0x00010000;
+		tmp = (tmp & ~0x00009090) | 0x00000090;
+		run_write(sc, RT2860_GPIO_CTRL, tmp);
+	}
+
 	/* set initial AGC value */
 	if (group == 0) {	/* 2GHz band */
 		if (sc->mac_ver >= 0x3070)
@@ -3571,7 +4067,9 @@ run_select_chan_group(struct run_softc *sc, int group)
 		else
 			agc = 0x2e + sc->lna[0];
 	} else {		/* 5GHz band */
-		if (sc->mac_ver == 0x3572)
+		if (sc->mac_ver == 0x5592)
+			agc = 0x24 + sc->lna[group] * 2;
+		else if (sc->mac_ver == 0x3572 || sc->mac_ver == 0x3593)
 			agc = 0x22 + (sc->lna[group] * 5) / 3;
 		else
 			agc = 0x32 + (sc->lna[group] * 5) / 3;
@@ -3580,7 +4078,7 @@ run_select_chan_group(struct run_softc *sc, int group)
 }
 
 static void
-run_rt2870_set_chan(struct run_softc *sc, uint32_t chan)
+run_rt2870_set_chan(struct run_softc *sc, u_int chan)
 {
 	const struct rfprog *rfprog = rt2860_rf2850;
 	uint32_t r2, r3, r4;
@@ -3592,58 +4090,71 @@ run_rt2870_set_chan(struct run_softc *sc, uint32_t chan)
 
 	r2 = rfprog[i].r2;
 	if (sc->ntxchains == 1)
-		r2 |= 1 << 12;		/* 1T: disable Tx chain 2 */
+		r2 |= 1 << 14;		/* 1T: disable Tx chain 2 */
 	if (sc->nrxchains == 1)
-		r2 |= 1 << 15 | 1 << 4;	/* 1R: disable Rx chains 2 & 3 */
+		r2 |= 1 << 17 | 1 << 6;	/* 1R: disable Rx chains 2 & 3 */
 	else if (sc->nrxchains == 2)
-		r2 |= 1 << 4;		/* 2R: disable Rx chain 3 */
+		r2 |= 1 << 6;		/* 2R: disable Rx chain 3 */
 
 	/* use Tx power values from EEPROM */
 	txpow1 = sc->txpow1[i];
 	txpow2 = sc->txpow2[i];
+
+	/* Initialize RF R3 and R4. */
+	r3 = rfprog[i].r3 & 0xffffc1ff;
+	r4 = (rfprog[i].r4 & ~(0x001f87c0)) | (sc->freq << 15);
 	if (chan > 14) {
-		if (txpow1 >= 0)
-			txpow1 = txpow1 << 1 | 1;
-		else
-			txpow1 = (7 + txpow1) << 1;
-		if (txpow2 >= 0)
-			txpow2 = txpow2 << 1 | 1;
-		else
-			txpow2 = (7 + txpow2) << 1;
+		if (txpow1 >= 0) {
+			txpow1 = (txpow1 > 0xf) ? (0xf) : (txpow1);
+			r3 |= (txpow1 << 10) | (1 << 9);
+		} else {
+			txpow1 += 7;
+
+			/* txpow1 is not possible larger than 15. */
+			r3 |= (txpow1 << 10);
+		}
+		if (txpow2 >= 0) {
+			txpow2 = (txpow2 > 0xf) ? (0xf) : (txpow2);
+			r4 |= (txpow2 << 7) | (1 << 6);
+		} else {
+			txpow2 += 7;
+			r4 |= (txpow2 << 7);
+		}
+	} else {
+		/* Set Tx0 power. */
+		r3 |= (txpow1 << 9);
+
+		/* Set frequency offset and Tx1 power. */
+		r4 |= (txpow2 << 6);
 	}
-	r3 = rfprog[i].r3 | txpow1 << 7;
-	r4 = rfprog[i].r4 | sc->freq << 13 | txpow2 << 4;
 
-	run_rt2870_rf_write(sc, RT2860_RF1, rfprog[i].r1);
-	run_rt2870_rf_write(sc, RT2860_RF2, r2);
-	run_rt2870_rf_write(sc, RT2860_RF3, r3);
-	run_rt2870_rf_write(sc, RT2860_RF4, r4);
+	run_rt2870_rf_write(sc, rfprog[i].r1);
+	run_rt2870_rf_write(sc, r2);
+	run_rt2870_rf_write(sc, r3 & ~(1 << 2));
+	run_rt2870_rf_write(sc, r4);
 
 	run_delay(sc, 10);
 
-	run_rt2870_rf_write(sc, RT2860_RF1, rfprog[i].r1);
-	run_rt2870_rf_write(sc, RT2860_RF2, r2);
-	run_rt2870_rf_write(sc, RT2860_RF3, r3 | 1);
-	run_rt2870_rf_write(sc, RT2860_RF4, r4);
+	run_rt2870_rf_write(sc, rfprog[i].r1);
+	run_rt2870_rf_write(sc, r2);
+	run_rt2870_rf_write(sc, r3 | (1 << 2));
+	run_rt2870_rf_write(sc, r4);
 
 	run_delay(sc, 10);
 
-	run_rt2870_rf_write(sc, RT2860_RF1, rfprog[i].r1);
-	run_rt2870_rf_write(sc, RT2860_RF2, r2);
-	run_rt2870_rf_write(sc, RT2860_RF3, r3);
-	run_rt2870_rf_write(sc, RT2860_RF4, r4);
+	run_rt2870_rf_write(sc, rfprog[i].r1);
+	run_rt2870_rf_write(sc, r2);
+	run_rt2870_rf_write(sc, r3 & ~(1 << 2));
+	run_rt2870_rf_write(sc, r4);
 }
 
 static void
-run_rt3070_set_chan(struct run_softc *sc, uint32_t chan)
+run_rt3070_set_chan(struct run_softc *sc, u_int chan)
 {
 	int8_t txpow1, txpow2;
 	uint8_t rf;
 	int i;
 
-	/* RT3070 is 2GHz only */
-	KASSERT(chan >= 1 && chan <= 14, ("wrong channel selected\n"));
-
 	/* find the settings for this channel (we know it exists) */
 	for (i = 0; rt2860_rf2850[i].chan != chan; i++);
 
@@ -3652,7 +4163,12 @@ run_rt3070_set_chan(struct run_softc *sc, uint32_t chan)
 	txpow2 = sc->txpow2[i];
 
 	run_rt3070_rf_write(sc, 2, rt3070_freqs[i].n);
-	run_rt3070_rf_write(sc, 3, rt3070_freqs[i].k);
+
+	/* RT3370/RT3390: RF R3 [7:4] is not reserved bits. */
+	run_rt3070_rf_read(sc, 3, &rf);
+	rf = (rf & ~0x0f) | rt3070_freqs[i].k;
+	run_rt3070_rf_write(sc, 3, rf);
+
 	run_rt3070_rf_read(sc, 6, &rf);
 	rf = (rf & ~0x03) | rt3070_freqs[i].r;
 	run_rt3070_rf_write(sc, 6, rf);
@@ -3848,32 +4364,456 @@ run_rt3572_set_chan(struct run_softc *sc, u_int chan)
 }
 
 static void
-run_set_rx_antenna(struct run_softc *sc, int aux)
+run_rt3593_set_chan(struct run_softc *sc, u_int chan)
 {
-	uint32_t tmp;
+	int8_t txpow1, txpow2, txpow3;
+	uint8_t h20mhz, rf;
+	int i;
 
-	if (aux) {
-		run_mcu_cmd(sc, RT2860_MCU_CMD_ANTSEL, 0);
-		run_read(sc, RT2860_GPIO_CTRL, &tmp);
-		run_write(sc, RT2860_GPIO_CTRL, (tmp & ~0x0808) | 0x08);
+	/* find the settings for this channel (we know it exists) */
+	for (i = 0; rt2860_rf2850[i].chan != chan; i++);
+
+	/* use Tx power values from EEPROM */
+	txpow1 = sc->txpow1[i];
+	txpow2 = sc->txpow2[i];
+	txpow3 = (sc->ntxchains == 3) ? sc->txpow3[i] : 0;
+
+	if (chan <= 14) {
+		run_bbp_write(sc, 25, sc->bbp25);
+		run_bbp_write(sc, 26, sc->bbp26);
 	} else {
-		run_mcu_cmd(sc, RT2860_MCU_CMD_ANTSEL, 1);
-		run_read(sc, RT2860_GPIO_CTRL, &tmp);
-		run_write(sc, RT2860_GPIO_CTRL, tmp & ~0x0808);
+		/* Enable IQ phase correction. */
+		run_bbp_write(sc, 25, 0x09);
+		run_bbp_write(sc, 26, 0xff);
 	}
-}
 
-static int
-run_set_chan(struct run_softc *sc, struct ieee80211_channel *c)
-{
+	run_rt3070_rf_write(sc, 8, rt3070_freqs[i].n);
+	run_rt3070_rf_write(sc, 9, rt3070_freqs[i].k & 0x0f);
+	run_rt3070_rf_read(sc, 11, &rf);
+	rf = (rf & ~0x03) | (rt3070_freqs[i].r & 0x03);
+	run_rt3070_rf_write(sc, 11, rf);
+
+	/* Set pll_idoh. */
+	run_rt3070_rf_read(sc, 11, &rf);
+	rf &= ~0x4c;
+	rf |= (chan <= 14) ? 0x44 : 0x48;
+	run_rt3070_rf_write(sc, 11, rf);
+
+	if (chan <= 14)
+		rf = txpow1 & 0x1f;
+	else
+		rf = 0x40 | ((txpow1 & 0x18) << 1) | (txpow1 & 0x07);
+	run_rt3070_rf_write(sc, 53, rf);
+
+	if (chan <= 14)
+		rf = txpow2 & 0x1f;
+	else
+		rf = 0x40 | ((txpow2 & 0x18) << 1) | (txpow2 & 0x07);
+	run_rt3070_rf_write(sc, 55, rf);
+
+	if (chan <= 14)
+		rf = txpow3 & 0x1f;
+	else
+		rf = 0x40 | ((txpow3 & 0x18) << 1) | (txpow3 & 0x07);
+	run_rt3070_rf_write(sc, 54, rf);
+
+	rf = RT3070_RF_BLOCK | RT3070_PLL_PD;
+	if (sc->ntxchains == 3)
+		rf |= RT3070_TX0_PD | RT3070_TX1_PD | RT3070_TX2_PD;
+	else
+		rf |= RT3070_TX0_PD | RT3070_TX1_PD;
+	rf |= RT3070_RX0_PD | RT3070_RX1_PD | RT3070_RX2_PD;
+	run_rt3070_rf_write(sc, 1, rf);
+
+	run_adjust_freq_offset(sc);
+
+	run_rt3070_rf_write(sc, 31, (chan <= 14) ? 0xa0 : 0x80);
+
+	h20mhz = (sc->rf24_20mhz & 0x20) >> 5; 
+	run_rt3070_rf_read(sc, 30, &rf);
+	rf = (rf & ~0x06) | (h20mhz << 1) | (h20mhz << 2);
+	run_rt3070_rf_write(sc, 30, rf);
+
+	run_rt3070_rf_read(sc, 36, &rf);
+	if (chan <= 14)
+		rf |= 0x80;
+	else
+		rf &= ~0x80;
+	run_rt3070_rf_write(sc, 36, rf);
+
+	/* Set vcolo_bs. */
+	run_rt3070_rf_write(sc, 34, (chan <= 14) ? 0x3c : 0x20);
+	/* Set pfd_delay. */
+	run_rt3070_rf_write(sc, 12, (chan <= 14) ? 0x1a : 0x12);
+
+	/* Set vco bias current control. */
+	run_rt3070_rf_read(sc, 6, &rf);
+	rf &= ~0xc0;
+	if (chan <= 14)
+		rf |= 0x40;
+	else if (chan <= 128)
+		rf |= 0x80;
+	else
+		rf |= 0x40;
+	run_rt3070_rf_write(sc, 6, rf);
+		
+	run_rt3070_rf_read(sc, 30, &rf);
+	rf = (rf & ~0x18) | 0x10;
+	run_rt3070_rf_write(sc, 30, rf);
+
+	run_rt3070_rf_write(sc, 10, (chan <= 14) ? 0xd3 : 0xd8);
+	run_rt3070_rf_write(sc, 13, (chan <= 14) ? 0x12 : 0x23);
+
+	run_rt3070_rf_read(sc, 51, &rf);
+	rf = (rf & ~0x03) | 0x01;
+	run_rt3070_rf_write(sc, 51, rf);
+	/* Set tx_mx1_cc. */
+	run_rt3070_rf_read(sc, 51, &rf);
+	rf &= ~0x1c;
+	rf |= (chan <= 14) ? 0x14 : 0x10;
+	run_rt3070_rf_write(sc, 51, rf);
+	/* Set tx_mx1_ic. */
+	run_rt3070_rf_read(sc, 51, &rf);
+	rf &= ~0xe0;
+	rf |= (chan <= 14) ? 0x60 : 0x40;
+	run_rt3070_rf_write(sc, 51, rf);
+	/* Set tx_lo1_ic. */
+	run_rt3070_rf_read(sc, 49, &rf);
+	rf &= ~0x1c;
+	rf |= (chan <= 14) ? 0x0c : 0x08;
+	run_rt3070_rf_write(sc, 49, rf);
+	/* Set tx_lo1_en. */
+	run_rt3070_rf_read(sc, 50, &rf);
+	run_rt3070_rf_write(sc, 50, rf & ~0x20);
+	/* Set drv_cc. */
+	run_rt3070_rf_read(sc, 57, &rf);
+	rf &= ~0xfc;
+	rf |= (chan <= 14) ?  0x6c : 0x3c;
+	run_rt3070_rf_write(sc, 57, rf);
+	/* Set rx_mix1_ic, rxa_lnactr, lna_vc, lna_inbias_en and lna_en. */
+	run_rt3070_rf_write(sc, 44, (chan <= 14) ? 0x93 : 0x9b);
+	/* Set drv_gnd_a, tx_vga_cc_a and tx_mx2_gain. */
+	run_rt3070_rf_write(sc, 52, (chan <= 14) ? 0x45 : 0x05);
+	/* Enable VCO calibration. */
+	run_rt3070_rf_read(sc, 3, &rf);
+	rf &= ~RT5390_VCOCAL;
+	rf |= (chan <= 14) ? RT5390_VCOCAL : 0xbe;
+	run_rt3070_rf_write(sc, 3, rf);
+
+	if (chan <= 14)
+		rf = 0x23;
+	else if (chan <= 64)
+		rf = 0x36;
+	else if (chan <= 128)
+		rf = 0x32;
+	else
+		rf = 0x30;
+	run_rt3070_rf_write(sc, 39, rf);
+	if (chan <= 14)
+		rf = 0xbb;
+	else if (chan <= 64)
+		rf = 0xeb;
+	else if (chan <= 128)
+		rf = 0xb3;
+	else
+		rf = 0x9b;
+	run_rt3070_rf_write(sc, 45, rf);
+
+	/* Set FEQ/AEQ control. */
+	run_bbp_write(sc, 105, 0x34);
+}
+
+static void
+run_rt5390_set_chan(struct run_softc *sc, u_int chan)
+{
+	int8_t txpow1, txpow2;
+	uint8_t rf;
+	int i;
+
+	/* find the settings for this channel (we know it exists) */
+	for (i = 0; rt2860_rf2850[i].chan != chan; i++);
+
+	/* use Tx power values from EEPROM */
+	txpow1 = sc->txpow1[i];
+	txpow2 = sc->txpow2[i];
+
+	run_rt3070_rf_write(sc, 8, rt3070_freqs[i].n);
+	run_rt3070_rf_write(sc, 9, rt3070_freqs[i].k & 0x0f);
+	run_rt3070_rf_read(sc, 11, &rf);
+	rf = (rf & ~0x03) | (rt3070_freqs[i].r & 0x03);
+	run_rt3070_rf_write(sc, 11, rf);
+
+	run_rt3070_rf_read(sc, 49, &rf);
+	rf = (rf & ~0x3f) | (txpow1 & 0x3f);
+	/* The valid range of the RF R49 is 0x00 to 0x27. */
+	if ((rf & 0x3f) > 0x27)
+		rf = (rf & ~0x3f) | 0x27;
+	run_rt3070_rf_write(sc, 49, rf);
+
+	if (sc->mac_ver == 0x5392) {
+		run_rt3070_rf_read(sc, 50, &rf);
+		rf = (rf & ~0x3f) | (txpow2 & 0x3f);
+		/* The valid range of the RF R50 is 0x00 to 0x27. */
+		if ((rf & 0x3f) > 0x27)
+			rf = (rf & ~0x3f) | 0x27;
+		run_rt3070_rf_write(sc, 50, rf);
+	}
+
+	run_rt3070_rf_read(sc, 1, &rf);
+	rf |= RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | RT3070_TX0_PD;
+	if (sc->mac_ver == 0x5392)
+		rf |= RT3070_RX1_PD | RT3070_TX1_PD;
+	run_rt3070_rf_write(sc, 1, rf);
+
+	if (sc->mac_ver != 0x5392) {
+		run_rt3070_rf_read(sc, 2, &rf);
+		rf |= 0x80;
+		run_rt3070_rf_write(sc, 2, rf);
+		run_delay(sc, 10);
+		rf &= 0x7f;
+		run_rt3070_rf_write(sc, 2, rf);
+	}
+
+	run_adjust_freq_offset(sc);
+
+	if (sc->mac_ver == 0x5392) {
+		/* Fix for RT5392C. */
+		if (sc->mac_rev >= 0x0223) {
+			if (chan <= 4)
+				rf = 0x0f;
+			else if (chan >= 5 && chan <= 7)
+				rf = 0x0e;
+			else
+				rf = 0x0d;
+			run_rt3070_rf_write(sc, 23, rf);
+
+			if (chan <= 4)
+				rf = 0x0c;
+			else if (chan == 5)
+				rf = 0x0b;
+			else if (chan >= 6 && chan <= 7)
+				rf = 0x0a;
+			else if (chan >= 8 && chan <= 10)
+				rf = 0x09;
+			else
+				rf = 0x08;
+			run_rt3070_rf_write(sc, 59, rf);
+		} else {
+			if (chan <= 11)
+				rf = 0x0f;
+			else
+				rf = 0x0b;
+			run_rt3070_rf_write(sc, 59, rf);
+		}
+	} else {
+		/* Fix for RT5390F. */
+		if (sc->mac_rev >= 0x0502) {
+			if (chan <= 11)
+				rf = 0x43;
+			else
+				rf = 0x23;
+			run_rt3070_rf_write(sc, 55, rf);
+
+			if (chan <= 11)
+				rf = 0x0f;
+			else if (chan == 12)
+				rf = 0x0d;
+			else
+				rf = 0x0b;
+			run_rt3070_rf_write(sc, 59, rf);
+		} else {
+			run_rt3070_rf_write(sc, 55, 0x44);
+			run_rt3070_rf_write(sc, 59, 0x8f);
+		}
+	}
+
+	/* Enable VCO calibration. */
+	run_rt3070_rf_read(sc, 3, &rf);
+	rf |= RT5390_VCOCAL;
+	run_rt3070_rf_write(sc, 3, rf);
+}
+
+static void
+run_rt5592_set_chan(struct run_softc *sc, u_int chan)
+{
+	const struct rt5592_freqs *freqs;
+	uint32_t tmp;
+	uint8_t reg, rf, txpow_bound;
+	int8_t txpow1, txpow2;
+	int i;
+
+	run_read(sc, RT5592_DEBUG_INDEX, &tmp);
+	freqs = (tmp & RT5592_SEL_XTAL) ?
+	    rt5592_freqs_40mhz : rt5592_freqs_20mhz;
+
+	/* find the settings for this channel (we know it exists) */
+	for (i = 0; rt2860_rf2850[i].chan != chan; i++, freqs++);
+
+	/* use Tx power values from EEPROM */
+	txpow1 = sc->txpow1[i];
+	txpow2 = sc->txpow2[i];
+
+	run_read(sc, RT3070_LDO_CFG0, &tmp);
+	tmp &= ~0x1c000000;
+	if (chan > 14)
+		tmp |= 0x14000000;
+	run_write(sc, RT3070_LDO_CFG0, tmp);
+
+	/* N setting. */
+	run_rt3070_rf_write(sc, 8, freqs->n & 0xff);
+	run_rt3070_rf_read(sc, 9, &rf);
+	rf &= ~(1 << 4);
+	rf |= ((freqs->n & 0x0100) >> 8) << 4;
+	run_rt3070_rf_write(sc, 9, rf);
+
+	/* K setting. */
+	run_rt3070_rf_read(sc, 9, &rf);
+	rf &= ~0x0f;
+	rf |= (freqs->k & 0x0f);
+	run_rt3070_rf_write(sc, 9, rf);
+
+	/* Mode setting. */
+	run_rt3070_rf_read(sc, 11, &rf);
+	rf &= ~0x0c;
+	rf |= ((freqs->m - 0x8) & 0x3) << 2;
+	run_rt3070_rf_write(sc, 11, rf);
+	run_rt3070_rf_read(sc, 9, &rf);
+	rf &= ~(1 << 7);
+	rf |= (((freqs->m - 0x8) & 0x4) >> 2) << 7;
+	run_rt3070_rf_write(sc, 9, rf);
+
+	/* R setting. */
+	run_rt3070_rf_read(sc, 11, &rf);
+	rf &= ~0x03;
+	rf |= (freqs->r - 0x1);
+	run_rt3070_rf_write(sc, 11, rf);
+
+	if (chan <= 14) {
+		/* Initialize RF registers for 2GHZ. */
+		for (i = 0; i < NELEM(rt5592_2ghz_def_rf); i++) {
+			run_rt3070_rf_write(sc, rt5592_2ghz_def_rf[i].reg,
+			    rt5592_2ghz_def_rf[i].val);
+		}
+
+		rf = (chan <= 10) ? 0x07 : 0x06;
+		run_rt3070_rf_write(sc, 23, rf);
+		run_rt3070_rf_write(sc, 59, rf);
+
+		run_rt3070_rf_write(sc, 55, 0x43);
+
+		/* 
+		 * RF R49/R50 Tx power ALC code.
+		 * G-band bit<7:6>=1:0, bit<5:0> range from 0x0 ~ 0x27.
+		 */
+		reg = 2;
+		txpow_bound = 0x27;
+	} else {
+		/* Initialize RF registers for 5GHZ. */
+		for (i = 0; i < NELEM(rt5592_5ghz_def_rf); i++) {
+			run_rt3070_rf_write(sc, rt5592_5ghz_def_rf[i].reg,
+			    rt5592_5ghz_def_rf[i].val);
+		}
+		for (i = 0; i < NELEM(rt5592_chan_5ghz); i++) {
+			if (chan >= rt5592_chan_5ghz[i].firstchan &&
+			    chan <= rt5592_chan_5ghz[i].lastchan) {
+				run_rt3070_rf_write(sc, rt5592_chan_5ghz[i].reg,
+				    rt5592_chan_5ghz[i].val);
+			}
+		}
+
+		/* 
+		 * RF R49/R50 Tx power ALC code.
+		 * A-band bit<7:6>=1:1, bit<5:0> range from 0x0 ~ 0x2b.
+		 */
+		reg = 3;
+		txpow_bound = 0x2b;
+	}
+
+	/* RF R49 ch0 Tx power ALC code. */
+	run_rt3070_rf_read(sc, 49, &rf);
+	rf &= ~0xc0;
+	rf |= (reg << 6);
+	rf = (rf & ~0x3f) | (txpow1 & 0x3f);
+	if ((rf & 0x3f) > txpow_bound)
+		rf = (rf & ~0x3f) | txpow_bound;
+	run_rt3070_rf_write(sc, 49, rf);
+
+	/* RF R50 ch1 Tx power ALC code. */
+	run_rt3070_rf_read(sc, 50, &rf);
+	rf &= ~(1 << 7 | 1 << 6);
+	rf |= (reg << 6);
+	rf = (rf & ~0x3f) | (txpow2 & 0x3f);
+	if ((rf & 0x3f) > txpow_bound)
+		rf = (rf & ~0x3f) | txpow_bound;
+	run_rt3070_rf_write(sc, 50, rf);
+
+	/* Enable RF_BLOCK, PLL_PD, RX0_PD, and TX0_PD. */
+	run_rt3070_rf_read(sc, 1, &rf);
+	rf |= (RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | RT3070_TX0_PD);
+	if (sc->ntxchains > 1)
+		rf |= RT3070_TX1_PD;
+	if (sc->nrxchains > 1)
+		rf |= RT3070_RX1_PD;
+	run_rt3070_rf_write(sc, 1, rf);
+
+	run_rt3070_rf_write(sc, 6, 0xe4);
+
+	run_rt3070_rf_write(sc, 30, 0x10);
+	run_rt3070_rf_write(sc, 31, 0x80);
+	run_rt3070_rf_write(sc, 32, 0x80);
+
+	run_adjust_freq_offset(sc);
+
+	/* Enable VCO calibration. */
+	run_rt3070_rf_read(sc, 3, &rf);
+	rf |= RT5390_VCOCAL;
+	run_rt3070_rf_write(sc, 3, rf);
+}
+
+static void
+run_set_rx_antenna(struct run_softc *sc, int aux)
+{
+	uint32_t tmp;
+	uint8_t bbp152;
+
+	if (aux) {
+		if (sc->rf_rev == RT5390_RF_5370) {
+			run_bbp_read(sc, 152, &bbp152);
+			run_bbp_write(sc, 152, bbp152 & ~0x80);
+		} else {
+			run_mcu_cmd(sc, RT2860_MCU_CMD_ANTSEL, 0);
+			run_read(sc, RT2860_GPIO_CTRL, &tmp);
+			run_write(sc, RT2860_GPIO_CTRL, (tmp & ~0x0808) | 0x08);
+		}
+	} else {
+		if (sc->rf_rev == RT5390_RF_5370) {
+			run_bbp_read(sc, 152, &bbp152);
+			run_bbp_write(sc, 152, bbp152 | 0x80);
+		} else {
+			run_mcu_cmd(sc, RT2860_MCU_CMD_ANTSEL, 1);
+			run_read(sc, RT2860_GPIO_CTRL, &tmp);
+			run_write(sc, RT2860_GPIO_CTRL, tmp & ~0x0808);
+		}
+	}
+}
+
+static int
+run_set_chan(struct run_softc *sc, struct ieee80211_channel *c)
+{
 	struct ieee80211com *ic = sc->sc_ifp->if_l2com;
-	uint32_t chan, group;
+	u_int chan, group;
 
 	chan = ieee80211_chan2ieee(ic, c);
 	if (chan == 0 || chan == IEEE80211_CHAN_ANY)
 		return (EINVAL);
 
-	if (sc->mac_ver == 0x3572)
+	if (sc->mac_ver == 0x5592)
+		run_rt5592_set_chan(sc, chan);
+	else if (sc->mac_ver >= 0x5390)
+		run_rt5390_set_chan(sc, chan);
+	else if (sc->mac_ver == 0x3593)
+		run_rt3593_set_chan(sc, chan);
+	else if (sc->mac_ver == 0x3572)
 		run_rt3572_set_chan(sc, chan);
 	else if (sc->mac_ver >= 0x3070)
 		run_rt3070_set_chan(sc, chan);
@@ -3895,6 +4835,10 @@ run_set_chan(struct run_softc *sc, struct ieee80211_channel *c)
 
 	run_delay(sc, 10);
 
+	/* Perform IQ calibration. */
+	if (sc->mac_ver >= 0x5392)
+		run_iq_calib(sc, chan);
+
 	return (0);
 }
 
@@ -3996,6 +4940,7 @@ run_update_beacon_cb(void *arg)
 	struct run_softc *sc = ic->ic_ifp->if_softc;
 	struct rt2860_txwi txwi;
 	struct mbuf *m;
+	uint16_t txwisize;
 	uint8_t ridx;
 
 	if (vap->iv_bss->ni_chan == IEEE80211_CHAN_ANYC)
@@ -4015,25 +4960,26 @@ run_update_beacon_cb(void *arg)
 	}
 	m = rvp->beacon_mbuf;
 
-	memset(&txwi, 0, sizeof txwi);
+	memset(&txwi, 0, sizeof(txwi));
 	txwi.wcid = 0xff;
 	txwi.len = htole16(m->m_pkthdr.len);
+
 	/* send beacons at the lowest available rate */
 	ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ?
 	    RT2860_RIDX_OFDM6 : RT2860_RIDX_CCK1;
 	txwi.phy = htole16(rt2860_rates[ridx].mcs);
 	if (rt2860_rates[ridx].phy == IEEE80211_T_OFDM)
-	        txwi.phy |= htole16(RT2860_PHY_OFDM);
+		txwi.phy |= htole16(RT2860_PHY_OFDM);
 	txwi.txop = RT2860_TX_TXOP_HT;
 	txwi.flags = RT2860_TX_TS;
 	txwi.xflags = RT2860_TX_NSEQ;
 
-	run_write_region_1(sc, RT2860_BCN_BASE(rvp->rvp_id),
-	    (uint8_t *)&txwi, sizeof txwi);
-	run_write_region_1(sc, RT2860_BCN_BASE(rvp->rvp_id) + sizeof txwi,
-	    mtod(m, uint8_t *), (m->m_pkthdr.len + 1) & ~1);	/* roundup len */
-
-	return;
+	txwisize = (sc->mac_ver == 0x5592) ?
+	    sizeof(txwi) + sizeof(uint32_t) : sizeof(txwi);
+	run_write_region_1(sc, RT2860_BCN_BASE(rvp->rvp_id), (uint8_t *)&txwi,
+	    txwisize);
+	run_write_region_1(sc, RT2860_BCN_BASE(rvp->rvp_id) + txwisize,
+	    mtod(m, uint8_t *), (m->m_pkthdr.len + 1) & ~1);
 }
 
 static void
@@ -4153,7 +5099,8 @@ run_enable_tsf_sync(struct run_softc *sc)
 	struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
 	uint32_t tmp;
 
-	DPRINTF("rvp_id=%d ic_opmode=%d\n", RUN_VAP(vap)->rvp_id, ic->ic_opmode);
+	DPRINTF("rvp_id=%d ic_opmode=%d\n", RUN_VAP(vap)->rvp_id,
+	    ic->ic_opmode);
 
 	run_read(sc, RT2860_BCN_TIME_CFG, &tmp);
 	tmp &= ~0x1fffff;
@@ -4189,8 +5136,8 @@ run_enable_tsf_sync(struct run_softc *sc)
 static void
 run_enable_mrr(struct run_softc *sc)
 {
-#define CCK(mcs)	(mcs)
-#define OFDM(mcs)	(1 << 3 | (mcs))
+#define	CCK(mcs)	(mcs)
+#define	OFDM(mcs)	(1 << 3 | (mcs))
 	run_write(sc, RT2860_LG_FBK_CFG0,
 	    OFDM(6) << 28 |	/* 54->48 */
 	    OFDM(5) << 24 |	/* 48->36 */
@@ -4309,7 +5256,7 @@ run_rssi2dbm(struct run_softc *sc, uint8_t rssi, uint8_t rxchain)
 	int delta;
 
 	if (IEEE80211_IS_CHAN_5GHZ(c)) {
-		uint32_t chan = ieee80211_chan2ieee(ic, c);
+		u_int chan = ieee80211_chan2ieee(ic, c);
 		delta = sc->rssi_5ghz[rxchain];
 
 		/* determine channel group */
@@ -4325,6 +5272,64 @@ run_rssi2dbm(struct run_softc *sc, uint8_t rssi, uint8_t rxchain)
 	return (-12 - delta - rssi);
 }
 
+static void
+run_rt5390_bbp_init(struct run_softc *sc)
+{
+	int i;
+	uint8_t bbp;
+
+	/* Apply maximum likelihood detection for 2 stream case. */
+	run_bbp_read(sc, 105, &bbp);
+	if (sc->nrxchains > 1)
+		run_bbp_write(sc, 105, bbp | RT5390_MLD);
+
+	/* Avoid data lost and CRC error. */
+	run_bbp_read(sc, 4, &bbp);
+	run_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL);
+
+	if (sc->mac_ver == 0x5592) {
+		for (i = 0; i < NELEM(rt5592_def_bbp); i++) {
+			run_bbp_write(sc, rt5592_def_bbp[i].reg,
+			    rt5592_def_bbp[i].val);
+		}
+		for (i = 0; i < NELEM(rt5592_bbp_r196); i++) {
+			run_bbp_write(sc, 195, i + 0x80);
+			run_bbp_write(sc, 196, rt5592_bbp_r196[i]);
+		}
+	} else {
+		for (i = 0; i < NELEM(rt5390_def_bbp); i++) {
+			run_bbp_write(sc, rt5390_def_bbp[i].reg,
+			    rt5390_def_bbp[i].val);
+		}
+	}
+	if (sc->mac_ver == 0x5392) {
+		run_bbp_write(sc, 88, 0x90);
+		run_bbp_write(sc, 95, 0x9a);
+		run_bbp_write(sc, 98, 0x12);
+		run_bbp_write(sc, 106, 0x12);
+		run_bbp_write(sc, 134, 0xd0);
+		run_bbp_write(sc, 135, 0xf6);
+		run_bbp_write(sc, 148, 0x84);
+	}
+
+	run_bbp_read(sc, 152, &bbp);
+	run_bbp_write(sc, 152, bbp | 0x80);
+
+	/* Fix BBP254 for RT5592C. */
+	if (sc->mac_ver == 0x5592 && sc->mac_rev >= 0x0221) {
+		run_bbp_read(sc, 254, &bbp);
+		run_bbp_write(sc, 254, bbp | 0x80);
+	}
+
+	/* Disable hardware antenna diversity. */
+	if (sc->mac_ver == 0x5390)
+		run_bbp_write(sc, 154, 0);
+
+	/* Initialize Rx CCK/OFDM frequency offset report. */
+	run_bbp_write(sc, 142, 1);
+	run_bbp_write(sc, 143, 57);
+}
+
 static int
 run_bbp_init(struct run_softc *sc)
 {
@@ -4342,16 +5347,29 @@ run_bbp_init(struct run_softc *sc)
 		return (ETIMEDOUT);
 
 	/* initialize BBP registers to default values */
-	for (i = 0; i < NELEM(rt2860_def_bbp); i++) {
-		run_bbp_write(sc, rt2860_def_bbp[i].reg,
-		    rt2860_def_bbp[i].val);
+	if (sc->mac_ver >= 0x5390)
+		run_rt5390_bbp_init(sc);
+	else {
+		for (i = 0; i < NELEM(rt2860_def_bbp); i++) {
+			run_bbp_write(sc, rt2860_def_bbp[i].reg,
+			    rt2860_def_bbp[i].val);
+		}
 	}
 
+	if (sc->mac_ver == 0x3593) {
+		run_bbp_write(sc, 79, 0x13);
+		run_bbp_write(sc, 80, 0x05);
+		run_bbp_write(sc, 81, 0x33);
+		run_bbp_write(sc, 86, 0x46);
+		run_bbp_write(sc, 137, 0x0f);
+	}
+		
 	/* fix BBP84 for RT2860E */
 	if (sc->mac_ver == 0x2860 && sc->mac_rev != 0x0101)
 		run_bbp_write(sc, 84, 0x19);
 
-	if (sc->mac_ver >= 0x3070) {
+	if (sc->mac_ver >= 0x3070 && (sc->mac_ver != 0x3593 &&
+	    sc->mac_ver != 0x5592)) {
 		run_bbp_write(sc, 79, 0x13);
 		run_bbp_write(sc, 80, 0x05);
 		run_bbp_write(sc, 81, 0x33);
@@ -4366,7 +5384,7 @@ static int
 run_rt3070_rf_init(struct run_softc *sc)
 {
 	uint32_t tmp;
-	uint8_t rf, target, bbp4;
+	uint8_t bbp4, mingain, rf, target;
 	int i;
 
 	run_rt3070_rf_read(sc, 30, &rf);
@@ -4388,8 +5406,12 @@ run_rt3070_rf_init(struct run_softc *sc)
 		}
 	}
 
-	if (sc->mac_ver == 0x3070) {
-		/* change voltage from 1.2V to 1.35V for RT3070 */
+	if (sc->mac_ver == 0x3070 && sc->mac_rev < 0x0201) {
+		/* 
+		 * Change voltage from 1.2V to 1.35V for RT3070.
+		 * The DAC issue (RT3070_LDO_CFG0) has been fixed
+		 * in RT3070(F).
+		 */
 		run_read(sc, RT3070_LDO_CFG0, &tmp);
 		tmp = (tmp & ~0x0f000000) | 0x0d000000;
 		run_write(sc, RT3070_LDO_CFG0, tmp);
@@ -4439,7 +5461,7 @@ run_rt3070_rf_init(struct run_softc *sc)
 
 	/* select 40MHz bandwidth */
 	run_bbp_read(sc, 4, &bbp4);
-	run_bbp_write(sc, 4, (bbp4 & ~0x08) | 0x10);
+	run_bbp_write(sc, 4, (bbp4 & ~0x18) | 0x10);
 	run_rt3070_rf_read(sc, 31, &rf);
 	run_rt3070_rf_write(sc, 31, rf | 0x20);
 
@@ -4456,7 +5478,7 @@ run_rt3070_rf_init(struct run_softc *sc)
 		/* save default BBP registers 25 and 26 values */
 		run_bbp_read(sc, 25, &sc->bbp25);
 		run_bbp_read(sc, 26, &sc->bbp26);
-	} else if (sc->mac_rev < 0x0211)
+	} else if (sc->mac_rev < 0x0201 || sc->mac_rev < 0x0211)
 		run_rt3070_rf_write(sc, 27, 0x03);
 
 	run_read(sc, RT3070_OPT_14, &tmp);
@@ -4469,7 +5491,8 @@ run_rt3070_rf_init(struct run_softc *sc)
 		     (sc->mac_ver == 0x3071 && sc->mac_rev >= 0x0211)) &&
 		    !sc->ext_2ghz_lna)
 			rf |= 0x20;	/* fix for long range Rx issue */
-		if (sc->txmixgain_2ghz >= 1)
+		mingain = (sc->mac_ver == 0x3070) ? 1 : 2;
+		if (sc->txmixgain_2ghz >= mingain)
 			rf = (rf & ~0x7) | sc->txmixgain_2ghz;
 		run_rt3070_rf_write(sc, 17, rf);
 	}
@@ -4501,6 +5524,119 @@ run_rt3070_rf_init(struct run_softc *sc)
 	return (0);
 }
 
+static void
+run_rt3593_rf_init(struct run_softc *sc)
+{
+	uint32_t tmp;
+	uint8_t rf;
+	int i;
+
+	/* Disable the GPIO bits 4 and 7 for LNA PE control. */
+	run_read(sc, RT3070_GPIO_SWITCH, &tmp);
+	tmp &= ~(1 << 4 | 1 << 7);
+	run_write(sc, RT3070_GPIO_SWITCH, tmp);
+
+	/* Initialize RF registers to default value. */
+	for (i = 0; i < NELEM(rt3593_def_rf); i++) {
+		run_rt3070_rf_write(sc, rt3593_def_rf[i].reg,
+		    rt3593_def_rf[i].val);
+	}
+
+	/* Toggle RF R2 to initiate calibration. */
+	run_rt3070_rf_write(sc, 2, RT5390_RESCAL);
+
+	/* Initialize RF frequency offset. */
+	run_adjust_freq_offset(sc);
+
+	run_rt3070_rf_read(sc, 18, &rf);
+	run_rt3070_rf_write(sc, 18, rf | RT3593_AUTOTUNE_BYPASS);
+
+	/*
+	 * Increase voltage from 1.2V to 1.35V, wait for 1 msec to
+	 * decrease voltage back to 1.2V.
+	 */
+	run_read(sc, RT3070_LDO_CFG0, &tmp);
+	tmp = (tmp & ~0x1f000000) | 0x0d000000;
+	run_write(sc, RT3070_LDO_CFG0, tmp);
+	run_delay(sc, 1);
+	tmp = (tmp & ~0x1f000000) | 0x01000000;
+	run_write(sc, RT3070_LDO_CFG0, tmp);
+
+	sc->rf24_20mhz = 0x1f;
+	sc->rf24_40mhz = 0x2f;
+
+	/* Save default BBP registers 25 and 26 values. */
+	run_bbp_read(sc, 25, &sc->bbp25);
+	run_bbp_read(sc, 26, &sc->bbp26);
+
+	run_read(sc, RT3070_OPT_14, &tmp);
+	run_write(sc, RT3070_OPT_14, tmp | 1);
+}
+
+static void
+run_rt5390_rf_init(struct run_softc *sc)
+{
+	uint32_t tmp;
+	uint8_t rf;
+	int i;
+
+	/* Toggle RF R2 to initiate calibration. */
+	if (sc->mac_ver == 0x5390) {
+		run_rt3070_rf_read(sc, 2, &rf);
+		run_rt3070_rf_write(sc, 2, rf | RT5390_RESCAL);
+		run_delay(sc, 10);
+		run_rt3070_rf_write(sc, 2, rf & ~RT5390_RESCAL);
+	} else {
+		run_rt3070_rf_write(sc, 2, RT5390_RESCAL);
+		run_delay(sc, 10);
+	}
+
+	/* Initialize RF registers to default value. */
+	if (sc->mac_ver == 0x5592) {
+		for (i = 0; i < NELEM(rt5592_def_rf); i++) {
+			run_rt3070_rf_write(sc, rt5592_def_rf[i].reg,
+			    rt5592_def_rf[i].val);
+		}
+		/* Initialize RF frequency offset. */
+		run_adjust_freq_offset(sc);
+	} else if (sc->mac_ver == 0x5392) {
+		for (i = 0; i < NELEM(rt5392_def_rf); i++) {
+			run_rt3070_rf_write(sc, rt5392_def_rf[i].reg,
+			    rt5392_def_rf[i].val);
+		}
+		if (sc->mac_rev >= 0x0223) {
+			run_rt3070_rf_write(sc, 23, 0x0f);
+			run_rt3070_rf_write(sc, 24, 0x3e);
+			run_rt3070_rf_write(sc, 51, 0x32);
+			run_rt3070_rf_write(sc, 53, 0x22);
+			run_rt3070_rf_write(sc, 56, 0xc1);
+			run_rt3070_rf_write(sc, 59, 0x0f);
+		}
+	} else {
+		for (i = 0; i < NELEM(rt5390_def_rf); i++) {
+			run_rt3070_rf_write(sc, rt5390_def_rf[i].reg,
+			    rt5390_def_rf[i].val);
+		}
+		if (sc->mac_rev >= 0x0502) {
+			run_rt3070_rf_write(sc, 6, 0xe0);
+			run_rt3070_rf_write(sc, 25, 0x80);
+			run_rt3070_rf_write(sc, 46, 0x73);
+			run_rt3070_rf_write(sc, 53, 0x00);
+			run_rt3070_rf_write(sc, 56, 0x42);
+			run_rt3070_rf_write(sc, 61, 0xd1);
+		}
+	}
+
+	sc->rf24_20mhz = 0x1f;	/* default value */
+	sc->rf24_40mhz = (sc->mac_ver == 0x5592) ? 0 : 0x2f;
+
+	if (sc->mac_rev < 0x0211)
+		run_rt3070_rf_write(sc, 27, 0x3);
+
+	run_read(sc, RT3070_OPT_14, &tmp);
+	run_write(sc, RT3070_OPT_14, tmp | 1);
+}
+
 static int
 run_rt3070_filter_calib(struct run_softc *sc, uint8_t init, uint8_t target,
     uint8_t *val)
@@ -4530,7 +5666,7 @@ run_rt3070_filter_calib(struct run_softc *sc, uint8_t init, uint8_t target,
 			break;
 	}
 	if (ntries == 100)
-		return ETIMEDOUT;
+		return (ETIMEDOUT);
 
 	/* set power and frequency of stopband test tone */
 	run_bbp_write(sc, 24, 0x06);
@@ -4595,10 +5731,15 @@ run_rt3070_rf_setup(struct run_softc *sc)
 		run_rt3070_rf_write(sc, 16, rf);
 
 	} else if (sc->mac_ver == 0x3071) {
-		/* enable DC filter */
-		if (sc->mac_rev >= 0x0201)
+		if (sc->mac_rev >= 0x0211) {
+			/* enable DC filter */
 			run_bbp_write(sc, 103, 0xc0);
 
+			/* improve power consumption */
+			run_bbp_read(sc, 31, &bbp);
+			run_bbp_write(sc, 31, bbp & ~0x03);
+		}
+
 		run_bbp_read(sc, 138, &bbp);
 		if (sc->ntxchains == 1)
 			bbp |= 0x20;	/* turn off DAC1 */
@@ -4606,12 +5747,6 @@ run_rt3070_rf_setup(struct run_softc *sc)
 			bbp &= ~0x02;	/* turn off ADC1 */
 		run_bbp_write(sc, 138, bbp);
 
-		if (sc->mac_rev >= 0x0211) {
-			/* improve power consumption */
-			run_bbp_read(sc, 31, &bbp);
-			run_bbp_write(sc, 31, bbp & ~0x03);
-		}
-
 		run_write(sc, RT2860_TX_SW_CFG1, 0);
 		if (sc->mac_rev < 0x0211) {
 			run_write(sc, RT2860_TX_SW_CFG2,
@@ -4629,7 +5764,7 @@ run_rt3070_rf_setup(struct run_softc *sc)
 			run_bbp_write(sc, 31, bbp & ~0x03);
 		}
 
-		if (sc->mac_rev < 0x0211) {
+		if (sc->mac_rev < 0x0201) {
 			run_write(sc, RT2860_TX_SW_CFG1, 0);
 			run_write(sc, RT2860_TX_SW_CFG2, 0x2c);
 		} else
@@ -4646,6 +5781,123 @@ run_rt3070_rf_setup(struct run_softc *sc)
 	}
 }
 
+static void
+run_rt3593_rf_setup(struct run_softc *sc)
+{
+	uint8_t bbp, rf;
+
+	if (sc->mac_rev >= 0x0211) {
+		/* Enable DC filter. */
+		run_bbp_write(sc, 103, 0xc0);
+	}
+	run_write(sc, RT2860_TX_SW_CFG1, 0);
+	if (sc->mac_rev < 0x0211) {
+		run_write(sc, RT2860_TX_SW_CFG2,
+		    sc->patch_dac ? 0x2c : 0x0f);
+	} else
+		run_write(sc, RT2860_TX_SW_CFG2, 0);
+
+	run_rt3070_rf_read(sc, 50, &rf);
+	run_rt3070_rf_write(sc, 50, rf & ~RT3593_TX_LO2);
+
+	run_rt3070_rf_read(sc, 51, &rf);
+	rf = (rf & ~(RT3593_TX_LO1 | 0x0c)) |
+	    ((sc->txmixgain_2ghz & 0x07) << 2);
+	run_rt3070_rf_write(sc, 51, rf);
+
+	run_rt3070_rf_read(sc, 38, &rf);
+	run_rt3070_rf_write(sc, 38, rf & ~RT5390_RX_LO1);
+
+	run_rt3070_rf_read(sc, 39, &rf);
+	run_rt3070_rf_write(sc, 39, rf & ~RT5390_RX_LO2);
+
+	run_rt3070_rf_read(sc, 1, &rf);
+	run_rt3070_rf_write(sc, 1, rf & ~(RT3070_RF_BLOCK | RT3070_PLL_PD));
+
+	run_rt3070_rf_read(sc, 30, &rf);
+	rf = (rf & ~0x18) | 0x10;
+	run_rt3070_rf_write(sc, 30, rf);
+
+	/* Apply maximum likelihood detection for 2 stream case. */
+	run_bbp_read(sc, 105, &bbp);
+	if (sc->nrxchains > 1)
+		run_bbp_write(sc, 105, bbp | RT5390_MLD);
+
+	/* Avoid data lost and CRC error. */
+	run_bbp_read(sc, 4, &bbp);
+	run_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL);
+
+	run_bbp_write(sc, 92, 0x02);
+	run_bbp_write(sc, 82, 0x82);
+	run_bbp_write(sc, 106, 0x05);
+	run_bbp_write(sc, 104, 0x92);
+	run_bbp_write(sc, 88, 0x90);
+	run_bbp_write(sc, 148, 0xc8);
+	run_bbp_write(sc, 47, 0x48);
+	run_bbp_write(sc, 120, 0x50);
+
+	run_bbp_write(sc, 163, 0x9d);
+
+	/* SNR mapping. */
+	run_bbp_write(sc, 142, 0x06);
+	run_bbp_write(sc, 143, 0xa0);
+	run_bbp_write(sc, 142, 0x07);
+	run_bbp_write(sc, 143, 0xa1);
+	run_bbp_write(sc, 142, 0x08);
+	run_bbp_write(sc, 143, 0xa2);
+
+	run_bbp_write(sc, 31, 0x08);
+	run_bbp_write(sc, 68, 0x0b);
+	run_bbp_write(sc, 105, 0x04);
+}
+
+static void
+run_rt5390_rf_setup(struct run_softc *sc)
+{
+	uint8_t bbp, rf;
+
+	if (sc->mac_rev >= 0x0211) {
+		/* Enable DC filter. */
+		run_bbp_write(sc, 103, 0xc0);
+
+		if (sc->mac_ver != 0x5592) {
+			/* Improve power consumption. */
+			run_bbp_read(sc, 31, &bbp);
+			run_bbp_write(sc, 31, bbp & ~0x03);
+		}
+	}
+
+	run_bbp_read(sc, 138, &bbp);
+	if (sc->ntxchains == 1)
+		bbp |= 0x20;	/* turn off DAC1 */
+	if (sc->nrxchains == 1)
+		bbp &= ~0x02;	/* turn off ADC1 */
+	run_bbp_write(sc, 138, bbp);
+
+	run_rt3070_rf_read(sc, 38, &rf);
+	run_rt3070_rf_write(sc, 38, rf & ~RT5390_RX_LO1);
+
+	run_rt3070_rf_read(sc, 39, &rf);
+	run_rt3070_rf_write(sc, 39, rf & ~RT5390_RX_LO2);
+
+	/* Avoid data lost and CRC error. */
+	run_bbp_read(sc, 4, &bbp);
+	run_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL);
+
+	run_rt3070_rf_read(sc, 30, &rf);
+	rf = (rf & ~0x18) | 0x10;
+	run_rt3070_rf_write(sc, 30, rf);
+
+	if (sc->mac_ver != 0x5592) {
+		run_write(sc, RT2860_TX_SW_CFG1, 0);
+		if (sc->mac_rev < 0x0211) {
+			run_write(sc, RT2860_TX_SW_CFG2,
+			    sc->patch_dac ? 0x2c : 0x0f);
+		} else
+			run_write(sc, RT2860_TX_SW_CFG2, 0);
+	}
+}
+
 static int
 run_txrx_enable(struct run_softc *sc)
 {
@@ -4656,13 +5908,13 @@ run_txrx_enable(struct run_softc *sc)
 	run_write(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_TX_EN);
 	for (ntries = 0; ntries < 200; ntries++) {
 		if ((error = run_read(sc, RT2860_WPDMA_GLO_CFG, &tmp)) != 0)
-			return error;
+			return (error);
 		if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0)
 			break;
 		run_delay(sc, 50);
 	}
 	if (ntries == 200)
-		return ETIMEDOUT;
+		return (ETIMEDOUT);
 
 	run_delay(sc, 50);
 
@@ -4693,6 +5945,20 @@ run_txrx_enable(struct run_softc *sc)
 }
 
 static void
+run_adjust_freq_offset(struct run_softc *sc)
+{
+	uint8_t rf, tmp;
+
+	run_rt3070_rf_read(sc, 17, &rf);
+	tmp = rf;
+	rf = (rf & ~0x7f) | (sc->freq & 0x7f);
+	rf = MIN(rf, 0x5f);
+
+	if (tmp != rf)
+		run_mcu_cmd(sc, 0x74, (tmp << 8 ) | rf);
+}
+
+static void
 run_init_locked(struct run_softc *sc)
 {
 	struct ifnet *ifp = sc->sc_ifp;
@@ -4771,7 +6037,23 @@ run_init_locked(struct run_softc *sc)
 	run_write(sc, RT2860_WMM_CWMIN_CFG, 0x00002344);
 	run_write(sc, RT2860_WMM_CWMAX_CFG, 0x000034aa);
 
-	if (sc->mac_ver >= 0x3070) {
+	if (sc->mac_ver >= 0x5390) {
+		run_write(sc, RT2860_TX_SW_CFG0,
+		    4 << RT2860_DLY_PAPE_EN_SHIFT | 4);
+		if (sc->mac_ver >= 0x5392) {
+			run_write(sc, RT2860_MAX_LEN_CFG, 0x00002fff);
+			if (sc->mac_ver == 0x5592) {
+				run_write(sc, RT2860_HT_FBK_CFG1, 0xedcba980);
+				run_write(sc, RT2860_TXOP_HLDR_ET, 0x00000082);
+			} else {
+				run_write(sc, RT2860_HT_FBK_CFG1, 0xedcb4980);
+				run_write(sc, RT2860_LG_FBK_CFG0, 0xedcba322);
+			}
+		}
+	} else if (sc->mac_ver == 0x3593) {
+		run_write(sc, RT2860_TX_SW_CFG0,
+		    4 << RT2860_DLY_PAPE_EN_SHIFT | 2);
+	} else if (sc->mac_ver >= 0x3070) {
 		/* set delay of PA_PE assertion to 1us (unit of 0.25us) */
 		run_write(sc, RT2860_TX_SW_CFG0,
 		    4 << RT2860_DLY_PAPE_EN_SHIFT);
@@ -4828,14 +6110,16 @@ run_init_locked(struct run_softc *sc)
 	run_write(sc, RT2860_WMM_TXOP1_CFG, 48 << 16 | 96);
 
 	/* write vendor-specific BBP values (from EEPROM) */
-	for (i = 0; i < 10; i++) {
-		if (sc->bbp[i].reg == 0 || sc->bbp[i].reg == 0xff)
-			continue;
-		run_bbp_write(sc, sc->bbp[i].reg, sc->bbp[i].val);
+	if (sc->mac_ver < 0x3593) {
+		for (i = 0; i < 10; i++) {
+			if (sc->bbp[i].reg == 0 || sc->bbp[i].reg == 0xff)
+				continue;
+			run_bbp_write(sc, sc->bbp[i].reg, sc->bbp[i].val);
+		}
 	}
 
 	/* select Main antenna for 1T1R devices */
-	if (sc->rf_rev == RT3070_RF_3020)
+	if (sc->rf_rev == RT3070_RF_3020 || sc->rf_rev == RT5390_RF_5370)
 		run_set_rx_antenna(sc, 0);
 
 	/* send LEDs operating mode to microcontroller */
@@ -4843,7 +6127,11 @@ run_init_locked(struct run_softc *sc)
 	(void)run_mcu_cmd(sc, RT2860_MCU_CMD_LED2, sc->led[1]);
 	(void)run_mcu_cmd(sc, RT2860_MCU_CMD_LED3, sc->led[2]);
 
-	if (sc->mac_ver >= 0x3070)
+	if (sc->mac_ver >= 0x5390)
+		run_rt5390_rf_init(sc);
+	else if (sc->mac_ver == 0x3593)
+		run_rt3593_rf_init(sc);
+	else if (sc->mac_ver >= 0x3070)
 		run_rt3070_rf_init(sc);
 
 	/* disable non-existing Rx chains */
@@ -4861,7 +6149,11 @@ run_init_locked(struct run_softc *sc)
 		bbp1 &= ~(1 << 3 | 1 << 4);
 	run_bbp_write(sc, 1, bbp1);
 
-	if (sc->mac_ver >= 0x3070)
+	if (sc->mac_ver >= 0x5390)
+		run_rt5390_rf_setup(sc);
+	else if (sc->mac_ver == 0x3593)
+		run_rt3593_rf_setup(sc);
+	else if (sc->mac_ver >= 0x3070)
 		run_rt3070_rf_setup(sc);
 
 	/* select default channel */
@@ -4938,6 +6230,24 @@ run_stop(void *arg)
 		sc->rx_m = NULL;
 	}
 
+	/* Disable Tx/Rx DMA. */
+	if (run_read(sc, RT2860_WPDMA_GLO_CFG, &tmp) != 0)
+		return;
+	tmp &= ~(RT2860_RX_DMA_EN | RT2860_TX_DMA_EN);
+	run_write(sc, RT2860_WPDMA_GLO_CFG, tmp);
+
+	for (ntries = 0; ntries < 100; ntries++) {
+		if (run_read(sc, RT2860_WPDMA_GLO_CFG, &tmp) != 0)
+			return;
+		if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0)
+				break;
+		run_delay(sc, 10);
+	}
+	if (ntries == 100) {
+		device_printf(sc->sc_dev, "timeout waiting for DMA engine\n");
+		return;
+	}
+
 	/* disable Tx/Rx */
 	run_read(sc, RT2860_MAC_SYS_CTRL, &tmp);
 	tmp &= ~(RT2860_MAC_RX_EN | RT2860_MAC_TX_EN);
@@ -4965,12 +6275,10 @@ run_stop(void *arg)
 
 	for (i = 0; i != RUN_EP_QUEUES; i++)
 		run_unsetup_tx_list(sc, &sc->sc_epq[i]);
-
-	return;
 }
 
 static void
-run_delay(struct run_softc *sc, unsigned int ms)
+run_delay(struct run_softc *sc, u_int ms)
 {
 	zsleep(sc, &wlan_global_serializer, 0, "rundelay",
 	    USB_MS_TO_TICKS(ms));
@@ -4994,7 +6302,7 @@ static driver_t run_driver = {
 
 static devclass_t run_devclass;
 
-DRIVER_MODULE(run, uhub, run_driver, run_devclass, NULL, 0);
+DRIVER_MODULE(run, uhub, run_driver, run_devclass, run_driver_loaded, NULL);
 MODULE_DEPEND(run, wlan, 1, 1, 1);
 MODULE_DEPEND(run, usb, 1, 1, 1);
 MODULE_DEPEND(run, firmware, 1, 1, 1);
diff --git a/sys/bus/u4b/wlan/if_runreg.h b/sys/bus/u4b/wlan/if_runreg.h
index 3a5125f..af9ebf1 100644
--- a/sys/bus/u4b/wlan/if_runreg.h
+++ b/sys/bus/u4b/wlan/if_runreg.h
@@ -16,715 +16,743 @@
  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  *
- * $FreeBSD$
+ * $FreeBSD: head/sys/dev/usb/wlan/if_runreg.h 260219 2014-01-03 06:01:05Z kevlo $
  */
 
 #ifndef _IF_RUNREG_H_
 #define	_IF_RUNREG_H_
 
-/* PCI registers */
-#define RT2860_PCI_CFG			0x0000
-#define RT2860_PCI_EECTRL		0x0004
-#define RT2860_PCI_MCUCTRL		0x0008
-#define RT2860_PCI_SYSCTRL		0x000c
-#define RT2860_PCIE_JTAG		0x0010
+#define	RT2860_CONFIG_NO		1
+#define	RT2860_IFACE_INDEX		0
 
-#define RT2860_CONFIG_NO		1
-#define RT2860_IFACE_INDEX		0
-
-#define RT3070_OPT_14			0x0114
+#define	RT3070_OPT_14			0x0114
 
 /* SCH/DMA registers */
-#define RT2860_INT_STATUS		0x0200
-#define RT2860_INT_MASK			0x0204
-#define RT2860_WPDMA_GLO_CFG		0x0208
-#define RT2860_WPDMA_RST_IDX		0x020c
-#define RT2860_DELAY_INT_CFG		0x0210
-#define RT2860_WMM_AIFSN_CFG		0x0214
-#define RT2860_WMM_CWMIN_CFG		0x0218
-#define RT2860_WMM_CWMAX_CFG		0x021c
-#define RT2860_WMM_TXOP0_CFG		0x0220
-#define RT2860_WMM_TXOP1_CFG		0x0224
-#define RT2860_GPIO_CTRL		0x0228
-#define RT2860_MCU_CMD_REG		0x022c
-#define RT2860_TX_BASE_PTR(qid)		(0x0230 + (qid) * 16)
-#define RT2860_TX_MAX_CNT(qid)		(0x0234 + (qid) * 16)
-#define RT2860_TX_CTX_IDX(qid)		(0x0238 + (qid) * 16)
-#define RT2860_TX_DTX_IDX(qid)		(0x023c + (qid) * 16)
-#define RT2860_RX_BASE_PTR		0x0290
-#define RT2860_RX_MAX_CNT		0x0294
-#define RT2860_RX_CALC_IDX		0x0298
-#define RT2860_FS_DRX_IDX		0x029c
-#define RT2860_USB_DMA_CFG		0x02a0	/* RT2870 only */
-#define RT2860_US_CYC_CNT		0x02a4
+#define	RT2860_INT_STATUS		0x0200
+#define	RT2860_INT_MASK			0x0204
+#define	RT2860_WPDMA_GLO_CFG		0x0208
+#define	RT2860_WPDMA_RST_IDX		0x020c
+#define	RT2860_DELAY_INT_CFG		0x0210
+#define	RT2860_WMM_AIFSN_CFG		0x0214
+#define	RT2860_WMM_CWMIN_CFG		0x0218
+#define	RT2860_WMM_CWMAX_CFG		0x021c
+#define	RT2860_WMM_TXOP0_CFG		0x0220
+#define	RT2860_WMM_TXOP1_CFG		0x0224
+#define	RT2860_GPIO_CTRL		0x0228
+#define	RT2860_MCU_CMD_REG		0x022c
+#define	RT2860_TX_BASE_PTR(qid)		(0x0230 + (qid) * 16)
+#define	RT2860_TX_MAX_CNT(qid)		(0x0234 + (qid) * 16)
+#define	RT2860_TX_CTX_IDX(qid)		(0x0238 + (qid) * 16)
+#define	RT2860_TX_DTX_IDX(qid)		(0x023c + (qid) * 16)
+#define	RT2860_RX_BASE_PTR		0x0290
+#define	RT2860_RX_MAX_CNT		0x0294
+#define	RT2860_RX_CALC_IDX		0x0298
+#define	RT2860_FS_DRX_IDX		0x029c
+#define	RT2860_USB_DMA_CFG		0x02a0	/* RT2870 only */
+#define	RT2860_US_CYC_CNT		0x02a4
 
 /* PBF registers */
-#define RT2860_SYS_CTRL			0x0400
-#define RT2860_HOST_CMD			0x0404
-#define RT2860_PBF_CFG			0x0408
-#define RT2860_MAX_PCNT			0x040c
-#define RT2860_BUF_CTRL			0x0410
-#define RT2860_MCU_INT_STA		0x0414
-#define RT2860_MCU_INT_ENA		0x0418
-#define RT2860_TXQ_IO(qid)		(0x041c + (qid) * 4)
-#define RT2860_RX0Q_IO			0x0424
-#define RT2860_BCN_OFFSET0		0x042c
-#define RT2860_BCN_OFFSET1		0x0430
-#define RT2860_TXRXQ_STA		0x0434
-#define RT2860_TXRXQ_PCNT		0x0438
-#define RT2860_PBF_DBG			0x043c
-#define RT2860_CAP_CTRL			0x0440
+#define	RT2860_SYS_CTRL			0x0400
+#define	RT2860_HOST_CMD			0x0404
+#define	RT2860_PBF_CFG			0x0408
+#define	RT2860_MAX_PCNT			0x040c
+#define	RT2860_BUF_CTRL			0x0410
+#define	RT2860_MCU_INT_STA		0x0414
+#define	RT2860_MCU_INT_ENA		0x0418
+#define	RT2860_TXQ_IO(qid)		(0x041c + (qid) * 4)
+#define	RT2860_RX0Q_IO			0x0424
+#define	RT2860_BCN_OFFSET0		0x042c
+#define	RT2860_BCN_OFFSET1		0x0430
+#define	RT2860_TXRXQ_STA		0x0434
+#define	RT2860_TXRXQ_PCNT		0x0438
+#define	RT2860_PBF_DBG			0x043c
+#define	RT2860_CAP_CTRL			0x0440
 
 /* RT3070 registers */
-#define RT3070_RF_CSR_CFG		0x0500
-#define RT3070_EFUSE_CTRL		0x0580
-#define RT3070_EFUSE_DATA0		0x0590
-#define RT3070_EFUSE_DATA1		0x0594
-#define RT3070_EFUSE_DATA2		0x0598
-#define RT3070_EFUSE_DATA3		0x059c
-#define RT3070_LDO_CFG0			0x05d4
-#define RT3070_GPIO_SWITCH		0x05dc
+#define	RT3070_RF_CSR_CFG		0x0500
+#define	RT3070_EFUSE_CTRL		0x0580
+#define	RT3070_EFUSE_DATA0		0x0590
+#define	RT3070_EFUSE_DATA1		0x0594
+#define	RT3070_EFUSE_DATA2		0x0598
+#define	RT3070_EFUSE_DATA3		0x059c
+#define	RT3070_LDO_CFG0			0x05d4
+#define	RT3070_GPIO_SWITCH		0x05dc
+
+/* RT5592 registers */
+#define	RT5592_DEBUG_INDEX		0x05e8
 
 /* MAC registers */
-#define RT2860_ASIC_VER_ID		0x1000
-#define RT2860_MAC_SYS_CTRL		0x1004
-#define RT2860_MAC_ADDR_DW0		0x1008
-#define RT2860_MAC_ADDR_DW1		0x100c
-#define RT2860_MAC_BSSID_DW0		0x1010
-#define RT2860_MAC_BSSID_DW1		0x1014
-#define RT2860_MAX_LEN_CFG		0x1018
-#define RT2860_BBP_CSR_CFG		0x101c
-#define RT2860_RF_CSR_CFG0		0x1020
-#define RT2860_RF_CSR_CFG1		0x1024
-#define RT2860_RF_CSR_CFG2		0x1028
-#define RT2860_LED_CFG			0x102c
+#define	RT2860_ASIC_VER_ID		0x1000
+#define	RT2860_MAC_SYS_CTRL		0x1004
+#define	RT2860_MAC_ADDR_DW0		0x1008
+#define	RT2860_MAC_ADDR_DW1		0x100c
+#define	RT2860_MAC_BSSID_DW0		0x1010
+#define	RT2860_MAC_BSSID_DW1		0x1014
+#define	RT2860_MAX_LEN_CFG		0x1018
+#define	RT2860_BBP_CSR_CFG		0x101c
+#define	RT2860_RF_CSR_CFG0		0x1020
+#define	RT2860_RF_CSR_CFG1		0x1024
+#define	RT2860_RF_CSR_CFG2		0x1028
+#define	RT2860_LED_CFG			0x102c
 
 /* undocumented registers */
-#define RT2860_DEBUG			0x10f4
+#define	RT2860_DEBUG			0x10f4
 
 /* MAC Timing control registers */
-#define RT2860_XIFS_TIME_CFG		0x1100
-#define RT2860_BKOFF_SLOT_CFG		0x1104
-#define RT2860_NAV_TIME_CFG		0x1108
-#define RT2860_CH_TIME_CFG		0x110c
-#define RT2860_PBF_LIFE_TIMER		0x1110
-#define RT2860_BCN_TIME_CFG		0x1114
-#define RT2860_TBTT_SYNC_CFG		0x1118
-#define RT2860_TSF_TIMER_DW0		0x111c
-#define RT2860_TSF_TIMER_DW1		0x1120
-#define RT2860_TBTT_TIMER		0x1124
-#define RT2860_INT_TIMER_CFG		0x1128
-#define RT2860_INT_TIMER_EN		0x112c
-#define RT2860_CH_IDLE_TIME		0x1130
+#define	RT2860_XIFS_TIME_CFG		0x1100
+#define	RT2860_BKOFF_SLOT_CFG		0x1104
+#define	RT2860_NAV_TIME_CFG		0x1108
+#define	RT2860_CH_TIME_CFG		0x110c
+#define	RT2860_PBF_LIFE_TIMER		0x1110
+#define	RT2860_BCN_TIME_CFG		0x1114
+#define	RT2860_TBTT_SYNC_CFG		0x1118
+#define	RT2860_TSF_TIMER_DW0		0x111c
+#define	RT2860_TSF_TIMER_DW1		0x1120
+#define	RT2860_TBTT_TIMER		0x1124
+#define	RT2860_INT_TIMER_CFG		0x1128
+#define	RT2860_INT_TIMER_EN		0x112c
+#define	RT2860_CH_IDLE_TIME		0x1130
 
 /* MAC Power Save configuration registers */
-#define RT2860_MAC_STATUS_REG		0x1200
-#define RT2860_PWR_PIN_CFG		0x1204
-#define RT2860_AUTO_WAKEUP_CFG		0x1208
+#define	RT2860_MAC_STATUS_REG		0x1200
+#define	RT2860_PWR_PIN_CFG		0x1204
+#define	RT2860_AUTO_WAKEUP_CFG		0x1208
 
 /* MAC TX configuration registers */
-#define RT2860_EDCA_AC_CFG(aci)		(0x1300 + (aci) * 4)
-#define RT2860_EDCA_TID_AC_MAP		0x1310
-#define RT2860_TX_PWR_CFG(ridx)		(0x1314 + (ridx) * 4)
-#define RT2860_TX_PIN_CFG		0x1328
-#define RT2860_TX_BAND_CFG		0x132c
-#define RT2860_TX_SW_CFG0		0x1330
-#define RT2860_TX_SW_CFG1		0x1334
-#define RT2860_TX_SW_CFG2		0x1338
-#define RT2860_TXOP_THRES_CFG		0x133c
-#define RT2860_TXOP_CTRL_CFG		0x1340
-#define RT2860_TX_RTS_CFG		0x1344
-#define RT2860_TX_TIMEOUT_CFG		0x1348
-#define RT2860_TX_RTY_CFG		0x134c
-#define RT2860_TX_LINK_CFG		0x1350
-#define RT2860_HT_FBK_CFG0		0x1354
-#define RT2860_HT_FBK_CFG1		0x1358
-#define RT2860_LG_FBK_CFG0		0x135c
-#define RT2860_LG_FBK_CFG1		0x1360
-#define RT2860_CCK_PROT_CFG		0x1364
-#define RT2860_OFDM_PROT_CFG		0x1368
-#define RT2860_MM20_PROT_CFG		0x136c
-#define RT2860_MM40_PROT_CFG		0x1370
-#define RT2860_GF20_PROT_CFG		0x1374
-#define RT2860_GF40_PROT_CFG		0x1378
-#define RT2860_EXP_CTS_TIME		0x137c
-#define RT2860_EXP_ACK_TIME		0x1380
+#define	RT2860_EDCA_AC_CFG(aci)		(0x1300 + (aci) * 4)
+#define	RT2860_EDCA_TID_AC_MAP		0x1310
+#define	RT2860_TX_PWR_CFG(ridx)		(0x1314 + (ridx) * 4)
+#define	RT2860_TX_PIN_CFG		0x1328
+#define	RT2860_TX_BAND_CFG		0x132c
+#define	RT2860_TX_SW_CFG0		0x1330
+#define	RT2860_TX_SW_CFG1		0x1334
+#define	RT2860_TX_SW_CFG2		0x1338
+#define	RT2860_TXOP_THRES_CFG		0x133c
+#define	RT2860_TXOP_CTRL_CFG		0x1340
+#define	RT2860_TX_RTS_CFG		0x1344
+#define	RT2860_TX_TIMEOUT_CFG		0x1348
+#define	RT2860_TX_RTY_CFG		0x134c
+#define	RT2860_TX_LINK_CFG		0x1350
+#define	RT2860_HT_FBK_CFG0		0x1354
+#define	RT2860_HT_FBK_CFG1		0x1358
+#define	RT2860_LG_FBK_CFG0		0x135c
+#define	RT2860_LG_FBK_CFG1		0x1360
+#define	RT2860_CCK_PROT_CFG		0x1364
+#define	RT2860_OFDM_PROT_CFG		0x1368
+#define	RT2860_MM20_PROT_CFG		0x136c
+#define	RT2860_MM40_PROT_CFG		0x1370
+#define	RT2860_GF20_PROT_CFG		0x1374
+#define	RT2860_GF40_PROT_CFG		0x1378
+#define	RT2860_EXP_CTS_TIME		0x137c
+#define	RT2860_EXP_ACK_TIME		0x1380
 
 /* MAC RX configuration registers */
-#define RT2860_RX_FILTR_CFG		0x1400
-#define RT2860_AUTO_RSP_CFG		0x1404
-#define RT2860_LEGACY_BASIC_RATE	0x1408
-#define RT2860_HT_BASIC_RATE		0x140c
-#define RT2860_HT_CTRL_CFG		0x1410
-#define RT2860_SIFS_COST_CFG		0x1414
-#define RT2860_RX_PARSER_CFG		0x1418
+#define	RT2860_RX_FILTR_CFG		0x1400
+#define	RT2860_AUTO_RSP_CFG		0x1404
+#define	RT2860_LEGACY_BASIC_RATE	0x1408
+#define	RT2860_HT_BASIC_RATE		0x140c
+#define	RT2860_HT_CTRL_CFG		0x1410
+#define	RT2860_SIFS_COST_CFG		0x1414
+#define	RT2860_RX_PARSER_CFG		0x1418
 
 /* MAC Security configuration registers */
-#define RT2860_TX_SEC_CNT0		0x1500
-#define RT2860_RX_SEC_CNT0		0x1504
-#define RT2860_CCMP_FC_MUTE		0x1508
+#define	RT2860_TX_SEC_CNT0		0x1500
+#define	RT2860_RX_SEC_CNT0		0x1504
+#define	RT2860_CCMP_FC_MUTE		0x1508
 
 /* MAC HCCA/PSMP configuration registers */
-#define RT2860_TXOP_HLDR_ADDR0		0x1600
-#define RT2860_TXOP_HLDR_ADDR1		0x1604
-#define RT2860_TXOP_HLDR_ET		0x1608
-#define RT2860_QOS_CFPOLL_RA_DW0	0x160c
-#define RT2860_QOS_CFPOLL_A1_DW1	0x1610
-#define RT2860_QOS_CFPOLL_QC		0x1614
+#define	RT2860_TXOP_HLDR_ADDR0		0x1600
+#define	RT2860_TXOP_HLDR_ADDR1		0x1604
+#define	RT2860_TXOP_HLDR_ET		0x1608
+#define	RT2860_QOS_CFPOLL_RA_DW0	0x160c
+#define	RT2860_QOS_CFPOLL_A1_DW1	0x1610
+#define	RT2860_QOS_CFPOLL_QC		0x1614
 
 /* MAC Statistics Counters */
-#define RT2860_RX_STA_CNT0		0x1700
-#define RT2860_RX_STA_CNT1		0x1704
-#define RT2860_RX_STA_CNT2		0x1708
-#define RT2860_TX_STA_CNT0		0x170c
-#define RT2860_TX_STA_CNT1		0x1710
-#define RT2860_TX_STA_CNT2		0x1714
-#define RT2860_TX_STAT_FIFO		0x1718
+#define	RT2860_RX_STA_CNT0		0x1700
+#define	RT2860_RX_STA_CNT1		0x1704
+#define	RT2860_RX_STA_CNT2		0x1708
+#define	RT2860_TX_STA_CNT0		0x170c
+#define	RT2860_TX_STA_CNT1		0x1710
+#define	RT2860_TX_STA_CNT2		0x1714
+#define	RT2860_TX_STAT_FIFO		0x1718
 
 /* RX WCID search table */
-#define RT2860_WCID_ENTRY(wcid)		(0x1800 + (wcid) * 8)
+#define	RT2860_WCID_ENTRY(wcid)		(0x1800 + (wcid) * 8)
 
-#define RT2860_FW_BASE			0x2000
-#define RT2870_FW_BASE			0x3000
+#define	RT2860_FW_BASE			0x2000
+#define	RT2870_FW_BASE			0x3000
 
 /* Pair-wise key table */
-#define RT2860_PKEY(wcid)		(0x4000 + (wcid) * 32)
+#define	RT2860_PKEY(wcid)		(0x4000 + (wcid) * 32)
 
 /* IV/EIV table */
-#define RT2860_IVEIV(wcid)		(0x6000 + (wcid) * 8)
+#define	RT2860_IVEIV(wcid)		(0x6000 + (wcid) * 8)
 
 /* WCID attribute table */
-#define RT2860_WCID_ATTR(wcid)		(0x6800 + (wcid) * 4)
+#define	RT2860_WCID_ATTR(wcid)		(0x6800 + (wcid) * 4)
 
 /* Shared Key Table */
-#define RT2860_SKEY(vap, kidx)		(0x6c00 + (vap) * 128 + (kidx) * 32)
+#define	RT2860_SKEY(vap, kidx)		(0x6c00 + (vap) * 128 + (kidx) * 32)
 
 /* Shared Key Mode */
-#define RT2860_SKEY_MODE_0_7		0x7000
-#define RT2860_SKEY_MODE_8_15		0x7004
-#define RT2860_SKEY_MODE_16_23		0x7008
-#define RT2860_SKEY_MODE_24_31		0x700c
+#define	RT2860_SKEY_MODE_0_7		0x7000
+#define	RT2860_SKEY_MODE_8_15		0x7004
+#define	RT2860_SKEY_MODE_16_23		0x7008
+#define	RT2860_SKEY_MODE_24_31		0x700c
 
 /* Shared Memory between MCU and host */
-#define RT2860_H2M_MAILBOX		0x7010
-#define RT2860_H2M_MAILBOX_CID		0x7014
-#define RT2860_H2M_MAILBOX_STATUS	0x701c
-#define RT2860_H2M_BBPAGENT		0x7028
-#define RT2860_BCN_BASE(vap)		(0x7800 + (vap) * 512)
+#define	RT2860_H2M_MAILBOX		0x7010
+#define	RT2860_H2M_MAILBOX_CID		0x7014
+#define	RT2860_H2M_MAILBOX_STATUS	0x701c
+#define	RT2860_H2M_INTSRC		0x7024
+#define	RT2860_H2M_BBPAGENT		0x7028
+#define	RT2860_BCN_BASE(vap)		(0x7800 + (vap) * 512)
 
 
 /* possible flags for register RT2860_PCI_EECTRL */
-#define RT2860_C	(1 << 0)
-#define RT2860_S	(1 << 1)
-#define RT2860_D	(1 << 2)
-#define RT2860_SHIFT_D	2
-#define RT2860_Q	(1 << 3)
-#define RT2860_SHIFT_Q	3
+#define	RT2860_C	(1 << 0)
+#define	RT2860_S	(1 << 1)
+#define	RT2860_D	(1 << 2)
+#define	RT2860_SHIFT_D	2
+#define	RT2860_Q	(1 << 3)
+#define	RT2860_SHIFT_Q	3
 
 /* possible flags for registers INT_STATUS/INT_MASK */
-#define RT2860_TX_COHERENT	(1 << 17)
-#define RT2860_RX_COHERENT	(1 << 16)
-#define RT2860_MAC_INT_4	(1 << 15)
-#define RT2860_MAC_INT_3	(1 << 14)
-#define RT2860_MAC_INT_2	(1 << 13)
-#define RT2860_MAC_INT_1	(1 << 12)
-#define RT2860_MAC_INT_0	(1 << 11)
-#define RT2860_TX_RX_COHERENT	(1 << 10)
-#define RT2860_MCU_CMD_INT	(1 <<  9)
-#define RT2860_TX_DONE_INT5	(1 <<  8)
-#define RT2860_TX_DONE_INT4	(1 <<  7)
-#define RT2860_TX_DONE_INT3	(1 <<  6)
-#define RT2860_TX_DONE_INT2	(1 <<  5)
-#define RT2860_TX_DONE_INT1	(1 <<  4)
-#define RT2860_TX_DONE_INT0	(1 <<  3)
-#define RT2860_RX_DONE_INT	(1 <<  2)
-#define RT2860_TX_DLY_INT	(1 <<  1)
-#define RT2860_RX_DLY_INT	(1 <<  0)
+#define	RT2860_TX_COHERENT	(1 << 17)
+#define	RT2860_RX_COHERENT	(1 << 16)
+#define	RT2860_MAC_INT_4	(1 << 15)
+#define	RT2860_MAC_INT_3	(1 << 14)
+#define	RT2860_MAC_INT_2	(1 << 13)
+#define	RT2860_MAC_INT_1	(1 << 12)
+#define	RT2860_MAC_INT_0	(1 << 11)
+#define	RT2860_TX_RX_COHERENT	(1 << 10)
+#define	RT2860_MCU_CMD_INT	(1 <<  9)
+#define	RT2860_TX_DONE_INT5	(1 <<  8)
+#define	RT2860_TX_DONE_INT4	(1 <<  7)
+#define	RT2860_TX_DONE_INT3	(1 <<  6)
+#define	RT2860_TX_DONE_INT2	(1 <<  5)
+#define	RT2860_TX_DONE_INT1	(1 <<  4)
+#define	RT2860_TX_DONE_INT0	(1 <<  3)
+#define	RT2860_RX_DONE_INT	(1 <<  2)
+#define	RT2860_TX_DLY_INT	(1 <<  1)
+#define	RT2860_RX_DLY_INT	(1 <<  0)
 
 /* possible flags for register WPDMA_GLO_CFG */
-#define RT2860_HDR_SEG_LEN_SHIFT	8
-#define RT2860_BIG_ENDIAN		(1 << 7)
-#define RT2860_TX_WB_DDONE		(1 << 6)
-#define RT2860_WPDMA_BT_SIZE_SHIFT	4
-#define RT2860_WPDMA_BT_SIZE16		0
-#define RT2860_WPDMA_BT_SIZE32		1
-#define RT2860_WPDMA_BT_SIZE64		2
-#define RT2860_WPDMA_BT_SIZE128		3
-#define RT2860_RX_DMA_BUSY		(1 << 3)
-#define RT2860_RX_DMA_EN		(1 << 2)
-#define RT2860_TX_DMA_BUSY		(1 << 1)
-#define RT2860_TX_DMA_EN		(1 << 0)
+#define	RT2860_HDR_SEG_LEN_SHIFT	8
+#define	RT2860_BIG_ENDIAN		(1 << 7)
+#define	RT2860_TX_WB_DDONE		(1 << 6)
+#define	RT2860_WPDMA_BT_SIZE_SHIFT	4
+#define	RT2860_WPDMA_BT_SIZE16		0
+#define	RT2860_WPDMA_BT_SIZE32		1
+#define	RT2860_WPDMA_BT_SIZE64		2
+#define	RT2860_WPDMA_BT_SIZE128		3
+#define	RT2860_RX_DMA_BUSY		(1 << 3)
+#define	RT2860_RX_DMA_EN		(1 << 2)
+#define	RT2860_TX_DMA_BUSY		(1 << 1)
+#define	RT2860_TX_DMA_EN		(1 << 0)
 
 /* possible flags for register DELAY_INT_CFG */
-#define RT2860_TXDLY_INT_EN		(1 << 31)
-#define RT2860_TXMAX_PINT_SHIFT		24
-#define RT2860_TXMAX_PTIME_SHIFT	16
-#define RT2860_RXDLY_INT_EN		(1 << 15)
-#define RT2860_RXMAX_PINT_SHIFT		8
-#define RT2860_RXMAX_PTIME_SHIFT	0
+#define	RT2860_TXDLY_INT_EN		(1U << 31)
+#define	RT2860_TXMAX_PINT_SHIFT		24
+#define	RT2860_TXMAX_PTIME_SHIFT	16
+#define	RT2860_RXDLY_INT_EN		(1 << 15)
+#define	RT2860_RXMAX_PINT_SHIFT		8
+#define	RT2860_RXMAX_PTIME_SHIFT	0
 
 /* possible flags for register GPIO_CTRL */
-#define RT2860_GPIO_D_SHIFT	8
-#define RT2860_GPIO_O_SHIFT	0
+#define	RT2860_GPIO_D_SHIFT	8
+#define	RT2860_GPIO_O_SHIFT	0
 
 /* possible flags for register USB_DMA_CFG */
-#define RT2860_USB_TX_BUSY		(1 << 31)
-#define RT2860_USB_RX_BUSY		(1 << 30)
-#define RT2860_USB_EPOUT_VLD_SHIFT	24
-#define RT2860_USB_TX_EN		(1 << 23)
-#define RT2860_USB_RX_EN		(1 << 22)
-#define RT2860_USB_RX_AGG_EN		(1 << 21)
-#define RT2860_USB_TXOP_HALT		(1 << 20)
-#define RT2860_USB_TX_CLEAR		(1 << 19)
-#define RT2860_USB_PHY_WD_EN		(1 << 16)
-#define RT2860_USB_PHY_MAN_RST		(1 << 15)
-#define RT2860_USB_RX_AGG_LMT(x)	((x) << 8)	/* in unit of 1KB */
-#define RT2860_USB_RX_AGG_TO(x)		((x) & 0xff)	/* in unit of 33ns */
+#define	RT2860_USB_TX_BUSY		(1U << 31)
+#define	RT2860_USB_RX_BUSY		(1 << 30)
+#define	RT2860_USB_EPOUT_VLD_SHIFT	24
+#define	RT2860_USB_TX_EN		(1 << 23)
+#define	RT2860_USB_RX_EN		(1 << 22)
+#define	RT2860_USB_RX_AGG_EN		(1 << 21)
+#define	RT2860_USB_TXOP_HALT		(1 << 20)
+#define	RT2860_USB_TX_CLEAR		(1 << 19)
+#define	RT2860_USB_PHY_WD_EN		(1 << 16)
+#define	RT2860_USB_PHY_MAN_RST		(1 << 15)
+#define	RT2860_USB_RX_AGG_LMT(x)	((x) << 8)	/* in unit of 1KB */
+#define	RT2860_USB_RX_AGG_TO(x)		((x) & 0xff)	/* in unit of 33ns */
 
 /* possible flags for register US_CYC_CNT */
-#define RT2860_TEST_EN		(1 << 24)
-#define RT2860_TEST_SEL_SHIFT	16
-#define RT2860_BT_MODE_EN	(1 <<  8)
-#define RT2860_US_CYC_CNT_SHIFT	0
+#define	RT2860_TEST_EN		(1 << 24)
+#define	RT2860_TEST_SEL_SHIFT	16
+#define	RT2860_BT_MODE_EN	(1 <<  8)
+#define	RT2860_US_CYC_CNT_SHIFT	0
 
 /* possible flags for register SYS_CTRL */
-#define RT2860_HST_PM_SEL	(1 << 16)
-#define RT2860_CAP_MODE		(1 << 14)
-#define RT2860_PME_OEN		(1 << 13)
-#define RT2860_CLKSELECT	(1 << 12)
-#define RT2860_PBF_CLK_EN	(1 << 11)
-#define RT2860_MAC_CLK_EN	(1 << 10)
-#define RT2860_DMA_CLK_EN	(1 <<  9)
-#define RT2860_MCU_READY	(1 <<  7)
-#define RT2860_ASY_RESET	(1 <<  4)
-#define RT2860_PBF_RESET	(1 <<  3)
-#define RT2860_MAC_RESET	(1 <<  2)
-#define RT2860_DMA_RESET	(1 <<  1)
-#define RT2860_MCU_RESET	(1 <<  0)
+#define	RT2860_HST_PM_SEL	(1 << 16)
+#define	RT2860_CAP_MODE		(1 << 14)
+#define	RT2860_PME_OEN		(1 << 13)
+#define	RT2860_CLKSELECT	(1 << 12)
+#define	RT2860_PBF_CLK_EN	(1 << 11)
+#define	RT2860_MAC_CLK_EN	(1 << 10)
+#define	RT2860_DMA_CLK_EN	(1 <<  9)
+#define	RT2860_MCU_READY	(1 <<  7)
+#define	RT2860_ASY_RESET	(1 <<  4)
+#define	RT2860_PBF_RESET	(1 <<  3)
+#define	RT2860_MAC_RESET	(1 <<  2)
+#define	RT2860_DMA_RESET	(1 <<  1)
+#define	RT2860_MCU_RESET	(1 <<  0)
 
 /* possible values for register HOST_CMD */
-#define RT2860_MCU_CMD_SLEEP	0x30
-#define RT2860_MCU_CMD_WAKEUP	0x31
-#define RT2860_MCU_CMD_LEDS	0x50
-#define RT2860_MCU_CMD_LED_RSSI	0x51
-#define RT2860_MCU_CMD_LED1	0x52
-#define RT2860_MCU_CMD_LED2	0x53
-#define RT2860_MCU_CMD_LED3	0x54
-#define RT2860_MCU_CMD_RFRESET	0x72
-#define RT2860_MCU_CMD_ANTSEL	0x73
-#define RT2860_MCU_CMD_BBP	0x80
-#define RT2860_MCU_CMD_PSLEVEL	0x83
+#define	RT2860_MCU_CMD_SLEEP	0x30
+#define	RT2860_MCU_CMD_WAKEUP	0x31
+#define	RT2860_MCU_CMD_LEDS	0x50
+#define	RT2860_MCU_CMD_LED_RSSI	0x51
+#define	RT2860_MCU_CMD_LED1	0x52
+#define	RT2860_MCU_CMD_LED2	0x53
+#define	RT2860_MCU_CMD_LED3	0x54
+#define	RT2860_MCU_CMD_RFRESET	0x72
+#define	RT2860_MCU_CMD_ANTSEL	0x73
+#define	RT2860_MCU_CMD_BBP	0x80
+#define	RT2860_MCU_CMD_PSLEVEL	0x83
 
 /* possible flags for register PBF_CFG */
-#define RT2860_TX1Q_NUM_SHIFT	21
-#define RT2860_TX2Q_NUM_SHIFT	16
-#define RT2860_NULL0_MODE	(1 << 15)
-#define RT2860_NULL1_MODE	(1 << 14)
-#define RT2860_RX_DROP_MODE	(1 << 13)
-#define RT2860_TX0Q_MANUAL	(1 << 12)
-#define RT2860_TX1Q_MANUAL	(1 << 11)
-#define RT2860_TX2Q_MANUAL	(1 << 10)
-#define RT2860_RX0Q_MANUAL	(1 <<  9)
-#define RT2860_HCCA_EN		(1 <<  8)
-#define RT2860_TX0Q_EN		(1 <<  4)
-#define RT2860_TX1Q_EN		(1 <<  3)
-#define RT2860_TX2Q_EN		(1 <<  2)
-#define RT2860_RX0Q_EN		(1 <<  1)
+#define	RT2860_TX1Q_NUM_SHIFT	21
+#define	RT2860_TX2Q_NUM_SHIFT	16
+#define	RT2860_NULL0_MODE	(1 << 15)
+#define	RT2860_NULL1_MODE	(1 << 14)
+#define	RT2860_RX_DROP_MODE	(1 << 13)
+#define	RT2860_TX0Q_MANUAL	(1 << 12)
+#define	RT2860_TX1Q_MANUAL	(1 << 11)
+#define	RT2860_TX2Q_MANUAL	(1 << 10)
+#define	RT2860_RX0Q_MANUAL	(1 <<  9)
+#define	RT2860_HCCA_EN		(1 <<  8)
+#define	RT2860_TX0Q_EN		(1 <<  4)
+#define	RT2860_TX1Q_EN		(1 <<  3)
+#define	RT2860_TX2Q_EN		(1 <<  2)
+#define	RT2860_RX0Q_EN		(1 <<  1)
 
 /* possible flags for register BUF_CTRL */
-#define RT2860_WRITE_TXQ(qid)	(1 << (11 - (qid)))
-#define RT2860_NULL0_KICK	(1 << 7)
-#define RT2860_NULL1_KICK	(1 << 6)
-#define RT2860_BUF_RESET	(1 << 5)
-#define RT2860_READ_TXQ(qid)	(1 << (3 - (qid))
-#define RT2860_READ_RX0Q	(1 << 0)
+#define	RT2860_WRITE_TXQ(qid)	(1 << (11 - (qid)))
+#define	RT2860_NULL0_KICK	(1 << 7)
+#define	RT2860_NULL1_KICK	(1 << 6)
+#define	RT2860_BUF_RESET	(1 << 5)
+#define	RT2860_READ_TXQ(qid)	(1 << (3 - (qid))
+#define	RT2860_READ_RX0Q	(1 << 0)
 
 /* possible flags for registers MCU_INT_STA/MCU_INT_ENA */
-#define RT2860_MCU_MAC_INT_8	(1 << 24)
-#define RT2860_MCU_MAC_INT_7	(1 << 23)
-#define RT2860_MCU_MAC_INT_6	(1 << 22)
-#define RT2860_MCU_MAC_INT_4	(1 << 20)
-#define RT2860_MCU_MAC_INT_3	(1 << 19)
-#define RT2860_MCU_MAC_INT_2	(1 << 18)
-#define RT2860_MCU_MAC_INT_1	(1 << 17)
-#define RT2860_MCU_MAC_INT_0	(1 << 16)
-#define RT2860_DTX0_INT		(1 << 11)
-#define RT2860_DTX1_INT		(1 << 10)
-#define RT2860_DTX2_INT		(1 <<  9)
-#define RT2860_DRX0_INT		(1 <<  8)
-#define RT2860_HCMD_INT		(1 <<  7)
-#define RT2860_N0TX_INT		(1 <<  6)
-#define RT2860_N1TX_INT		(1 <<  5)
-#define RT2860_BCNTX_INT	(1 <<  4)
-#define RT2860_MTX0_INT		(1 <<  3)
-#define RT2860_MTX1_INT		(1 <<  2)
-#define RT2860_MTX2_INT		(1 <<  1)
-#define RT2860_MRX0_INT		(1 <<  0)
+#define	RT2860_MCU_MAC_INT_8	(1 << 24)
+#define	RT2860_MCU_MAC_INT_7	(1 << 23)
+#define	RT2860_MCU_MAC_INT_6	(1 << 22)
+#define	RT2860_MCU_MAC_INT_4	(1 << 20)
+#define	RT2860_MCU_MAC_INT_3	(1 << 19)
+#define	RT2860_MCU_MAC_INT_2	(1 << 18)
+#define	RT2860_MCU_MAC_INT_1	(1 << 17)
+#define	RT2860_MCU_MAC_INT_0	(1 << 16)
+#define	RT2860_DTX0_INT		(1 << 11)
+#define	RT2860_DTX1_INT		(1 << 10)
+#define	RT2860_DTX2_INT		(1 <<  9)
+#define	RT2860_DRX0_INT		(1 <<  8)
+#define	RT2860_HCMD_INT		(1 <<  7)
+#define	RT2860_N0TX_INT		(1 <<  6)
+#define	RT2860_N1TX_INT		(1 <<  5)
+#define	RT2860_BCNTX_INT	(1 <<  4)
+#define	RT2860_MTX0_INT		(1 <<  3)
+#define	RT2860_MTX1_INT		(1 <<  2)
+#define	RT2860_MTX2_INT		(1 <<  1)
+#define	RT2860_MRX0_INT		(1 <<  0)
 
 /* possible flags for register TXRXQ_PCNT */
-#define RT2860_RX0Q_PCNT_MASK	0xff000000
-#define RT2860_TX2Q_PCNT_MASK	0x00ff0000
-#define RT2860_TX1Q_PCNT_MASK	0x0000ff00
-#define RT2860_TX0Q_PCNT_MASK	0x000000ff
+#define	RT2860_RX0Q_PCNT_MASK	0xff000000
+#define	RT2860_TX2Q_PCNT_MASK	0x00ff0000
+#define	RT2860_TX1Q_PCNT_MASK	0x0000ff00
+#define	RT2860_TX0Q_PCNT_MASK	0x000000ff
 
 /* possible flags for register CAP_CTRL */
-#define RT2860_CAP_ADC_FEQ		(1 << 31)
-#define RT2860_CAP_START		(1 << 30)
-#define RT2860_MAN_TRIG			(1 << 29)
-#define RT2860_TRIG_OFFSET_SHIFT	16
-#define RT2860_START_ADDR_SHIFT		0
+#define	RT2860_CAP_ADC_FEQ		(1U << 31)
+#define	RT2860_CAP_START		(1 << 30)
+#define	RT2860_MAN_TRIG			(1 << 29)
+#define	RT2860_TRIG_OFFSET_SHIFT	16
+#define	RT2860_START_ADDR_SHIFT		0
 
 /* possible flags for register RF_CSR_CFG */
-#define RT3070_RF_KICK		(1 << 17)
-#define RT3070_RF_WRITE		(1 << 16)
+#define	RT3070_RF_KICK		(1 << 17)
+#define	RT3070_RF_WRITE		(1 << 16)
 
 /* possible flags for register EFUSE_CTRL */
-#define RT3070_SEL_EFUSE	(1 << 31)
-#define RT3070_EFSROM_KICK	(1 << 30)
-#define RT3070_EFSROM_AIN_MASK	0x03ff0000
-#define RT3070_EFSROM_AIN_SHIFT	16
-#define RT3070_EFSROM_MODE_MASK	0x000000c0
-#define RT3070_EFUSE_AOUT_MASK	0x0000003f
+#define	RT3070_SEL_EFUSE	(1U << 31)
+#define	RT3070_EFSROM_KICK	(1 << 30)
+#define	RT3070_EFSROM_AIN_MASK	0x03ff0000
+#define	RT3070_EFSROM_AIN_SHIFT	16
+#define	RT3070_EFSROM_MODE_MASK	0x000000c0
+#define	RT3070_EFUSE_AOUT_MASK	0x0000003f
+
+/* possible flag for register DEBUG_INDEX */
+#define	RT5592_SEL_XTAL		(1U << 31)
 
 /* possible flags for register MAC_SYS_CTRL */
-#define RT2860_RX_TS_EN		(1 << 7)
-#define RT2860_WLAN_HALT_EN	(1 << 6)
-#define RT2860_PBF_LOOP_EN	(1 << 5)
-#define RT2860_CONT_TX_TEST	(1 << 4)
-#define RT2860_MAC_RX_EN	(1 << 3)
-#define RT2860_MAC_TX_EN	(1 << 2)
-#define RT2860_BBP_HRST		(1 << 1)
-#define RT2860_MAC_SRST		(1 << 0)
+#define	RT2860_RX_TS_EN		(1 << 7)
+#define	RT2860_WLAN_HALT_EN	(1 << 6)
+#define	RT2860_PBF_LOOP_EN	(1 << 5)
+#define	RT2860_CONT_TX_TEST	(1 << 4)
+#define	RT2860_MAC_RX_EN	(1 << 3)
+#define	RT2860_MAC_TX_EN	(1 << 2)
+#define	RT2860_BBP_HRST		(1 << 1)
+#define	RT2860_MAC_SRST		(1 << 0)
 
 /* possible flags for register MAC_BSSID_DW1 */
-#define RT2860_MULTI_BCN_NUM_SHIFT	18
-#define RT2860_MULTI_BSSID_MODE_SHIFT	16
+#define	RT2860_MULTI_BCN_NUM_SHIFT	18
+#define	RT2860_MULTI_BSSID_MODE_SHIFT	16
 
 /* possible flags for register MAX_LEN_CFG */
-#define RT2860_MIN_MPDU_LEN_SHIFT	16
-#define RT2860_MAX_PSDU_LEN_SHIFT	12
-#define RT2860_MAX_PSDU_LEN8K		0
-#define RT2860_MAX_PSDU_LEN16K		1
-#define RT2860_MAX_PSDU_LEN32K		2
-#define RT2860_MAX_PSDU_LEN64K		3
-#define RT2860_MAX_MPDU_LEN_SHIFT	0
+#define	RT2860_MIN_MPDU_LEN_SHIFT	16
+#define	RT2860_MAX_PSDU_LEN_SHIFT	12
+#define	RT2860_MAX_PSDU_LEN8K		0
+#define	RT2860_MAX_PSDU_LEN16K		1
+#define	RT2860_MAX_PSDU_LEN32K		2
+#define	RT2860_MAX_PSDU_LEN64K		3
+#define	RT2860_MAX_MPDU_LEN_SHIFT	0
 
 /* possible flags for registers BBP_CSR_CFG/H2M_BBPAGENT */
-#define RT2860_BBP_RW_PARALLEL		(1 << 19)
-#define RT2860_BBP_PAR_DUR_112_5	(1 << 18)
-#define RT2860_BBP_CSR_KICK		(1 << 17)
-#define RT2860_BBP_CSR_READ		(1 << 16)
-#define RT2860_BBP_ADDR_SHIFT		8
-#define RT2860_BBP_DATA_SHIFT		0
+#define	RT2860_BBP_RW_PARALLEL		(1 << 19)
+#define	RT2860_BBP_PAR_DUR_112_5	(1 << 18)
+#define	RT2860_BBP_CSR_KICK		(1 << 17)
+#define	RT2860_BBP_CSR_READ		(1 << 16)
+#define	RT2860_BBP_ADDR_SHIFT		8
+#define	RT2860_BBP_DATA_SHIFT		0
 
 /* possible flags for register RF_CSR_CFG0 */
-#define RT2860_RF_REG_CTRL		(1 << 31)
-#define RT2860_RF_LE_SEL1		(1 << 30)
-#define RT2860_RF_LE_STBY		(1 << 29)
-#define RT2860_RF_REG_WIDTH_SHIFT	24
-#define RT2860_RF_REG_0_SHIFT		0
+#define	RT2860_RF_REG_CTRL		(1U << 31)
+#define	RT2860_RF_LE_SEL1		(1 << 30)
+#define	RT2860_RF_LE_STBY		(1 << 29)
+#define	RT2860_RF_REG_WIDTH_SHIFT	24
+#define	RT2860_RF_REG_0_SHIFT		0
 
 /* possible flags for register RF_CSR_CFG1 */
-#define RT2860_RF_DUR_5		(1 << 24)
-#define RT2860_RF_REG_1_SHIFT	0
+#define	RT2860_RF_DUR_5		(1 << 24)
+#define	RT2860_RF_REG_1_SHIFT	0
 
 /* possible flags for register LED_CFG */
-#define RT2860_LED_POL			(1 << 30)
-#define RT2860_Y_LED_MODE_SHIFT		28
-#define RT2860_G_LED_MODE_SHIFT		26
-#define RT2860_R_LED_MODE_SHIFT		24
-#define RT2860_LED_MODE_OFF		0
-#define RT2860_LED_MODE_BLINK_TX	1
-#define RT2860_LED_MODE_SLOW_BLINK	2
-#define RT2860_LED_MODE_ON		3
-#define RT2860_SLOW_BLK_TIME_SHIFT	16
-#define RT2860_LED_OFF_TIME_SHIFT	8
-#define RT2860_LED_ON_TIME_SHIFT	0
+#define	RT2860_LED_POL			(1 << 30)
+#define	RT2860_Y_LED_MODE_SHIFT		28
+#define	RT2860_G_LED_MODE_SHIFT		26
+#define	RT2860_R_LED_MODE_SHIFT		24
+#define	RT2860_LED_MODE_OFF		0
+#define	RT2860_LED_MODE_BLINK_TX	1
+#define	RT2860_LED_MODE_SLOW_BLINK	2
+#define	RT2860_LED_MODE_ON		3
+#define	RT2860_SLOW_BLK_TIME_SHIFT	16
+#define	RT2860_LED_OFF_TIME_SHIFT	8
+#define	RT2860_LED_ON_TIME_SHIFT	0
 
 /* possible flags for register XIFS_TIME_CFG */
-#define RT2860_BB_RXEND_EN		(1 << 29)
-#define RT2860_EIFS_TIME_SHIFT		20
-#define RT2860_OFDM_XIFS_TIME_SHIFT	16
-#define RT2860_OFDM_SIFS_TIME_SHIFT	8
-#define RT2860_CCK_SIFS_TIME_SHIFT	0
+#define	RT2860_BB_RXEND_EN		(1 << 29)
+#define	RT2860_EIFS_TIME_SHIFT		20
+#define	RT2860_OFDM_XIFS_TIME_SHIFT	16
+#define	RT2860_OFDM_SIFS_TIME_SHIFT	8
+#define	RT2860_CCK_SIFS_TIME_SHIFT	0
 
 /* possible flags for register BKOFF_SLOT_CFG */
-#define RT2860_CC_DELAY_TIME_SHIFT	8
-#define RT2860_SLOT_TIME		0
+#define	RT2860_CC_DELAY_TIME_SHIFT	8
+#define	RT2860_SLOT_TIME		0
 
 /* possible flags for register NAV_TIME_CFG */
-#define RT2860_NAV_UPD			(1 << 31)
-#define RT2860_NAV_UPD_VAL_SHIFT	16
-#define RT2860_NAV_CLR_EN		(1 << 15)
-#define RT2860_NAV_TIMER_SHIFT		0
+#define	RT2860_NAV_UPD			(1U << 31)
+#define	RT2860_NAV_UPD_VAL_SHIFT	16
+#define	RT2860_NAV_CLR_EN		(1 << 15)
+#define	RT2860_NAV_TIMER_SHIFT		0
 
 /* possible flags for register CH_TIME_CFG */
-#define RT2860_EIFS_AS_CH_BUSY	(1 << 4)
-#define RT2860_NAV_AS_CH_BUSY	(1 << 3)
-#define RT2860_RX_AS_CH_BUSY	(1 << 2)
-#define RT2860_TX_AS_CH_BUSY	(1 << 1)
-#define RT2860_CH_STA_TIMER_EN	(1 << 0)
+#define	RT2860_EIFS_AS_CH_BUSY	(1 << 4)
+#define	RT2860_NAV_AS_CH_BUSY	(1 << 3)
+#define	RT2860_RX_AS_CH_BUSY	(1 << 2)
+#define	RT2860_TX_AS_CH_BUSY	(1 << 1)
+#define	RT2860_CH_STA_TIMER_EN	(1 << 0)
 
 /* possible values for register BCN_TIME_CFG */
-#define RT2860_TSF_INS_COMP_SHIFT	24
-#define RT2860_BCN_TX_EN		(1 << 20)
-#define RT2860_TBTT_TIMER_EN		(1 << 19)
-#define RT2860_TSF_SYNC_MODE_SHIFT	17
-#define RT2860_TSF_SYNC_MODE_DIS	0
-#define RT2860_TSF_SYNC_MODE_STA	1
-#define RT2860_TSF_SYNC_MODE_IBSS	2
-#define RT2860_TSF_SYNC_MODE_HOSTAP	3
-#define RT2860_TSF_TIMER_EN		(1 << 16)
-#define RT2860_BCN_INTVAL_SHIFT		0
+#define	RT2860_TSF_INS_COMP_SHIFT	24
+#define	RT2860_BCN_TX_EN		(1 << 20)
+#define	RT2860_TBTT_TIMER_EN		(1 << 19)
+#define	RT2860_TSF_SYNC_MODE_SHIFT	17
+#define	RT2860_TSF_SYNC_MODE_DIS	0
+#define	RT2860_TSF_SYNC_MODE_STA	1
+#define	RT2860_TSF_SYNC_MODE_IBSS	2
+#define	RT2860_TSF_SYNC_MODE_HOSTAP	3
+#define	RT2860_TSF_TIMER_EN		(1 << 16)
+#define	RT2860_BCN_INTVAL_SHIFT		0
 
 /* possible flags for register TBTT_SYNC_CFG */
-#define RT2860_BCN_CWMIN_SHIFT		20
-#define RT2860_BCN_AIFSN_SHIFT		16
-#define RT2860_BCN_EXP_WIN_SHIFT	8
-#define RT2860_TBTT_ADJUST_SHIFT	0
+#define	RT2860_BCN_CWMIN_SHIFT		20
+#define	RT2860_BCN_AIFSN_SHIFT		16
+#define	RT2860_BCN_EXP_WIN_SHIFT	8
+#define	RT2860_TBTT_ADJUST_SHIFT	0
 
 /* possible flags for register INT_TIMER_CFG */
-#define RT2860_GP_TIMER_SHIFT		16
-#define RT2860_PRE_TBTT_TIMER_SHIFT	0
+#define	RT2860_GP_TIMER_SHIFT		16
+#define	RT2860_PRE_TBTT_TIMER_SHIFT	0
 
 /* possible flags for register INT_TIMER_EN */
-#define RT2860_GP_TIMER_EN	(1 << 1)
-#define RT2860_PRE_TBTT_INT_EN	(1 << 0)
+#define	RT2860_GP_TIMER_EN	(1 << 1)
+#define	RT2860_PRE_TBTT_INT_EN	(1 << 0)
 
 /* possible flags for register MAC_STATUS_REG */
-#define RT2860_RX_STATUS_BUSY	(1 << 1)
-#define RT2860_TX_STATUS_BUSY	(1 << 0)
+#define	RT2860_RX_STATUS_BUSY	(1 << 1)
+#define	RT2860_TX_STATUS_BUSY	(1 << 0)
 
 /* possible flags for register PWR_PIN_CFG */
-#define RT2860_IO_ADDA_PD	(1 << 3)
-#define RT2860_IO_PLL_PD	(1 << 2)
-#define RT2860_IO_RA_PE		(1 << 1)
-#define RT2860_IO_RF_PE		(1 << 0)
+#define	RT2860_IO_ADDA_PD	(1 << 3)
+#define	RT2860_IO_PLL_PD	(1 << 2)
+#define	RT2860_IO_RA_PE		(1 << 1)
+#define	RT2860_IO_RF_PE		(1 << 0)
 
 /* possible flags for register AUTO_WAKEUP_CFG */
-#define RT2860_AUTO_WAKEUP_EN		(1 << 15)
-#define RT2860_SLEEP_TBTT_NUM_SHIFT	8
-#define RT2860_WAKEUP_LEAD_TIME_SHIFT	0
+#define	RT2860_AUTO_WAKEUP_EN		(1 << 15)
+#define	RT2860_SLEEP_TBTT_NUM_SHIFT	8
+#define	RT2860_WAKEUP_LEAD_TIME_SHIFT	0
 
 /* possible flags for register TX_PIN_CFG */
-#define RT2860_TRSW_POL		(1 << 19)
-#define RT2860_TRSW_EN		(1 << 18)
-#define RT2860_RFTR_POL		(1 << 17)
-#define RT2860_RFTR_EN		(1 << 16)
-#define RT2860_LNA_PE_G1_POL	(1 << 15)
-#define RT2860_LNA_PE_A1_POL	(1 << 14)
-#define RT2860_LNA_PE_G0_POL	(1 << 13)
-#define RT2860_LNA_PE_A0_POL	(1 << 12)
-#define RT2860_LNA_PE_G1_EN	(1 << 11)
-#define RT2860_LNA_PE_A1_EN	(1 << 10)
-#define RT2860_LNA_PE1_EN	(RT2860_LNA_PE_A1_EN | RT2860_LNA_PE_G1_EN)
-#define RT2860_LNA_PE_G0_EN	(1 <<  9)
-#define RT2860_LNA_PE_A0_EN	(1 <<  8)
-#define RT2860_LNA_PE0_EN	(RT2860_LNA_PE_A0_EN | RT2860_LNA_PE_G0_EN)
-#define RT2860_PA_PE_G1_POL	(1 <<  7)
-#define RT2860_PA_PE_A1_POL	(1 <<  6)
-#define RT2860_PA_PE_G0_POL	(1 <<  5)
-#define RT2860_PA_PE_A0_POL	(1 <<  4)
-#define RT2860_PA_PE_G1_EN	(1 <<  3)
-#define RT2860_PA_PE_A1_EN	(1 <<  2)
-#define RT2860_PA_PE_G0_EN	(1 <<  1)
-#define RT2860_PA_PE_A0_EN	(1 <<  0)
+#define	RT2860_TRSW_POL		(1 << 19)
+#define	RT2860_TRSW_EN		(1 << 18)
+#define	RT2860_RFTR_POL		(1 << 17)
+#define	RT2860_RFTR_EN		(1 << 16)
+#define	RT2860_LNA_PE_G1_POL	(1 << 15)
+#define	RT2860_LNA_PE_A1_POL	(1 << 14)
+#define	RT2860_LNA_PE_G0_POL	(1 << 13)
+#define	RT2860_LNA_PE_A0_POL	(1 << 12)
+#define	RT2860_LNA_PE_G1_EN	(1 << 11)
+#define	RT2860_LNA_PE_A1_EN	(1 << 10)
+#define	RT2860_LNA_PE1_EN	(RT2860_LNA_PE_A1_EN | RT2860_LNA_PE_G1_EN)
+#define	RT2860_LNA_PE_G0_EN	(1 <<  9)
+#define	RT2860_LNA_PE_A0_EN	(1 <<  8)
+#define	RT2860_LNA_PE0_EN	(RT2860_LNA_PE_A0_EN | RT2860_LNA_PE_G0_EN)
+#define	RT2860_PA_PE_G1_POL	(1 <<  7)
+#define	RT2860_PA_PE_A1_POL	(1 <<  6)
+#define	RT2860_PA_PE_G0_POL	(1 <<  5)
+#define	RT2860_PA_PE_A0_POL	(1 <<  4)
+#define	RT2860_PA_PE_G1_EN	(1 <<  3)
+#define	RT2860_PA_PE_A1_EN	(1 <<  2)
+#define	RT2860_PA_PE_G0_EN	(1 <<  1)
+#define	RT2860_PA_PE_A0_EN	(1 <<  0)
 
 /* possible flags for register TX_BAND_CFG */
-#define RT2860_5G_BAND_SEL_N	(1 << 2)
-#define RT2860_5G_BAND_SEL_P	(1 << 1)
-#define RT2860_TX_BAND_SEL	(1 << 0)
+#define	RT2860_5G_BAND_SEL_N	(1 << 2)
+#define	RT2860_5G_BAND_SEL_P	(1 << 1)
+#define	RT2860_TX_BAND_SEL	(1 << 0)
 
 /* possible flags for register TX_SW_CFG0 */
-#define RT2860_DLY_RFTR_EN_SHIFT	24
-#define RT2860_DLY_TRSW_EN_SHIFT	16
-#define RT2860_DLY_PAPE_EN_SHIFT	8
-#define RT2860_DLY_TXPE_EN_SHIFT	0
+#define	RT2860_DLY_RFTR_EN_SHIFT	24
+#define	RT2860_DLY_TRSW_EN_SHIFT	16
+#define	RT2860_DLY_PAPE_EN_SHIFT	8
+#define	RT2860_DLY_TXPE_EN_SHIFT	0
 
 /* possible flags for register TX_SW_CFG1 */
-#define RT2860_DLY_RFTR_DIS_SHIFT	16
-#define RT2860_DLY_TRSW_DIS_SHIFT	8
-#define RT2860_DLY_PAPE_DIS SHIFT	0
+#define	RT2860_DLY_RFTR_DIS_SHIFT	16
+#define	RT2860_DLY_TRSW_DIS_SHIFT	8
+#define	RT2860_DLY_PAPE_DIS SHIFT	0
 
 /* possible flags for register TX_SW_CFG2 */
-#define RT2860_DLY_LNA_EN_SHIFT		24
-#define RT2860_DLY_LNA_DIS_SHIFT	16
-#define RT2860_DLY_DAC_EN_SHIFT		8
-#define RT2860_DLY_DAC_DIS_SHIFT	0
+#define	RT2860_DLY_LNA_EN_SHIFT		24
+#define	RT2860_DLY_LNA_DIS_SHIFT	16
+#define	RT2860_DLY_DAC_EN_SHIFT		8
+#define	RT2860_DLY_DAC_DIS_SHIFT	0
 
 /* possible flags for register TXOP_THRES_CFG */
-#define RT2860_TXOP_REM_THRES_SHIFT	24
-#define RT2860_CF_END_THRES_SHIFT	16
-#define RT2860_RDG_IN_THRES		8
-#define RT2860_RDG_OUT_THRES		0
+#define	RT2860_TXOP_REM_THRES_SHIFT	24
+#define	RT2860_CF_END_THRES_SHIFT	16
+#define	RT2860_RDG_IN_THRES		8
+#define	RT2860_RDG_OUT_THRES		0
 
 /* possible flags for register TXOP_CTRL_CFG */
-#define RT2860_EXT_CW_MIN_SHIFT		16
-#define RT2860_EXT_CCA_DLY_SHIFT	8
-#define RT2860_EXT_CCA_EN		(1 << 7)
-#define RT2860_LSIG_TXOP_EN		(1 << 6)
-#define RT2860_TXOP_TRUN_EN_MIMOPS	(1 << 4)
-#define RT2860_TXOP_TRUN_EN_TXOP	(1 << 3)
-#define RT2860_TXOP_TRUN_EN_RATE	(1 << 2)
-#define RT2860_TXOP_TRUN_EN_AC		(1 << 1)
-#define RT2860_TXOP_TRUN_EN_TIMEOUT	(1 << 0)
+#define	RT2860_EXT_CW_MIN_SHIFT		16
+#define	RT2860_EXT_CCA_DLY_SHIFT	8
+#define	RT2860_EXT_CCA_EN		(1 << 7)
+#define	RT2860_LSIG_TXOP_EN		(1 << 6)
+#define	RT2860_TXOP_TRUN_EN_MIMOPS	(1 << 4)
+#define	RT2860_TXOP_TRUN_EN_TXOP	(1 << 3)
+#define	RT2860_TXOP_TRUN_EN_RATE	(1 << 2)
+#define	RT2860_TXOP_TRUN_EN_AC		(1 << 1)
+#define	RT2860_TXOP_TRUN_EN_TIMEOUT	(1 << 0)
 
 /* possible flags for register TX_RTS_CFG */
-#define RT2860_RTS_FBK_EN		(1 << 24)
-#define RT2860_RTS_THRES_SHIFT		8
-#define RT2860_RTS_RTY_LIMIT_SHIFT	0
+#define	RT2860_RTS_FBK_EN		(1 << 24)
+#define	RT2860_RTS_THRES_SHIFT		8
+#define	RT2860_RTS_RTY_LIMIT_SHIFT	0
 
 /* possible flags for register TX_TIMEOUT_CFG */
-#define RT2860_TXOP_TIMEOUT_SHIFT	16
-#define RT2860_RX_ACK_TIMEOUT_SHIFT	8
-#define RT2860_MPDU_LIFE_TIME_SHIFT	4
+#define	RT2860_TXOP_TIMEOUT_SHIFT	16
+#define	RT2860_RX_ACK_TIMEOUT_SHIFT	8
+#define	RT2860_MPDU_LIFE_TIME_SHIFT	4
 
 /* possible flags for register TX_RTY_CFG */
-#define RT2860_TX_AUTOFB_EN		(1 << 30)
-#define RT2860_AGG_RTY_MODE_TIMER	(1 << 29)
-#define RT2860_NAG_RTY_MODE_TIMER	(1 << 28)
-#define RT2860_LONG_RTY_THRES_SHIFT	16
-#define RT2860_LONG_RTY_LIMIT_SHIFT	8
-#define RT2860_SHORT_RTY_LIMIT_SHIFT	0
+#define	RT2860_TX_AUTOFB_EN		(1 << 30)
+#define	RT2860_AGG_RTY_MODE_TIMER	(1 << 29)
+#define	RT2860_NAG_RTY_MODE_TIMER	(1 << 28)
+#define	RT2860_LONG_RTY_THRES_SHIFT	16
+#define	RT2860_LONG_RTY_LIMIT_SHIFT	8
+#define	RT2860_SHORT_RTY_LIMIT_SHIFT	0
 
 /* possible flags for register TX_LINK_CFG */
-#define RT2860_REMOTE_MFS_SHIFT		24
-#define RT2860_REMOTE_MFB_SHIFT		16
-#define RT2860_TX_CFACK_EN		(1 << 12)
-#define RT2860_TX_RDG_EN		(1 << 11)
-#define RT2860_TX_MRQ_EN		(1 << 10)
-#define RT2860_REMOTE_UMFS_EN		(1 <<  9)
-#define RT2860_TX_MFB_EN		(1 <<  8)
-#define RT2860_REMOTE_MFB_LT_SHIFT	0
+#define	RT2860_REMOTE_MFS_SHIFT		24
+#define	RT2860_REMOTE_MFB_SHIFT		16
+#define	RT2860_TX_CFACK_EN		(1 << 12)
+#define	RT2860_TX_RDG_EN		(1 << 11)
+#define	RT2860_TX_MRQ_EN		(1 << 10)
+#define	RT2860_REMOTE_UMFS_EN		(1 <<  9)
+#define	RT2860_TX_MFB_EN		(1 <<  8)
+#define	RT2860_REMOTE_MFB_LT_SHIFT	0
 
 /* possible flags for registers *_PROT_CFG */
-#define RT2860_RTSTH_EN			(1 << 26)
-#define RT2860_TXOP_ALLOW_GF40		(1 << 25)
-#define RT2860_TXOP_ALLOW_GF20		(1 << 24)
-#define RT2860_TXOP_ALLOW_MM40		(1 << 23)
-#define RT2860_TXOP_ALLOW_MM20		(1 << 22)
-#define RT2860_TXOP_ALLOW_OFDM		(1 << 21)
-#define RT2860_TXOP_ALLOW_CCK		(1 << 20)
-#define RT2860_TXOP_ALLOW_ALL		(0x3f << 20)
-#define RT2860_PROT_NAV_SHORT		(1 << 18)
-#define RT2860_PROT_NAV_LONG		(2 << 18)
-#define RT2860_PROT_CTRL_RTS_CTS	(1 << 16)
-#define RT2860_PROT_CTRL_CTS		(2 << 16)
+#define	RT2860_RTSTH_EN			(1 << 26)
+#define	RT2860_TXOP_ALLOW_GF40		(1 << 25)
+#define	RT2860_TXOP_ALLOW_GF20		(1 << 24)
+#define	RT2860_TXOP_ALLOW_MM40		(1 << 23)
+#define	RT2860_TXOP_ALLOW_MM20		(1 << 22)
+#define	RT2860_TXOP_ALLOW_OFDM		(1 << 21)
+#define	RT2860_TXOP_ALLOW_CCK		(1 << 20)
+#define	RT2860_TXOP_ALLOW_ALL		(0x3f << 20)
+#define	RT2860_PROT_NAV_SHORT		(1 << 18)
+#define	RT2860_PROT_NAV_LONG		(2 << 18)
+#define	RT2860_PROT_CTRL_RTS_CTS	(1 << 16)
+#define	RT2860_PROT_CTRL_CTS		(2 << 16)
 
 /* possible flags for registers EXP_{CTS,ACK}_TIME */
-#define RT2860_EXP_OFDM_TIME_SHIFT	16
-#define RT2860_EXP_CCK_TIME_SHIFT	0
+#define	RT2860_EXP_OFDM_TIME_SHIFT	16
+#define	RT2860_EXP_CCK_TIME_SHIFT	0
 
 /* possible flags for register RX_FILTR_CFG */
-#define RT2860_DROP_CTRL_RSV	(1 << 16)
-#define RT2860_DROP_BAR		(1 << 15)
-#define RT2860_DROP_BA		(1 << 14)
-#define RT2860_DROP_PSPOLL	(1 << 13)
-#define RT2860_DROP_RTS		(1 << 12)
-#define RT2860_DROP_CTS		(1 << 11)
-#define RT2860_DROP_ACK		(1 << 10)
-#define RT2860_DROP_CFEND	(1 <<  9)
-#define RT2860_DROP_CFACK	(1 <<  8)
-#define RT2860_DROP_DUPL	(1 <<  7)
-#define RT2860_DROP_BC		(1 <<  6)
-#define RT2860_DROP_MC		(1 <<  5)
-#define RT2860_DROP_VER_ERR	(1 <<  4)
-#define RT2860_DROP_NOT_MYBSS	(1 <<  3)
-#define RT2860_DROP_UC_NOME	(1 <<  2)
-#define RT2860_DROP_PHY_ERR	(1 <<  1)
-#define RT2860_DROP_CRC_ERR	(1 <<  0)
+#define	RT2860_DROP_CTRL_RSV	(1 << 16)
+#define	RT2860_DROP_BAR		(1 << 15)
+#define	RT2860_DROP_BA		(1 << 14)
+#define	RT2860_DROP_PSPOLL	(1 << 13)
+#define	RT2860_DROP_RTS		(1 << 12)
+#define	RT2860_DROP_CTS		(1 << 11)
+#define	RT2860_DROP_ACK		(1 << 10)
+#define	RT2860_DROP_CFEND	(1 <<  9)
+#define	RT2860_DROP_CFACK	(1 <<  8)
+#define	RT2860_DROP_DUPL	(1 <<  7)
+#define	RT2860_DROP_BC		(1 <<  6)
+#define	RT2860_DROP_MC		(1 <<  5)
+#define	RT2860_DROP_VER_ERR	(1 <<  4)
+#define	RT2860_DROP_NOT_MYBSS	(1 <<  3)
+#define	RT2860_DROP_UC_NOME	(1 <<  2)
+#define	RT2860_DROP_PHY_ERR	(1 <<  1)
+#define	RT2860_DROP_CRC_ERR	(1 <<  0)
 
 /* possible flags for register AUTO_RSP_CFG */
-#define RT2860_CTRL_PWR_BIT	(1 << 7)
-#define RT2860_BAC_ACK_POLICY	(1 << 6)
-#define RT2860_CCK_SHORT_EN	(1 << 4)
-#define RT2860_CTS_40M_REF_EN	(1 << 3)
-#define RT2860_CTS_40M_MODE_EN	(1 << 2)
-#define RT2860_BAC_ACKPOLICY_EN	(1 << 1)
-#define RT2860_AUTO_RSP_EN	(1 << 0)
+#define	RT2860_CTRL_PWR_BIT	(1 << 7)
+#define	RT2860_BAC_ACK_POLICY	(1 << 6)
+#define	RT2860_CCK_SHORT_EN	(1 << 4)
+#define	RT2860_CTS_40M_REF_EN	(1 << 3)
+#define	RT2860_CTS_40M_MODE_EN	(1 << 2)
+#define	RT2860_BAC_ACKPOLICY_EN	(1 << 1)
+#define	RT2860_AUTO_RSP_EN	(1 << 0)
 
 /* possible flags for register SIFS_COST_CFG */
-#define RT2860_OFDM_SIFS_COST_SHIFT	8
-#define RT2860_CCK_SIFS_COST_SHIFT	0
+#define	RT2860_OFDM_SIFS_COST_SHIFT	8
+#define	RT2860_CCK_SIFS_COST_SHIFT	0
 
 /* possible flags for register TXOP_HLDR_ET */
-#define RT2860_TXOP_ETM1_EN		(1 << 25)
-#define RT2860_TXOP_ETM0_EN		(1 << 24)
-#define RT2860_TXOP_ETM_THRES_SHIFT	16
-#define RT2860_TXOP_ETO_EN		(1 <<  8)
-#define RT2860_TXOP_ETO_THRES_SHIFT	1
-#define RT2860_PER_RX_RST_EN		(1 <<  0)
+#define	RT2860_TXOP_ETM1_EN		(1 << 25)
+#define	RT2860_TXOP_ETM0_EN		(1 << 24)
+#define	RT2860_TXOP_ETM_THRES_SHIFT	16
+#define	RT2860_TXOP_ETO_EN		(1 <<  8)
+#define	RT2860_TXOP_ETO_THRES_SHIFT	1
+#define	RT2860_PER_RX_RST_EN		(1 <<  0)
 
 /* possible flags for register TX_STAT_FIFO */
-#define RT2860_TXQ_MCS_SHIFT	16
-#define RT2860_TXQ_WCID_SHIFT	8
-#define RT2860_TXQ_ACKREQ	(1 << 7)
-#define RT2860_TXQ_AGG		(1 << 6)
-#define RT2860_TXQ_OK		(1 << 5)
-#define RT2860_TXQ_PID_SHIFT	1
-#define RT2860_TXQ_VLD		(1 << 0)
+#define	RT2860_TXQ_MCS_SHIFT	16
+#define	RT2860_TXQ_WCID_SHIFT	8
+#define	RT2860_TXQ_ACKREQ	(1 << 7)
+#define	RT2860_TXQ_AGG		(1 << 6)
+#define	RT2860_TXQ_OK		(1 << 5)
+#define	RT2860_TXQ_PID_SHIFT	1
+#define	RT2860_TXQ_VLD		(1 << 0)
 
 /* possible flags for register WCID_ATTR */
-#define RT2860_MODE_NOSEC	0
-#define RT2860_MODE_WEP40	1
-#define RT2860_MODE_WEP104	2
-#define RT2860_MODE_TKIP	3
-#define RT2860_MODE_AES_CCMP	4
-#define RT2860_MODE_CKIP40	5
-#define RT2860_MODE_CKIP104	6
-#define RT2860_MODE_CKIP128	7
-#define RT2860_RX_PKEY_EN	(1 << 0)
+#define	RT2860_MODE_NOSEC	0
+#define	RT2860_MODE_WEP40	1
+#define	RT2860_MODE_WEP104	2
+#define	RT2860_MODE_TKIP	3
+#define	RT2860_MODE_AES_CCMP	4
+#define	RT2860_MODE_CKIP40	5
+#define	RT2860_MODE_CKIP104	6
+#define	RT2860_MODE_CKIP128	7
+#define	RT2860_RX_PKEY_EN	(1 << 0)
 
 /* possible flags for register H2M_MAILBOX */
-#define RT2860_H2M_BUSY		(1 << 24)
-#define RT2860_TOKEN_NO_INTR	0xff
-
+#define	RT2860_H2M_BUSY		(1 << 24)
+#define	RT2860_TOKEN_NO_INTR	0xff
 
 /* possible flags for MCU command RT2860_MCU_CMD_LEDS */
-#define RT2860_LED_RADIO	(1 << 13)
-#define RT2860_LED_LINK_2GHZ	(1 << 14)
-#define RT2860_LED_LINK_5GHZ	(1 << 15)
-
+#define	RT2860_LED_RADIO	(1 << 13)
+#define	RT2860_LED_LINK_2GHZ	(1 << 14)
+#define	RT2860_LED_LINK_5GHZ	(1 << 15)
 
 /* possible flags for RT3020 RF register 1 */
-#define RT3070_RF_BLOCK	(1 << 0)
-#define RT3070_RX0_PD	(1 << 2)
-#define RT3070_TX0_PD	(1 << 3)
-#define RT3070_RX1_PD	(1 << 4)
-#define RT3070_TX1_PD	(1 << 5)
+#define	RT3070_RF_BLOCK	(1 << 0)
+#define	RT3070_PLL_PD	(1 << 1)
+#define	RT3070_RX0_PD	(1 << 2)
+#define	RT3070_TX0_PD	(1 << 3)
+#define	RT3070_RX1_PD	(1 << 4)
+#define	RT3070_TX1_PD	(1 << 5)
+#define	RT3070_RX2_PD	(1 << 6)
+#define	RT3070_TX2_PD	(1 << 7)
 
 /* possible flags for RT3020 RF register 15 */
-#define RT3070_TX_LO2	(1 << 3)
+#define	RT3070_TX_LO2	(1 << 3)
 
 /* possible flags for RT3020 RF register 17 */
-#define RT3070_TX_LO1	(1 << 3)
+#define	RT3070_TX_LO1	(1 << 3)
 
 /* possible flags for RT3020 RF register 20 */
-#define RT3070_RX_LO1	(1 << 3)
+#define	RT3070_RX_LO1	(1 << 3)
 
 /* possible flags for RT3020 RF register 21 */
-#define RT3070_RX_LO2	(1 << 3)
+#define	RT3070_RX_LO2	(1 << 3)
+
+/* possible flags for RT3053 RF register 18 */
+#define	RT3593_AUTOTUNE_BYPASS	(1 << 6)
+
+/* possible flags for RT3053 RF register 50 */
+#define	RT3593_TX_LO2	(1 << 4)
+
+/* possible flags for RT3053 RF register 51 */
+#define	RT3593_TX_LO1	(1 << 4)
+
+/* Possible flags for RT5390 RF register 2. */
+#define	RT5390_RESCAL	(1 << 7)
 
+/* Possible flags for RT5390 RF register 3. */
+#define	RT5390_VCOCAL	(1 << 7)
+
+/* Possible flags for RT5390 RF register 38. */
+#define	RT5390_RX_LO1	(1 << 5)
+
+/* Possible flags for RT5390 RF register 39. */
+#define	RT5390_RX_LO2	(1 << 7)
+
+/* Possible flags for RT5390 BBP register 4. */
+#define	RT5390_MAC_IF_CTRL	(1 << 6)
+
+/* Possible flags for RT5390 BBP register 105. */
+#define	RT5390_MLD			(1 << 2)
+#define	RT5390_EN_SIG_MODULATION	(1 << 3)
 
 /* RT2860 TX descriptor */
 struct rt2860_txd {
 	uint32_t	sdp0;		/* Segment Data Pointer 0 */
 	uint16_t	sdl1;		/* Segment Data Length 1 */
-#define RT2860_TX_BURST	(1 << 15)
-#define RT2860_TX_LS1	(1 << 14)	/* SDP1 is the last segment */
+#define	RT2860_TX_BURST	(1 << 15)
+#define	RT2860_TX_LS1	(1 << 14)	/* SDP1 is the last segment */
 
 	uint16_t	sdl0;		/* Segment Data Length 0 */
-#define RT2860_TX_DDONE	(1 << 15)
-#define RT2860_TX_LS0	(1 << 14)	/* SDP0 is the last segment */
+#define	RT2860_TX_DDONE	(1 << 15)
+#define	RT2860_TX_LS0	(1 << 14)	/* SDP0 is the last segment */
 
 	uint32_t	sdp1;		/* Segment Data Pointer 1 */
 	uint8_t		reserved[3];
 	uint8_t		flags;
-#define RT2860_TX_QSEL_SHIFT	1
-#define RT2860_TX_QSEL_MGMT	(0 << 1)
-#define RT2860_TX_QSEL_HCCA	(1 << 1)
-#define RT2860_TX_QSEL_EDCA	(2 << 1)
-#define RT2860_TX_WIV		(1 << 0)
+#define	RT2860_TX_QSEL_SHIFT	1
+#define	RT2860_TX_QSEL_MGMT	(0 << 1)
+#define	RT2860_TX_QSEL_HCCA	(1 << 1)
+#define	RT2860_TX_QSEL_EDCA	(2 << 1)
+#define	RT2860_TX_WIV		(1 << 0)
 } __packed;
 
 /* RT2870 TX descriptor */
@@ -737,38 +765,38 @@ struct rt2870_txd {
 /* TX Wireless Information */
 struct rt2860_txwi {
 	uint8_t		flags;
-#define RT2860_TX_MPDU_DSITY_SHIFT	5
-#define RT2860_TX_AMPDU			(1 << 4)
-#define RT2860_TX_TS			(1 << 3)
-#define RT2860_TX_CFACK			(1 << 2)
-#define RT2860_TX_MMPS			(1 << 1)
-#define RT2860_TX_FRAG			(1 << 0)
+#define	RT2860_TX_MPDU_DSITY_SHIFT	5
+#define	RT2860_TX_AMPDU			(1 << 4)
+#define	RT2860_TX_TS			(1 << 3)
+#define	RT2860_TX_CFACK			(1 << 2)
+#define	RT2860_TX_MMPS			(1 << 1)
+#define	RT2860_TX_FRAG			(1 << 0)
 
 	uint8_t		txop;
-#define RT2860_TX_TXOP_HT	0
-#define RT2860_TX_TXOP_PIFS	1
-#define RT2860_TX_TXOP_SIFS	2
-#define RT2860_TX_TXOP_BACKOFF	3
+#define	RT2860_TX_TXOP_HT	0
+#define	RT2860_TX_TXOP_PIFS	1
+#define	RT2860_TX_TXOP_SIFS	2
+#define	RT2860_TX_TXOP_BACKOFF	3
 
 	uint16_t	phy;
-#define RT2860_PHY_MODE		0xc000
-#define RT2860_PHY_CCK		(0 << 14)
-#define RT2860_PHY_OFDM		(1 << 14)
-#define RT2860_PHY_HT		(2 << 14)
-#define RT2860_PHY_HT_GF	(3 << 14)
-#define RT2860_PHY_SGI		(1 << 8)
-#define RT2860_PHY_BW40		(1 << 7)
-#define RT2860_PHY_MCS		0x7f
-#define RT2860_PHY_SHPRE	(1 << 3)
+#define	RT2860_PHY_MODE		0xc000
+#define	RT2860_PHY_CCK		(0 << 14)
+#define	RT2860_PHY_OFDM		(1 << 14)
+#define	RT2860_PHY_HT		(2 << 14)
+#define	RT2860_PHY_HT_GF	(3 << 14)
+#define	RT2860_PHY_SGI		(1 << 8)
+#define	RT2860_PHY_BW40		(1 << 7)
+#define	RT2860_PHY_MCS		0x7f
+#define	RT2860_PHY_SHPRE	(1 << 3)
 
 	uint8_t		xflags;
-#define RT2860_TX_BAWINSIZE_SHIFT	2
-#define RT2860_TX_NSEQ			(1 << 1)
-#define RT2860_TX_ACK			(1 << 0)
+#define	RT2860_TX_BAWINSIZE_SHIFT	2
+#define	RT2860_TX_NSEQ			(1 << 1)
+#define	RT2860_TX_ACK			(1 << 0)
 
 	uint8_t		wcid;	/* Wireless Client ID */
 	uint16_t	len;
-#define RT2860_TX_PID_SHIFT	12
+#define	RT2860_TX_PID_SHIFT	12
 
 	uint32_t	iv;
 	uint32_t	eiv;
@@ -779,28 +807,28 @@ struct rt2860_rxd {
 	uint32_t	sdp0;
 	uint16_t	sdl1;	/* unused */
 	uint16_t	sdl0;
-#define RT2860_RX_DDONE	(1 << 15)
-#define RT2860_RX_LS0	(1 << 14)
+#define	RT2860_RX_DDONE	(1 << 15)
+#define	RT2860_RX_LS0	(1 << 14)
 
 	uint32_t	sdp1;	/* unused */
 	uint32_t	flags;
-#define RT2860_RX_DEC		(1 << 16)
-#define RT2860_RX_AMPDU		(1 << 15)
-#define RT2860_RX_L2PAD		(1 << 14)
-#define RT2860_RX_RSSI		(1 << 13)
-#define RT2860_RX_HTC		(1 << 12)
-#define RT2860_RX_AMSDU		(1 << 11)
-#define RT2860_RX_MICERR	(1 << 10)
-#define RT2860_RX_ICVERR	(1 <<  9)
-#define RT2860_RX_CRCERR	(1 <<  8)
-#define RT2860_RX_MYBSS		(1 <<  7)
-#define RT2860_RX_BC		(1 <<  6)
-#define RT2860_RX_MC		(1 <<  5)
-#define RT2860_RX_UC2ME		(1 <<  4)
-#define RT2860_RX_FRAG		(1 <<  3)
-#define RT2860_RX_NULL		(1 <<  2)
-#define RT2860_RX_DATA		(1 <<  1)
-#define RT2860_RX_BA		(1 <<  0)
+#define	RT2860_RX_DEC		(1 << 16)
+#define	RT2860_RX_AMPDU		(1 << 15)
+#define	RT2860_RX_L2PAD		(1 << 14)
+#define	RT2860_RX_RSSI		(1 << 13)
+#define	RT2860_RX_HTC		(1 << 12)
+#define	RT2860_RX_AMSDU		(1 << 11)
+#define	RT2860_RX_MICERR	(1 << 10)
+#define	RT2860_RX_ICVERR	(1 <<  9)
+#define	RT2860_RX_CRCERR	(1 <<  8)
+#define	RT2860_RX_MYBSS		(1 <<  7)
+#define	RT2860_RX_BC		(1 <<  6)
+#define	RT2860_RX_MC		(1 <<  5)
+#define	RT2860_RX_UC2ME		(1 <<  4)
+#define	RT2860_RX_FRAG		(1 <<  3)
+#define	RT2860_RX_NULL		(1 <<  2)
+#define	RT2860_RX_DATA		(1 <<  1)
+#define	RT2860_RX_BA		(1 <<  0)
 } __packed;
 
 /* RT2870 RX descriptor */
@@ -813,11 +841,11 @@ struct rt2870_rxd {
 struct rt2860_rxwi {
 	uint8_t		wcid;
 	uint8_t		keyidx;
-#define RT2860_RX_UDF_SHIFT	5
-#define RT2860_RX_BSS_IDX_SHIFT	2
+#define	RT2860_RX_UDF_SHIFT	5
+#define	RT2860_RX_BSS_IDX_SHIFT	2
 
 	uint16_t	len;
-#define RT2860_RX_TID_SHIFT	12
+#define	RT2860_RX_TID_SHIFT	12
 
 	uint16_t	seq;
 	uint16_t	phy;
@@ -827,124 +855,111 @@ struct rt2860_rxwi {
 	uint16_t	reserved2;
 } __packed;
 
-
-/* first DMA segment contains TXWI + 802.11 header + 32-bit padding */
-#define RT2860_TXWI_DMASZ			\
-	(sizeof (struct rt2860_txwi) +		\
-	 sizeof (struct ieee80211_htframe) +	\
-	 sizeof (uint16_t))
-
-#define RT2860_RF1	0
-#define RT2860_RF2	2
-#define RT2860_RF3	1
-#define RT2860_RF4	3
-
-#define RT2860_RF_2820	1	/* 2T3R */
-#define RT2860_RF_2850	2	/* dual-band 2T3R */
-#define RT2860_RF_2720	3	/* 1T2R */
-#define RT2860_RF_2750	4	/* dual-band 1T2R */
-#define RT3070_RF_3020	5	/* 1T1R */
-#define RT3070_RF_2020	6	/* b/g */
-#define RT3070_RF_3021	7	/* 1T2R */
-#define RT3070_RF_3022	8	/* 2T2R */
-#define RT3070_RF_3052	9	/* dual-band 2T2R */
+#define	RT2860_RF_2820	0x0001	/* 2T3R */
+#define	RT2860_RF_2850	0x0002	/* dual-band 2T3R */
+#define	RT2860_RF_2720	0x0003	/* 1T2R */
+#define	RT2860_RF_2750	0x0004	/* dual-band 1T2R */
+#define	RT3070_RF_3020	0x0005	/* 1T1R */
+#define	RT3070_RF_2020	0x0006	/* b/g */
+#define	RT3070_RF_3021	0x0007	/* 1T2R */
+#define	RT3070_RF_3022	0x0008	/* 2T2R */
+#define	RT3070_RF_3052	0x0009	/* dual-band 2T2R */
+#define	RT3593_RF_3053	0x000d	/* dual-band 3T3R */
+#define	RT5592_RF_5592	0x000f	/* dual-band 2T2R */
+#define	RT5390_RF_5370	0x5370	/* 1T1R */
+#define	RT5390_RF_5372	0x5372	/* 2T2R */
 
 /* USB commands for RT2870 only */
-#define RT2870_RESET		1
-#define RT2870_WRITE_2		2
-#define RT2870_WRITE_REGION_1	6
-#define RT2870_READ_REGION_1	7
-#define RT2870_EEPROM_READ	9
-
-#define RT2860_EEPROM_DELAY	1	/* minimum hold time (microsecond) */
-
-#define RT2860_EEPROM_VERSION		0x01
-#define RT2860_EEPROM_MAC01		0x02
-#define RT2860_EEPROM_MAC23		0x03
-#define RT2860_EEPROM_MAC45		0x04
-#define RT2860_EEPROM_PCIE_PSLEVEL	0x11
-#define RT2860_EEPROM_REV		0x12
-#define RT2860_EEPROM_ANTENNA		0x1a
-#define RT2860_EEPROM_CONFIG		0x1b
-#define RT2860_EEPROM_COUNTRY		0x1c
-#define RT2860_EEPROM_FREQ_LEDS		0x1d
-#define RT2860_EEPROM_LED1		0x1e
-#define RT2860_EEPROM_LED2		0x1f
-#define RT2860_EEPROM_LED3		0x20
-#define RT2860_EEPROM_LNA		0x22
-#define RT2860_EEPROM_RSSI1_2GHZ	0x23
-#define RT2860_EEPROM_RSSI2_2GHZ	0x24
-#define RT2860_EEPROM_RSSI1_5GHZ	0x25
-#define RT2860_EEPROM_RSSI2_5GHZ	0x26
-#define RT2860_EEPROM_DELTAPWR		0x28
-#define RT2860_EEPROM_PWR2GHZ_BASE1	0x29
-#define RT2860_EEPROM_PWR2GHZ_BASE2	0x30
-#define RT2860_EEPROM_TSSI1_2GHZ	0x37
-#define RT2860_EEPROM_TSSI2_2GHZ	0x38
-#define RT2860_EEPROM_TSSI3_2GHZ	0x39
-#define RT2860_EEPROM_TSSI4_2GHZ	0x3a
-#define RT2860_EEPROM_TSSI5_2GHZ	0x3b
-#define RT2860_EEPROM_PWR5GHZ_BASE1	0x3c
-#define RT2860_EEPROM_PWR5GHZ_BASE2	0x53
-#define RT2860_EEPROM_TSSI1_5GHZ	0x6a
-#define RT2860_EEPROM_TSSI2_5GHZ	0x6b
-#define RT2860_EEPROM_TSSI3_5GHZ	0x6c
-#define RT2860_EEPROM_TSSI4_5GHZ	0x6d
-#define RT2860_EEPROM_TSSI5_5GHZ	0x6e
-#define RT2860_EEPROM_RPWR		0x6f
-#define RT2860_EEPROM_BBP_BASE		0x78
-#define RT3071_EEPROM_RF_BASE		0x82
-
-#define RT2860_RIDX_CCK1	 0
-#define RT2860_RIDX_CCK11	 3
-#define RT2860_RIDX_OFDM6	 4
-#define RT2860_RIDX_MAX		12
-static const struct rt2860_rate {
-	uint8_t		rate;
-	uint8_t		mcs;
-	enum		ieee80211_phytype phy;
-	uint8_t		ctl_ridx;
-	uint16_t	sp_ack_dur;
-	uint16_t	lp_ack_dur;
-} rt2860_rates[] = {
-	{   2, 0, IEEE80211_T_DS,   0, 314, 314 },
-	{   4, 1, IEEE80211_T_DS,   1, 258, 162 },
-	{  11, 2, IEEE80211_T_DS,   2, 223, 127 },
-	{  22, 3, IEEE80211_T_DS,   3, 213, 117 },
-	{  12, 0, IEEE80211_T_OFDM, 4,  60,  60 },
-	{  18, 1, IEEE80211_T_OFDM, 4,  52,  52 },
-	{  24, 2, IEEE80211_T_OFDM, 6,  48,  48 },
-	{  36, 3, IEEE80211_T_OFDM, 6,  44,  44 },
-	{  48, 4, IEEE80211_T_OFDM, 8,  44,  44 },
-	{  72, 5, IEEE80211_T_OFDM, 8,  40,  40 },
-	{  96, 6, IEEE80211_T_OFDM, 8,  40,  40 },
-	{ 108, 7, IEEE80211_T_OFDM, 8,  40,  40 }
-};
+#define	RT2870_RESET		1
+#define	RT2870_WRITE_2		2
+#define	RT2870_WRITE_REGION_1	6
+#define	RT2870_READ_REGION_1	7
+#define	RT2870_EEPROM_READ	9
+
+#define	RT2860_EEPROM_DELAY	1	/* minimum hold time (microsecond) */
+
+#define	RT2860_EEPROM_VERSION		0x01
+#define	RT2860_EEPROM_MAC01		0x02
+#define	RT2860_EEPROM_MAC23		0x03
+#define	RT2860_EEPROM_MAC45		0x04
+#define	RT2860_EEPROM_PCIE_PSLEVEL	0x11
+#define	RT2860_EEPROM_REV		0x12
+#define	RT2860_EEPROM_ANTENNA		0x1a
+#define	RT2860_EEPROM_CONFIG		0x1b
+#define	RT2860_EEPROM_COUNTRY		0x1c
+#define	RT2860_EEPROM_FREQ_LEDS		0x1d
+#define	RT2860_EEPROM_LED1		0x1e
+#define	RT2860_EEPROM_LED2		0x1f
+#define	RT2860_EEPROM_LED3		0x20
+#define	RT2860_EEPROM_LNA		0x22
+#define	RT2860_EEPROM_RSSI1_2GHZ	0x23
+#define	RT2860_EEPROM_RSSI2_2GHZ	0x24
+#define	RT2860_EEPROM_RSSI1_5GHZ	0x25
+#define	RT2860_EEPROM_RSSI2_5GHZ	0x26
+#define	RT2860_EEPROM_DELTAPWR		0x28
+#define	RT2860_EEPROM_PWR2GHZ_BASE1	0x29
+#define	RT2860_EEPROM_PWR2GHZ_BASE2	0x30
+#define	RT2860_EEPROM_TSSI1_2GHZ	0x37
+#define	RT2860_EEPROM_TSSI2_2GHZ	0x38
+#define	RT2860_EEPROM_TSSI3_2GHZ	0x39
+#define	RT2860_EEPROM_TSSI4_2GHZ	0x3a
+#define	RT2860_EEPROM_TSSI5_2GHZ	0x3b
+#define	RT2860_EEPROM_PWR5GHZ_BASE1	0x3c
+#define	RT2860_EEPROM_PWR5GHZ_BASE2	0x53
+#define	RT2860_EEPROM_TSSI1_5GHZ	0x6a
+#define	RT2860_EEPROM_TSSI2_5GHZ	0x6b
+#define	RT2860_EEPROM_TSSI3_5GHZ	0x6c
+#define	RT2860_EEPROM_TSSI4_5GHZ	0x6d
+#define	RT2860_EEPROM_TSSI5_5GHZ	0x6e
+#define	RT2860_EEPROM_RPWR		0x6f
+#define	RT2860_EEPROM_BBP_BASE		0x78
+#define	RT3071_EEPROM_RF_BASE		0x82
+
+/* EEPROM registers for RT3593. */
+#define	RT3593_EEPROM_FREQ_LEDS		0x21
+#define	RT3593_EEPROM_FREQ		0x22
+#define	RT3593_EEPROM_LED1		0x22
+#define	RT3593_EEPROM_LED2		0x23
+#define	RT3593_EEPROM_LED3		0x24
+#define	RT3593_EEPROM_LNA		0x26
+#define	RT3593_EEPROM_LNA_5GHZ		0x27
+#define	RT3593_EEPROM_RSSI1_2GHZ	0x28
+#define	RT3593_EEPROM_RSSI2_2GHZ	0x29
+#define	RT3593_EEPROM_RSSI1_5GHZ	0x2a
+#define	RT3593_EEPROM_RSSI2_5GHZ	0x2b
+#define	RT3593_EEPROM_PWR2GHZ_BASE1	0x30
+#define	RT3593_EEPROM_PWR2GHZ_BASE2	0x37
+#define	RT3593_EEPROM_PWR2GHZ_BASE3	0x3e
+#define	RT3593_EEPROM_PWR5GHZ_BASE1	0x4b
+#define	RT3593_EEPROM_PWR5GHZ_BASE2	0x65
+#define	RT3593_EEPROM_PWR5GHZ_BASE3	0x7f
 
 /*
- * Control and status registers access macros.
+ * EEPROM IQ calibration.
  */
-#define RAL_READ(sc, reg)						\
-	bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
-
-#define RAL_WRITE(sc, reg, val)						\
-	bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
-
-#define RAL_BARRIER_WRITE(sc)						\
-	bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, 0x1800,		\
-	    BUS_SPACE_BARRIER_WRITE)
-
-#define RAL_BARRIER_READ_WRITE(sc)					\
-	bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, 0x1800,		\
-	    BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE)
-
-#define RAL_WRITE_REGION_1(sc, offset, datap, count)			\
-	bus_space_write_region_1((sc)->sc_st, (sc)->sc_sh, (offset),	\
-	    (datap), (count))
-
-#define RAL_SET_REGION_4(sc, offset, val, count)			\
-	bus_space_set_region_4((sc)->sc_st, (sc)->sc_sh, (offset),	\
-	    (val), (count))
+#define	RT5390_EEPROM_IQ_GAIN_CAL_TX0_2GHZ			0x130
+#define	RT5390_EEPROM_IQ_PHASE_CAL_TX0_2GHZ			0x131
+#define	RT5390_EEPROM_IQ_GAIN_CAL_TX1_2GHZ			0x133
+#define	RT5390_EEPROM_IQ_PHASE_CAL_TX1_2GHZ			0x134
+#define	RT5390_EEPROM_RF_IQ_COMPENSATION_CTL			0x13c
+#define	RT5390_EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CTL		0x13d
+#define	RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5GHZ		0x144
+#define	RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5GHZ	0x145
+#define	RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5GHZ	0x146
+#define	RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5GHZ	0x147
+#define	RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5GHZ	0x148
+#define	RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5GHZ	0x149
+#define	RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5GHZ		0x14a
+#define	RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5GHZ	0x14b
+#define	RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5GHZ	0x14c
+#define	RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5GHZ	0x14d
+#define	RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5GHZ	0x14e
+#define	RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5GHZ	0x14f
+
+#define	RT2860_RIDX_CCK1	 0
+#define	RT2860_RIDX_CCK11	 3
+#define	RT2860_RIDX_OFDM6	 4
+#define	RT2860_RIDX_MAX		12
 
 /*
  * EEPROM access macro.
@@ -958,39 +973,9 @@ static const struct rt2860_rate {
 /*
  * Default values for MAC registers; values taken from the reference driver.
  */
-#define RT2860_DEF_MAC					\
-	{ RT2860_BCN_OFFSET0,		0xf8f0e8e0 },	\
-	{ RT2860_LEGACY_BASIC_RATE,	0x0000013f },	\
-	{ RT2860_HT_BASIC_RATE,		0x00008003 },	\
-	{ RT2860_MAC_SYS_CTRL,		0x00000000 },	\
-	{ RT2860_BKOFF_SLOT_CFG,	0x00000209 },	\
-	{ RT2860_TX_SW_CFG0,		0x00000000 },	\
-	{ RT2860_TX_SW_CFG1,		0x00080606 },	\
-	{ RT2860_TX_LINK_CFG,		0x00001020 },	\
-	{ RT2860_TX_TIMEOUT_CFG,	0x000a2090 },	\
-	{ RT2860_LED_CFG,		0x7f031e46 },	\
-	{ RT2860_WMM_AIFSN_CFG,		0x00002273 },	\
-	{ RT2860_WMM_CWMIN_CFG,		0x00002344 },	\
-	{ RT2860_WMM_CWMAX_CFG,		0x000034aa },	\
-	{ RT2860_MAX_PCNT,		0x1f3fbf9f },	\
-	{ RT2860_TX_RTY_CFG,		0x47d01f0f },	\
-	{ RT2860_AUTO_RSP_CFG,		0x00000013 },	\
-	{ RT2860_CCK_PROT_CFG,		0x05740003 },	\
-	{ RT2860_OFDM_PROT_CFG,		0x05740003 },	\
-	{ RT2860_GF20_PROT_CFG,		0x01744004 },	\
-	{ RT2860_GF40_PROT_CFG,		0x03f44084 },	\
-	{ RT2860_MM20_PROT_CFG,		0x01744004 },	\
-	{ RT2860_MM40_PROT_CFG,		0x03f54084 },	\
-	{ RT2860_TXOP_CTRL_CFG,		0x0000583f },	\
-	{ RT2860_TXOP_HLDR_ET,		0x00000002 },	\
-	{ RT2860_TX_RTS_CFG,		0x00092b20 },	\
-	{ RT2860_EXP_ACK_TIME,		0x002400ca },	\
-	{ RT2860_XIFS_TIME_CFG,		0x33a41010 },	\
-	{ RT2860_PWR_PIN_CFG,		0x00000003 }
-
-/* XXX only a few registers differ from above, try to merge? */
-#define RT2870_DEF_MAC					\
+#define	RT2870_DEF_MAC					\
 	{ RT2860_BCN_OFFSET0,		0xf8f0e8e0 },	\
+	{ RT2860_BCN_OFFSET1,		0x6f77d0c8 },	\
 	{ RT2860_LEGACY_BASIC_RATE,	0x0000013f },	\
 	{ RT2860_HT_BASIC_RATE,		0x00008003 },	\
 	{ RT2860_MAC_SYS_CTRL,		0x00000000 },	\
@@ -999,6 +984,7 @@ static const struct rt2860_rate {
 	{ RT2860_TX_SW_CFG1,		0x00080606 },	\
 	{ RT2860_TX_LINK_CFG,		0x00001020 },	\
 	{ RT2860_TX_TIMEOUT_CFG,	0x000a2090 },	\
+	{ RT2860_MAX_LEN_CFG,		0x00001f00 },	\
 	{ RT2860_LED_CFG,		0x7f031e46 },	\
 	{ RT2860_WMM_AIFSN_CFG,		0x00002273 },	\
 	{ RT2860_WMM_CWMIN_CFG,		0x00002344 },	\
@@ -1024,9 +1010,10 @@ static const struct rt2860_rate {
 /*
  * Default values for BBP registers; values taken from the reference driver.
  */
-#define RT2860_DEF_BBP	\
+#define	RT2860_DEF_BBP	\
 	{  65, 0x2c },	\
 	{  66, 0x38 },	\
+	{  68, 0x0b },	\
 	{  69, 0x12 },	\
 	{  70, 0x0a },	\
 	{  73, 0x10 },	\
@@ -1041,65 +1028,128 @@ static const struct rt2860_rate {
 	{ 105, 0x05 },	\
 	{ 106, 0x35 }
 
+#define	RT5390_DEF_BBP	\
+	{  31, 0x08 },	\
+	{  65, 0x2c },	\
+	{  66, 0x38 },	\
+	{  68, 0x0b },	\
+	{  69, 0x0d },	\
+	{  70, 0x06 },	\
+	{  73, 0x13 },	\
+	{  75, 0x46 },	\
+	{  76, 0x28 },	\
+	{  77, 0x59 },	\
+	{  81, 0x37 },	\
+	{  82, 0x62 },	\
+	{  83, 0x7a },	\
+	{  84, 0x9a },	\
+	{  86, 0x38 },	\
+	{  91, 0x04 },	\
+	{  92, 0x02 },	\
+	{ 103, 0xc0 },	\
+	{ 104, 0x92 },	\
+	{ 105, 0x3c },	\
+	{ 106, 0x03 },	\
+	{ 128, 0x12 }
+
+#define	RT5592_DEF_BBP	\
+	{  20, 0x06 },	\
+	{  31, 0x08 },	\
+	{  65, 0x2c },	\
+	{  66, 0x38 },	\
+	{  68, 0xdd },	\
+	{  69, 0x1a },	\
+	{  70, 0x05 },	\
+	{  73, 0x13 },	\
+	{  74, 0x0f },	\
+	{  75, 0x4f },	\
+	{  76, 0x28 },	\
+	{  77, 0x59 },	\
+	{  81, 0x37 },	\
+	{  82, 0x62 },	\
+	{  83, 0x6a },	\
+	{  84, 0x9a },	\
+	{  86, 0x38 },	\
+	{  88, 0x90 },	\
+	{  91, 0x04 },	\
+	{  92, 0x02 },	\
+	{  95, 0x9a },	\
+	{  98, 0x12 },	\
+	{ 103, 0xc0 },	\
+	{ 104, 0x92 },	\
+	{ 105, 0x3c },	\
+	{ 106, 0x35 },	\
+	{ 128, 0x12 },	\
+	{ 134, 0xd0 },	\
+	{ 135, 0xf6 },	\
+	{ 137, 0x0f }
+
 /*
  * Default settings for RF registers; values derived from the reference driver.
  */
-#define RT2860_RF2850						\
-	{   1, 0x100bb3, 0x1301e1, 0x05a014, 0x001402 },	\
-	{   2, 0x100bb3, 0x1301e1, 0x05a014, 0x001407 },	\
-	{   3, 0x100bb3, 0x1301e2, 0x05a014, 0x001402 },	\
-	{   4, 0x100bb3, 0x1301e2, 0x05a014, 0x001407 },	\
-	{   5, 0x100bb3, 0x1301e3, 0x05a014, 0x001402 },	\
-	{   6, 0x100bb3, 0x1301e3, 0x05a014, 0x001407 },	\
-	{   7, 0x100bb3, 0x1301e4, 0x05a014, 0x001402 },	\
-	{   8, 0x100bb3, 0x1301e4, 0x05a014, 0x001407 },	\
-	{   9, 0x100bb3, 0x1301e5, 0x05a014, 0x001402 },	\
-	{  10, 0x100bb3, 0x1301e5, 0x05a014, 0x001407 },	\
-	{  11, 0x100bb3, 0x1301e6, 0x05a014, 0x001402 },	\
-	{  12, 0x100bb3, 0x1301e6, 0x05a014, 0x001407 },	\
-	{  13, 0x100bb3, 0x1301e7, 0x05a014, 0x001402 },	\
-	{  14, 0x100bb3, 0x1301e8, 0x05a014, 0x001404 },	\
-	{  36, 0x100bb3, 0x130266, 0x056014, 0x001408 },	\
-	{  38, 0x100bb3, 0x130267, 0x056014, 0x001404 },	\
-	{  40, 0x100bb2, 0x1301a0, 0x056014, 0x001400 },	\
-	{  44, 0x100bb2, 0x1301a0, 0x056014, 0x001408 },	\
-	{  46, 0x100bb2, 0x1301a1, 0x056014, 0x001402 },	\
-	{  48, 0x100bb2, 0x1301a1, 0x056014, 0x001406 },	\
-	{  52, 0x100bb2, 0x1301a2, 0x056014, 0x001404 },	\
-	{  54, 0x100bb2, 0x1301a2, 0x056014, 0x001408 },	\
-	{  56, 0x100bb2, 0x1301a3, 0x056014, 0x001402 },	\
-	{  60, 0x100bb2, 0x1301a4, 0x056014, 0x001400 },	\
-	{  62, 0x100bb2, 0x1301a4, 0x056014, 0x001404 },	\
-	{  64, 0x100bb2, 0x1301a4, 0x056014, 0x001408 },	\
-	{ 100, 0x100bb2, 0x1301ac, 0x05e014, 0x001400 },	\
-	{ 102, 0x100bb2, 0x1701ac, 0x15e014, 0x001404 },	\
-	{ 104, 0x100bb2, 0x1701ac, 0x15e014, 0x001408 },	\
-	{ 108, 0x100bb3, 0x17028c, 0x15e014, 0x001404 },	\
-	{ 110, 0x100bb3, 0x13028d, 0x05e014, 0x001400 },	\
-	{ 112, 0x100bb3, 0x13028d, 0x05e014, 0x001406 },	\
-	{ 116, 0x100bb3, 0x13028e, 0x05e014, 0x001408 },	\
-	{ 118, 0x100bb3, 0x13028f, 0x05e014, 0x001404 },	\
-	{ 120, 0x100bb1, 0x1300e0, 0x05e014, 0x001400 },	\
-	{ 124, 0x100bb1, 0x1300e0, 0x05e014, 0x001404 },	\
-	{ 126, 0x100bb1, 0x1300e0, 0x05e014, 0x001406 },	\
-	{ 128, 0x100bb1, 0x1300e0, 0x05e014, 0x001408 },	\
-	{ 132, 0x100bb1, 0x1300e1, 0x05e014, 0x001402 },	\
-	{ 134, 0x100bb1, 0x1300e1, 0x05e014, 0x001404 },	\
-	{ 136, 0x100bb1, 0x1300e1, 0x05e014, 0x001406 },	\
-	{ 140, 0x100bb1, 0x1300e2, 0x05e014, 0x001400 },	\
-	{ 149, 0x100bb1, 0x1300e2, 0x05e014, 0x001409 },	\
-	{ 151, 0x100bb1, 0x1300e3, 0x05e014, 0x001401 },	\
-	{ 153, 0x100bb1, 0x1300e3, 0x05e014, 0x001403 },	\
-	{ 157, 0x100bb1, 0x1300e3, 0x05e014, 0x001407 },	\
-	{ 159, 0x100bb1, 0x1300e3, 0x05e014, 0x001409 },	\
-	{ 161, 0x100bb1, 0x1300e4, 0x05e014, 0x001401 },	\
-	{ 165, 0x100bb1, 0x1300e4, 0x05e014, 0x001405 },	\
-	{ 167, 0x100bb1, 0x1300f4, 0x05e014, 0x001407 },	\
-	{ 169, 0x100bb1, 0x1300f4, 0x05e014, 0x001409 },	\
-	{ 171, 0x100bb1, 0x1300f5, 0x05e014, 0x001401 },	\
-	{ 173, 0x100bb1, 0x1300f5, 0x05e014, 0x001403 }
-
-#define RT3070_RF3052		\
+#define	RT2860_RF2850							\
+	{   1, 0x98402ecc, 0x984c0786, 0x9816b455, 0x9800510b },	\
+	{   2, 0x98402ecc, 0x984c0786, 0x98168a55, 0x9800519f },	\
+	{   3, 0x98402ecc, 0x984c078a, 0x98168a55, 0x9800518b },	\
+	{   4, 0x98402ecc, 0x984c078a, 0x98168a55, 0x9800519f },	\
+	{   5, 0x98402ecc, 0x984c078e, 0x98168a55, 0x9800518b },	\
+	{   6, 0x98402ecc, 0x984c078e, 0x98168a55, 0x9800519f },	\
+	{   7, 0x98402ecc, 0x984c0792, 0x98168a55, 0x9800518b },	\
+	{   8, 0x98402ecc, 0x984c0792, 0x98168a55, 0x9800519f },	\
+	{   9, 0x98402ecc, 0x984c0796, 0x98168a55, 0x9800518b },	\
+	{  10, 0x98402ecc, 0x984c0796, 0x98168a55, 0x9800519f },	\
+	{  11, 0x98402ecc, 0x984c079a, 0x98168a55, 0x9800518b },	\
+	{  12, 0x98402ecc, 0x984c079a, 0x98168a55, 0x9800519f },	\
+	{  13, 0x98402ecc, 0x984c079e, 0x98168a55, 0x9800518b },	\
+	{  14, 0x98402ecc, 0x984c07a2, 0x98168a55, 0x98005193 },	\
+	{  36, 0x98402ecc, 0x984c099a, 0x98158a55, 0x980ed1a3 },	\
+	{  38, 0x98402ecc, 0x984c099e, 0x98158a55, 0x980ed193 },	\
+	{  40, 0x98402ec8, 0x984c0682, 0x98158a55, 0x980ed183 },	\
+	{  44, 0x98402ec8, 0x984c0682, 0x98158a55, 0x980ed1a3 },	\
+	{  46, 0x98402ec8, 0x984c0686, 0x98158a55, 0x980ed18b },	\
+	{  48, 0x98402ec8, 0x984c0686, 0x98158a55, 0x980ed19b },	\
+	{  52, 0x98402ec8, 0x984c068a, 0x98158a55, 0x980ed193 },	\
+	{  54, 0x98402ec8, 0x984c068a, 0x98158a55, 0x980ed1a3 },	\
+	{  56, 0x98402ec8, 0x984c068e, 0x98158a55, 0x980ed18b },	\
+	{  60, 0x98402ec8, 0x984c0692, 0x98158a55, 0x980ed183 },	\
+	{  62, 0x98402ec8, 0x984c0692, 0x98158a55, 0x980ed193 },	\
+	{  64, 0x98402ec8, 0x984c0692, 0x98158a55, 0x980ed1a3 },	\
+	{ 100, 0x98402ec8, 0x984c06b2, 0x98178a55, 0x980ed783 },	\
+	{ 102, 0x98402ec8, 0x985c06b2, 0x98578a55, 0x980ed793 },	\
+	{ 104, 0x98402ec8, 0x985c06b2, 0x98578a55, 0x980ed1a3 },	\
+	{ 108, 0x98402ecc, 0x985c0a32, 0x98578a55, 0x980ed193 },	\
+	{ 110, 0x98402ecc, 0x984c0a36, 0x98178a55, 0x980ed183 },	\
+	{ 112, 0x98402ecc, 0x984c0a36, 0x98178a55, 0x980ed19b },	\
+	{ 116, 0x98402ecc, 0x984c0a3a, 0x98178a55, 0x980ed1a3 },	\
+	{ 118, 0x98402ecc, 0x984c0a3e, 0x98178a55, 0x980ed193 },	\
+	{ 120, 0x98402ec4, 0x984c0382, 0x98178a55, 0x980ed183 },	\
+	{ 124, 0x98402ec4, 0x984c0382, 0x98178a55, 0x980ed193 },	\
+	{ 126, 0x98402ec4, 0x984c0382, 0x98178a55, 0x980ed15b },	\
+	{ 128, 0x98402ec4, 0x984c0382, 0x98178a55, 0x980ed1a3 },	\
+	{ 132, 0x98402ec4, 0x984c0386, 0x98178a55, 0x980ed18b },	\
+	{ 134, 0x98402ec4, 0x984c0386, 0x98178a55, 0x980ed193 },	\
+	{ 136, 0x98402ec4, 0x984c0386, 0x98178a55, 0x980ed19b },	\
+	{ 140, 0x98402ec4, 0x984c038a, 0x98178a55, 0x980ed183 },	\
+	{ 149, 0x98402ec4, 0x984c038a, 0x98178a55, 0x980ed1a7 },	\
+	{ 151, 0x98402ec4, 0x984c038e, 0x98178a55, 0x980ed187 },	\
+	{ 153, 0x98402ec4, 0x984c038e, 0x98178a55, 0x980ed18f },	\
+	{ 157, 0x98402ec4, 0x984c038e, 0x98178a55, 0x980ed19f },	\
+	{ 159, 0x98402ec4, 0x984c038e, 0x98178a55, 0x980ed1a7 },	\
+	{ 161, 0x98402ec4, 0x984c0392, 0x98178a55, 0x980ed187 },	\
+	{ 165, 0x98402ec4, 0x984c0392, 0x98178a55, 0x980ed197 },	\
+	{ 167, 0x98402ec4, 0x984c03d2, 0x98179855, 0x9815531f },	\
+	{ 169, 0x98402ec4, 0x984c03d2, 0x98179855, 0x98155327 },	\
+	{ 171, 0x98402ec4, 0x984c03d6, 0x98179855, 0x98155307 },	\
+	{ 173, 0x98402ec4, 0x984c03d6, 0x98179855, 0x9815530f },	\
+	{ 184, 0x95002ccc, 0x9500491e, 0x9509be55, 0x950c0a0b },	\
+	{ 188, 0x95002ccc, 0x95004922, 0x9509be55, 0x950c0a13 },	\
+	{ 192, 0x95002ccc, 0x95004926, 0x9509be55, 0x950c0a1b },	\
+	{ 196, 0x95002ccc, 0x9500492a, 0x9509be55, 0x950c0a23 },	\
+	{ 208, 0x95002ccc, 0x9500493a, 0x9509be55, 0x950c0a13 },	\
+	{ 212, 0x95002ccc, 0x9500493e, 0x9509be55, 0x950c0a1b },	\
+	{ 216, 0x95002ccc, 0x95004982, 0x9509be55, 0x950c0a23 }
+
+#define	RT3070_RF3052		\
 	{ 0xf1, 2,  2 },	\
 	{ 0xf1, 2,  7 },	\
 	{ 0xf2, 2,  2 },	\
@@ -1154,11 +1204,121 @@ static const struct rt2860_rate {
 	{ 0x61, 0,  7 },	\
 	{ 0x61, 0,  9 }
 
-#define RT3070_DEF_RF	\
+#define	RT5592_RF5592_20MHZ	\
+	{ 0x1e2,  4, 10, 3 },	\
+	{ 0x1e3,  4, 10, 3 },	\
+	{ 0x1e4,  4, 10, 3 },	\
+	{ 0x1e5,  4, 10, 3 },	\
+	{ 0x1e6,  4, 10, 3 },	\
+	{ 0x1e7,  4, 10, 3 },	\
+	{ 0x1e8,  4, 10, 3 },	\
+	{ 0x1e9,  4, 10, 3 },	\
+	{ 0x1ea,  4, 10, 3 },	\
+	{ 0x1eb,  4, 10, 3 },	\
+	{ 0x1ec,  4, 10, 3 },	\
+	{ 0x1ed,  4, 10, 3 },	\
+	{ 0x1ee,  4, 10, 3 },	\
+	{ 0x1f0,  8, 10, 3 },	\
+	{  0xac,  8, 12, 1 },	\
+	{  0xad,  0, 12, 1 },	\
+	{  0xad,  4, 12, 1 },	\
+	{  0xae,  0, 12, 1 },	\
+	{  0xae,  4, 12, 1 },	\
+	{  0xae,  8, 12, 1 },	\
+	{  0xaf,  4, 12, 1 },	\
+	{  0xaf,  8, 12, 1 },	\
+	{  0xb0,  0, 12, 1 },	\
+	{  0xb0,  8, 12, 1 },	\
+	{  0xb1,  0, 12, 1 },	\
+	{  0xb1,  4, 12, 1 },	\
+	{  0xb7,  4, 12, 1 },	\
+	{  0xb7,  8, 12, 1 },	\
+	{  0xb8,  0, 12, 1 },	\
+	{  0xb8,  8, 12, 1 },	\
+	{  0xb9,  0, 12, 1 },	\
+	{  0xb9,  4, 12, 1 },	\
+	{  0xba,  0, 12, 1 },	\
+	{  0xba,  4, 12, 1 },	\
+	{  0xba,  8, 12, 1 },	\
+	{  0xbb,  4, 12, 1 },	\
+	{  0xbb,  8, 12, 1 },	\
+	{  0xbc,  0, 12, 1 },	\
+	{  0xbc,  8, 12, 1 },	\
+	{  0xbd,  0, 12, 1 },	\
+	{  0xbd,  4, 12, 1 },	\
+	{  0xbe,  0, 12, 1 },	\
+	{  0xbf,  6, 12, 1 },	\
+	{  0xbf, 10, 12, 1 },	\
+	{  0xc0,  2, 12, 1 },	\
+	{  0xc0, 10, 12, 1 },	\
+	{  0xc1,  2, 12, 1 },	\
+	{  0xc1,  6, 12, 1 },	\
+	{  0xc2,  2, 12, 1 },	\
+	{  0xa4,  0, 12, 1 },	\
+	{  0xa4,  4, 12, 1 },	\
+	{  0xa5,  8, 12, 1 },	\
+	{  0xa6,  0, 12, 1 }
+
+#define	RT5592_RF5592_40MHZ	\
+	{ 0xf1,  2, 10, 3 },	\
+	{ 0xf1,  7, 10, 3 },	\
+	{ 0xf2,  2, 10, 3 },	\
+	{ 0xf2,  7, 10, 3 },	\
+	{ 0xf3,  2, 10, 3 },	\
+	{ 0xf3,  7, 10, 3 },	\
+	{ 0xf4,  2, 10, 3 },	\
+	{ 0xf4,  7, 10, 3 },	\
+	{ 0xf5,  2, 10, 3 },	\
+	{ 0xf5,  7, 10, 3 },	\
+	{ 0xf6,  2, 10, 3 },	\
+	{ 0xf6,  7, 10, 3 },	\
+	{ 0xf7,  2, 10, 3 },	\
+	{ 0xf8,  4, 10, 3 },	\
+	{ 0x56,  4, 12, 1 },	\
+	{ 0x56,  6, 12, 1 },	\
+	{ 0x56,  8, 12, 1 },	\
+	{ 0x57,  0, 12, 1 },	\
+	{ 0x57,  2, 12, 1 },	\
+	{ 0x57,  4, 12, 1 },	\
+	{ 0x57,  8, 12, 1 },	\
+	{ 0x57, 10, 12, 1 },	\
+	{ 0x58,  0, 12, 1 },	\
+	{ 0x58,  4, 12, 1 },	\
+	{ 0x58,  6, 12, 1 },	\
+	{ 0x58,  8, 12, 1 },	\
+	{ 0x5b,  8, 12, 1 },	\
+	{ 0x5b, 10, 12, 1 },	\
+	{ 0x5c,  0, 12, 1 },	\
+	{ 0x5c,  4, 12, 1 },	\
+	{ 0x5c,  6, 12, 1 },	\
+	{ 0x5c,  8, 12, 1 },	\
+	{ 0x5d,  0, 12, 1 },	\
+	{ 0x5d,  2, 12, 1 },	\
+	{ 0x5d,  4, 12, 1 },	\
+	{ 0x5d,  8, 12, 1 },	\
+	{ 0x5d, 10, 12, 1 },	\
+	{ 0x5e,  0, 12, 1 },	\
+	{ 0x5e,  4, 12, 1 },	\
+	{ 0x5e,  6, 12, 1 },	\
+	{ 0x5e,  8, 12, 1 },	\
+	{ 0x5f,  0, 12, 1 },	\
+	{ 0x5f,  9, 12, 1 },	\
+	{ 0x5f, 11, 12, 1 },	\
+	{ 0x60,  1, 12, 1 },	\
+	{ 0x60,  5, 12, 1 },	\
+	{ 0x60,  7, 12, 1 },	\
+	{ 0x60,  9, 12, 1 },	\
+	{ 0x61,  1, 12, 1 },	\
+	{ 0x52,  0, 12, 1 },	\
+	{ 0x52,  4, 12, 1 },	\
+	{ 0x52,  8, 12, 1 },	\
+	{ 0x53,  0, 12, 1 }
+
+#define	RT3070_DEF_RF	\
 	{  4, 0x40 },	\
 	{  5, 0x03 },	\
 	{  6, 0x02 },	\
-	{  7, 0x70 },	\
+	{  7, 0x60 },	\
 	{  9, 0x0f },	\
 	{ 10, 0x41 },	\
 	{ 11, 0x21 },	\
@@ -1172,10 +1332,10 @@ static const struct rt2860_rate {
 	{ 20, 0xba },	\
 	{ 21, 0xdb },	\
 	{ 24, 0x16 },	\
-	{ 25, 0x01 },	\
+	{ 25, 0x03 },	\
 	{ 29, 0x1f }
 
-#define RT3572_DEF_RF	\
+#define	RT3572_DEF_RF	\
 	{  0, 0x70 },	\
 	{  1, 0x81 },	\
 	{  2, 0xf1 },	\
@@ -1208,6 +1368,280 @@ static const struct rt2860_rate {
 	{ 30, 0x09 },	\
 	{ 31, 0x10 }
 
+#define	RT3593_DEF_RF	\
+	{  1, 0x03 },	\
+	{  3, 0x80 },	\
+	{  5, 0x00 },	\
+	{  6, 0x40 },	\
+	{  8, 0xf1 },	\
+	{  9, 0x02 },	\
+	{ 10, 0xd3 },	\
+	{ 11, 0x40 },	\
+	{ 12, 0x4e },	\
+	{ 13, 0x12 },	\
+	{ 18, 0x40 },	\
+	{ 22, 0x20 },	\
+	{ 30, 0x10 },	\
+	{ 31, 0x80 },	\
+	{ 32, 0x78 },	\
+	{ 33, 0x3b },	\
+	{ 34, 0x3c },	\
+	{ 35, 0xe0 },	\
+	{ 38, 0x86 },	\
+	{ 39, 0x23 },	\
+	{ 44, 0xd3 },	\
+	{ 45, 0xbb },	\
+	{ 46, 0x60 },	\
+	{ 49, 0x81 },	\
+	{ 50, 0x86 },	\
+	{ 51, 0x75 },	\
+	{ 52, 0x45 },	\
+	{ 53, 0x18 },	\
+	{ 54, 0x18 },	\
+	{ 55, 0x18 },	\
+	{ 56, 0xdb },	\
+	{ 57, 0x6e }
+
+#define	RT5390_DEF_RF	\
+	{  1, 0x0f },	\
+	{  2, 0x80 },	\
+	{  3, 0x88 },	\
+	{  5, 0x10 },	\
+	{  6, 0xa0 },	\
+	{  7, 0x00 },	\
+	{ 10, 0x53 },	\
+	{ 11, 0x4a },	\
+	{ 12, 0x46 },	\
+	{ 13, 0x9f },	\
+	{ 14, 0x00 },	\
+	{ 15, 0x00 },	\
+	{ 16, 0x00 },	\
+	{ 18, 0x03 },	\
+	{ 19, 0x00 },	\
+	{ 20, 0x00 },	\
+	{ 21, 0x00 },	\
+	{ 22, 0x20 },  	\
+	{ 23, 0x00 },	\
+	{ 24, 0x00 },	\
+	{ 25, 0xc0 },	\
+	{ 26, 0x00 },	\
+	{ 27, 0x09 },	\
+	{ 28, 0x00 },	\
+	{ 29, 0x10 },	\
+	{ 30, 0x10 },	\
+	{ 31, 0x80 },	\
+	{ 32, 0x80 },	\
+	{ 33, 0x00 },	\
+	{ 34, 0x07 },	\
+	{ 35, 0x12 },	\
+	{ 36, 0x00 },	\
+	{ 37, 0x08 },	\
+	{ 38, 0x85 },	\
+	{ 39, 0x1b },	\
+	{ 40, 0x0b },	\
+	{ 41, 0xbb },	\
+	{ 42, 0xd2 },	\
+	{ 43, 0x9a },	\
+	{ 44, 0x0e },	\
+	{ 45, 0xa2 },	\
+	{ 46, 0x7b },	\
+	{ 47, 0x00 },	\
+	{ 48, 0x10 },	\
+	{ 49, 0x94 },	\
+	{ 52, 0x38 },	\
+	{ 53, 0x84 },	\
+	{ 54, 0x78 },	\
+	{ 55, 0x44 },	\
+	{ 56, 0x22 },	\
+	{ 57, 0x80 },	\
+	{ 58, 0x7f },	\
+	{ 59, 0x8f },	\
+	{ 60, 0x45 },	\
+	{ 61, 0xdd },	\
+	{ 62, 0x00 },	\
+	{ 63, 0x00 }
+
+#define	RT5392_DEF_RF	\
+	{  1, 0x17 },	\
+	{  3, 0x88 },	\
+	{  5, 0x10 },	\
+	{  6, 0xe0 },	\
+	{  7, 0x00 },	\
+	{ 10, 0x53 },	\
+	{ 11, 0x4a },	\
+	{ 12, 0x46 },	\
+	{ 13, 0x9f },	\
+	{ 14, 0x00 },	\
+	{ 15, 0x00 },	\
+	{ 16, 0x00 },	\
+	{ 18, 0x03 },	\
+	{ 19, 0x4d },	\
+	{ 20, 0x00 },	\
+	{ 21, 0x8d },	\
+	{ 22, 0x20 },  	\
+	{ 23, 0x0b },	\
+	{ 24, 0x44 },	\
+	{ 25, 0x80 },	\
+	{ 26, 0x82 },	\
+	{ 27, 0x09 },	\
+	{ 28, 0x00 },	\
+	{ 29, 0x10 },	\
+	{ 30, 0x10 },	\
+	{ 31, 0x80 },	\
+	{ 32, 0x20 },	\
+	{ 33, 0xc0 },	\
+	{ 34, 0x07 },	\
+	{ 35, 0x12 },	\
+	{ 36, 0x00 },	\
+	{ 37, 0x08 },	\
+	{ 38, 0x89 },	\
+	{ 39, 0x1b },	\
+	{ 40, 0x0f },	\
+	{ 41, 0xbb },	\
+	{ 42, 0xd5 },	\
+	{ 43, 0x9b },	\
+	{ 44, 0x0e },	\
+	{ 45, 0xa2 },	\
+	{ 46, 0x73 },	\
+	{ 47, 0x0c },	\
+	{ 48, 0x10 },	\
+	{ 49, 0x94 },	\
+	{ 50, 0x94 },	\
+	{ 51, 0x3a },	\
+	{ 52, 0x48 },	\
+	{ 53, 0x44 },	\
+	{ 54, 0x38 },	\
+	{ 55, 0x43 },	\
+	{ 56, 0xa1 },	\
+	{ 57, 0x00 },	\
+	{ 58, 0x39 },	\
+	{ 59, 0x07 },	\
+	{ 60, 0x45 },	\
+	{ 61, 0x91 },	\
+	{ 62, 0x39 },	\
+	{ 63, 0x07 }
+
+#define	RT5592_DEF_RF	\
+	{  1, 0x3f },	\
+	{  3, 0x08 },	\
+	{  5, 0x10 },	\
+	{  6, 0xe4 },	\
+	{  7, 0x00 },	\
+	{ 14, 0x00 },	\
+	{ 15, 0x00 },	\
+	{ 16, 0x00 },	\
+	{ 18, 0x03 },	\
+	{ 19, 0x4d },	\
+	{ 20, 0x10 },	\
+	{ 21, 0x8d },	\
+	{ 26, 0x82 },	\
+	{ 28, 0x00 },	\
+	{ 29, 0x10 },	\
+	{ 33, 0xc0 },	\
+	{ 34, 0x07 },	\
+	{ 35, 0x12 },	\
+	{ 47, 0x0c },	\
+	{ 53, 0x22 },	\
+	{ 63, 0x07 }
+
+#define	RT5592_2GHZ_DEF_RF	\
+	{ 10, 0x90 },		\
+	{ 11, 0x4a },		\
+	{ 12, 0x52 },		\
+	{ 13, 0x42 },		\
+	{ 22, 0x40 },		\
+	{ 24, 0x4a },		\
+	{ 25, 0x80 },		\
+	{ 27, 0x42 },		\
+	{ 36, 0x80 },		\
+	{ 37, 0x08 },		\
+	{ 38, 0x89 },		\
+	{ 39, 0x1b },		\
+	{ 40, 0x0d },		\
+	{ 41, 0x9b },		\
+	{ 42, 0xd5 },		\
+	{ 43, 0x72 },		\
+	{ 44, 0x0e },		\
+	{ 45, 0xa2 },		\
+	{ 46, 0x6b },		\
+	{ 48, 0x10 },		\
+	{ 51, 0x3e },		\
+	{ 52, 0x48 },		\
+	{ 54, 0x38 },		\
+	{ 56, 0xa1 },		\
+	{ 57, 0x00 },		\
+	{ 58, 0x39 },		\
+	{ 60, 0x45 },		\
+	{ 61, 0x91 },		\
+	{ 62, 0x39 }
+
+#define	RT5592_5GHZ_DEF_RF	\
+	{ 10, 0x97 },		\
+	{ 11, 0x40 },		\
+	{ 25, 0xbf },		\
+	{ 27, 0x42 },		\
+	{ 36, 0x00 },		\
+	{ 37, 0x04 },		\
+	{ 38, 0x85 },		\
+	{ 40, 0x42 },		\
+	{ 41, 0xbb },		\
+	{ 42, 0xd7 },		\
+	{ 45, 0x41 },		\
+	{ 48, 0x00 },		\
+	{ 57, 0x77 },		\
+	{ 60, 0x05 },		\
+	{ 61, 0x01 }
+
+#define	RT5592_CHAN_5GHZ	\
+	{  36,  64, 12, 0x2e },	\
+	{ 100, 165, 12, 0x0e },	\
+	{  36,  64, 13, 0x22 },	\
+	{ 100, 165, 13, 0x42 },	\
+	{  36,  64, 22, 0x60 },	\
+	{ 100, 165, 22, 0x40 },	\
+	{  36,  64, 23, 0x7f },	\
+	{ 100, 153, 23, 0x3c },	\
+	{ 155, 165, 23, 0x38 },	\
+	{  36,  50, 24, 0x09 },	\
+	{  52,  64, 24, 0x07 },	\
+	{ 100, 153, 24, 0x06 },	\
+	{ 155, 165, 24, 0x05 },	\
+	{  36,  64, 39, 0x1c },	\
+	{ 100, 138, 39, 0x1a },	\
+	{ 140, 165, 39, 0x18 },	\
+	{  36,  64, 43, 0x5b },	\
+	{ 100, 138, 43, 0x3b },	\
+	{ 140, 165, 43, 0x1b },	\
+	{  36,  64, 44, 0x40 },	\
+	{ 100, 138, 44, 0x20 },	\
+	{ 140, 165, 44, 0x10 },	\
+	{  36,  64, 46, 0x00 },	\
+	{ 100, 138, 46, 0x18 },	\
+	{ 140, 165, 46, 0x08 },	\
+	{  36,  64, 51, 0xfe },	\
+	{ 100, 124, 51, 0xfc },	\
+	{ 126, 165, 51, 0xec },	\
+	{  36,  64, 52, 0x0c },	\
+	{ 100, 138, 52, 0x06 },	\
+	{ 140, 165, 52, 0x06 },	\
+	{  36,  64, 54, 0xf8 },	\
+	{ 100, 165, 54, 0xeb },	\
+	{ 36,   50, 55, 0x06 },	\
+	{ 52,   64, 55, 0x04 },	\
+	{ 100, 138, 55, 0x01 },	\
+	{ 140, 165, 55, 0x00 },	\
+	{  36,  50, 56, 0xd3 },	\
+	{  52, 128, 56, 0xbb },	\
+	{ 130, 165, 56, 0xab },	\
+	{  36,  64, 58, 0x15 },	\
+	{ 100, 116, 58, 0x1d },	\
+	{ 118, 165, 58, 0x15 },	\
+	{  36,  64, 59, 0x7f },	\
+	{ 100, 138, 59, 0x3f },	\
+	{ 140, 165, 59, 0x7c },	\
+	{  36,  64, 62, 0x15 },	\
+	{ 100, 116, 62, 0x1d },	\
+	{ 118, 165, 62, 0x15 }
 
 union run_stats {
 	uint32_t	raw;
diff --git a/sys/bus/u4b/wlan/if_runvar.h b/sys/bus/u4b/wlan/if_runvar.h
index aa9ac95..f7e0240 100644
--- a/sys/bus/u4b/wlan/if_runvar.h
+++ b/sys/bus/u4b/wlan/if_runvar.h
@@ -17,37 +17,31 @@
  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  *
- * $FreeBSD: src/sys/dev/usb/wlan/if_runvar.h,v 1.10 2013/02/11 00:34:54 svnexp Exp $
+ * $FreeBSD: head/sys/dev/usb/wlan/if_runvar.h 262465 2014-02-25 01:42:02Z kevlo $
  */
 
 #ifndef _IF_RUNVAR_H_
 #define	_IF_RUNVAR_H_
 
-#define RUN_MAX_RXSZ			\
+#define	RUN_MAX_RXSZ			\
 	MIN(4096, MJUMPAGESIZE)
-#if 0
-	(sizeof (uint32_t) +		\
-	 sizeof (struct rt2860_rxwi) +	\
-	 sizeof (uint16_t) +		\
-	 MCLBYTES +			\
-	 sizeof (struct rt2870_rxd))
-#endif
+
 /* NB: "11" is the maximum number of padding bytes needed for Tx */
-#define RUN_MAX_TXSZ			\
+#define	RUN_MAX_TXSZ			\
 	(sizeof (struct rt2870_txd) +	\
-	 sizeof (struct rt2860_rxwi) +	\
+	 sizeof (struct rt2860_txwi) +	\
 	 MCLBYTES + 11)
 
-#define RUN_TX_TIMEOUT	5000	/* ms */
+#define	RUN_TX_TIMEOUT	5000	/* ms */
 
 /* Tx ring count was 8/endpoint, now 32 for all 4 (or 6) endpoints. */
-#define RUN_TX_RING_COUNT	32
-#define RUN_RX_RING_COUNT	1
+#define	RUN_TX_RING_COUNT	32
+#define	RUN_RX_RING_COUNT	1
 
-#define RT2870_WCID_MAX		64
-#define RUN_AID2WCID(aid)	((aid) & 0xff)
+#define	RT2870_WCID_MAX		64
+#define	RUN_AID2WCID(aid)	((aid) & 0xff)
 
-#define RUN_VAP_MAX		8
+#define	RUN_VAP_MAX		8
 
 struct run_rx_radiotap_header {
 	struct ieee80211_radiotap_header wr_ihdr;
@@ -58,9 +52,9 @@ struct run_rx_radiotap_header {
 	int8_t		wr_dbm_antsignal;
 	uint8_t		wr_antenna;
 	uint8_t		wr_antsignal;
-} __packed;
+} __packed __aligned(8);
 
-#define RUN_RX_RADIOTAP_PRESENT				\
+#define	RUN_RX_RADIOTAP_PRESENT				\
 	(1 << IEEE80211_RADIOTAP_FLAGS |		\
 	 1 << IEEE80211_RADIOTAP_RATE |			\
 	 1 << IEEE80211_RADIOTAP_CHANNEL |		\
@@ -75,11 +69,11 @@ struct run_tx_radiotap_header {
 	uint16_t	wt_chan_freq;
 	uint16_t	wt_chan_flags;
 	uint8_t		wt_hwqueue;
-} __packed;
+} __packed __aligned(8);
 
 #define IEEE80211_RADIOTAP_HWQUEUE 15
 
-#define RUN_TX_RADIOTAP_PRESENT				\
+#define	RUN_TX_RADIOTAP_PRESENT				\
 	(1 << IEEE80211_RADIOTAP_FLAGS |		\
 	 1 << IEEE80211_RADIOTAP_RATE |			\
 	 1 << IEEE80211_RADIOTAP_CHANNEL |		\
@@ -128,7 +122,7 @@ struct run_vap {
 
 	uint8_t				rvp_id;
 };
-#define RUN_VAP(vap)    ((struct run_vap *)(vap))
+#define	RUN_VAP(vap)	((struct run_vap *)(vap))
 
 /*
  * There are 7 bulk endpoints: 1 for RX
@@ -160,6 +154,11 @@ struct run_softc {
 	device_t			sc_dev;
 	struct usb_device		*sc_udev;
 	struct ifnet			*sc_ifp;
+	int				sc_need_fwload;
+
+	int				sc_flags;
+#define	RUN_FLAG_FWLOAD_NEEDED		0x01
+
 	uint16_t			wcid_stats[RT2870_WCID_MAX + 1][3];
 #define	RUN_TXCNT	0
 #define	RUN_SUCCESS	1
@@ -170,7 +169,7 @@ struct run_softc {
 
 	uint16_t			mac_ver;
 	uint16_t			mac_rev;
-	uint8_t				rf_rev;
+	uint16_t			rf_rev;
 	uint8_t				freq;
 	uint8_t				ntxchains;
 	uint8_t				nrxchains;
@@ -189,6 +188,7 @@ struct run_softc {
 	uint8_t				txmixgain_5ghz;
 	int8_t				txpow1[54];
 	int8_t				txpow2[54];
+	int8_t				txpow3[54];
 	int8_t				rssi_2ghz[3];
 	int8_t				rssi_5ghz[3];
 	uint8_t				lna[4];
@@ -212,19 +212,19 @@ struct run_softc {
 	struct task                     ratectl_task;
 	struct usb_callout              ratectl_ch;
 	uint8_t				ratectl_run;
-#define RUN_RATECTL_OFF	0
+#define	RUN_RATECTL_OFF	0
 
 /* need to be power of 2, otherwise RUN_CMDQ_GET fails */
-#define RUN_CMDQ_MAX	16
-#define RUN_CMDQ_MASQ	(RUN_CMDQ_MAX - 1)
+#define	RUN_CMDQ_MAX	16
+#define	RUN_CMDQ_MASQ	(RUN_CMDQ_MAX - 1)
 	struct run_cmdq			cmdq[RUN_CMDQ_MAX];
 	struct task			cmdq_task;
 	uint32_t			cmdq_store;
 	uint8_t				cmdq_exec;
 	uint8_t				cmdq_run;
 	uint8_t				cmdq_key_set;
-#define RUN_CMDQ_ABORT	0
-#define RUN_CMDQ_GO	1
+#define	RUN_CMDQ_ABORT	0
+#define	RUN_CMDQ_GO	1
 
 	struct usb_xfer			*sc_xfer[RUN_N_XFER];
 
@@ -256,8 +256,8 @@ struct run_softc {
 	int				sc_txtap_len;
 };
 
-#define RUN_LOCK(sc)		lockmgr(&(sc)->sc_lock, LK_EXCLUSIVE)
-#define RUN_UNLOCK(sc)		lockmgr(&(sc)->sc_lock, LK_RELEASE)
-#define RUN_LOCK_ASSERT(sc, t)	KKASSERT(lockstatus(&(sc)->sc_lock, curthread) != 0)
+#define	RUN_LOCK(sc)		lockmgr(&(sc)->sc_lock, LK_EXCLUSIVE)
+#define	RUN_UNLOCK(sc)		lockmgr(&(sc)->sc_lock, LK_RELEASE)
+#define	RUN_LOCK_ASSERT(sc, t)	KKASSERT(lockstatus(&(sc)->sc_lock, curthread) != 0)
 
 #endif	/* _IF_RUNVAR_H_ */
-- 
1.8.2.2

