From 09143011d9c7e41095d38a2e088af7b4e9b56efb Mon Sep 17 00:00:00 2001
From: Sascha Wildner <saw@online.de>
Date: Sun, 19 Jun 2011 21:54:34 +0200
Subject: [PATCH 05/18] hwpmc: Bring in the rest (driver, headers, utils) from FreeBSD unchanged.

---
 share/examples/hwpmc/README        |    7 +
 share/man/man4/hwpmc.4             |  833 ++++++
 sys/cpu/i386/include/pmc_mdep.h    |  169 ++
 sys/cpu/x86_64/include/pmc_mdep.h  |  134 +
 sys/dev/misc/hwpmc/Makefile        |   39 +
 sys/dev/misc/hwpmc/hwpmc_amd.c     | 1037 ++++++++
 sys/dev/misc/hwpmc/hwpmc_amd.h     |   97 +
 sys/dev/misc/hwpmc/hwpmc_core.c    | 2268 +++++++++++++++++
 sys/dev/misc/hwpmc/hwpmc_core.h    |  190 ++
 sys/dev/misc/hwpmc/hwpmc_intel.c   |  311 +++
 sys/dev/misc/hwpmc/hwpmc_logging.c | 1024 ++++++++
 sys/dev/misc/hwpmc/hwpmc_mod.c     | 4949 ++++++++++++++++++++++++++++++++++++
 sys/dev/misc/hwpmc/hwpmc_pentium.c |   57 +
 sys/dev/misc/hwpmc/hwpmc_pentium.h |   73 +
 sys/dev/misc/hwpmc/hwpmc_piv.c     | 1698 +++++++++++++
 sys/dev/misc/hwpmc/hwpmc_piv.h     |  125 +
 sys/dev/misc/hwpmc/hwpmc_ppro.c    |  866 +++++++
 sys/dev/misc/hwpmc/hwpmc_ppro.h    |   84 +
 sys/dev/misc/hwpmc/hwpmc_tsc.c     |  388 +++
 sys/dev/misc/hwpmc/hwpmc_tsc.h     |   43 +
 sys/dev/misc/hwpmc/hwpmc_uncore.c  | 1121 ++++++++
 sys/dev/misc/hwpmc/hwpmc_uncore.h  |  120 +
 sys/dev/misc/hwpmc/hwpmc_x86.c     |  271 ++
 sys/dev/misc/hwpmc/pmc_events.h    | 3145 +++++++++++++++++++++++
 sys/kern/kern_pmc.c                |  184 ++
 sys/sys/pmc.h                      | 1064 ++++++++
 sys/sys/pmckern.h                  |  140 +
 sys/sys/pmclog.h                   |  269 ++
 usr.sbin/pmcannotate/Makefile      |   10 +
 usr.sbin/pmcannotate/pmcannotate.8 |  109 +
 usr.sbin/pmcannotate/pmcannotate.c |  804 ++++++
 usr.sbin/pmccontrol/Makefile       |   13 +
 usr.sbin/pmccontrol/pmccontrol.8   |  127 +
 usr.sbin/pmccontrol/pmccontrol.c   |  501 ++++
 usr.sbin/pmcstat/Makefile          |   14 +
 usr.sbin/pmcstat/pmcpl_annotate.c  |  111 +
 usr.sbin/pmcstat/pmcpl_annotate.h  |   41 +
 usr.sbin/pmcstat/pmcpl_callgraph.c |  686 +++++
 usr.sbin/pmcstat/pmcpl_callgraph.h |   67 +
 usr.sbin/pmcstat/pmcpl_calltree.c  | 1044 ++++++++
 usr.sbin/pmcstat/pmcpl_calltree.h  |   42 +
 usr.sbin/pmcstat/pmcpl_gprof.c     |  535 ++++
 usr.sbin/pmcstat/pmcpl_gprof.h     |   47 +
 usr.sbin/pmcstat/pmcstat.8         |  456 ++++
 usr.sbin/pmcstat/pmcstat.c         | 1449 +++++++++++
 usr.sbin/pmcstat/pmcstat.h         |  184 ++
 usr.sbin/pmcstat/pmcstat_log.c     | 2177 ++++++++++++++++
 usr.sbin/pmcstat/pmcstat_log.h     |  198 ++
 usr.sbin/pmcstat/pmcstat_top.h     |   75 +
 49 files changed, 29396 insertions(+), 0 deletions(-)
 create mode 100644 share/examples/hwpmc/README
 create mode 100644 share/man/man4/hwpmc.4
 create mode 100644 sys/cpu/i386/include/pmc_mdep.h
 create mode 100644 sys/cpu/x86_64/include/pmc_mdep.h
 create mode 100644 sys/dev/misc/hwpmc/Makefile
 create mode 100644 sys/dev/misc/hwpmc/hwpmc_amd.c
 create mode 100644 sys/dev/misc/hwpmc/hwpmc_amd.h
 create mode 100644 sys/dev/misc/hwpmc/hwpmc_core.c
 create mode 100644 sys/dev/misc/hwpmc/hwpmc_core.h
 create mode 100644 sys/dev/misc/hwpmc/hwpmc_intel.c
 create mode 100644 sys/dev/misc/hwpmc/hwpmc_logging.c
 create mode 100644 sys/dev/misc/hwpmc/hwpmc_mod.c
 create mode 100644 sys/dev/misc/hwpmc/hwpmc_pentium.c
 create mode 100644 sys/dev/misc/hwpmc/hwpmc_pentium.h
 create mode 100644 sys/dev/misc/hwpmc/hwpmc_piv.c
 create mode 100644 sys/dev/misc/hwpmc/hwpmc_piv.h
 create mode 100644 sys/dev/misc/hwpmc/hwpmc_ppro.c
 create mode 100644 sys/dev/misc/hwpmc/hwpmc_ppro.h
 create mode 100644 sys/dev/misc/hwpmc/hwpmc_tsc.c
 create mode 100644 sys/dev/misc/hwpmc/hwpmc_tsc.h
 create mode 100644 sys/dev/misc/hwpmc/hwpmc_uncore.c
 create mode 100644 sys/dev/misc/hwpmc/hwpmc_uncore.h
 create mode 100644 sys/dev/misc/hwpmc/hwpmc_x86.c
 create mode 100644 sys/dev/misc/hwpmc/pmc_events.h
 create mode 100644 sys/kern/kern_pmc.c
 create mode 100644 sys/sys/pmc.h
 create mode 100644 sys/sys/pmckern.h
 create mode 100644 sys/sys/pmclog.h
 create mode 100644 usr.sbin/pmcannotate/Makefile
 create mode 100644 usr.sbin/pmcannotate/pmcannotate.8
 create mode 100644 usr.sbin/pmcannotate/pmcannotate.c
 create mode 100644 usr.sbin/pmccontrol/Makefile
 create mode 100644 usr.sbin/pmccontrol/pmccontrol.8
 create mode 100644 usr.sbin/pmccontrol/pmccontrol.c
 create mode 100644 usr.sbin/pmcstat/Makefile
 create mode 100644 usr.sbin/pmcstat/pmcpl_annotate.c
 create mode 100644 usr.sbin/pmcstat/pmcpl_annotate.h
 create mode 100644 usr.sbin/pmcstat/pmcpl_callgraph.c
 create mode 100644 usr.sbin/pmcstat/pmcpl_callgraph.h
 create mode 100644 usr.sbin/pmcstat/pmcpl_calltree.c
 create mode 100644 usr.sbin/pmcstat/pmcpl_calltree.h
 create mode 100644 usr.sbin/pmcstat/pmcpl_gprof.c
 create mode 100644 usr.sbin/pmcstat/pmcpl_gprof.h
 create mode 100644 usr.sbin/pmcstat/pmcstat.8
 create mode 100644 usr.sbin/pmcstat/pmcstat.c
 create mode 100644 usr.sbin/pmcstat/pmcstat.h
 create mode 100644 usr.sbin/pmcstat/pmcstat_log.c
 create mode 100644 usr.sbin/pmcstat/pmcstat_log.h
 create mode 100644 usr.sbin/pmcstat/pmcstat_top.h

diff --git a/share/examples/hwpmc/README b/share/examples/hwpmc/README
new file mode 100644
index 0000000..f339daf
--- /dev/null
+++ b/share/examples/hwpmc/README
@@ -0,0 +1,7 @@
+# $FreeBSD: src/share/examples/hwpmc/README,v 1.1 2005/04/19 04:01:22 jkoshy Exp $
+
+Examples illustrating the use of the hwpmc(4) driver and pmc(3)
+library interface.
+
+While there is nothing here yet, the source code for pmccontrol(8)
+and pmcstat(8) could serve as examples.
diff --git a/share/man/man4/hwpmc.4 b/share/man/man4/hwpmc.4
new file mode 100644
index 0000000..a7990c9
--- /dev/null
+++ b/share/man/man4/hwpmc.4
@@ -0,0 +1,833 @@
+.\" Copyright (c) 2003-2008 Joseph Koshy
+.\" Copyright (c) 2007 The FreeBSD Foundation
+.\" All rights reserved.
+.\"
+.\" Portions of this software were developed by A. Joseph Koshy under
+.\" sponsorship from the FreeBSD Foundation and Google, Inc.
+.\"
+.\" Redistribution and use in source and binary forms, with or without
+.\" modification, are permitted provided that the following conditions
+.\" are met:
+.\" 1. Redistributions of source code must retain the above copyright
+.\"    notice, this list of conditions and the following disclaimer.
+.\" 2. Redistributions in binary form must reproduce the above copyright
+.\"    notice, this list of conditions and the following disclaimer in the
+.\"    documentation and/or other materials provided with the distribution.
+.\"
+.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+.\" ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+.\" SUCH DAMAGE.
+.\"
+.\" $FreeBSD: src/share/man/man4/hwpmc.4,v 1.25 2010/08/16 15:18:30 joel Exp $
+.\"
+.Dd September 22, 2008
+.Dt HWPMC 4
+.Os
+.Sh NAME
+.Nm hwpmc
+.Nd "Hardware Performance Monitoring Counter support"
+.Sh SYNOPSIS
+.Cd "options HWPMC_HOOKS"
+.Cd "device hwpmc"
+.Pp
+Additionally, for i386 systems:
+.Cd "device apic"
+.Sh DESCRIPTION
+The
+.Nm
+driver virtualizes the hardware performance monitoring facilities in
+modern CPUs and provides support for using these facilities from
+user level processes.
+.Pp
+The driver supports multi-processor systems.
+.Pp
+PMCs are allocated using the
+.Dv PMC_OP_PMCALLOCATE
+request.
+A successful
+.Dv PMC_OP_PMCALLOCATE
+request will return a handle to the requesting process.
+Subsequent operations on the allocated PMC use this handle to denote
+the specific PMC.
+A process that has successfully allocated a PMC is termed an
+.Dq "owner process" .
+.Pp
+PMCs may be allocated with process or system scope.
+.Bl -tag -width ".Em Process-scope"
+.It Em "Process-scope"
+The PMC is active only when a thread belonging
+to a process it is attached to is scheduled on a CPU.
+.It Em "System-scope"
+The PMC operates independently of processes and
+measures hardware events for the system as a whole.
+.El
+.Pp
+PMCs may be allocated for counting or for sampling:
+.Bl -tag -width ".Em Counting"
+.It Em Counting
+In counting modes, the PMCs count hardware events.
+These counts are retrievable using the
+.Dv PMC_OP_PMCREAD
+system call on all architectures.
+Some architectures offer faster methods of reading these counts.
+.It Em Sampling
+In sampling modes, the PMCs are configured to sample the CPU
+instruction pointer (and optionally to capture the call chain leading
+up to the sampled instruction pointer) after a configurable number of
+hardware events have been observed.
+Instruction pointer samples and call chain records are usually
+directed to a log file for subsequent analysis.
+.El
+.Pp
+Scope and operational mode are orthogonal; a PMC may thus be
+configured to operate in one of the following four modes:
+.Bl -tag -width indent
+.It Process-scope, counting
+These PMCs count hardware events whenever a thread in their attached process is
+scheduled on a CPU.
+These PMCs normally count from zero, but the initial count may be
+set using the
+.Dv PMC_OP_SETCOUNT
+operation.
+Applications can read the value of the PMC anytime using the
+.Dv PMC_OP_PMCRW
+operation.
+.It Process-scope, sampling
+These PMCs sample the target processes instruction pointer after they
+have seen the configured number of hardware events.
+The PMCs only count events when a thread belonging to their attached
+process is active.
+The desired frequency of sampling is set using the
+.Dv PMC_OP_SETCOUNT
+operation prior to starting the PMC.
+Log files are configured using the
+.Dv PMC_OP_CONFIGURELOG
+operation.
+.It System-scope, counting
+These PMCs count hardware events seen by them independent of the
+processes that are executing.
+The current count on these PMCs can be read using the
+.Dv PMC_OP_PMCRW
+request.
+These PMCs normally count from zero, but the initial count may be
+set using the
+.Dv PMC_OP_SETCOUNT
+operation.
+.It System-scope, sampling
+These PMCs will periodically sample the instruction pointer of the CPU
+they are allocated on, and will write the sample to a log for further
+processing.
+The desired frequency of sampling is set using the
+.Dv PMC_OP_SETCOUNT
+operation prior to starting the PMC.
+Log files are configured using the
+.Dv PMC_OP_CONFIGURELOG
+operation.
+.Pp
+System-wide statistical sampling can only be enabled by a process with
+super-user privileges.
+.El
+.Pp
+Processes are allowed to allocate as many PMCs as the hardware and
+current operating conditions permit.
+Processes may mix allocations of system-wide and process-private
+PMCs.
+Multiple processes may be using PMCs simultaneously.
+.Pp
+Allocated PMCs are started using the
+.Dv PMC_OP_PMCSTART
+operation, and stopped using the
+.Dv PMC_OP_PMCSTOP
+operation.
+Stopping and starting a PMC is permitted at any time the owner process
+has a valid handle to the PMC.
+.Pp
+Process-private PMCs need to be attached to a target process before
+they can be used.
+Attaching a process to a PMC is done using the
+.Dv PMC_OP_PMCATTACH
+operation.
+An already attached PMC may be detached from its target process
+using the converse
+.Dv PMC_OP_PMCDETACH
+operation.
+Issuing a
+.Dv PMC_OP_PMCSTART
+operation on an as yet unattached PMC will cause it to be attached
+to its owner process.
+The following rules determine whether a given process may attach
+a PMC to another target process:
+.Bl -bullet -compact
+.It
+A non-jailed process with super-user privileges is allowed to attach
+to any other process in the system.
+.It
+Other processes are only allowed to attach to targets that they would
+be able to attach to for debugging (as determined by
+.Xr p_candebug 9 ) .
+.El
+.Pp
+PMCs are released using
+.Dv PMC_OP_PMCRELEASE .
+After a successful
+.Dv PMC_OP_PMCRELEASE
+operation the handle to the PMC will become invalid.
+.Ss Modifier Flags
+The
+.Dv PMC_OP_PMCALLOCATE
+operation supports the following flags that modify the behavior
+of an allocated PMC:
+.Bl -tag -width indent
+.It Dv PMC_F_CALLCHAIN
+This modifier informs sampling PMCs to record a callchain when
+capturing a sample.
+The maximum depth to which call chains are recorded is specified
+by the
+.Va "kern.hwpmc.callchaindepth"
+kernel tunable.
+.It Dv PMC_F_DESCENDANTS
+This modifier is valid only for a PMC being allocated in process-private
+mode.
+It signifies that the PMC will track hardware events for its
+target process and the target's current and future descendants.
+.It Dv PMC_F_KGMON
+This modifier is valid only for a PMC being allocated in system-wide
+sampling mode.
+It signifies that the PMC's sampling interrupt is to be used to drive
+kernel profiling via
+.Xr kgmon 8 .
+This functionality is currently unimplemented.
+.It Dv PMC_F_LOG_PROCCSW
+This modifier is valid only for a PMC being allocated in process-private
+mode.
+When this modifier is present, at every context switch,
+.Nm
+will log a record containing the number of hardware events
+seen by the target process when it was scheduled on the CPU.
+.It Dv PMC_F_LOG_PROCEXIT
+This modifier is valid only for a PMC being allocated in process-private
+mode.
+With this modifier present,
+.Nm
+will maintain per-process counts for each target process attached to
+a PMC.
+At process exit time, a record containing the target process' PID and
+the accumulated per-process count for that process will be written to the
+configured log file.
+.El
+.Pp
+Modifiers
+.Dv PMC_F_LOG_PROCEXIT
+and
+.Dv PMC_F_LOG_PROCCSW
+may be used in combination with modifier
+.Dv PMC_F_DESCENDANTS
+to track the behavior of complex pipelines of processes.
+PMCs with modifiers
+.Dv PMC_F_LOG_PROCEXIT
+and
+.Dv PMC_F_LOG_PROCCSW
+cannot be started until their owner process has configured a log file.
+.Ss Signals
+The
+.Nm
+driver may deliver signals to processes that have allocated PMCs:
+.Bl -tag -width ".Dv SIGBUS"
+.It Dv SIGIO
+A
+.Dv PMC_OP_PMCRW
+operation was attempted on a process-private PMC that does not have
+attached target processes.
+.It Dv SIGBUS
+The
+.Nm
+driver is being unloaded from the kernel.
+.El
+.Ss PMC ROW DISPOSITIONS
+A PMC row is defined as the set of PMC resources at the same hardware
+address in the CPUs in a system.
+Since process scope PMCs need to move between CPUs following their
+target threads, allocation of a process scope PMC reserves all PMCs in
+a PMC row for use only with process scope PMCs.
+Accordingly a PMC row will be in one of the following dispositions:
+.Bl -tag -width ".Dv PMC_DISP_STANDALONE" -compact
+.It Dv PMC_DISP_FREE
+Hardware counters in this row are free and may be use to satisfy
+either of system scope or process scope allocation requests.
+.It Dv PMC_DISP_THREAD
+Hardware counters in this row are in use by process scope PMCs
+and are only available for process scope allocation requests.
+.It Dv PMC_DISP_STANDALONE
+Some hardware counters in this row have been administratively
+disabled or are in use by system scope PMCs.
+Non-disabled hardware counters in such a row may be used
+for satisfying system scope allocation requests.
+No process scope PMCs will use hardware counters in this row.
+.El
+.Sh PROGRAMMING API
+The recommended way for application programs to use the facilities of
+the
+.Nm
+driver is using the API provided by the
+.Xr pmc 3
+library.
+.Pp
+The
+.Nm
+driver operates using a system call number that is dynamically
+allotted to it when it is loaded into the kernel.
+.Pp
+The
+.Nm
+driver supports the following operations:
+.Bl -tag -width indent
+.It Dv PMC_OP_CONFIGURELOG
+Configure a log file for PMCs that require a log file.
+The
+.Nm
+driver will write log data to this file asynchronously.
+If it encounters an error, logging will be stopped and the error code
+encountered will be saved for subsequent retrieval by a
+.Dv PMC_OP_FLUSHLOG
+request.
+.It Dv PMC_OP_FLUSHLOG
+Transfer buffered log data inside
+.Nm
+to a configured output file.
+This operation returns to the caller after the write operation
+has returned.
+The returned error code reflects any pending error state inside
+.Nm .
+.It Dv PMC_OP_GETCPUINFO
+Retrieve information about the highest possible CPU number for the system,
+and the number of hardware performance monitoring counters available per CPU.
+.It Dv PMC_OP_GETDRIVERSTATS
+Retrieve module statistics (for analyzing the behavior of
+.Nm
+itself).
+.It Dv PMC_OP_GETMODULEVERSION
+Retrieve the version number of API.
+.It Dv PMC_OP_GETPMCINFO
+Retrieve information about the current state of the PMCs on a
+given CPU.
+.It Dv PMC_OP_PMCADMIN
+Set the administrative state (i.e., whether enabled or disabled) for
+the hardware PMCs managed by the
+.Nm
+driver.
+The invoking process needs to possess the
+.Dv PRIV_PMC_MANAGE
+privilege.
+.It Dv PMC_OP_PMCALLOCATE
+Allocate and configure a PMC.
+On successful allocation, a handle to the PMC (a 32 bit value)
+is returned.
+.It Dv PMC_OP_PMCATTACH
+Attach a process mode PMC to a target process.
+The PMC will be active whenever a thread in the target process is
+scheduled on a CPU.
+.Pp
+If the
+.Dv PMC_F_DESCENDANTS
+flag had been specified at PMC allocation time, then the PMC is
+attached to all current and future descendants of the target process.
+.It Dv PMC_OP_PMCDETACH
+Detach a PMC from its target process.
+.It Dv PMC_OP_PMCRELEASE
+Release a PMC.
+.It Dv PMC_OP_PMCRW
+Read and write a PMC.
+This operation is valid only for PMCs configured in counting modes.
+.It Dv PMC_OP_SETCOUNT
+Set the initial count (for counting mode PMCs) or the desired sampling
+rate (for sampling mode PMCs).
+.It Dv PMC_OP_PMCSTART
+Start a PMC.
+.It Dv PMC_OP_PMCSTOP
+Stop a PMC.
+.It Dv PMC_OP_WRITELOG
+Insert a timestamped user record into the log file.
+.El
+.Ss i386 Specific API
+Some i386 family CPUs support the RDPMC instruction which allows a
+user process to read a PMC value without needing to invoke a
+.Dv PMC_OP_PMCRW
+operation.
+On such CPUs, the machine address associated with an allocated PMC is
+retrievable using the
+.Dv PMC_OP_PMCX86GETMSR
+system call.
+.Bl -tag -width indent
+.It Dv PMC_OP_PMCX86GETMSR
+Retrieve the MSR (machine specific register) number associated with
+the given PMC handle.
+.Pp
+The PMC needs to be in process-private mode and allocated without the
+.Dv PMC_F_DESCENDANTS
+modifier flag, and should be attached only to its owner process at the
+time of the call.
+.El
+.Ss amd64 Specific API
+AMD64 CPUs support the RDPMC instruction which allows a
+user process to read a PMC value without needing to invoke a
+.Dv PMC_OP_PMCRW
+operation.
+The machine address associated with an allocated PMC is
+retrievable using the
+.Dv PMC_OP_PMCX86GETMSR
+system call.
+.Bl -tag -width indent
+.It Dv PMC_OP_PMCX86GETMSR
+Retrieve the MSR (machine specific register) number associated with
+the given PMC handle.
+.Pp
+The PMC needs to be in process-private mode and allocated without the
+.Dv PMC_F_DESCENDANTS
+modifier flag, and should be attached only to its owner process at the
+time of the call.
+.El
+.Sh SYSCTL VARIABLES AND LOADER TUNABLES
+The behavior of
+.Nm
+is influenced by the following
+.Xr sysctl 8
+and
+.Xr loader 8
+tunables:
+.Bl -tag -width indent
+.It Va kern.hwpmc.callchaindepth Pq integer, read-only
+The maximum number of call chain records to capture per sample.
+The default is 8.
+.It Va kern.hwpmc.debugflags Pq string, read-write
+(Only available if the
+.Nm
+driver was compiled with
+.Fl DDEBUG . )
+Control the verbosity of debug messages from the
+.Nm
+driver.
+.It Va kern.hwpmc.hashsize Pq integer, read-only
+The number of rows in the hash tables used to keep track of owner and
+target processes.
+The default is 16.
+.It Va kern.hwpmc.logbuffersize Pq integer, read-only
+The size in kilobytes of each log buffer used by
+.Nm Ns 's
+logging function.
+The default buffer size is 4KB.
+.It Va kern.hwpmc.mtxpoolsize Pq integer, read-only
+The size of the spin mutex pool used by the PMC driver.
+The default is 32.
+.It Va kern.hwpmc.nbuffers Pq integer, read-only
+The number of log buffers used by
+.Nm
+for logging.
+The default is 16.
+.It Va kern.hwpmc.nsamples Pq integer, read-only
+The number of entries in the per-CPU ring buffer used during sampling.
+The default is 16.
+.It Va security.bsd.unprivileged_syspmcs Pq boolean, read-write
+If set to non-zero, allow unprivileged processes to allocate system-wide
+PMCs.
+The default value is 0.
+.It Va security.bsd.unprivileged_proc_debug Pq boolean, read-write
+If set to 0, the
+.Nm
+driver will only allow privileged processes to attach PMCs to other
+processes.
+.El
+.Pp
+These variables may be set in the kernel environment using
+.Xr kenv 1
+before
+.Nm
+is loaded.
+.Sh IMPLEMENTATION NOTES
+.Ss SMP Symmetry
+The kernel driver requires all physical CPUs in an SMP system to have
+identical performance monitoring counter hardware.
+.Ss Sparse CPU Numbering
+On platforms that sparsely number CPUs and which support hot-plugging
+of CPUs, requests that specify non-existent or disabled CPUs will fail
+with an error.
+Applications allocating system-scope PMCs need to be aware of
+the possibility of such transient failures.
+.Ss x86 TSC Handling
+Historically, on the x86 architecture,
+.Fx
+has permitted user processes running at a processor CPL of 3 to
+read the TSC using the RDTSC instruction.
+The
+.Nm
+driver preserves this behavior.
+.Ss Intel P4/HTT Handling
+On CPUs with HTT support, Intel P4 PMCs are capable of qualifying
+only a subset of hardware events on a per-logical CPU basis.
+Consequently, if HTT is enabled on a system with Intel Pentium P4
+PMCs, then the
+.Nm
+driver will reject allocation requests for process-private PMCs that
+request counting of hardware events that cannot be counted separately
+for each logical CPU.
+.Ss Intel Pentium-Pro Handling
+Writing a value to the PMC MSRs found in Intel Pentium-Pro style PMCs
+(found in
+.Tn "Intel Pentium Pro" ,
+.Tn "Pentium II" ,
+.Tn "Pentium III" ,
+.Tn "Pentium M"
+and
+.Tn "Celeron"
+processors) will replicate bit 31 of the
+value being written into the upper 8 bits of the MSR,
+bringing down the usable width of these PMCs to 31 bits.
+For process-virtual PMCs, the
+.Nm
+driver implements a workaround in software and makes the corrected 64
+bit count available via the
+.Dv PMC_OP_RW
+operation.
+Processes that intend to use RDPMC instructions directly or
+that intend to write values larger than 2^31 into these PMCs with
+.Dv PMC_OP_RW
+need to be aware of this hardware limitation.
+.Sh DIAGNOSTICS
+.Bl -diag
+.It "hwpmc: [class/npmc/capabilities]..."
+Announce the presence of
+.Va npmc
+PMCs of class
+.Va class ,
+with capabilities described by bit string
+.Va capabilities .
+.It "hwpmc: kernel version (0x%x) does not match module version (0x%x)."
+The module loading process failed because a version mismatch was detected
+between the currently executing kernel and the module being loaded.
+.It "hwpmc: this kernel has not been compiled with 'options HWPMC_HOOKS'."
+The module loading process failed because the currently executing kernel
+was not configured with the required configuration option
+.Dv HWPMC_HOOKS .
+.It "hwpmc: tunable hashsize=%d must be greater than zero."
+A negative value was supplied for tunable
+.Va kern.hwpmc.hashsize .
+.It "hwpmc: tunable logbuffersize=%d must be greater than zero."
+A negative value was supplied for tunable
+.Va kern.hwpmc.logbuffersize .
+.It "hwpmc: tunable nlogbuffers=%d must be greater than zero."
+A negative value was supplied for tunable
+.Va kern.hwpmc.nlogbuffers .
+.It "hwpmc: tunable nsamples=%d out of range."
+The value for tunable
+.Va kern.hwpmc.nsamples
+was negative or greater than 65535.
+.El
+.Sh COMPATIBILITY
+The
+.Nm
+driver is
+.Ud
+The API and ABI documented in this manual page may change in
+the future.
+The recommended method of accessing this driver is using the
+.Xr pmc 3
+API.
+.Sh ERRORS
+A command issued to the
+.Nm
+driver may fail with the following errors:
+.Bl -tag -width Er
+.It Bq Er EAGAIN
+Helper process creation failed for a
+.Dv PMC_OP_CONFIGURELOG
+request due to a temporary resource shortage in the kernel.
+.It Bq Er EBUSY
+A
+.Dv PMC_OP_CONFIGURELOG
+operation was requested while an existing log was active.
+.It Bq Er EBUSY
+A DISABLE operation was requested using the
+.Dv PMC_OP_PMCADMIN
+request for a set of hardware resources currently in use for
+process-private PMCs.
+.It Bq Er EBUSY
+A
+.Dv PMC_OP_PMCADMIN
+operation was requested on an active system mode PMC.
+.It Bq Er EBUSY
+A
+.Dv PMC_OP_PMCATTACH
+operation was requested for a target process that already had another
+PMC using the same hardware resources attached to it.
+.It Bq Er EBUSY
+A
+.Dv PMC_OP_PMCRW
+request writing a new value was issued on a PMC that was active.
+.It Bq Er EBUSY
+A
+.Dv PMC_OP_PMCSETCOUNT
+request was issued on a PMC that was active.
+.It Bq Er EDOOFUS
+A
+.Dv PMC_OP_PMCSTART
+operation was requested without a log file being configured for a
+PMC allocated with
+.Dv PMC_F_LOG_PROCCSW
+and
+.Dv PMC_F_LOG_PROCEXIT
+modifiers.
+.It Bq Er EDOOFUS
+A
+.Dv PMC_OP_PMCSTART
+operation was requested on a system-wide sampling PMC without a log
+file being configured.
+.It Bq Er EEXIST
+A
+.Dv PMC_OP_PMCATTACH
+request was reissued for a target process that already is the target
+of this PMC.
+.It Bq Er EFAULT
+A bad address was passed in to the driver.
+.It Bq Er EINVAL
+An invalid PMC handle was specified.
+.It Bq Er EINVAL
+An invalid CPU number was passed in for a
+.Dv PMC_OP_GETPMCINFO
+operation.
+.It Bq Er EINVAL
+A
+.Dv PMC_OP_CONFIGURELOG
+request to de-configure a log file was issued without a log file
+being configured.
+.It Bq Er EINVAL
+A
+.Dv PMC_OP_FLUSHLOG
+request was issued without a log file being configured.
+.It Bq Er EINVAL
+An invalid CPU number was passed in for a
+.Dv PMC_OP_PMCADMIN
+operation.
+.It Bq Er EINVAL
+An invalid operation request was passed in for a
+.Dv PMC_OP_PMCADMIN
+operation.
+.It Bq Er EINVAL
+An invalid PMC ID was passed in for a
+.Dv PMC_OP_PMCADMIN
+operation.
+.It Bq Er EINVAL
+A suitable PMC matching the parameters passed in to a
+.Dv PMC_OP_PMCALLOCATE
+request could not be allocated.
+.It Bq Er EINVAL
+An invalid PMC mode was requested during a
+.Dv PMC_OP_PMCALLOCATE
+request.
+.It Bq Er EINVAL
+An invalid CPU number was specified during a
+.Dv PMC_OP_PMCALLOCATE
+request.
+.It Bq Er EINVAL
+A CPU other than
+.Dv PMC_CPU_ANY
+was specified in a
+.Dv PMC_OP_PMCALLOCATE
+request for a process-private PMC.
+.It Bq Er EINVAL
+A CPU number of
+.Dv PMC_CPU_ANY
+was specified in a
+.Dv PMC_OP_PMCALLOCATE
+request for a system-wide PMC.
+.It Bq Er EINVAL
+The
+.Ar pm_flags
+argument to an
+.Dv PMC_OP_PMCALLOCATE
+request contained unknown flags.
+.It Bq Er EINVAL
+(On Intel Pentium 4 CPUs with HTT support)
+A
+.Dv PMC_OP_PMCALLOCATE
+request for a process-private PMC was issued for an event that does
+not support counting on a per-logical CPU basis.
+.It Bq Er EINVAL
+A PMC allocated for system-wide operation was specified with a
+.Dv PMC_OP_PMCATTACH
+or
+.Dv PMC_OP_PMCDETACH
+request.
+.It Bq Er EINVAL
+The
+.Ar pm_pid
+argument to a
+.Dv PMC_OP_PMCATTACH
+or
+.Dv PMC_OP_PMCDETACH
+request specified an illegal process ID.
+.It Bq Er EINVAL
+A
+.Dv PMC_OP_PMCDETACH
+request was issued for a PMC not attached to the target process.
+.It Bq Er EINVAL
+Argument
+.Ar pm_flags
+to a
+.Dv PMC_OP_PMCRW
+request contained illegal flags.
+.It Bq Er EINVAL
+A
+.Dv PMC_OP_PMCX86GETMSR
+operation was requested for a PMC not in process-virtual mode, or
+for a PMC that is not solely attached to its owner process, or for
+a PMC that was allocated with flag
+.Dv PMC_F_DESCENDANTS .
+.It Bq Er EINVAL
+A
+.Dv PMC_OP_WRITELOG
+request was issued for an owner process without a log file
+configured.
+.It Bq Er ENOMEM
+The system was not able to allocate kernel memory.
+.It Bq Er ENOSYS
+(On i386 and amd64 architectures)
+A
+.Dv PMC_OP_PMCX86GETMSR
+operation was requested for hardware that does not support reading
+PMCs directly with the RDPMC instruction.
+.It Bq Er ENXIO
+A
+.Dv PMC_OP_GETPMCINFO
+operation was requested for an absent or disabled CPU.
+.It Bq Er ENXIO
+A
+.Dv PMC_OP_PMCALLOCATE
+operation specified allocation of a system-wide PMC on an absent or
+disabled CPU.
+.It Bq Er ENXIO
+A
+.Dv PMC_OP_PMCSTART
+or
+.Dv PMC_OP_PMCSTOP
+request was issued for a system-wide PMC that was allocated on a CPU
+that is currently absent or disabled.
+.It Bq Er EOPNOTSUPP
+A
+.Dv PMC_OP_PMCALLOCATE
+request was issued for PMC capabilities not supported
+by the specified PMC class.
+.It Bq Er EOPNOTSUPP
+(i386 architectures)
+A sampling mode PMC was requested on a CPU lacking an APIC.
+.It Bq Er EPERM
+A
+.Dv PMC_OP_PMCADMIN
+request was issued by a process without super-user
+privilege or by a jailed super-user process.
+.It Bq Er EPERM
+A
+.Dv PMC_OP_PMCATTACH
+operation was issued for a target process that the current process
+does not have permission to attach to.
+.It Bq Er EPERM
+(i386 and amd64 architectures)
+A
+.Dv PMC_OP_PMCATTACH
+operation was issued on a PMC whose MSR has been retrieved using
+.Dv PMC_OP_PMCX86GETMSR .
+.It Bq Er ESRCH
+A process issued a PMC operation request without having allocated any
+PMCs.
+.It Bq Er ESRCH
+A process issued a PMC operation request after the PMC was detached
+from all of its target processes.
+.It Bq Er ESRCH
+A
+.Dv PMC_OP_PMCATTACH
+or
+.Dv PMC_OP_PMCDETACH
+request specified a non-existent process ID.
+.It Bq Er ESRCH
+The target process for a
+.Dv PMC_OP_PMCDETACH
+operation is not being monitored by
+.Nm .
+.El
+.Sh SEE ALSO
+.Xr kenv 1 ,
+.Xr pmc 3 ,
+.Xr pmclog 3 ,
+.Xr kgmon 8 ,
+.Xr kldload 8 ,
+.Xr pmccontrol 8 ,
+.Xr pmcstat 8 ,
+.Xr sysctl 8 ,
+.Xr kproc_create 9 ,
+.Xr p_candebug 9
+.Sh HISTORY
+The
+.Nm
+driver first appeared in
+.Fx 6.0 .
+.Sh AUTHORS
+The
+.Nm
+driver was written by
+.An "Joseph Koshy"
+.Aq jkoshy@FreeBSD.org .
+.Sh BUGS
+The driver samples the state of the kernel's logical processor support
+at the time of initialization (i.e., at module load time).
+On CPUs supporting logical processors, the driver could misbehave if
+logical processors are subsequently enabled or disabled while the
+driver is active.
+.Pp
+On the i386 architecture, the driver requires that the local APIC on the
+CPU be enabled for sampling mode to be supported.
+Many single-processor motherboards keep the APIC disabled in BIOS; on
+such systems
+.Nm
+will not support sampling PMCs.
+.Sh SECURITY CONSIDERATIONS
+PMCs may be used to monitor the actual behavior of the system on hardware.
+In situations where this constitutes an undesirable information leak,
+the following options are available:
+.Bl -enum
+.It
+Set the
+.Xr sysctl 8
+tunable
+.Va security.bsd.unprivileged_syspmcs
+to 0.
+This ensures that unprivileged processes cannot allocate system-wide
+PMCs and thus cannot observe the hardware behavior of the system
+as a whole.
+This tunable may also be set at boot time using
+.Xr loader 8 ,
+or with
+.Xr kenv 1
+prior to loading the
+.Nm
+driver into the kernel.
+.It
+Set the
+.Xr sysctl 8
+tunable
+.Va security.bsd.unprivileged_proc_debug
+to 0.
+This will ensure that an unprivileged process cannot attach a PMC
+to any process other than itself and thus cannot observe the hardware
+behavior of other processes with the same credentials.
+.El
+.Pp
+System administrators should note that on IA-32 platforms
+.Fx
+makes the content of the IA-32 TSC counter available to all processes
+via the RDTSC instruction.
diff --git a/sys/cpu/i386/include/pmc_mdep.h b/sys/cpu/i386/include/pmc_mdep.h
new file mode 100644
index 0000000..f125cc0
--- /dev/null
+++ b/sys/cpu/i386/include/pmc_mdep.h
@@ -0,0 +1,169 @@
+/*-
+ * Copyright (c) 2003-2005,2008 Joseph Koshy
+ * Copyright (c) 2007 The FreeBSD Foundation
+ * All rights reserved.
+ *
+ * Portions of this software were developed by A. Joseph Koshy under
+ * sponsorship from the FreeBSD Foundation and Google, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: src/sys/i386/include/pmc_mdep.h,v 1.12 2010/04/02 13:23:49 fabient Exp $
+ */
+
+#ifndef _MACHINE_PMC_MDEP_H
+#define	_MACHINE_PMC_MDEP_H 1
+
+#ifdef	_KERNEL
+struct pmc_mdep;
+#endif
+
+/*
+ * On the i386 platform we support the following PMCs.
+ *
+ * TSC		The timestamp counter
+ * K7		AMD Athlon XP/MP and other 32 bit processors.
+ * K8		AMD Athlon64 and Opteron PMCs in 32 bit mode.
+ * PIV		Intel P4/HTT and P4/EMT64
+ * PPRO		Intel Pentium Pro, Pentium-II, Pentium-III, Celeron and
+ *		Pentium-M processors
+ * PENTIUM	Intel Pentium MMX.
+ * IAP		Intel Core/Core2/Atom programmable PMCs.
+ * IAF		Intel fixed-function PMCs.
+ * UCP		Intel Uncore programmable PMCs.
+ * UCF		Intel Uncore fixed-function PMCs.
+ */
+
+#include <dev/hwpmc/hwpmc_amd.h> /* K7 and K8 */
+#include <dev/hwpmc/hwpmc_core.h>
+#include <dev/hwpmc/hwpmc_piv.h>
+#include <dev/hwpmc/hwpmc_ppro.h>
+#include <dev/hwpmc/hwpmc_pentium.h>
+#include <dev/hwpmc/hwpmc_tsc.h>
+#include <dev/hwpmc/hwpmc_uncore.h>
+
+/*
+ * Intel processors implementing V2 and later of the Intel performance
+ * measurement architecture have PMCs of the following classes: TSC,
+ * IAF, IAP, UCF and UCP.
+ */
+#define	PMC_MDEP_CLASS_INDEX_TSC	0
+#define	PMC_MDEP_CLASS_INDEX_K7		1
+#define	PMC_MDEP_CLASS_INDEX_K8		1
+#define	PMC_MDEP_CLASS_INDEX_P4		1
+#define	PMC_MDEP_CLASS_INDEX_P5		1
+#define	PMC_MDEP_CLASS_INDEX_P6		1
+#define	PMC_MDEP_CLASS_INDEX_IAP	1
+#define	PMC_MDEP_CLASS_INDEX_IAF	2
+#define PMC_MDEP_CLASS_INDEX_UCP	3
+#define PMC_MDEP_CLASS_INDEX_UCF	4
+
+/*
+ * Architecture specific extensions to <sys/pmc.h> structures.
+ */
+
+union pmc_md_op_pmcallocate  {
+	struct pmc_md_amd_op_pmcallocate	pm_amd;
+	struct pmc_md_iaf_op_pmcallocate	pm_iaf;
+	struct pmc_md_iap_op_pmcallocate	pm_iap;
+	struct pmc_md_ucf_op_pmcallocate	pm_ucf;
+	struct pmc_md_ucp_op_pmcallocate	pm_ucp;
+	struct pmc_md_p4_op_pmcallocate		pm_p4;
+	struct pmc_md_pentium_op_pmcallocate	pm_pentium;
+	struct pmc_md_ppro_op_pmcallocate	pm_ppro;
+	uint64_t				__pad[4];
+};
+
+/* Logging */
+#define	PMCLOG_READADDR		PMCLOG_READ32
+#define	PMCLOG_EMITADDR		PMCLOG_EMIT32
+
+#ifdef _KERNEL
+
+/* MD extension for 'struct pmc' */
+union pmc_md_pmc  {
+	struct pmc_md_amd_pmc	pm_amd;
+	struct pmc_md_iaf_pmc	pm_iaf;
+	struct pmc_md_iap_pmc	pm_iap;
+	struct pmc_md_ucf_pmc	pm_ucf;
+	struct pmc_md_ucp_pmc	pm_ucp;
+	struct pmc_md_p4_pmc	pm_p4;
+	struct pmc_md_pentium_pmc pm_pentium;
+	struct pmc_md_ppro_pmc	pm_ppro;
+};
+
+struct pmc;
+struct pmc_mdep;
+
+#define	PMC_TRAPFRAME_TO_PC(TF)	((TF)->tf_eip)
+#define	PMC_TRAPFRAME_TO_FP(TF)	((TF)->tf_ebp)
+
+/*
+ * The layout of the stack frame on entry into the NMI handler depends on
+ * whether a privilege level change (and consequent stack switch) was
+ * required for entry.
+ *
+ * When processing an interrupt when in user mode, the processor switches
+ * stacks, and saves the user mode stack pointer on the kernel stack.  The
+ * user mode stack pointer is then available to the interrupt handler
+ * at frame->tf_esp.
+ *
+ * When processing an interrupt while in kernel mode, the processor
+ * continues to use the existing (kernel) stack.  Therefore we determine
+ * the stack pointer for the interrupted kernel procedure by adding an
+ * offset to the current frame pointer.
+ */
+
+#define	PMC_TRAPFRAME_TO_USER_SP(TF)	((TF)->tf_esp)
+#define	PMC_TRAPFRAME_TO_KERNEL_SP(TF)	((uintptr_t) &((TF)->tf_esp))
+
+#define	PMC_IN_KERNEL_STACK(S,START,END)		\
+	((S) >= (START) && (S) < (END))
+#define	PMC_IN_KERNEL(va) (((va) >= USRSTACK) &&	\
+	((va) < VM_MAX_KERNEL_ADDRESS))
+
+#define	PMC_IN_USERSPACE(va) ((va) <= VM_MAXUSER_ADDRESS)
+
+#define	PMC_IN_TRAP_HANDLER(PC) 			\
+	((PC) >= (uintptr_t) start_exceptions &&	\
+	 (PC) < (uintptr_t) end_exceptions)
+
+#define	PMC_AT_FUNCTION_PROLOGUE_PUSH_BP(I)		\
+	(((I) & 0x00ffffff) == 0xe58955) /* pushl %ebp; movl %esp,%ebp */
+#define	PMC_AT_FUNCTION_PROLOGUE_MOV_SP_BP(I)		\
+	(((I) & 0x0000ffff) == 0xe589)	/* movl %esp,%ebp */
+#define	PMC_AT_FUNCTION_EPILOGUE_RET(I)			\
+	(((I) & 0xFF) == 0xC3)		   /* ret */
+
+/*
+ * Prototypes
+ */
+
+void	start_exceptions(void), end_exceptions(void);
+
+struct pmc_mdep *pmc_amd_initialize(void);
+void	pmc_amd_finalize(struct pmc_mdep *_md);
+struct pmc_mdep *pmc_intel_initialize(void);
+void	pmc_intel_finalize(struct pmc_mdep *_md);
+
+#endif /* _KERNEL */
+#endif /* _MACHINE_PMC_MDEP_H */
diff --git a/sys/cpu/x86_64/include/pmc_mdep.h b/sys/cpu/x86_64/include/pmc_mdep.h
new file mode 100644
index 0000000..16fa11d
--- /dev/null
+++ b/sys/cpu/x86_64/include/pmc_mdep.h
@@ -0,0 +1,134 @@
+/*-
+ * Copyright (c) 2003-2008 Joseph Koshy
+ * Copyright (c) 2007 The FreeBSD Foundation
+ * All rights reserved.
+ *
+ * Portions of this software were developed by A. Joseph Koshy under
+ * sponsorship from the FreeBSD Foundation and Google, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: src/sys/amd64/include/pmc_mdep.h,v 1.10 2010/04/02 13:23:49 fabient Exp $
+ */
+
+/* Machine dependent interfaces */
+
+#ifndef _MACHINE_PMC_MDEP_H
+#define	_MACHINE_PMC_MDEP_H 1
+
+#ifdef	_KERNEL
+struct pmc_mdep;
+#endif
+
+#include <dev/hwpmc/hwpmc_amd.h>
+#include <dev/hwpmc/hwpmc_core.h>
+#include <dev/hwpmc/hwpmc_piv.h>
+#include <dev/hwpmc/hwpmc_tsc.h>
+#include <dev/hwpmc/hwpmc_uncore.h>
+
+/*
+ * Intel processors implementing V2 and later of the Intel performance
+ * measurement architecture have PMCs of the following classes: TSC,
+ * IAF, IAP, UCF and UCP.
+ */
+#define	PMC_MDEP_CLASS_INDEX_TSC	0
+#define	PMC_MDEP_CLASS_INDEX_K8		1
+#define	PMC_MDEP_CLASS_INDEX_P4		1
+#define	PMC_MDEP_CLASS_INDEX_IAP	1
+#define	PMC_MDEP_CLASS_INDEX_IAF	2
+#define	PMC_MDEP_CLASS_INDEX_UCP	3
+#define	PMC_MDEP_CLASS_INDEX_UCF	4
+
+/*
+ * On the amd64 platform we support the following PMCs.
+ *
+ * TSC		The timestamp counter
+ * K8		AMD Athlon64 and Opteron PMCs in 64 bit mode.
+ * PIV		Intel P4/HTT and P4/EMT64
+ * IAP		Intel Core/Core2/Atom CPUs in 64 bits mode.
+ * IAF		Intel fixed-function PMCs in Core2 and later CPUs.
+ * UCP		Intel Uncore programmable PMCs.
+ * UCF		Intel Uncore fixed-function PMCs.
+ */
+
+union pmc_md_op_pmcallocate  {
+	struct pmc_md_amd_op_pmcallocate	pm_amd;
+	struct pmc_md_iaf_op_pmcallocate	pm_iaf;
+	struct pmc_md_iap_op_pmcallocate	pm_iap;
+	struct pmc_md_ucf_op_pmcallocate	pm_ucf;
+	struct pmc_md_ucp_op_pmcallocate	pm_ucp;
+	struct pmc_md_p4_op_pmcallocate		pm_p4;
+	uint64_t				__pad[4];
+};
+
+/* Logging */
+#define	PMCLOG_READADDR		PMCLOG_READ64
+#define	PMCLOG_EMITADDR		PMCLOG_EMIT64
+
+#ifdef	_KERNEL
+
+union pmc_md_pmc {
+	struct pmc_md_amd_pmc	pm_amd;
+	struct pmc_md_iaf_pmc	pm_iaf;
+	struct pmc_md_iap_pmc	pm_iap;
+	struct pmc_md_ucf_pmc	pm_ucf;
+	struct pmc_md_ucp_pmc	pm_ucp;
+	struct pmc_md_p4_pmc	pm_p4;
+};
+
+#define	PMC_TRAPFRAME_TO_PC(TF)	((TF)->tf_rip)
+#define	PMC_TRAPFRAME_TO_FP(TF)	((TF)->tf_rbp)
+#define	PMC_TRAPFRAME_TO_USER_SP(TF)	((TF)->tf_rsp)
+#define	PMC_TRAPFRAME_TO_KERNEL_SP(TF)	((TF)->tf_rsp)
+
+#define	PMC_AT_FUNCTION_PROLOGUE_PUSH_BP(I)		\
+	(((I) & 0xffffffff) == 0xe5894855) /* pushq %rbp; movq %rsp,%rbp */
+#define	PMC_AT_FUNCTION_PROLOGUE_MOV_SP_BP(I)		\
+	(((I) & 0x00ffffff) == 0x00e58948) /* movq %rsp,%rbp */
+#define	PMC_AT_FUNCTION_EPILOGUE_RET(I)			\
+	(((I) & 0xFF) == 0xC3)		   /* ret */
+
+#define	PMC_IN_TRAP_HANDLER(PC) 			\
+	((PC) >= (uintptr_t) start_exceptions &&	\
+	 (PC) < (uintptr_t) end_exceptions)
+
+#define	PMC_IN_KERNEL_STACK(S,START,END)		\
+	((S) >= (START) && (S) < (END))
+#define	PMC_IN_KERNEL(va) (((va) >= DMAP_MIN_ADDRESS &&			\
+	(va) < DMAP_MAX_ADDRESS) || ((va) >= VM_MIN_KERNEL_ADDRESS &&	\
+	(va) < VM_MAX_KERNEL_ADDRESS))
+
+#define	PMC_IN_USERSPACE(va) ((va) <= VM_MAXUSER_ADDRESS)
+
+/*
+ * Prototypes
+ */
+
+void	start_exceptions(void), end_exceptions(void);
+
+struct pmc_mdep *pmc_amd_initialize(void);
+void	pmc_amd_finalize(struct pmc_mdep *_md);
+struct pmc_mdep *pmc_intel_initialize(void);
+void	pmc_intel_finalize(struct pmc_mdep *_md);
+
+#endif /* _KERNEL */
+#endif /* _MACHINE_PMC_MDEP_H */
diff --git a/sys/dev/misc/hwpmc/Makefile b/sys/dev/misc/hwpmc/Makefile
new file mode 100644
index 0000000..3f65faa
--- /dev/null
+++ b/sys/dev/misc/hwpmc/Makefile
@@ -0,0 +1,39 @@
+#
+# $FreeBSD: src/sys/modules/hwpmc/Makefile,v 1.10 2010/08/23 06:13:29 imp Exp $
+#
+
+.PATH: ${.CURDIR}/../../dev/hwpmc
+
+KMOD=	hwpmc
+
+SRCS=	hwpmc_mod.c hwpmc_logging.c vnode_if.h
+
+.if ${MACHINE_CPUARCH} == "amd64"
+SRCS+=	hwpmc_amd.c hwpmc_core.c hwpmc_intel.c hwpmc_piv.c hwpmc_tsc.c
+SRCS+=	hwpmc_x86.c hwpmc_uncore.c
+SRCS+=	device_if.h bus_if.h
+.endif
+
+.if ${MACHINE_CPUARCH} == "arm"
+SRCS+=	hwpmc_arm.c
+.endif
+
+.if ${MACHINE_CPUARCH} == "i386"
+SRCS+=	hwpmc_amd.c hwpmc_core.c hwpmc_intel.c hwpmc_piv.c hwpmc_ppro.c
+SRCS+=	hwpmc_pentium.c hwpmc_tsc.c hwpmc_x86.c hwpmc_uncore.c
+SRCS+=	device_if.h bus_if.h
+.endif
+
+.if ${MACHINE_CPUARCH} == "ia64"
+SRCS+=	hwpmc_ia64.c
+.endif
+
+.if ${MACHINE_CPUARCH} == "powerpc"
+SRCS+=	hwpmc_powerpc.c
+.endif
+
+.if ${MACHINE_CPUARCH} == "sparc64"
+SRCS+=	hwpmc_sparc64.c
+.endif
+
+.include <bsd.kmod.mk>
diff --git a/sys/dev/misc/hwpmc/hwpmc_amd.c b/sys/dev/misc/hwpmc/hwpmc_amd.c
new file mode 100644
index 0000000..d755c55
--- /dev/null
+++ b/sys/dev/misc/hwpmc/hwpmc_amd.c
@@ -0,0 +1,1037 @@
+/*-
+ * Copyright (c) 2003-2008 Joseph Koshy
+ * Copyright (c) 2007 The FreeBSD Foundation
+ * All rights reserved.
+ *
+ * Portions of this software were developed by A. Joseph Koshy under
+ * sponsorship from the FreeBSD Foundation and Google, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: src/sys/dev/hwpmc/hwpmc_amd.c,v 1.21 2008/12/02 10:46:35 jkoshy Exp $");
+
+/* Support for the AMD K7 and later processors */
+
+#include <sys/param.h>
+#include <sys/lock.h>
+#include <sys/malloc.h>
+#include <sys/mutex.h>
+#include <sys/pmc.h>
+#include <sys/pmckern.h>
+#include <sys/smp.h>
+#include <sys/systm.h>
+
+#include <machine/cpu.h>
+#include <machine/cpufunc.h>
+#include <machine/md_var.h>
+#include <machine/specialreg.h>
+
+#ifdef	DEBUG
+enum pmc_class	amd_pmc_class;
+#endif
+
+/* AMD K7 & K8 PMCs */
+struct amd_descr {
+	struct pmc_descr pm_descr;  /* "base class" */
+	uint32_t	pm_evsel;   /* address of EVSEL register */
+	uint32_t	pm_perfctr; /* address of PERFCTR register */
+};
+
+static  struct amd_descr amd_pmcdesc[AMD_NPMCS] =
+{
+    {
+	.pm_descr =
+	{
+		.pd_name  = "",
+		.pd_class = -1,
+		.pd_caps  = AMD_PMC_CAPS,
+		.pd_width = 48
+	},
+	.pm_evsel   = AMD_PMC_EVSEL_0,
+	.pm_perfctr = AMD_PMC_PERFCTR_0
+    },
+    {
+	.pm_descr =
+	{
+		.pd_name  = "",
+		.pd_class = -1,
+		.pd_caps  = AMD_PMC_CAPS,
+		.pd_width = 48
+	},
+	.pm_evsel   = AMD_PMC_EVSEL_1,
+	.pm_perfctr = AMD_PMC_PERFCTR_1
+    },
+    {
+	.pm_descr =
+	{
+		.pd_name  = "",
+		.pd_class = -1,
+		.pd_caps  = AMD_PMC_CAPS,
+		.pd_width = 48
+	},
+	.pm_evsel   = AMD_PMC_EVSEL_2,
+	.pm_perfctr = AMD_PMC_PERFCTR_2
+    },
+    {
+	.pm_descr =
+	{
+		.pd_name  = "",
+		.pd_class = -1,
+		.pd_caps  = AMD_PMC_CAPS,
+		.pd_width = 48
+	},
+	.pm_evsel   = AMD_PMC_EVSEL_3,
+	.pm_perfctr = AMD_PMC_PERFCTR_3
+    }
+};
+
+struct amd_event_code_map {
+	enum pmc_event	pe_ev;	 /* enum value */
+	uint8_t		pe_code; /* encoded event mask */
+	uint8_t		pe_mask; /* bits allowed in unit mask */
+};
+
+const struct amd_event_code_map amd_event_codes[] = {
+#if	defined(__i386__)	/* 32 bit Athlon (K7) only */
+	{ PMC_EV_K7_DC_ACCESSES, 		0x40, 0 },
+	{ PMC_EV_K7_DC_MISSES,			0x41, 0 },
+	{ PMC_EV_K7_DC_REFILLS_FROM_L2,		0x42, AMD_PMC_UNITMASK_MOESI },
+	{ PMC_EV_K7_DC_REFILLS_FROM_SYSTEM,	0x43, AMD_PMC_UNITMASK_MOESI },
+	{ PMC_EV_K7_DC_WRITEBACKS,		0x44, AMD_PMC_UNITMASK_MOESI },
+	{ PMC_EV_K7_L1_DTLB_MISS_AND_L2_DTLB_HITS, 0x45, 0 },
+	{ PMC_EV_K7_L1_AND_L2_DTLB_MISSES,	0x46, 0 },
+	{ PMC_EV_K7_MISALIGNED_REFERENCES,	0x47, 0 },
+
+	{ PMC_EV_K7_IC_FETCHES,			0x80, 0 },
+	{ PMC_EV_K7_IC_MISSES,			0x81, 0 },
+
+	{ PMC_EV_K7_L1_ITLB_MISSES,		0x84, 0 },
+	{ PMC_EV_K7_L1_L2_ITLB_MISSES,		0x85, 0 },
+
+	{ PMC_EV_K7_RETIRED_INSTRUCTIONS,	0xC0, 0 },
+	{ PMC_EV_K7_RETIRED_OPS,		0xC1, 0 },
+	{ PMC_EV_K7_RETIRED_BRANCHES,		0xC2, 0 },
+	{ PMC_EV_K7_RETIRED_BRANCHES_MISPREDICTED, 0xC3, 0 },
+	{ PMC_EV_K7_RETIRED_TAKEN_BRANCHES, 	0xC4, 0 },
+	{ PMC_EV_K7_RETIRED_TAKEN_BRANCHES_MISPREDICTED, 0xC5, 0 },
+	{ PMC_EV_K7_RETIRED_FAR_CONTROL_TRANSFERS, 0xC6, 0 },
+	{ PMC_EV_K7_RETIRED_RESYNC_BRANCHES,	0xC7, 0 },
+	{ PMC_EV_K7_INTERRUPTS_MASKED_CYCLES,	0xCD, 0 },
+	{ PMC_EV_K7_INTERRUPTS_MASKED_WHILE_PENDING_CYCLES, 0xCE, 0 },
+	{ PMC_EV_K7_HARDWARE_INTERRUPTS,	0xCF, 0 },
+#endif
+
+	{ PMC_EV_K8_FP_DISPATCHED_FPU_OPS,		0x00, 0x3F },
+	{ PMC_EV_K8_FP_CYCLES_WITH_NO_FPU_OPS_RETIRED,	0x01, 0x00 },
+	{ PMC_EV_K8_FP_DISPATCHED_FPU_FAST_FLAG_OPS,	0x02, 0x00 },
+
+	{ PMC_EV_K8_LS_SEGMENT_REGISTER_LOAD, 		0x20, 0x7F },
+	{ PMC_EV_K8_LS_MICROARCHITECTURAL_RESYNC_BY_SELF_MODIFYING_CODE,
+							0x21, 0x00 },
+	{ PMC_EV_K8_LS_MICROARCHITECTURAL_RESYNC_BY_SNOOP, 0x22, 0x00 },
+	{ PMC_EV_K8_LS_BUFFER2_FULL,			0x23, 0x00 },
+	{ PMC_EV_K8_LS_LOCKED_OPERATION,		0x24, 0x07 },
+	{ PMC_EV_K8_LS_MICROARCHITECTURAL_LATE_CANCEL,	0x25, 0x00 },
+	{ PMC_EV_K8_LS_RETIRED_CFLUSH_INSTRUCTIONS,	0x26, 0x00 },
+	{ PMC_EV_K8_LS_RETIRED_CPUID_INSTRUCTIONS,	0x27, 0x00 },
+
+	{ PMC_EV_K8_DC_ACCESS,				0x40, 0x00 },
+	{ PMC_EV_K8_DC_MISS,				0x41, 0x00 },
+	{ PMC_EV_K8_DC_REFILL_FROM_L2,			0x42, 0x1F },
+	{ PMC_EV_K8_DC_REFILL_FROM_SYSTEM,		0x43, 0x1F },
+	{ PMC_EV_K8_DC_COPYBACK,			0x44, 0x1F },
+	{ PMC_EV_K8_DC_L1_DTLB_MISS_AND_L2_DTLB_HIT,	0x45, 0x00 },
+	{ PMC_EV_K8_DC_L1_DTLB_MISS_AND_L2_DTLB_MISS,	0x46, 0x00 },
+	{ PMC_EV_K8_DC_MISALIGNED_DATA_REFERENCE,	0x47, 0x00 },
+	{ PMC_EV_K8_DC_MICROARCHITECTURAL_LATE_CANCEL,	0x48, 0x00 },
+	{ PMC_EV_K8_DC_MICROARCHITECTURAL_EARLY_CANCEL, 0x49, 0x00 },
+	{ PMC_EV_K8_DC_ONE_BIT_ECC_ERROR,		0x4A, 0x03 },
+	{ PMC_EV_K8_DC_DISPATCHED_PREFETCH_INSTRUCTIONS, 0x4B, 0x07 },
+	{ PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS,	0x4C, 0x03 },
+
+	{ PMC_EV_K8_BU_CPU_CLK_UNHALTED,		0x76, 0x00 },
+	{ PMC_EV_K8_BU_INTERNAL_L2_REQUEST,		0x7D, 0x1F },
+	{ PMC_EV_K8_BU_FILL_REQUEST_L2_MISS,		0x7E, 0x07 },
+	{ PMC_EV_K8_BU_FILL_INTO_L2,			0x7F, 0x03 },
+
+	{ PMC_EV_K8_IC_FETCH,				0x80, 0x00 },
+	{ PMC_EV_K8_IC_MISS,				0x81, 0x00 },
+	{ PMC_EV_K8_IC_REFILL_FROM_L2,			0x82, 0x00 },
+	{ PMC_EV_K8_IC_REFILL_FROM_SYSTEM,		0x83, 0x00 },
+	{ PMC_EV_K8_IC_L1_ITLB_MISS_AND_L2_ITLB_HIT,	0x84, 0x00 },
+	{ PMC_EV_K8_IC_L1_ITLB_MISS_AND_L2_ITLB_MISS,	0x85, 0x00 },
+	{ PMC_EV_K8_IC_MICROARCHITECTURAL_RESYNC_BY_SNOOP, 0x86, 0x00 },
+	{ PMC_EV_K8_IC_INSTRUCTION_FETCH_STALL,		0x87, 0x00 },
+	{ PMC_EV_K8_IC_RETURN_STACK_HIT,		0x88, 0x00 },
+	{ PMC_EV_K8_IC_RETURN_STACK_OVERFLOW,		0x89, 0x00 },
+
+	{ PMC_EV_K8_FR_RETIRED_X86_INSTRUCTIONS,	0xC0, 0x00 },
+	{ PMC_EV_K8_FR_RETIRED_UOPS,			0xC1, 0x00 },
+	{ PMC_EV_K8_FR_RETIRED_BRANCHES,		0xC2, 0x00 },
+	{ PMC_EV_K8_FR_RETIRED_BRANCHES_MISPREDICTED,	0xC3, 0x00 },
+	{ PMC_EV_K8_FR_RETIRED_TAKEN_BRANCHES,		0xC4, 0x00 },
+	{ PMC_EV_K8_FR_RETIRED_TAKEN_BRANCHES_MISPREDICTED, 0xC5, 0x00 },
+	{ PMC_EV_K8_FR_RETIRED_FAR_CONTROL_TRANSFERS,	0xC6, 0x00 },
+	{ PMC_EV_K8_FR_RETIRED_RESYNCS,			0xC7, 0x00 },
+	{ PMC_EV_K8_FR_RETIRED_NEAR_RETURNS,		0xC8, 0x00 },
+	{ PMC_EV_K8_FR_RETIRED_NEAR_RETURNS_MISPREDICTED, 0xC9, 0x00 },
+	{ PMC_EV_K8_FR_RETIRED_TAKEN_BRANCHES_MISPREDICTED_BY_ADDR_MISCOMPARE,
+							0xCA, 0x00 },
+	{ PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS,	0xCB, 0x0F },
+	{ PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS,
+							0xCC, 0x07 },
+	{ PMC_EV_K8_FR_INTERRUPTS_MASKED_CYCLES,	0xCD, 0x00 },
+	{ PMC_EV_K8_FR_INTERRUPTS_MASKED_WHILE_PENDING_CYCLES, 0xCE, 0x00 },
+	{ PMC_EV_K8_FR_TAKEN_HARDWARE_INTERRUPTS,	0xCF, 0x00 },
+
+	{ PMC_EV_K8_FR_DECODER_EMPTY,			0xD0, 0x00 },
+	{ PMC_EV_K8_FR_DISPATCH_STALLS,			0xD1, 0x00 },
+	{ PMC_EV_K8_FR_DISPATCH_STALL_FROM_BRANCH_ABORT_TO_RETIRE,
+							0xD2, 0x00 },
+	{ PMC_EV_K8_FR_DISPATCH_STALL_FOR_SERIALIZATION, 0xD3, 0x00 },
+	{ PMC_EV_K8_FR_DISPATCH_STALL_FOR_SEGMENT_LOAD,	0xD4, 0x00 },
+	{ PMC_EV_K8_FR_DISPATCH_STALL_WHEN_REORDER_BUFFER_IS_FULL,
+							0xD5, 0x00 },
+	{ PMC_EV_K8_FR_DISPATCH_STALL_WHEN_RESERVATION_STATIONS_ARE_FULL,
+							0xD6, 0x00 },
+	{ PMC_EV_K8_FR_DISPATCH_STALL_WHEN_FPU_IS_FULL,	0xD7, 0x00 },
+	{ PMC_EV_K8_FR_DISPATCH_STALL_WHEN_LS_IS_FULL,	0xD8, 0x00 },
+	{ PMC_EV_K8_FR_DISPATCH_STALL_WHEN_WAITING_FOR_ALL_TO_BE_QUIET,
+							0xD9, 0x00 },
+	{ PMC_EV_K8_FR_DISPATCH_STALL_WHEN_FAR_XFER_OR_RESYNC_BRANCH_PENDING,
+							0xDA, 0x00 },
+	{ PMC_EV_K8_FR_FPU_EXCEPTIONS,			0xDB, 0x0F },
+	{ PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR0,	0xDC, 0x00 },
+	{ PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR1,	0xDD, 0x00 },
+	{ PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR2,	0xDE, 0x00 },
+	{ PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR3,	0xDF, 0x00 },
+
+	{ PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENT, 0xE0, 0x7 },
+	{ PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_TABLE_OVERFLOW, 0xE1, 0x00 },
+	{ PMC_EV_K8_NB_MEMORY_CONTROLLER_DRAM_COMMAND_SLOTS_MISSED,
+							0xE2, 0x00 },
+	{ PMC_EV_K8_NB_MEMORY_CONTROLLER_TURNAROUND,	0xE3, 0x07 },
+	{ PMC_EV_K8_NB_MEMORY_CONTROLLER_BYPASS_SATURATION, 0xE4, 0x0F },
+	{ PMC_EV_K8_NB_SIZED_COMMANDS,			0xEB, 0x7F },
+	{ PMC_EV_K8_NB_PROBE_RESULT,			0xEC, 0x0F },
+	{ PMC_EV_K8_NB_HT_BUS0_BANDWIDTH,		0xF6, 0x0F },
+	{ PMC_EV_K8_NB_HT_BUS1_BANDWIDTH,		0xF7, 0x0F },
+	{ PMC_EV_K8_NB_HT_BUS2_BANDWIDTH,		0xF8, 0x0F }
+
+};
+
+const int amd_event_codes_size =
+	sizeof(amd_event_codes) / sizeof(amd_event_codes[0]);
+
+/*
+ * Per-processor information
+ */
+
+struct amd_cpu {
+	struct pmc_hw	pc_amdpmcs[AMD_NPMCS];
+};
+
+static struct amd_cpu **amd_pcpu;
+
+/*
+ * read a pmc register
+ */
+
+static int
+amd_read_pmc(int cpu, int ri, pmc_value_t *v)
+{
+	enum pmc_mode mode;
+	const struct amd_descr *pd;
+	struct pmc *pm;
+	pmc_value_t tmp;
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[amd,%d] illegal CPU value %d", __LINE__, cpu));
+	KASSERT(ri >= 0 && ri < AMD_NPMCS,
+	    ("[amd,%d] illegal row-index %d", __LINE__, ri));
+	KASSERT(amd_pcpu[cpu],
+	    ("[amd,%d] null per-cpu, cpu %d", __LINE__, cpu));
+
+	pm = amd_pcpu[cpu]->pc_amdpmcs[ri].phw_pmc;
+	pd = &amd_pmcdesc[ri];
+
+	KASSERT(pm != NULL,
+	    ("[amd,%d] No owner for HWPMC [cpu%d,pmc%d]", __LINE__,
+		cpu, ri));
+
+	mode = PMC_TO_MODE(pm);
+
+	PMCDBG(MDP,REA,1,"amd-read id=%d class=%d", ri, pd->pm_descr.pd_class);
+
+#ifdef	DEBUG
+	KASSERT(pd->pm_descr.pd_class == amd_pmc_class,
+	    ("[amd,%d] unknown PMC class (%d)", __LINE__,
+		pd->pm_descr.pd_class));
+#endif
+
+	tmp = rdmsr(pd->pm_perfctr); /* RDMSR serializes */
+	PMCDBG(MDP,REA,2,"amd-read (pre-munge) id=%d -> %jd", ri, tmp);
+	if (PMC_IS_SAMPLING_MODE(mode)) {
+		/* Sign extend 48 bit value to 64 bits. */
+		tmp = (pmc_value_t) (((int64_t) tmp << 16) >> 16);
+		tmp = AMD_PERFCTR_VALUE_TO_RELOAD_COUNT(tmp);
+	}
+	*v = tmp;
+
+	PMCDBG(MDP,REA,2,"amd-read (post-munge) id=%d -> %jd", ri, *v);
+
+	return 0;
+}
+
+/*
+ * Write a PMC MSR.
+ */
+
+static int
+amd_write_pmc(int cpu, int ri, pmc_value_t v)
+{
+	const struct amd_descr *pd;
+	enum pmc_mode mode;
+	struct pmc *pm;
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[amd,%d] illegal CPU value %d", __LINE__, cpu));
+	KASSERT(ri >= 0 && ri < AMD_NPMCS,
+	    ("[amd,%d] illegal row-index %d", __LINE__, ri));
+
+	pm = amd_pcpu[cpu]->pc_amdpmcs[ri].phw_pmc;
+	pd = &amd_pmcdesc[ri];
+
+	KASSERT(pm != NULL,
+	    ("[amd,%d] PMC not owned (cpu%d,pmc%d)", __LINE__,
+		cpu, ri));
+
+	mode = PMC_TO_MODE(pm);
+
+#ifdef	DEBUG
+	KASSERT(pd->pm_descr.pd_class == amd_pmc_class,
+	    ("[amd,%d] unknown PMC class (%d)", __LINE__,
+		pd->pm_descr.pd_class));
+#endif
+
+	/* use 2's complement of the count for sampling mode PMCs */
+	if (PMC_IS_SAMPLING_MODE(mode))
+		v = AMD_RELOAD_COUNT_TO_PERFCTR_VALUE(v);
+
+	PMCDBG(MDP,WRI,1,"amd-write cpu=%d ri=%d v=%jx", cpu, ri, v);
+
+	/* write the PMC value */
+	wrmsr(pd->pm_perfctr, v);
+	return 0;
+}
+
+/*
+ * configure hardware pmc according to the configuration recorded in
+ * pmc 'pm'.
+ */
+
+static int
+amd_config_pmc(int cpu, int ri, struct pmc *pm)
+{
+	struct pmc_hw *phw;
+
+	PMCDBG(MDP,CFG,1, "cpu=%d ri=%d pm=%p", cpu, ri, pm);
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[amd,%d] illegal CPU value %d", __LINE__, cpu));
+	KASSERT(ri >= 0 && ri < AMD_NPMCS,
+	    ("[amd,%d] illegal row-index %d", __LINE__, ri));
+
+	phw = &amd_pcpu[cpu]->pc_amdpmcs[ri];
+
+	KASSERT(pm == NULL || phw->phw_pmc == NULL,
+	    ("[amd,%d] pm=%p phw->pm=%p hwpmc not unconfigured",
+		__LINE__, pm, phw->phw_pmc));
+
+	phw->phw_pmc = pm;
+	return 0;
+}
+
+/*
+ * Retrieve a configured PMC pointer from hardware state.
+ */
+
+static int
+amd_get_config(int cpu, int ri, struct pmc **ppm)
+{
+	*ppm = amd_pcpu[cpu]->pc_amdpmcs[ri].phw_pmc;
+
+	return 0;
+}
+
+/*
+ * Machine dependent actions taken during the context switch in of a
+ * thread.
+ */
+
+static int
+amd_switch_in(struct pmc_cpu *pc, struct pmc_process *pp)
+{
+	(void) pc;
+
+	PMCDBG(MDP,SWI,1, "pc=%p pp=%p enable-msr=%d", pc, pp,
+	    (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS) != 0);
+
+	/* enable the RDPMC instruction if needed */
+	if (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS)
+		load_cr4(rcr4() | CR4_PCE);
+
+	return 0;
+}
+
+/*
+ * Machine dependent actions taken during the context switch out of a
+ * thread.
+ */
+
+static int
+amd_switch_out(struct pmc_cpu *pc, struct pmc_process *pp)
+{
+	(void) pc;
+	(void) pp;		/* can be NULL */
+
+	PMCDBG(MDP,SWO,1, "pc=%p pp=%p enable-msr=%d", pc, pp, pp ?
+	    (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS) == 1 : 0);
+
+	/* always turn off the RDPMC instruction */
+	load_cr4(rcr4() & ~CR4_PCE);
+
+	return 0;
+}
+
+/*
+ * Check if a given allocation is feasible.
+ */
+
+static int
+amd_allocate_pmc(int cpu, int ri, struct pmc *pm,
+    const struct pmc_op_pmcallocate *a)
+{
+	int i;
+	uint32_t allowed_unitmask, caps, config, unitmask;
+	enum pmc_event pe;
+	const struct pmc_descr *pd;
+
+	(void) cpu;
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[amd,%d] illegal CPU value %d", __LINE__, cpu));
+	KASSERT(ri >= 0 && ri < AMD_NPMCS,
+	    ("[amd,%d] illegal row index %d", __LINE__, ri));
+
+	pd = &amd_pmcdesc[ri].pm_descr;
+
+	/* check class match */
+	if (pd->pd_class != a->pm_class)
+		return EINVAL;
+
+	caps = pm->pm_caps;
+
+	PMCDBG(MDP,ALL,1,"amd-allocate ri=%d caps=0x%x", ri, caps);
+
+	if ((pd->pd_caps & caps) != caps)
+		return EPERM;
+
+	pe = a->pm_ev;
+
+	/* map ev to the correct event mask code */
+	config = allowed_unitmask = 0;
+	for (i = 0; i < amd_event_codes_size; i++)
+		if (amd_event_codes[i].pe_ev == pe) {
+			config =
+			    AMD_PMC_TO_EVENTMASK(amd_event_codes[i].pe_code);
+			allowed_unitmask =
+			    AMD_PMC_TO_UNITMASK(amd_event_codes[i].pe_mask);
+			break;
+		}
+	if (i == amd_event_codes_size)
+		return EINVAL;
+
+	unitmask = a->pm_md.pm_amd.pm_amd_config & AMD_PMC_UNITMASK;
+	if (unitmask & ~allowed_unitmask) /* disallow reserved bits */
+		return EINVAL;
+
+	if (unitmask && (caps & PMC_CAP_QUALIFIER))
+		config |= unitmask;
+
+	if (caps & PMC_CAP_THRESHOLD)
+		config |= a->pm_md.pm_amd.pm_amd_config & AMD_PMC_COUNTERMASK;
+
+	/* set at least one of the 'usr' or 'os' caps */
+	if (caps & PMC_CAP_USER)
+		config |= AMD_PMC_USR;
+	if (caps & PMC_CAP_SYSTEM)
+		config |= AMD_PMC_OS;
+	if ((caps & (PMC_CAP_USER|PMC_CAP_SYSTEM)) == 0)
+		config |= (AMD_PMC_USR|AMD_PMC_OS);
+
+	if (caps & PMC_CAP_EDGE)
+		config |= AMD_PMC_EDGE;
+	if (caps & PMC_CAP_INVERT)
+		config |= AMD_PMC_INVERT;
+	if (caps & PMC_CAP_INTERRUPT)
+		config |= AMD_PMC_INT;
+
+	pm->pm_md.pm_amd.pm_amd_evsel = config; /* save config value */
+
+	PMCDBG(MDP,ALL,2,"amd-allocate ri=%d -> config=0x%x", ri, config);
+
+	return 0;
+}
+
+/*
+ * Release machine dependent state associated with a PMC.  This is a
+ * no-op on this architecture.
+ *
+ */
+
+/* ARGSUSED0 */
+static int
+amd_release_pmc(int cpu, int ri, struct pmc *pmc)
+{
+#ifdef	DEBUG
+	const struct amd_descr *pd;
+#endif
+	struct pmc_hw *phw;
+
+	(void) pmc;
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[amd,%d] illegal CPU value %d", __LINE__, cpu));
+	KASSERT(ri >= 0 && ri < AMD_NPMCS,
+	    ("[amd,%d] illegal row-index %d", __LINE__, ri));
+
+	phw = &amd_pcpu[cpu]->pc_amdpmcs[ri];
+
+	KASSERT(phw->phw_pmc == NULL,
+	    ("[amd,%d] PHW pmc %p non-NULL", __LINE__, phw->phw_pmc));
+
+#ifdef	DEBUG
+	pd = &amd_pmcdesc[ri];
+	if (pd->pm_descr.pd_class == amd_pmc_class)
+		KASSERT(AMD_PMC_IS_STOPPED(pd->pm_evsel),
+		    ("[amd,%d] PMC %d released while active", __LINE__, ri));
+#endif
+
+	return 0;
+}
+
+/*
+ * start a PMC.
+ */
+
+static int
+amd_start_pmc(int cpu, int ri)
+{
+	uint32_t config;
+	struct pmc *pm;
+	struct pmc_hw *phw;
+	const struct amd_descr *pd;
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[amd,%d] illegal CPU value %d", __LINE__, cpu));
+	KASSERT(ri >= 0 && ri < AMD_NPMCS,
+	    ("[amd,%d] illegal row-index %d", __LINE__, ri));
+
+	phw = &amd_pcpu[cpu]->pc_amdpmcs[ri];
+	pm  = phw->phw_pmc;
+	pd = &amd_pmcdesc[ri];
+
+	KASSERT(pm != NULL,
+	    ("[amd,%d] starting cpu%d,pmc%d with null pmc record", __LINE__,
+		cpu, ri));
+
+	PMCDBG(MDP,STA,1,"amd-start cpu=%d ri=%d", cpu, ri);
+
+	KASSERT(AMD_PMC_IS_STOPPED(pd->pm_evsel),
+	    ("[amd,%d] pmc%d,cpu%d: Starting active PMC \"%s\"", __LINE__,
+	    ri, cpu, pd->pm_descr.pd_name));
+
+	/* turn on the PMC ENABLE bit */
+	config = pm->pm_md.pm_amd.pm_amd_evsel | AMD_PMC_ENABLE;
+
+	PMCDBG(MDP,STA,2,"amd-start config=0x%x", config);
+
+	wrmsr(pd->pm_evsel, config);
+	return 0;
+}
+
+/*
+ * Stop a PMC.
+ */
+
+static int
+amd_stop_pmc(int cpu, int ri)
+{
+	struct pmc *pm;
+	struct pmc_hw *phw;
+	const struct amd_descr *pd;
+	uint64_t config;
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[amd,%d] illegal CPU value %d", __LINE__, cpu));
+	KASSERT(ri >= 0 && ri < AMD_NPMCS,
+	    ("[amd,%d] illegal row-index %d", __LINE__, ri));
+
+	phw = &amd_pcpu[cpu]->pc_amdpmcs[ri];
+	pm  = phw->phw_pmc;
+	pd  = &amd_pmcdesc[ri];
+
+	KASSERT(pm != NULL,
+	    ("[amd,%d] cpu%d,pmc%d no PMC to stop", __LINE__,
+		cpu, ri));
+	KASSERT(!AMD_PMC_IS_STOPPED(pd->pm_evsel),
+	    ("[amd,%d] PMC%d, CPU%d \"%s\" already stopped",
+		__LINE__, ri, cpu, pd->pm_descr.pd_name));
+
+	PMCDBG(MDP,STO,1,"amd-stop ri=%d", ri);
+
+	/* turn off the PMC ENABLE bit */
+	config = pm->pm_md.pm_amd.pm_amd_evsel & ~AMD_PMC_ENABLE;
+	wrmsr(pd->pm_evsel, config);
+	return 0;
+}
+
+/*
+ * Interrupt handler.  This function needs to return '1' if the
+ * interrupt was this CPU's PMCs or '0' otherwise.  It is not allowed
+ * to sleep or do anything a 'fast' interrupt handler is not allowed
+ * to do.
+ */
+
+static int
+amd_intr(int cpu, struct trapframe *tf)
+{
+	int i, error, retval;
+	uint32_t config, evsel, perfctr;
+	struct pmc *pm;
+	struct amd_cpu *pac;
+	pmc_value_t v;
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[amd,%d] out of range CPU %d", __LINE__, cpu));
+
+	PMCDBG(MDP,INT,1, "cpu=%d tf=%p um=%d", cpu, (void *) tf,
+	    TRAPF_USERMODE(tf));
+
+	retval = 0;
+
+	pac = amd_pcpu[cpu];
+
+	/*
+	 * look for all PMCs that have interrupted:
+	 * - look for a running, sampling PMC which has overflowed
+	 *   and which has a valid 'struct pmc' association
+	 *
+	 * If found, we call a helper to process the interrupt.
+	 *
+	 * If multiple PMCs interrupt at the same time, the AMD64
+	 * processor appears to deliver as many NMIs as there are
+	 * outstanding PMC interrupts.  So we process only one NMI
+	 * interrupt at a time.
+	 */
+
+	for (i = 0; retval == 0 && i < AMD_NPMCS; i++) {
+
+		if ((pm = pac->pc_amdpmcs[i].phw_pmc) == NULL ||
+		    !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) {
+			continue;
+		}
+
+		if (!AMD_PMC_HAS_OVERFLOWED(i))
+			continue;
+
+		retval = 1;	/* Found an interrupting PMC. */
+
+		if (pm->pm_state != PMC_STATE_RUNNING)
+			continue;
+
+		/* Stop the PMC, reload count. */
+		evsel   = AMD_PMC_EVSEL_0 + i;
+		perfctr = AMD_PMC_PERFCTR_0 + i;
+		v       = pm->pm_sc.pm_reloadcount;
+		config  = rdmsr(evsel);
+
+		KASSERT((config & ~AMD_PMC_ENABLE) ==
+		    (pm->pm_md.pm_amd.pm_amd_evsel & ~AMD_PMC_ENABLE),
+		    ("[amd,%d] config mismatch reg=0x%x pm=0x%x", __LINE__,
+			config, pm->pm_md.pm_amd.pm_amd_evsel));
+
+		wrmsr(evsel, config & ~AMD_PMC_ENABLE);
+		wrmsr(perfctr, AMD_RELOAD_COUNT_TO_PERFCTR_VALUE(v));
+
+		/* Restart the counter if logging succeeded. */
+		error = pmc_process_interrupt(cpu, pm, tf, TRAPF_USERMODE(tf));
+		if (error == 0)
+			wrmsr(evsel, config | AMD_PMC_ENABLE);
+	}
+
+	atomic_add_int(retval ? &pmc_stats.pm_intr_processed :
+	    &pmc_stats.pm_intr_ignored, 1);
+
+	return (retval);
+}
+
+/*
+ * describe a PMC
+ */
+static int
+amd_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc)
+{
+	int error;
+	size_t copied;
+	const struct amd_descr *pd;
+	struct pmc_hw *phw;
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[amd,%d] illegal CPU %d", __LINE__, cpu));
+	KASSERT(ri >= 0 && ri < AMD_NPMCS,
+	    ("[amd,%d] row-index %d out of range", __LINE__, ri));
+
+	phw = &amd_pcpu[cpu]->pc_amdpmcs[ri];
+	pd  = &amd_pmcdesc[ri];
+
+	if ((error = copystr(pd->pm_descr.pd_name, pi->pm_name,
+		 PMC_NAME_MAX, &copied)) != 0)
+		return error;
+
+	pi->pm_class = pd->pm_descr.pd_class;
+
+	if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) {
+		pi->pm_enabled = TRUE;
+		*ppmc          = phw->phw_pmc;
+	} else {
+		pi->pm_enabled = FALSE;
+		*ppmc          = NULL;
+	}
+
+	return 0;
+}
+
+/*
+ * i386 specific entry points
+ */
+
+/*
+ * return the MSR address of the given PMC.
+ */
+
+static int
+amd_get_msr(int ri, uint32_t *msr)
+{
+	KASSERT(ri >= 0 && ri < AMD_NPMCS,
+	    ("[amd,%d] ri %d out of range", __LINE__, ri));
+
+	*msr = amd_pmcdesc[ri].pm_perfctr - AMD_PMC_PERFCTR_0;
+
+	return (0);
+}
+
+/*
+ * processor dependent initialization.
+ */
+
+static int
+amd_pcpu_init(struct pmc_mdep *md, int cpu)
+{
+	int classindex, first_ri, n;
+	struct pmc_cpu *pc;
+	struct amd_cpu *pac;
+	struct pmc_hw  *phw;
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[amd,%d] insane cpu number %d", __LINE__, cpu));
+
+	PMCDBG(MDP,INI,1,"amd-init cpu=%d", cpu);
+
+	amd_pcpu[cpu] = pac = malloc(sizeof(struct amd_cpu), M_PMC,
+	    M_WAITOK|M_ZERO);
+
+	/*
+	 * Set the content of the hardware descriptors to a known
+	 * state and initialize pointers in the MI per-cpu descriptor.
+	 */
+	pc = pmc_pcpu[cpu];
+#if	defined(__amd64__)
+	classindex = PMC_MDEP_CLASS_INDEX_K8;
+#elif	defined(__i386__)
+	classindex = md->pmd_cputype == PMC_CPU_AMD_K8 ?
+	    PMC_MDEP_CLASS_INDEX_K8 : PMC_MDEP_CLASS_INDEX_K7;
+#endif
+	first_ri = md->pmd_classdep[classindex].pcd_ri;
+
+	KASSERT(pc != NULL, ("[amd,%d] NULL per-cpu pointer", __LINE__));
+
+	for (n = 0, phw = pac->pc_amdpmcs; n < AMD_NPMCS; n++, phw++) {
+		phw->phw_state 	  = PMC_PHW_FLAG_IS_ENABLED |
+		    PMC_PHW_CPU_TO_STATE(cpu) | PMC_PHW_INDEX_TO_STATE(n);
+		phw->phw_pmc	  = NULL;
+		pc->pc_hwpmcs[n + first_ri]  = phw;
+	}
+
+	return (0);
+}
+
+
+/*
+ * processor dependent cleanup prior to the KLD
+ * being unloaded
+ */
+
+static int
+amd_pcpu_fini(struct pmc_mdep *md, int cpu)
+{
+	int classindex, first_ri, i;
+	uint32_t evsel;
+	struct pmc_cpu *pc;
+	struct amd_cpu *pac;
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[amd,%d] insane cpu number (%d)", __LINE__, cpu));
+
+	PMCDBG(MDP,INI,1,"amd-cleanup cpu=%d", cpu);
+
+	/*
+	 * First, turn off all PMCs on this CPU.
+	 */
+	for (i = 0; i < 4; i++) { /* XXX this loop is now not needed */
+		evsel = rdmsr(AMD_PMC_EVSEL_0 + i);
+		evsel &= ~AMD_PMC_ENABLE;
+		wrmsr(AMD_PMC_EVSEL_0 + i, evsel);
+	}
+
+	/*
+	 * Next, free up allocated space.
+	 */
+	if ((pac = amd_pcpu[cpu]) == NULL)
+		return (0);
+
+	amd_pcpu[cpu] = NULL;
+
+#ifdef	DEBUG
+	for (i = 0; i < AMD_NPMCS; i++) {
+		KASSERT(pac->pc_amdpmcs[i].phw_pmc == NULL,
+		    ("[amd,%d] CPU%d/PMC%d in use", __LINE__, cpu, i));
+		KASSERT(AMD_PMC_IS_STOPPED(AMD_PMC_EVSEL_0 + (i-1)),
+		    ("[amd,%d] CPU%d/PMC%d not stopped", __LINE__, cpu, i));
+	}
+#endif
+
+	pc = pmc_pcpu[cpu];
+	KASSERT(pc != NULL, ("[amd,%d] NULL per-cpu state", __LINE__));
+
+#if	defined(__amd64__)
+	classindex = PMC_MDEP_CLASS_INDEX_K8;
+#elif	defined(__i386__)
+	classindex = md->pmd_cputype == PMC_CPU_AMD_K8 ? PMC_MDEP_CLASS_INDEX_K8 :
+	    PMC_MDEP_CLASS_INDEX_K7;
+#endif
+	first_ri = md->pmd_classdep[classindex].pcd_ri;
+
+	/*
+	 * Reset pointers in the MI 'per-cpu' state.
+	 */
+	for (i = 0; i < AMD_NPMCS; i++) {
+		pc->pc_hwpmcs[i + first_ri] = NULL;
+	}
+
+
+	free(pac, M_PMC);
+
+	return (0);
+}
+
+/*
+ * Initialize ourselves.
+ */
+
+struct pmc_mdep *
+pmc_amd_initialize(void)
+{
+	int classindex, error, i, nclasses, ncpus;
+	struct pmc_classdep *pcd;
+	enum pmc_cputype cputype;
+	struct pmc_mdep *pmc_mdep;
+	enum pmc_class class;
+	char *name;
+
+	/*
+	 * The presence of hardware performance counters on the AMD
+	 * Athlon, Duron or later processors, is _not_ indicated by
+	 * any of the processor feature flags set by the 'CPUID'
+	 * instruction, so we only check the 'instruction family'
+	 * field returned by CPUID for instruction family >= 6.
+	 */
+
+	class = cputype = -1;
+	name = NULL;
+	switch (cpu_id & 0xF00) {
+#if	defined(__i386__)
+	case 0x600:		/* Athlon(tm) processor */
+		classindex = PMC_MDEP_CLASS_INDEX_K7;
+		cputype = PMC_CPU_AMD_K7;
+		class = PMC_CLASS_K7;
+		name = "K7";
+		break;
+#endif
+	case 0xF00:		/* Athlon64/Opteron processor */
+		classindex = PMC_MDEP_CLASS_INDEX_K8;
+		cputype = PMC_CPU_AMD_K8;
+		class = PMC_CLASS_K8;
+		name = "K8";
+		break;
+	}
+
+	if ((int) cputype == -1) {
+		(void) printf("pmc: Unknown AMD CPU.\n");
+		return NULL;
+	}
+
+#ifdef	DEBUG
+	amd_pmc_class = class;
+#endif
+
+	/*
+	 * Allocate space for pointers to PMC HW descriptors and for
+	 * the MDEP structure used by MI code.
+	 */
+	amd_pcpu = malloc(sizeof(struct amd_cpu *) * pmc_cpu_max(), M_PMC,
+	    M_WAITOK|M_ZERO);
+
+	/*
+	 * These processors have two classes of PMCs: the TSC and
+	 * programmable PMCs.
+	 */
+	nclasses = 2;
+	pmc_mdep = malloc(sizeof(struct pmc_mdep) + nclasses * sizeof (struct pmc_classdep),
+	    M_PMC, M_WAITOK|M_ZERO);
+
+	pmc_mdep->pmd_cputype = cputype;
+	pmc_mdep->pmd_nclass  = nclasses;
+
+	ncpus = pmc_cpu_max();
+
+	/* Initialize the TSC. */
+	error = pmc_tsc_initialize(pmc_mdep, ncpus);
+	if (error)
+		goto error;
+
+	/* Initialize AMD K7 and K8 PMC handling. */
+	pcd = &pmc_mdep->pmd_classdep[classindex];
+
+	pcd->pcd_caps		= AMD_PMC_CAPS;
+	pcd->pcd_class		= class;
+	pcd->pcd_num		= AMD_NPMCS;
+	pcd->pcd_ri		= pmc_mdep->pmd_npmc;
+	pcd->pcd_width		= 48;
+
+	/* fill in the correct pmc name and class */
+	for (i = 0; i < AMD_NPMCS; i++) {
+		(void) snprintf(amd_pmcdesc[i].pm_descr.pd_name,
+		    sizeof(amd_pmcdesc[i].pm_descr.pd_name), "%s-%d",
+		    name, i);
+		amd_pmcdesc[i].pm_descr.pd_class = class;
+	}
+
+	pcd->pcd_allocate_pmc	= amd_allocate_pmc;
+	pcd->pcd_config_pmc	= amd_config_pmc;
+	pcd->pcd_describe	= amd_describe;
+	pcd->pcd_get_config	= amd_get_config;
+	pcd->pcd_get_msr	= amd_get_msr;
+	pcd->pcd_pcpu_fini	= amd_pcpu_fini;
+	pcd->pcd_pcpu_init	= amd_pcpu_init;
+	pcd->pcd_read_pmc	= amd_read_pmc;
+	pcd->pcd_release_pmc	= amd_release_pmc;
+	pcd->pcd_start_pmc	= amd_start_pmc;
+	pcd->pcd_stop_pmc	= amd_stop_pmc;
+	pcd->pcd_write_pmc	= amd_write_pmc;
+
+	pmc_mdep->pmd_pcpu_init = NULL;
+	pmc_mdep->pmd_pcpu_fini = NULL;
+	pmc_mdep->pmd_intr	= amd_intr;
+	pmc_mdep->pmd_switch_in = amd_switch_in;
+	pmc_mdep->pmd_switch_out = amd_switch_out;
+
+	pmc_mdep->pmd_npmc     += AMD_NPMCS;
+
+	PMCDBG(MDP,INI,0,"%s","amd-initialize");
+
+	return (pmc_mdep);
+
+  error:
+	if (error) {
+		free(pmc_mdep, M_PMC);
+		pmc_mdep = NULL;
+	}
+
+	return (NULL);
+}
+
+/*
+ * Finalization code for AMD CPUs.
+ */
+
+void
+pmc_amd_finalize(struct pmc_mdep *md)
+{
+#if	defined(INVARIANTS)
+	int classindex, i, ncpus, pmcclass;
+#endif
+
+	pmc_tsc_finalize(md);
+
+	KASSERT(amd_pcpu != NULL, ("[amd,%d] NULL per-cpu array pointer",
+	    __LINE__));
+
+#if	defined(INVARIANTS)
+	switch (md->pmd_cputype) {
+#if	defined(__i386__)
+	case PMC_CPU_AMD_K7:
+		classindex = PMC_MDEP_CLASS_INDEX_K7;
+		pmcclass = PMC_CLASS_K7;
+		break;
+#endif
+	default:
+		classindex = PMC_MDEP_CLASS_INDEX_K8;
+		pmcclass = PMC_CLASS_K8;
+	}
+
+	KASSERT(md->pmd_classdep[classindex].pcd_class == pmcclass,
+	    ("[amd,%d] pmc class mismatch", __LINE__));
+
+	ncpus = pmc_cpu_max();
+
+	for (i = 0; i < ncpus; i++)
+		KASSERT(amd_pcpu[i] == NULL, ("[amd,%d] non-null pcpu",
+		    __LINE__));
+#endif
+
+	free(amd_pcpu, M_PMC);
+	amd_pcpu = NULL;
+}
diff --git a/sys/dev/misc/hwpmc/hwpmc_amd.h b/sys/dev/misc/hwpmc/hwpmc_amd.h
new file mode 100644
index 0000000..3fd503e
--- /dev/null
+++ b/sys/dev/misc/hwpmc/hwpmc_amd.h
@@ -0,0 +1,97 @@
+/*-
+ * Copyright (c) 2005, Joseph Koshy
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: src/sys/dev/hwpmc/hwpmc_amd.h,v 1.2 2008/11/09 17:37:54 jkoshy Exp $
+ */
+
+/* Machine dependent interfaces */
+
+#ifndef _DEV_HWPMC_AMD_H_
+#define	_DEV_HWPMC_AMD_H_ 1
+
+/* AMD K7 and K8 PMCs */
+
+#define	AMD_PMC_EVSEL_0		0xC0010000
+#define	AMD_PMC_EVSEL_1		0xC0010001
+#define	AMD_PMC_EVSEL_2		0xC0010002
+#define	AMD_PMC_EVSEL_3		0xC0010003
+
+#define	AMD_PMC_PERFCTR_0	0xC0010004
+#define	AMD_PMC_PERFCTR_1	0xC0010005
+#define	AMD_PMC_PERFCTR_2	0xC0010006
+#define	AMD_PMC_PERFCTR_3	0xC0010007
+
+
+#define	AMD_NPMCS		4
+
+#define	AMD_PMC_COUNTERMASK	0xFF000000
+#define	AMD_PMC_TO_COUNTER(x)	(((x) << 24) & AMD_PMC_COUNTERMASK)
+#define	AMD_PMC_INVERT		(1 << 23)
+#define	AMD_PMC_ENABLE		(1 << 22)
+#define	AMD_PMC_INT		(1 << 20)
+#define	AMD_PMC_PC		(1 << 19)
+#define	AMD_PMC_EDGE		(1 << 18)
+#define	AMD_PMC_OS		(1 << 17)
+#define	AMD_PMC_USR		(1 << 16)
+
+#define	AMD_PMC_UNITMASK_M	0x10
+#define	AMD_PMC_UNITMASK_O	0x08
+#define	AMD_PMC_UNITMASK_E	0x04
+#define	AMD_PMC_UNITMASK_S	0x02
+#define	AMD_PMC_UNITMASK_I	0x01
+#define	AMD_PMC_UNITMASK_MOESI	0x1F
+
+#define	AMD_PMC_UNITMASK	0xFF00
+#define	AMD_PMC_EVENTMASK 	0x00FF
+
+#define	AMD_PMC_TO_UNITMASK(x)	(((x) << 8) & AMD_PMC_UNITMASK)
+#define	AMD_PMC_TO_EVENTMASK(x)	((x) & 0xFF)
+#define	AMD_VALID_BITS		(AMD_PMC_COUNTERMASK | AMD_PMC_INVERT |	\
+	AMD_PMC_ENABLE | AMD_PMC_INT | AMD_PMC_PC | AMD_PMC_EDGE | 	\
+	AMD_PMC_OS | AMD_PMC_USR | AMD_PMC_UNITMASK | AMD_PMC_EVENTMASK)
+
+#define AMD_PMC_CAPS		(PMC_CAP_INTERRUPT | PMC_CAP_USER | 	\
+	PMC_CAP_SYSTEM | PMC_CAP_EDGE | PMC_CAP_THRESHOLD | 		\
+	PMC_CAP_READ | PMC_CAP_WRITE | PMC_CAP_INVERT | PMC_CAP_QUALIFIER)
+
+#define AMD_PMC_IS_STOPPED(evsel) ((rdmsr((evsel)) & AMD_PMC_ENABLE) == 0)
+#define AMD_PMC_HAS_OVERFLOWED(pmc) ((rdpmc(pmc) & (1ULL << 47)) == 0)
+
+#define	AMD_RELOAD_COUNT_TO_PERFCTR_VALUE(V)	(-(V))
+#define	AMD_PERFCTR_VALUE_TO_RELOAD_COUNT(P)	(-(P))
+
+struct pmc_md_amd_op_pmcallocate {
+	uint32_t	pm_amd_config;
+};
+
+#ifdef _KERNEL
+
+/* MD extension for 'struct pmc' */
+struct pmc_md_amd_pmc {
+	uint32_t	pm_amd_evsel;
+};
+
+#endif /* _KERNEL */
+#endif /* _DEV_HWPMC_AMD_H_ */
diff --git a/sys/dev/misc/hwpmc/hwpmc_core.c b/sys/dev/misc/hwpmc/hwpmc_core.c
new file mode 100644
index 0000000..57d4bef
--- /dev/null
+++ b/sys/dev/misc/hwpmc/hwpmc_core.c
@@ -0,0 +1,2268 @@
+/*-
+ * Copyright (c) 2008 Joseph Koshy
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * Intel Core, Core 2 and Atom PMCs.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: src/sys/dev/hwpmc/hwpmc_core.c,v 1.13 2010/09/05 13:31:14 fabient Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/pmc.h>
+#include <sys/pmckern.h>
+#include <sys/systm.h>
+
+#include <machine/intr_machdep.h>
+#include <machine/apicvar.h>
+#include <machine/cpu.h>
+#include <machine/cpufunc.h>
+#include <machine/specialreg.h>
+
+#define	CORE_CPUID_REQUEST		0xA
+#define	CORE_CPUID_REQUEST_SIZE		0x4
+#define	CORE_CPUID_EAX			0x0
+#define	CORE_CPUID_EBX			0x1
+#define	CORE_CPUID_ECX			0x2
+#define	CORE_CPUID_EDX			0x3
+
+#define	IAF_PMC_CAPS			\
+	(PMC_CAP_READ | PMC_CAP_WRITE | PMC_CAP_INTERRUPT)
+#define	IAF_RI_TO_MSR(RI)		((RI) + (1 << 30))
+
+#define	IAP_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_USER | PMC_CAP_SYSTEM | \
+    PMC_CAP_EDGE | PMC_CAP_THRESHOLD | PMC_CAP_READ | PMC_CAP_WRITE |	 \
+    PMC_CAP_INVERT | PMC_CAP_QUALIFIER | PMC_CAP_PRECISE)
+
+/*
+ * "Architectural" events defined by Intel.  The values of these
+ * symbols correspond to positions in the bitmask returned by
+ * the CPUID.0AH instruction.
+ */
+enum core_arch_events {
+	CORE_AE_BRANCH_INSTRUCTION_RETIRED	= 5,
+	CORE_AE_BRANCH_MISSES_RETIRED		= 6,
+	CORE_AE_INSTRUCTION_RETIRED		= 1,
+	CORE_AE_LLC_MISSES			= 4,
+	CORE_AE_LLC_REFERENCE			= 3,
+	CORE_AE_UNHALTED_REFERENCE_CYCLES	= 2,
+	CORE_AE_UNHALTED_CORE_CYCLES		= 0
+};
+
+static enum pmc_cputype	core_cputype;
+
+struct core_cpu {
+	volatile uint32_t	pc_resync;
+	volatile uint32_t	pc_iafctrl;	/* Fixed function control. */
+	volatile uint64_t	pc_globalctrl;	/* Global control register. */
+	struct pmc_hw		pc_corepmcs[];
+};
+
+static struct core_cpu **core_pcpu;
+
+static uint32_t core_architectural_events;
+static uint64_t core_pmcmask;
+
+static int core_iaf_ri;		/* relative index of fixed counters */
+static int core_iaf_width;
+static int core_iaf_npmc;
+
+static int core_iap_width;
+static int core_iap_npmc;
+
+static int
+core_pcpu_noop(struct pmc_mdep *md, int cpu)
+{
+	(void) md;
+	(void) cpu;
+	return (0);
+}
+
+static int
+core_pcpu_init(struct pmc_mdep *md, int cpu)
+{
+	struct pmc_cpu *pc;
+	struct core_cpu *cc;
+	struct pmc_hw *phw;
+	int core_ri, n, npmc;
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[iaf,%d] insane cpu number %d", __LINE__, cpu));
+
+	PMCDBG(MDP,INI,1,"core-init cpu=%d", cpu);
+
+	core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri;
+	npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num;
+
+	if (core_cputype != PMC_CPU_INTEL_CORE)
+		npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num;
+
+	cc = malloc(sizeof(struct core_cpu) + npmc * sizeof(struct pmc_hw),
+	    M_PMC, M_WAITOK | M_ZERO);
+
+	core_pcpu[cpu] = cc;
+	pc = pmc_pcpu[cpu];
+
+	KASSERT(pc != NULL && cc != NULL,
+	    ("[core,%d] NULL per-cpu structures cpu=%d", __LINE__, cpu));
+
+	for (n = 0, phw = cc->pc_corepmcs; n < npmc; n++, phw++) {
+		phw->phw_state 	  = PMC_PHW_FLAG_IS_ENABLED |
+		    PMC_PHW_CPU_TO_STATE(cpu) |
+		    PMC_PHW_INDEX_TO_STATE(n + core_ri);
+		phw->phw_pmc	  = NULL;
+		pc->pc_hwpmcs[n + core_ri]  = phw;
+	}
+
+	return (0);
+}
+
+static int
+core_pcpu_fini(struct pmc_mdep *md, int cpu)
+{
+	int core_ri, n, npmc;
+	struct pmc_cpu *pc;
+	struct core_cpu *cc;
+	uint64_t msr = 0;
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[core,%d] insane cpu number (%d)", __LINE__, cpu));
+
+	PMCDBG(MDP,INI,1,"core-pcpu-fini cpu=%d", cpu);
+
+	if ((cc = core_pcpu[cpu]) == NULL)
+		return (0);
+
+	core_pcpu[cpu] = NULL;
+
+	pc = pmc_pcpu[cpu];
+
+	KASSERT(pc != NULL, ("[core,%d] NULL per-cpu %d state", __LINE__,
+		cpu));
+
+	npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num;
+	core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri;
+
+	for (n = 0; n < npmc; n++) {
+		msr = rdmsr(IAP_EVSEL0 + n) & ~IAP_EVSEL_MASK;
+		wrmsr(IAP_EVSEL0 + n, msr);
+	}
+
+	if (core_cputype != PMC_CPU_INTEL_CORE) {
+		msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK;
+		wrmsr(IAF_CTRL, msr);
+		npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num;
+	}
+
+	for (n = 0; n < npmc; n++)
+		pc->pc_hwpmcs[n + core_ri] = NULL;
+
+	free(cc, M_PMC);
+
+	return (0);
+}
+
+/*
+ * Fixed function counters.
+ */
+
+static pmc_value_t
+iaf_perfctr_value_to_reload_count(pmc_value_t v)
+{
+	v &= (1ULL << core_iaf_width) - 1;
+	return (1ULL << core_iaf_width) - v;
+}
+
+static pmc_value_t
+iaf_reload_count_to_perfctr_value(pmc_value_t rlc)
+{
+	return (1ULL << core_iaf_width) - rlc;
+}
+
+static int
+iaf_allocate_pmc(int cpu, int ri, struct pmc *pm,
+    const struct pmc_op_pmcallocate *a)
+{
+	enum pmc_event ev;
+	uint32_t caps, flags, validflags;
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[core,%d] illegal CPU %d", __LINE__, cpu));
+
+	PMCDBG(MDP,ALL,1, "iaf-allocate ri=%d reqcaps=0x%x", ri, pm->pm_caps);
+
+	if (ri < 0 || ri > core_iaf_npmc)
+		return (EINVAL);
+
+	caps = a->pm_caps;
+
+	if (a->pm_class != PMC_CLASS_IAF ||
+	    (caps & IAF_PMC_CAPS) != caps)
+		return (EINVAL);
+
+	ev = pm->pm_event;
+	if (ev < PMC_EV_IAF_FIRST || ev > PMC_EV_IAF_LAST)
+		return (EINVAL);
+
+	if (ev == PMC_EV_IAF_INSTR_RETIRED_ANY && ri != 0)
+		return (EINVAL);
+	if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_CORE && ri != 1)
+		return (EINVAL);
+	if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_REF && ri != 2)
+		return (EINVAL);
+
+	flags = a->pm_md.pm_iaf.pm_iaf_flags;
+
+	validflags = IAF_MASK;
+
+	if (core_cputype != PMC_CPU_INTEL_ATOM)
+		validflags &= ~IAF_ANY;
+
+	if ((flags & ~validflags) != 0)
+		return (EINVAL);
+
+	if (caps & PMC_CAP_INTERRUPT)
+		flags |= IAF_PMI;
+	if (caps & PMC_CAP_SYSTEM)
+		flags |= IAF_OS;
+	if (caps & PMC_CAP_USER)
+		flags |= IAF_USR;
+	if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0)
+		flags |= (IAF_OS | IAF_USR);
+
+	pm->pm_md.pm_iaf.pm_iaf_ctrl = (flags << (ri * 4));
+
+	PMCDBG(MDP,ALL,2, "iaf-allocate config=0x%jx",
+	    (uintmax_t) pm->pm_md.pm_iaf.pm_iaf_ctrl);
+
+	return (0);
+}
+
+static int
+iaf_config_pmc(int cpu, int ri, struct pmc *pm)
+{
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[core,%d] illegal CPU %d", __LINE__, cpu));
+
+	KASSERT(ri >= 0 && ri < core_iaf_npmc,
+	    ("[core,%d] illegal row-index %d", __LINE__, ri));
+
+	PMCDBG(MDP,CFG,1, "iaf-config cpu=%d ri=%d pm=%p", cpu, ri, pm);
+
+	KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__,
+	    cpu));
+
+	core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc = pm;
+
+	return (0);
+}
+
+static int
+iaf_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc)
+{
+	int error;
+	struct pmc_hw *phw;
+	char iaf_name[PMC_NAME_MAX];
+
+	phw = &core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri];
+
+	(void) snprintf(iaf_name, sizeof(iaf_name), "IAF-%d", ri);
+	if ((error = copystr(iaf_name, pi->pm_name, PMC_NAME_MAX,
+	    NULL)) != 0)
+		return (error);
+
+	pi->pm_class = PMC_CLASS_IAF;
+
+	if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) {
+		pi->pm_enabled = TRUE;
+		*ppmc          = phw->phw_pmc;
+	} else {
+		pi->pm_enabled = FALSE;
+		*ppmc          = NULL;
+	}
+
+	return (0);
+}
+
+static int
+iaf_get_config(int cpu, int ri, struct pmc **ppm)
+{
+	*ppm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc;
+
+	return (0);
+}
+
+static int
+iaf_get_msr(int ri, uint32_t *msr)
+{
+	KASSERT(ri >= 0 && ri < core_iaf_npmc,
+	    ("[iaf,%d] ri %d out of range", __LINE__, ri));
+
+	*msr = IAF_RI_TO_MSR(ri);
+
+	return (0);
+}
+
+static int
+iaf_read_pmc(int cpu, int ri, pmc_value_t *v)
+{
+	struct pmc *pm;
+	pmc_value_t tmp;
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[core,%d] illegal cpu value %d", __LINE__, cpu));
+	KASSERT(ri >= 0 && ri < core_iaf_npmc,
+	    ("[core,%d] illegal row-index %d", __LINE__, ri));
+
+	pm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc;
+
+	KASSERT(pm,
+	    ("[core,%d] cpu %d ri %d(%d) pmc not configured", __LINE__, cpu,
+		ri, ri + core_iaf_ri));
+
+	tmp = rdpmc(IAF_RI_TO_MSR(ri));
+
+	if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
+		*v = iaf_perfctr_value_to_reload_count(tmp);
+	else
+		*v = tmp;
+
+	PMCDBG(MDP,REA,1, "iaf-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri,
+	    IAF_RI_TO_MSR(ri), *v);
+
+	return (0);
+}
+
+static int
+iaf_release_pmc(int cpu, int ri, struct pmc *pmc)
+{
+	PMCDBG(MDP,REL,1, "iaf-release cpu=%d ri=%d pm=%p", cpu, ri, pmc);
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[core,%d] illegal CPU value %d", __LINE__, cpu));
+	KASSERT(ri >= 0 && ri < core_iaf_npmc,
+	    ("[core,%d] illegal row-index %d", __LINE__, ri));
+
+	KASSERT(core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc == NULL,
+	    ("[core,%d] PHW pmc non-NULL", __LINE__));
+
+	return (0);
+}
+
+static int
+iaf_start_pmc(int cpu, int ri)
+{
+	struct pmc *pm;
+	struct core_cpu *iafc;
+	uint64_t msr = 0;
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[core,%d] illegal CPU value %d", __LINE__, cpu));
+	KASSERT(ri >= 0 && ri < core_iaf_npmc,
+	    ("[core,%d] illegal row-index %d", __LINE__, ri));
+
+	PMCDBG(MDP,STA,1,"iaf-start cpu=%d ri=%d", cpu, ri);
+
+	iafc = core_pcpu[cpu];
+	pm = iafc->pc_corepmcs[ri + core_iaf_ri].phw_pmc;
+
+	iafc->pc_iafctrl |= pm->pm_md.pm_iaf.pm_iaf_ctrl;
+
+	msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK;
+	wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK));
+
+	do {
+		iafc->pc_resync = 0;
+		iafc->pc_globalctrl |= (1ULL << (ri + IAF_OFFSET));
+		msr = rdmsr(IA_GLOBAL_CTRL) & ~IAF_GLOBAL_CTRL_MASK;
+		wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl &
+					     IAF_GLOBAL_CTRL_MASK));
+	} while (iafc->pc_resync != 0);
+
+	PMCDBG(MDP,STA,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)",
+	    iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL),
+	    iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL));
+
+	return (0);
+}
+
+static int
+iaf_stop_pmc(int cpu, int ri)
+{
+	uint32_t fc;
+	struct core_cpu *iafc;
+	uint64_t msr = 0;
+
+	PMCDBG(MDP,STO,1,"iaf-stop cpu=%d ri=%d", cpu, ri);
+
+	iafc = core_pcpu[cpu];
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[core,%d] illegal CPU value %d", __LINE__, cpu));
+	KASSERT(ri >= 0 && ri < core_iaf_npmc,
+	    ("[core,%d] illegal row-index %d", __LINE__, ri));
+
+	fc = (IAF_MASK << (ri * 4));
+
+	if (core_cputype != PMC_CPU_INTEL_ATOM)
+		fc &= ~IAF_ANY;
+
+	iafc->pc_iafctrl &= ~fc;
+
+	PMCDBG(MDP,STO,1,"iaf-stop iafctrl=%x", iafc->pc_iafctrl);
+	msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK;
+	wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK));
+
+	do {
+		iafc->pc_resync = 0;
+		iafc->pc_globalctrl &= ~(1ULL << (ri + IAF_OFFSET));
+		msr = rdmsr(IA_GLOBAL_CTRL) & ~IAF_GLOBAL_CTRL_MASK;
+		wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl &
+					     IAF_GLOBAL_CTRL_MASK));
+	} while (iafc->pc_resync != 0);
+
+	PMCDBG(MDP,STO,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)",
+	    iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL),
+	    iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL));
+
+	return (0);
+}
+
+static int
+iaf_write_pmc(int cpu, int ri, pmc_value_t v)
+{
+	struct core_cpu *cc;
+	struct pmc *pm;
+	uint64_t msr;
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[core,%d] illegal cpu value %d", __LINE__, cpu));
+	KASSERT(ri >= 0 && ri < core_iaf_npmc,
+	    ("[core,%d] illegal row-index %d", __LINE__, ri));
+
+	cc = core_pcpu[cpu];
+	pm = cc->pc_corepmcs[ri + core_iaf_ri].phw_pmc;
+
+	KASSERT(pm,
+	    ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, ri));
+
+	if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
+		v = iaf_reload_count_to_perfctr_value(v);
+
+	/* Turn off fixed counters */
+	msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK;
+	wrmsr(IAF_CTRL, msr);
+
+	wrmsr(IAF_CTR0 + ri, v & ((1ULL << core_iaf_width) - 1));
+
+	/* Turn on fixed counters */
+	msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK;
+	wrmsr(IAF_CTRL, msr | (cc->pc_iafctrl & IAF_CTRL_MASK));
+
+	PMCDBG(MDP,WRI,1, "iaf-write cpu=%d ri=%d msr=0x%x v=%jx iafctrl=%jx "
+	    "pmc=%jx", cpu, ri, IAF_RI_TO_MSR(ri), v,
+	    (uintmax_t) rdmsr(IAF_CTRL),
+	    (uintmax_t) rdpmc(IAF_RI_TO_MSR(ri)));
+
+	return (0);
+}
+
+
+static void
+iaf_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth)
+{
+	struct pmc_classdep *pcd;
+
+	KASSERT(md != NULL, ("[iaf,%d] md is NULL", __LINE__));
+
+	PMCDBG(MDP,INI,1, "%s", "iaf-initialize");
+
+	pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF];
+
+	pcd->pcd_caps	= IAF_PMC_CAPS;
+	pcd->pcd_class	= PMC_CLASS_IAF;
+	pcd->pcd_num	= npmc;
+	pcd->pcd_ri	= md->pmd_npmc;
+	pcd->pcd_width	= pmcwidth;
+
+	pcd->pcd_allocate_pmc	= iaf_allocate_pmc;
+	pcd->pcd_config_pmc	= iaf_config_pmc;
+	pcd->pcd_describe	= iaf_describe;
+	pcd->pcd_get_config	= iaf_get_config;
+	pcd->pcd_get_msr	= iaf_get_msr;
+	pcd->pcd_pcpu_fini	= core_pcpu_noop;
+	pcd->pcd_pcpu_init	= core_pcpu_noop;
+	pcd->pcd_read_pmc	= iaf_read_pmc;
+	pcd->pcd_release_pmc	= iaf_release_pmc;
+	pcd->pcd_start_pmc	= iaf_start_pmc;
+	pcd->pcd_stop_pmc	= iaf_stop_pmc;
+	pcd->pcd_write_pmc	= iaf_write_pmc;
+
+	md->pmd_npmc	       += npmc;
+}
+
+/*
+ * Intel programmable PMCs.
+ */
+
+/*
+ * Event descriptor tables.
+ *
+ * For each event id, we track:
+ *
+ * 1. The CPUs that the event is valid for.
+ *
+ * 2. If the event uses a fixed UMASK, the value of the umask field.
+ *    If the event doesn't use a fixed UMASK, a mask of legal bits
+ *    to check against.
+ */
+
+struct iap_event_descr {
+	enum pmc_event	iap_ev;
+	unsigned char	iap_evcode;
+	unsigned char	iap_umask;
+	unsigned char	iap_flags;
+};
+
+#define	IAP_F_CC	(1 << 0)	/* CPU: Core */
+#define	IAP_F_CC2	(1 << 1)	/* CPU: Core2 family */
+#define	IAP_F_CC2E	(1 << 2)	/* CPU: Core2 Extreme only */
+#define	IAP_F_CA	(1 << 3)	/* CPU: Atom */
+#define	IAP_F_I7	(1 << 4)	/* CPU: Core i7 */
+#define	IAP_F_I7O	(1 << 4)	/* CPU: Core i7 (old) */
+#define	IAP_F_WM	(1 << 5)	/* CPU: Westmere */
+#define	IAP_F_FM	(1 << 6)	/* Fixed mask */
+
+#define	IAP_F_ALLCPUSCORE2					\
+    (IAP_F_CC | IAP_F_CC2 | IAP_F_CC2E | IAP_F_CA)
+
+/* Sub fields of UMASK that this event supports. */
+#define	IAP_M_CORE		(1 << 0) /* Core specificity */
+#define	IAP_M_AGENT		(1 << 1) /* Agent specificity */
+#define	IAP_M_PREFETCH		(1 << 2) /* Prefetch */
+#define	IAP_M_MESI		(1 << 3) /* MESI */
+#define	IAP_M_SNOOPRESPONSE	(1 << 4) /* Snoop response */
+#define	IAP_M_SNOOPTYPE		(1 << 5) /* Snoop type */
+#define	IAP_M_TRANSITION	(1 << 6) /* Transition */
+
+#define	IAP_F_CORE		(0x3 << 14) /* Core specificity */
+#define	IAP_F_AGENT		(0x1 << 13) /* Agent specificity */
+#define	IAP_F_PREFETCH		(0x3 << 12) /* Prefetch */
+#define	IAP_F_MESI		(0xF <<  8) /* MESI */
+#define	IAP_F_SNOOPRESPONSE	(0xB <<  8) /* Snoop response */
+#define	IAP_F_SNOOPTYPE		(0x3 <<  8) /* Snoop type */
+#define	IAP_F_TRANSITION	(0x1 << 12) /* Transition */
+
+#define	IAP_PREFETCH_RESERVED	(0x2 << 12)
+#define	IAP_CORE_THIS		(0x1 << 14)
+#define	IAP_CORE_ALL		(0x3 << 14)
+#define	IAP_F_CMASK		0xFF000000
+
+static struct iap_event_descr iap_events[] = {
+#undef IAPDESCR
+#define	IAPDESCR(N,EV,UM,FLAGS) {					\
+	.iap_ev = PMC_EV_IAP_EVENT_##N,					\
+	.iap_evcode = (EV),						\
+	.iap_umask = (UM),						\
+	.iap_flags = (FLAGS)						\
+	}
+
+    IAPDESCR(02H_01H, 0x02, 0x01, IAP_F_FM | IAP_F_I7O),
+    IAPDESCR(02H_81H, 0x02, 0x81, IAP_F_FM | IAP_F_CA),
+
+    IAPDESCR(03H_00H, 0x03, 0x00, IAP_F_FM | IAP_F_CC),
+    IAPDESCR(03H_01H, 0x03, 0x01, IAP_F_FM | IAP_F_I7O),
+    IAPDESCR(03H_02H, 0x03, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_WM),
+    IAPDESCR(03H_04H, 0x03, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O),
+    IAPDESCR(03H_08H, 0x03, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
+    IAPDESCR(03H_10H, 0x03, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
+    IAPDESCR(03H_20H, 0x03, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
+
+    IAPDESCR(04H_00H, 0x04, 0x00, IAP_F_FM | IAP_F_CC),
+    IAPDESCR(04H_01H, 0x04, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O),
+    IAPDESCR(04H_02H, 0x04, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
+    IAPDESCR(04H_07H, 0x04, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(04H_08H, 0x04, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
+
+    IAPDESCR(05H_00H, 0x05, 0x00, IAP_F_FM | IAP_F_CC),
+    IAPDESCR(05H_01H, 0x05, 0x01, IAP_F_FM | IAP_F_I7O),
+    IAPDESCR(05H_02H, 0x05, 0x02, IAP_F_FM | IAP_F_I7O | IAP_F_WM),
+    IAPDESCR(05H_03H, 0x05, 0x03, IAP_F_FM | IAP_F_I7O),
+
+    IAPDESCR(06H_00H, 0x06, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2 |
+	IAP_F_CC2E | IAP_F_CA),
+    IAPDESCR(06H_01H, 0x06, 0x01, IAP_F_FM | IAP_F_I7O),
+    IAPDESCR(06H_02H, 0x06, 0x02, IAP_F_FM | IAP_F_I7O),
+    IAPDESCR(06H_04H, 0x06, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(06H_08H, 0x06, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(06H_0FH, 0x06, 0x0F, IAP_F_FM | IAP_F_I7O),
+
+    IAPDESCR(07H_00H, 0x07, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2),
+    IAPDESCR(07H_01H, 0x07, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(07H_02H, 0x07, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2),
+    IAPDESCR(07H_03H, 0x07, 0x03, IAP_F_FM | IAP_F_ALLCPUSCORE2),
+    IAPDESCR(07H_06H, 0x07, 0x06, IAP_F_FM | IAP_F_CA),
+    IAPDESCR(07H_08H, 0x07, 0x08, IAP_F_FM | IAP_F_CA),
+
+    IAPDESCR(08H_01H, 0x08, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
+	IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(08H_02H, 0x08, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
+	IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(08H_04H, 0x08, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
+	IAP_F_WM),
+    IAPDESCR(08H_05H, 0x08, 0x05, IAP_F_FM | IAP_F_CA),
+    IAPDESCR(08H_06H, 0x08, 0x06, IAP_F_FM | IAP_F_CA),
+    IAPDESCR(08H_07H, 0x08, 0x07, IAP_F_FM | IAP_F_CA),
+    IAPDESCR(08H_08H, 0x08, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
+    IAPDESCR(08H_09H, 0x08, 0x09, IAP_F_FM | IAP_F_CA),
+    IAPDESCR(08H_10H, 0x08, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(08H_20H, 0x08, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(08H_40H, 0x08, 0x40, IAP_F_FM | IAP_F_I7),
+    IAPDESCR(08H_80H, 0x08, 0x80, IAP_F_FM | IAP_F_I7),
+
+    IAPDESCR(09H_01H, 0x09, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O),
+    IAPDESCR(09H_02H, 0x09, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O),
+    IAPDESCR(09H_04H, 0x09, 0x04, IAP_F_FM | IAP_F_I7O),
+    IAPDESCR(09H_08H, 0x09, 0x08, IAP_F_FM | IAP_F_I7O),
+
+    IAPDESCR(0BH_01H, 0x0B, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(0BH_02H, 0x0B, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(0BH_10H, 0x0B, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+
+    IAPDESCR(0CH_01H, 0x0C, 0x01, IAP_F_FM | IAP_F_CC2 | IAP_F_I7 |
+	IAP_F_WM),
+    IAPDESCR(0CH_02H, 0x0C, 0x02, IAP_F_FM | IAP_F_CC2),
+    IAPDESCR(0CH_03H, 0x0C, 0x03, IAP_F_FM | IAP_F_CA),
+
+    IAPDESCR(0EH_01H, 0x0E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(0EH_02H, 0x0E, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+
+    IAPDESCR(0FH_01H, 0x0F, 0x01, IAP_F_FM | IAP_F_I7),
+    IAPDESCR(0FH_02H, 0x0F, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(0FH_08H, 0x0F, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(0FH_10H, 0x0F, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(0FH_20H, 0x0F, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(0FH_80H, 0x0F, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+
+    IAPDESCR(10H_00H, 0x10, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
+    IAPDESCR(10H_01H, 0x10, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(10H_02H, 0x10, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(10H_04H, 0x10, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(10H_08H, 0x10, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(10H_10H, 0x10, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(10H_20H, 0x10, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(10H_40H, 0x10, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(10H_80H, 0x10, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(10H_81H, 0x10, 0x81, IAP_F_FM | IAP_F_CA),
+
+    IAPDESCR(11H_00H, 0x11, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2),
+    IAPDESCR(11H_01H, 0x11, 0x01, IAP_F_FM | IAP_F_CA),
+    IAPDESCR(11H_81H, 0x11, 0x81, IAP_F_FM | IAP_F_CA),
+
+    IAPDESCR(12H_00H, 0x12, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
+    IAPDESCR(12H_01H, 0x12, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(12H_02H, 0x12, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(12H_04H, 0x12, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(12H_08H, 0x12, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(12H_10H, 0x12, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(12H_20H, 0x12, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(12H_40H, 0x12, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(12H_81H, 0x12, 0x81, IAP_F_FM | IAP_F_CA),
+
+    IAPDESCR(13H_00H, 0x13, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
+    IAPDESCR(13H_01H, 0x13, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(13H_02H, 0x13, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(13H_04H, 0x13, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(13H_07H, 0x13, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(13H_81H, 0x13, 0x81, IAP_F_FM | IAP_F_CA),
+
+    IAPDESCR(14H_00H, 0x14, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2),
+    IAPDESCR(14H_01H, 0x14, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(14H_02H, 0x14, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+
+    IAPDESCR(17H_01H, 0x17, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+
+    IAPDESCR(18H_00H, 0x18, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
+    IAPDESCR(18H_01H, 0x18, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+
+    IAPDESCR(19H_00H, 0x19, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
+    IAPDESCR(19H_01H, 0x19, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
+	IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(19H_02H, 0x19, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
+
+    IAPDESCR(1DH_01H, 0x1D, 0x01, IAP_F_FM | IAP_F_I7O),
+    IAPDESCR(1DH_02H, 0x1D, 0x02, IAP_F_FM | IAP_F_I7O),
+    IAPDESCR(1DH_04H, 0x1D, 0x04, IAP_F_FM | IAP_F_I7O),
+
+    IAPDESCR(1EH_01H, 0x1E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+
+    IAPDESCR(20H_01H, 0x20, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(21H, 0x21, IAP_M_CORE, IAP_F_ALLCPUSCORE2),
+    IAPDESCR(22H, 0x22, IAP_M_CORE, IAP_F_CC2),
+    IAPDESCR(23H, 0x23, IAP_M_CORE, IAP_F_ALLCPUSCORE2),
+
+    IAPDESCR(24H, 0x24, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2),
+    IAPDESCR(24H_01H, 0x24, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(24H_02H, 0x24, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(24H_03H, 0x24, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(24H_04H, 0x24, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(24H_08H, 0x24, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(24H_0CH, 0x24, 0x0C, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(24H_10H, 0x24, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(24H_20H, 0x24, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(24H_30H, 0x24, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(24H_40H, 0x24, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(24H_80H, 0x24, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(24H_C0H, 0x24, 0xC0, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(24H_AAH, 0x24, 0xAA, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(24H_FFH, 0x24, 0xFF, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+
+    IAPDESCR(25H, 0x25, IAP_M_CORE, IAP_F_ALLCPUSCORE2),
+
+    IAPDESCR(26H, 0x26, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2),
+    IAPDESCR(26H_01H, 0x26, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(26H_02H, 0x26, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(26H_04H, 0x26, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(26H_08H, 0x26, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(26H_0FH, 0x26, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(26H_10H, 0x26, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(26H_20H, 0x26, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(26H_40H, 0x26, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(26H_80H, 0x26, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(26H_F0H, 0x26, 0xF0, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(26H_FFH, 0x26, 0xFF, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+
+    IAPDESCR(27H, 0x27, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2),
+    IAPDESCR(27H_01H, 0x27, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(27H_02H, 0x27, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(27H_04H, 0x27, 0x04, IAP_F_FM | IAP_F_I7O),
+    IAPDESCR(27H_08H, 0x27, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(27H_0EH, 0x27, 0x0E, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(27H_0FH, 0x27, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(27H_10H, 0x27, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(27H_20H, 0x27, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(27H_40H, 0x27, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(27H_80H, 0x27, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(27H_E0H, 0x27, 0xE0, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(27H_F0H, 0x27, 0xF0, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+
+    IAPDESCR(28H, 0x28, IAP_M_CORE | IAP_M_MESI, IAP_F_ALLCPUSCORE2),
+    IAPDESCR(28H_01H, 0x28, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(28H_02H, 0x28, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(28H_04H, 0x28, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(28H_08H, 0x28, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(28H_0FH, 0x28, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+
+    IAPDESCR(29H, 0x29, IAP_M_CORE | IAP_M_MESI, IAP_F_CC),
+    IAPDESCR(29H, 0x29, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH,
+	IAP_F_CA | IAP_F_CC2),
+    IAPDESCR(2AH, 0x2A, IAP_M_CORE | IAP_M_MESI, IAP_F_ALLCPUSCORE2),
+    IAPDESCR(2BH, 0x2B, IAP_M_CORE | IAP_M_MESI, IAP_F_CA | IAP_F_CC2),
+
+    IAPDESCR(2EH, 0x2E, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH,
+	IAP_F_ALLCPUSCORE2),
+    IAPDESCR(2EH_01H, 0x2E, 0x01, IAP_F_FM | IAP_F_WM),
+    IAPDESCR(2EH_02H, 0x2E, 0x02, IAP_F_FM | IAP_F_WM),
+    IAPDESCR(2EH_41H, 0x2E, 0x41, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7),
+    IAPDESCR(2EH_4FH, 0x2E, 0x4F, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7),
+
+    IAPDESCR(30H, 0x30, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH,
+	IAP_F_ALLCPUSCORE2),
+    IAPDESCR(32H, 0x32, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, IAP_F_CC),
+    IAPDESCR(32H, 0x32, IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
+
+    IAPDESCR(3AH, 0x3A, IAP_M_TRANSITION, IAP_F_CC),
+    IAPDESCR(3AH_00H, 0x3A, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
+
+    IAPDESCR(3BH_C0H, 0x3B, 0xC0, IAP_F_FM | IAP_F_ALLCPUSCORE2),
+
+    IAPDESCR(3CH_00H, 0x3C, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
+        IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(3CH_01H, 0x3C, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
+        IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(3CH_02H, 0x3C, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2),
+
+    IAPDESCR(3DH_01H, 0x3D, 0x01, IAP_F_FM | IAP_F_I7O),
+
+    IAPDESCR(40H, 0x40, IAP_M_MESI, IAP_F_CC | IAP_F_CC2),
+    IAPDESCR(40H_01H, 0x40, 0x01, IAP_F_FM | IAP_F_I7),
+    IAPDESCR(40H_02H, 0x40, 0x02, IAP_F_FM | IAP_F_I7),
+    IAPDESCR(40H_04H, 0x40, 0x04, IAP_F_FM | IAP_F_I7),
+    IAPDESCR(40H_08H, 0x40, 0x08, IAP_F_FM | IAP_F_I7),
+    IAPDESCR(40H_0FH, 0x40, 0x0F, IAP_F_FM | IAP_F_I7),
+    IAPDESCR(40H_21H, 0x40, 0x21, IAP_F_FM | IAP_F_CA),
+
+    IAPDESCR(41H, 0x41, IAP_M_MESI, IAP_F_CC | IAP_F_CC2),
+    IAPDESCR(41H_01H, 0x41, 0x01, IAP_F_FM | IAP_F_I7O),
+    IAPDESCR(41H_02H, 0x41, 0x02, IAP_F_FM | IAP_F_I7),
+    IAPDESCR(41H_04H, 0x41, 0x04, IAP_F_FM | IAP_F_I7),
+    IAPDESCR(41H_08H, 0x41, 0x08, IAP_F_FM | IAP_F_I7),
+    IAPDESCR(41H_0FH, 0x41, 0x0F, IAP_F_FM | IAP_F_I7O),
+    IAPDESCR(41H_22H, 0x41, 0x22, IAP_F_FM | IAP_F_CA),
+
+    IAPDESCR(42H, 0x42, IAP_M_MESI, IAP_F_ALLCPUSCORE2),
+    IAPDESCR(42H_01H, 0x42, 0x01, IAP_F_FM | IAP_F_I7),
+    IAPDESCR(42H_02H, 0x42, 0x02, IAP_F_FM | IAP_F_I7),
+    IAPDESCR(42H_04H, 0x42, 0x04, IAP_F_FM | IAP_F_I7),
+    IAPDESCR(42H_08H, 0x42, 0x08, IAP_F_FM | IAP_F_I7),
+    IAPDESCR(42H_10H, 0x42, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
+
+    IAPDESCR(43H_01H, 0x43, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
+	IAP_F_I7),
+    IAPDESCR(43H_02H, 0x43, 0x02, IAP_F_FM | IAP_F_CA |
+	IAP_F_CC2 | IAP_F_I7),
+
+    IAPDESCR(44H_02H, 0x44, 0x02, IAP_F_FM | IAP_F_CC),
+
+    IAPDESCR(45H_0FH, 0x45, 0x0F, IAP_F_FM | IAP_F_ALLCPUSCORE2),
+
+    IAPDESCR(46H_00H, 0x46, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
+    IAPDESCR(47H_00H, 0x47, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
+
+    IAPDESCR(48H_00H, 0x48, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
+    IAPDESCR(48H_02H, 0x48, 0x02, IAP_F_FM | IAP_F_I7),
+
+    IAPDESCR(49H_00H, 0x49, 0x00, IAP_F_FM | IAP_F_CC),
+    IAPDESCR(49H_01H, 0x49, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
+        IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(49H_02H, 0x49, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
+        IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(49H_04H, 0x49, 0x04, IAP_F_FM | IAP_F_WM),
+    IAPDESCR(49H_10H, 0x49, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(49H_20H, 0x49, 0x20, IAP_F_FM | IAP_F_I7O),
+    IAPDESCR(49H_40H, 0x49, 0x40, IAP_F_FM | IAP_F_I7O),
+    IAPDESCR(49H_80H, 0x49, 0x80, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
+
+    IAPDESCR(4BH_00H, 0x4B, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
+    IAPDESCR(4BH_01H, 0x4B, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7O),
+    IAPDESCR(4BH_02H, 0x4B, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2),
+    IAPDESCR(4BH_03H, 0x4B, 0x03, IAP_F_FM | IAP_F_CC),
+    IAPDESCR(4BH_08H, 0x4B, 0x08, IAP_F_FM | IAP_F_I7O),
+
+    IAPDESCR(4CH_00H, 0x4C, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
+    IAPDESCR(4CH_01H, 0x4C, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+
+    IAPDESCR(4DH_01H, 0x4D, 0x01, IAP_F_FM | IAP_F_I7O),
+
+    IAPDESCR(4EH_01H, 0x4E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(4EH_02H, 0x4E, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(4EH_04H, 0x4E, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(4EH_10H, 0x4E, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
+
+    IAPDESCR(4FH_00H, 0x4F, 0x00, IAP_F_FM | IAP_F_CC),
+    IAPDESCR(4FH_02H, 0x4F, 0x02, IAP_F_FM | IAP_F_I7O),
+    IAPDESCR(4FH_04H, 0x4F, 0x04, IAP_F_FM | IAP_F_I7O),
+    IAPDESCR(4FH_08H, 0x4F, 0x08, IAP_F_FM | IAP_F_I7O),
+    IAPDESCR(4FH_10H, 0x4F, 0x10, IAP_F_FM | IAP_F_WM),
+
+    IAPDESCR(51H_01H, 0x51, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(51H_02H, 0x51, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(51H_04H, 0x51, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(51H_08H, 0x51, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+
+    IAPDESCR(52H_01H, 0x52, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(53H_01H, 0x53, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+
+    IAPDESCR(60H, 0x60, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
+    IAPDESCR(60H_01H, 0x60, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
+    IAPDESCR(60H_02H, 0x60, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
+    IAPDESCR(60H_04H, 0x60, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
+    IAPDESCR(60H_08H, 0x60, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
+
+    IAPDESCR(61H, 0x61, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2),
+    IAPDESCR(61H_00H, 0x61, 0x00, IAP_F_FM | IAP_F_CC),
+
+    IAPDESCR(62H, 0x62, IAP_M_AGENT, IAP_F_ALLCPUSCORE2),
+    IAPDESCR(62H_00H, 0x62, 0x00, IAP_F_FM | IAP_F_CC),
+
+    IAPDESCR(63H, 0x63, IAP_M_AGENT | IAP_M_CORE,
+	IAP_F_CA | IAP_F_CC2),
+    IAPDESCR(63H, 0x63, IAP_M_CORE, IAP_F_CC),
+    IAPDESCR(63H_01H, 0x63, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(63H_02H, 0x63, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+
+    IAPDESCR(64H, 0x64, IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
+    IAPDESCR(64H_40H, 0x64, 0x40, IAP_F_FM | IAP_F_CC),
+
+    IAPDESCR(65H, 0x65, IAP_M_AGENT | IAP_M_CORE,
+	IAP_F_CA | IAP_F_CC2),
+    IAPDESCR(65H, 0x65, IAP_M_CORE, IAP_F_CC),
+
+    IAPDESCR(66H, 0x66, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
+
+    IAPDESCR(67H, 0x67, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
+    IAPDESCR(67H, 0x67, IAP_M_AGENT, IAP_F_CC),
+
+    IAPDESCR(68H, 0x68, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
+    IAPDESCR(69H, 0x69, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
+    IAPDESCR(6AH, 0x6A, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
+    IAPDESCR(6BH, 0x6B, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
+
+    IAPDESCR(6CH, 0x6C, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
+    IAPDESCR(6CH_01H, 0x6C, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+
+    IAPDESCR(6DH, 0x6D, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
+    IAPDESCR(6DH, 0x6D, IAP_M_CORE, IAP_F_CC),
+
+    IAPDESCR(6EH, 0x6E, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
+    IAPDESCR(6EH, 0x6E, IAP_M_CORE, IAP_F_CC),
+
+    IAPDESCR(6FH, 0x6F, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
+    IAPDESCR(6FH, 0x6F, IAP_M_CORE, IAP_F_CC),
+
+    IAPDESCR(70H, 0x70, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
+    IAPDESCR(70H, 0x70, IAP_M_CORE, IAP_F_CC),
+
+    IAPDESCR(77H, 0x77, IAP_M_AGENT | IAP_M_SNOOPRESPONSE,
+	IAP_F_CA | IAP_F_CC2),
+    IAPDESCR(77H, 0x77, IAP_M_AGENT | IAP_M_MESI, IAP_F_CC),
+
+    IAPDESCR(78H, 0x78, IAP_M_CORE, IAP_F_CC),
+    IAPDESCR(78H, 0x78, IAP_M_CORE | IAP_M_SNOOPTYPE, IAP_F_CA | IAP_F_CC2),
+
+    IAPDESCR(7AH, 0x7A, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2),
+
+    IAPDESCR(7BH, 0x7B, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2),
+
+    IAPDESCR(7DH, 0x7D, IAP_M_CORE, IAP_F_ALLCPUSCORE2),
+
+    IAPDESCR(7EH, 0x7E, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
+    IAPDESCR(7EH_00H, 0x7E, 0x00, IAP_F_FM | IAP_F_CC),
+
+    IAPDESCR(7FH, 0x7F, IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
+
+    IAPDESCR(80H_00H, 0x80, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
+    IAPDESCR(80H_01H, 0x80, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(80H_02H, 0x80, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
+	IAP_F_WM),
+    IAPDESCR(80H_03H, 0x80, 0x03, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
+	IAP_F_WM),
+    IAPDESCR(80H_04H, 0x80, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+
+    IAPDESCR(81H_00H, 0x81, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
+    IAPDESCR(81H_01H, 0x81, 0x01, IAP_F_FM | IAP_F_I7O),
+    IAPDESCR(81H_02H, 0x81, 0x02, IAP_F_FM | IAP_F_I7O),
+
+    IAPDESCR(82H_01H, 0x82, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(82H_02H, 0x82, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
+    IAPDESCR(82H_04H, 0x82, 0x04, IAP_F_FM | IAP_F_CA),
+    IAPDESCR(82H_10H, 0x82, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
+    IAPDESCR(82H_12H, 0x82, 0x12, IAP_F_FM | IAP_F_CC2),
+    IAPDESCR(82H_40H, 0x82, 0x40, IAP_F_FM | IAP_F_CC2),
+
+    IAPDESCR(83H_01H, 0x83, 0x01, IAP_F_FM | IAP_F_I7O),
+    IAPDESCR(83H_02H, 0x83, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
+
+    IAPDESCR(85H_00H, 0x85, 0x00, IAP_F_FM | IAP_F_CC),
+    IAPDESCR(85H_01H, 0x85, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(85H_02H, 0x85, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(85H_04H, 0x85, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
+    IAPDESCR(85H_10H, 0x85, 0x10, IAP_F_FM | IAP_F_I7O),
+    IAPDESCR(85H_20H, 0x85, 0x20, IAP_F_FM | IAP_F_I7O),
+    IAPDESCR(85H_40H, 0x85, 0x40, IAP_F_FM | IAP_F_I7O),
+    IAPDESCR(85H_80H, 0x85, 0x80, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
+
+    IAPDESCR(86H_00H, 0x86, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
+
+    IAPDESCR(87H_00H, 0x87, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
+    IAPDESCR(87H_01H, 0x87, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(87H_02H, 0x87, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(87H_04H, 0x87, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(87H_08H, 0x87, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(87H_0FH, 0x87, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+
+    IAPDESCR(88H_00H, 0x88, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
+    IAPDESCR(88H_01H, 0x88, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(88H_02H, 0x88, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(88H_04H, 0x88, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(88H_07H, 0x88, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(88H_08H, 0x88, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(88H_10H, 0x88, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(88H_20H, 0x88, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(88H_30H, 0x88, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(88H_40H, 0x88, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(88H_7FH, 0x88, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+
+    IAPDESCR(89H_00H, 0x89, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
+    IAPDESCR(89H_01H, 0x89, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(89H_02H, 0x89, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(89H_04H, 0x89, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(89H_07H, 0x89, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(89H_08H, 0x89, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(89H_10H, 0x89, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(89H_20H, 0x89, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(89H_30H, 0x89, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(89H_40H, 0x89, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(89H_7FH, 0x89, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+
+    IAPDESCR(8AH_00H, 0x8A, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
+    IAPDESCR(8BH_00H, 0x8B, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
+    IAPDESCR(8CH_00H, 0x8C, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
+    IAPDESCR(8DH_00H, 0x8D, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
+    IAPDESCR(8EH_00H, 0x8E, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
+    IAPDESCR(8FH_00H, 0x8F, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
+
+    IAPDESCR(90H_00H, 0x90, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
+    IAPDESCR(91H_00H, 0x91, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
+    IAPDESCR(92H_00H, 0x92, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
+    IAPDESCR(93H_00H, 0x93, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
+    IAPDESCR(94H_00H, 0x94, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
+
+    IAPDESCR(97H_00H, 0x97, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
+    IAPDESCR(98H_00H, 0x98, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
+    IAPDESCR(A0H_00H, 0xA0, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
+
+    IAPDESCR(A1H_01H, 0xA1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
+    IAPDESCR(A1H_02H, 0xA1, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
+    IAPDESCR(A1H_04H, 0xA1, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
+    IAPDESCR(A1H_08H, 0xA1, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
+    IAPDESCR(A1H_10H, 0xA1, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
+    IAPDESCR(A1H_20H, 0xA1, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
+
+    IAPDESCR(A2H_00H, 0xA2, 0x00, IAP_F_FM | IAP_F_CC),
+    IAPDESCR(A2H_01H, 0xA2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(A2H_02H, 0xA2, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(A2H_04H, 0xA2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(A2H_08H, 0xA2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(A2H_10H, 0xA2, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(A2H_20H, 0xA2, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(A2H_40H, 0xA2, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(A2H_80H, 0xA2, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+
+    IAPDESCR(A6H_01H, 0xA6, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(A7H_01H, 0xA7, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(A8H_01H, 0xA8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+
+    IAPDESCR(AAH_01H, 0xAA, 0x01, IAP_F_FM | IAP_F_CC2),
+    IAPDESCR(AAH_02H, 0xAA, 0x02, IAP_F_FM | IAP_F_CA),
+    IAPDESCR(AAH_03H, 0xAA, 0x03, IAP_F_FM | IAP_F_CA),
+    IAPDESCR(AAH_08H, 0xAA, 0x08, IAP_F_FM | IAP_F_CC2),
+
+    IAPDESCR(ABH_01H, 0xAB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
+    IAPDESCR(ABH_02H, 0xAB, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
+
+    IAPDESCR(AEH_01H, 0xAE, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+
+    IAPDESCR(B0H_00H, 0xB0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
+    IAPDESCR(B0H_01H, 0xB0, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
+    IAPDESCR(B0H_02H, 0xB0, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
+    IAPDESCR(B0H_04H, 0xB0, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
+    IAPDESCR(B0H_08H, 0xB0, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
+    IAPDESCR(B0H_10H, 0xB0, 0x10, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
+    IAPDESCR(B0H_20H, 0xB0, 0x20, IAP_F_FM | IAP_F_I7O),
+    IAPDESCR(B0H_40H, 0xB0, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(B0H_80H, 0xB0, 0x80, IAP_F_FM | IAP_F_CA | IAP_F_WM | IAP_F_I7O),
+
+    IAPDESCR(B1H_00H, 0xB1, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
+    IAPDESCR(B1H_01H, 0xB1, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(B1H_02H, 0xB1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(B1H_04H, 0xB1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(B1H_08H, 0xB1, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(B1H_10H, 0xB1, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(B1H_1FH, 0xB1, 0x1F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(B1H_20H, 0xB1, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(B1H_3FH, 0xB1, 0x3F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(B1H_40H, 0xB1, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(B1H_80H, 0xB1, 0x80, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
+	IAP_F_WM),
+
+    IAPDESCR(B2H_01H, 0xB2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+
+    IAPDESCR(B3H_01H, 0xB3, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
+	IAP_F_WM | IAP_F_I7O),
+    IAPDESCR(B3H_02H, 0xB3, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
+	IAP_F_WM | IAP_F_I7O),
+    IAPDESCR(B3H_04H, 0xB3, 0x04, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
+	IAP_F_WM | IAP_F_I7O),
+    IAPDESCR(B3H_08H, 0xB3, 0x08, IAP_F_FM | IAP_F_ALLCPUSCORE2),
+    IAPDESCR(B3H_10H, 0xB3, 0x10, IAP_F_FM | IAP_F_ALLCPUSCORE2),
+    IAPDESCR(B3H_20H, 0xB3, 0x20, IAP_F_FM | IAP_F_ALLCPUSCORE2),
+    IAPDESCR(B3H_81H, 0xB3, 0x81, IAP_F_FM | IAP_F_CA),
+    IAPDESCR(B3H_82H, 0xB3, 0x82, IAP_F_FM | IAP_F_CA),
+    IAPDESCR(B3H_84H, 0xB3, 0x84, IAP_F_FM | IAP_F_CA),
+    IAPDESCR(B3H_88H, 0xB3, 0x88, IAP_F_FM | IAP_F_CA),
+    IAPDESCR(B3H_90H, 0xB3, 0x90, IAP_F_FM | IAP_F_CA),
+    IAPDESCR(B3H_A0H, 0xB3, 0xA0, IAP_F_FM | IAP_F_CA),
+
+    IAPDESCR(B4H_01H, 0xB4, 0x01, IAP_F_FM | IAP_F_WM),
+    IAPDESCR(B4H_02H, 0xB4, 0x02, IAP_F_FM | IAP_F_WM),
+    IAPDESCR(B4H_04H, 0xB4, 0x04, IAP_F_FM | IAP_F_WM),
+
+    IAPDESCR(B7H_01H, 0xB7, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+
+    IAPDESCR(B8H_01H, 0xB8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(B8H_02H, 0xB8, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(B8H_04H, 0xB8, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+
+    IAPDESCR(BAH_01H, 0xBA, 0x01, IAP_F_FM | IAP_F_I7O),
+    IAPDESCR(BAH_02H, 0xBA, 0x02, IAP_F_FM | IAP_F_I7O),
+
+    IAPDESCR(BBH_01H, 0xBB, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+
+    IAPDESCR(C0H_00H, 0xC0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
+    IAPDESCR(C0H_01H, 0xC0, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
+	IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(C0H_02H, 0xC0, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
+	IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(C0H_04H, 0xC0, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
+	IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(C0H_08H, 0xC0, 0x08, IAP_F_FM | IAP_F_CC2E),
+
+    IAPDESCR(C1H_00H, 0xC1, 0x00, IAP_F_FM | IAP_F_CC),
+    IAPDESCR(C1H_01H, 0xC1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
+    IAPDESCR(C1H_FEH, 0xC1, 0xFE, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
+
+    IAPDESCR(C2H_00H, 0xC2, 0x00, IAP_F_FM | IAP_F_CC),
+    IAPDESCR(C2H_01H, 0xC2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
+	IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(C2H_02H, 0xC2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
+	IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(C2H_04H, 0xC2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
+	IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(C2H_07H, 0xC2, 0x07, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
+    IAPDESCR(C2H_08H, 0xC2, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
+    IAPDESCR(C2H_0FH, 0xC2, 0x0F, IAP_F_FM | IAP_F_CC2),
+    IAPDESCR(C2H_10H, 0xC2, 0x10, IAP_F_FM | IAP_F_CA),
+
+    IAPDESCR(C3H_00H, 0xC3, 0x00, IAP_F_FM | IAP_F_CC),
+    IAPDESCR(C3H_01H, 0xC3, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
+	IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(C3H_02H, 0xC3, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(C3H_04H, 0xC3, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
+	IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(C3H_10H, 0xC3, 0x10, IAP_F_FM | IAP_F_I7O),
+
+    IAPDESCR(C4H_00H, 0xC4, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
+	IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(C4H_01H, 0xC4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
+	IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(C4H_02H, 0xC4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
+	IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(C4H_04H, 0xC4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
+	IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(C4H_08H, 0xC4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
+    IAPDESCR(C4H_0CH, 0xC4, 0x0C, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
+    IAPDESCR(C4H_0FH, 0xC4, 0x0F, IAP_F_FM | IAP_F_CA),
+
+    IAPDESCR(C5H_00H, 0xC5, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
+	IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(C5H_01H, 0xC5, 0x01, IAP_F_FM | IAP_F_WM),
+    IAPDESCR(C5H_02H, 0xC5, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(C5H_04H, 0xC5, 0x04, IAP_F_FM | IAP_F_WM),
+
+    IAPDESCR(C6H_00H, 0xC6, 0x00, IAP_F_FM | IAP_F_CC),
+    IAPDESCR(C6H_01H, 0xC6, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
+    IAPDESCR(C6H_02H, 0xC6, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
+
+    IAPDESCR(C7H_00H, 0xC7, 0x00, IAP_F_FM | IAP_F_CC),
+    IAPDESCR(C7H_01H, 0xC7, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
+	IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(C7H_02H, 0xC7, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
+	IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(C7H_04H, 0xC7, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
+	IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(C7H_08H, 0xC7, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
+	IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(C7H_10H, 0xC7, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
+	IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(C7H_1FH, 0xC7, 0x1F, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
+
+    IAPDESCR(C8H_00H, 0xC8, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
+    IAPDESCR(C8H_20H, 0xC8, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+
+    IAPDESCR(C9H_00H, 0xC9, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
+
+    IAPDESCR(CAH_00H, 0xCA, 0x00, IAP_F_FM | IAP_F_CC),
+    IAPDESCR(CAH_01H, 0xCA, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
+    IAPDESCR(CAH_02H, 0xCA, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
+    IAPDESCR(CAH_04H, 0xCA, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
+    IAPDESCR(CAH_08H, 0xCA, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
+
+    IAPDESCR(CBH_01H, 0xCB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
+	IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(CBH_02H, 0xCB, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
+	IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(CBH_04H, 0xCB, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
+	IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(CBH_08H, 0xCB, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
+	IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(CBH_10H, 0xCB, 0x10, IAP_F_FM | IAP_F_CC2 | IAP_F_I7 |
+	IAP_F_WM),
+    IAPDESCR(CBH_40H, 0xCB, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(CBH_80H, 0xCB, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+
+    IAPDESCR(CCH_00H, 0xCC, 0x00, IAP_F_FM | IAP_F_CC),
+    IAPDESCR(CCH_01H, 0xCC, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
+	IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(CCH_02H, 0xCC, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
+	IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(CCH_03H, 0xCC, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+
+    IAPDESCR(CDH_00H, 0xCD, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
+    IAPDESCR(CEH_00H, 0xCE, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
+    IAPDESCR(CFH_00H, 0xCF, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
+
+    IAPDESCR(D0H_00H, 0xD0, 0x00, IAP_F_FM | IAP_F_CC),
+    IAPDESCR(D0H_01H, 0xD0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+
+    IAPDESCR(D1H_01H, 0xD1, 0x01, IAP_F_FM | IAP_F_WM),
+    IAPDESCR(D1H_02H, 0xD1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(D1H_04H, 0xD1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(D1H_08H, 0xD1, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+
+    IAPDESCR(D2H_01H, 0xD2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
+	IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(D2H_02H, 0xD2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
+	IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(D2H_04H, 0xD2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
+	IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(D2H_08H, 0xD2, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
+	IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(D2H_0FH, 0xD2, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
+	IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(D2H_10H, 0xD2, 0x10, IAP_F_FM | IAP_F_CC2E),
+
+    IAPDESCR(D4H_01H, 0xD4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
+	IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(D4H_02H, 0xD4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
+    IAPDESCR(D4H_04H, 0xD4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
+    IAPDESCR(D4H_08H, 0xD4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
+    IAPDESCR(D4H_0FH, 0xD4, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
+
+    IAPDESCR(D5H_01H, 0xD5, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
+	IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(D5H_02H, 0xD5, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
+    IAPDESCR(D5H_04H, 0xD5, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
+    IAPDESCR(D5H_08H, 0xD5, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
+    IAPDESCR(D5H_0FH, 0xD5, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
+
+    IAPDESCR(D7H_00H, 0xD7, 0x00, IAP_F_FM | IAP_F_CC),
+
+    IAPDESCR(D8H_00H, 0xD8, 0x00, IAP_F_FM | IAP_F_CC),
+    IAPDESCR(D8H_01H, 0xD8, 0x01, IAP_F_FM | IAP_F_CC),
+    IAPDESCR(D8H_02H, 0xD8, 0x02, IAP_F_FM | IAP_F_CC),
+    IAPDESCR(D8H_03H, 0xD8, 0x03, IAP_F_FM | IAP_F_CC),
+    IAPDESCR(D8H_04H, 0xD8, 0x04, IAP_F_FM | IAP_F_CC),
+
+    IAPDESCR(D9H_00H, 0xD9, 0x00, IAP_F_FM | IAP_F_CC),
+    IAPDESCR(D9H_01H, 0xD9, 0x01, IAP_F_FM | IAP_F_CC),
+    IAPDESCR(D9H_02H, 0xD9, 0x02, IAP_F_FM | IAP_F_CC),
+    IAPDESCR(D9H_03H, 0xD9, 0x03, IAP_F_FM | IAP_F_CC),
+
+    IAPDESCR(DAH_00H, 0xDA, 0x00, IAP_F_FM | IAP_F_CC),
+    IAPDESCR(DAH_01H, 0xDA, 0x01, IAP_F_FM | IAP_F_CC),
+    IAPDESCR(DAH_02H, 0xDA, 0x02, IAP_F_FM | IAP_F_CC),
+
+    IAPDESCR(DBH_00H, 0xDB, 0x00, IAP_F_FM | IAP_F_CC),
+    IAPDESCR(DBH_01H, 0xDB, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+
+    IAPDESCR(DCH_01H, 0xDC, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
+    IAPDESCR(DCH_02H, 0xDC, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
+    IAPDESCR(DCH_04H, 0xDC, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
+    IAPDESCR(DCH_08H, 0xDC, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
+    IAPDESCR(DCH_10H, 0xDC, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
+    IAPDESCR(DCH_1FH, 0xDC, 0x1F, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
+
+    IAPDESCR(E0H_00H, 0xE0, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2),
+    IAPDESCR(E0H_01H, 0xE0, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
+	IAP_F_WM),
+
+    IAPDESCR(E2H_00H, 0xE2, 0x00, IAP_F_FM | IAP_F_CC),
+
+    IAPDESCR(E4H_00H, 0xE4, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
+    IAPDESCR(E4H_01H, 0xE4, 0x01, IAP_F_FM | IAP_F_I7O),
+
+    IAPDESCR(E5H_01H, 0xE5, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+
+    IAPDESCR(E6H_00H, 0xE6, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2),
+    IAPDESCR(E6H_01H, 0xE6, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
+	IAP_F_WM),
+    IAPDESCR(E6H_02H, 0xE6, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+
+    IAPDESCR(E8H_01H, 0xE8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(E8H_02H, 0xE8, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(E8H_03H, 0xE8, 0x03, IAP_F_FM | IAP_F_I7),
+
+    IAPDESCR(ECH_01H, 0xEC, 0x01, IAP_F_FM | IAP_F_WM),
+
+    IAPDESCR(F0H_00H, 0xF0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
+    IAPDESCR(F0H_01H, 0xF0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(F0H_02H, 0xF0, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(F0H_04H, 0xF0, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(F0H_08H, 0xF0, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(F0H_10H, 0xF0, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(F0H_20H, 0xF0, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(F0H_40H, 0xF0, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(F0H_80H, 0xF0, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+
+    IAPDESCR(F1H_02H, 0xF1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(F1H_04H, 0xF1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(F1H_07H, 0xF1, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+
+    IAPDESCR(F2H_01H, 0xF2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(F2H_02H, 0xF2, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(F2H_04H, 0xF2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(F2H_08H, 0xF2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(F2H_0FH, 0xF2, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+
+    IAPDESCR(F3H_01H, 0xF3, 0x01, IAP_F_FM | IAP_F_I7O),
+    IAPDESCR(F3H_02H, 0xF3, 0x02, IAP_F_FM | IAP_F_I7O),
+    IAPDESCR(F3H_04H, 0xF3, 0x04, IAP_F_FM | IAP_F_I7O),
+    IAPDESCR(F3H_08H, 0xF3, 0x08, IAP_F_FM | IAP_F_I7O),
+    IAPDESCR(F3H_10H, 0xF3, 0x10, IAP_F_FM | IAP_F_I7O),
+    IAPDESCR(F3H_20H, 0xF3, 0x20, IAP_F_FM | IAP_F_I7O),
+
+    IAPDESCR(F4H_01H, 0xF4, 0x01, IAP_F_FM | IAP_F_I7O),
+    IAPDESCR(F4H_02H, 0xF4, 0x02, IAP_F_FM | IAP_F_I7O),
+    IAPDESCR(F4H_04H, 0xF4, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
+    IAPDESCR(F4H_08H, 0xF4, 0x08, IAP_F_FM | IAP_F_I7O),
+    IAPDESCR(F4H_10H, 0xF4, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+
+    IAPDESCR(F6H_01H, 0xF6, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+
+    IAPDESCR(F7H_01H, 0xF7, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7),
+    IAPDESCR(F7H_02H, 0xF7, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7),
+    IAPDESCR(F7H_04H, 0xF7, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7),
+
+    IAPDESCR(F8H_00H, 0xF8, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
+    IAPDESCR(F8H_01H, 0xF8, 0x01, IAP_F_FM | IAP_F_I7O),
+
+    IAPDESCR(FDH_01H, 0xFD, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7),
+    IAPDESCR(FDH_02H, 0xFD, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7),
+    IAPDESCR(FDH_04H, 0xFD, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7),
+    IAPDESCR(FDH_08H, 0xFD, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7),
+    IAPDESCR(FDH_10H, 0xFD, 0x10, IAP_F_FM | IAP_F_WM | IAP_F_I7),
+    IAPDESCR(FDH_20H, 0xFD, 0x20, IAP_F_FM | IAP_F_WM | IAP_F_I7),
+    IAPDESCR(FDH_40H, 0xFD, 0x40, IAP_F_FM | IAP_F_WM | IAP_F_I7),
+};
+
+static const int niap_events = sizeof(iap_events) / sizeof(iap_events[0]);
+
+static pmc_value_t
+iap_perfctr_value_to_reload_count(pmc_value_t v)
+{
+	v &= (1ULL << core_iap_width) - 1;
+	return (1ULL << core_iap_width) - v;
+}
+
+static pmc_value_t
+iap_reload_count_to_perfctr_value(pmc_value_t rlc)
+{
+	return (1ULL << core_iap_width) - rlc;
+}
+
+static int
+iap_pmc_has_overflowed(int ri)
+{
+	uint64_t v;
+
+	/*
+	 * We treat a Core (i.e., Intel architecture v1) PMC as has
+	 * having overflowed if its MSB is zero.
+	 */
+	v = rdpmc(ri);
+	return ((v & (1ULL << (core_iap_width - 1))) == 0);
+}
+
+/*
+ * Check an event against the set of supported architectural events.
+ *
+ * Returns 1 if the event is architectural and unsupported on this
+ * CPU.  Returns 0 otherwise.
+ */
+
+static int
+iap_architectural_event_is_unsupported(enum pmc_event pe)
+{
+	enum core_arch_events ae;
+
+	switch (pe) {
+	case PMC_EV_IAP_EVENT_3CH_00H:
+		ae = CORE_AE_UNHALTED_CORE_CYCLES;
+		break;
+	case PMC_EV_IAP_EVENT_C0H_00H:
+		ae = CORE_AE_INSTRUCTION_RETIRED;
+		break;
+	case PMC_EV_IAP_EVENT_3CH_01H:
+		ae = CORE_AE_UNHALTED_REFERENCE_CYCLES;
+		break;
+	case PMC_EV_IAP_EVENT_2EH_4FH:
+		ae = CORE_AE_LLC_REFERENCE;
+		break;
+	case PMC_EV_IAP_EVENT_2EH_41H:
+		ae = CORE_AE_LLC_MISSES;
+		break;
+	case PMC_EV_IAP_EVENT_C4H_00H:
+		ae = CORE_AE_BRANCH_INSTRUCTION_RETIRED;
+		break;
+	case PMC_EV_IAP_EVENT_C5H_00H:
+		ae = CORE_AE_BRANCH_MISSES_RETIRED;
+		break;
+
+	default:	/* Non architectural event. */
+		return (0);
+	}
+
+	return ((core_architectural_events & (1 << ae)) == 0);
+}
+
+static int
+iap_event_corei7_ok_on_counter(enum pmc_event pe, int ri)
+{
+	uint32_t mask;
+
+	switch (pe) {
+		/*
+		 * Events valid only on counter 0, 1.
+		 */
+	case PMC_EV_IAP_EVENT_40H_01H:
+	case PMC_EV_IAP_EVENT_40H_02H:
+	case PMC_EV_IAP_EVENT_40H_04H:
+	case PMC_EV_IAP_EVENT_40H_08H:
+	case PMC_EV_IAP_EVENT_40H_0FH:
+	case PMC_EV_IAP_EVENT_41H_02H:
+	case PMC_EV_IAP_EVENT_41H_04H:
+	case PMC_EV_IAP_EVENT_41H_08H:
+	case PMC_EV_IAP_EVENT_42H_01H:
+	case PMC_EV_IAP_EVENT_42H_02H:
+	case PMC_EV_IAP_EVENT_42H_04H:
+	case PMC_EV_IAP_EVENT_42H_08H:
+	case PMC_EV_IAP_EVENT_43H_01H:
+	case PMC_EV_IAP_EVENT_43H_02H:
+	case PMC_EV_IAP_EVENT_48H_02H:
+	case PMC_EV_IAP_EVENT_51H_01H:
+	case PMC_EV_IAP_EVENT_51H_02H:
+	case PMC_EV_IAP_EVENT_51H_04H:
+	case PMC_EV_IAP_EVENT_51H_08H:
+	case PMC_EV_IAP_EVENT_63H_01H:
+	case PMC_EV_IAP_EVENT_63H_02H:
+		mask = 0x3;
+		break;
+
+	default:
+		mask = ~0;	/* Any row index is ok. */
+	}
+
+	return (mask & (1 << ri));
+}
+
+static int
+iap_event_westmere_ok_on_counter(enum pmc_event pe, int ri)
+{
+	uint32_t mask;
+
+	switch (pe) {
+		/*
+		 * Events valid only on counter 0.
+		 */
+	case PMC_EV_IAP_EVENT_B3H_01H:
+	case PMC_EV_IAP_EVENT_B3H_02H:
+	case PMC_EV_IAP_EVENT_B3H_04H:
+		mask = 0x1;
+		break;
+
+		/*
+		 * Events valid only on counter 0, 1.
+		 */
+	case PMC_EV_IAP_EVENT_51H_01H:
+	case PMC_EV_IAP_EVENT_51H_02H:
+	case PMC_EV_IAP_EVENT_51H_04H:
+	case PMC_EV_IAP_EVENT_51H_08H:
+	case PMC_EV_IAP_EVENT_63H_01H:
+	case PMC_EV_IAP_EVENT_63H_02H:
+		mask = 0x3;
+		break;
+
+	default:
+		mask = ~0;	/* Any row index is ok. */
+	}
+
+	return (mask & (1 << ri));
+}
+
+static int
+iap_event_ok_on_counter(enum pmc_event pe, int ri)
+{
+	uint32_t mask;
+
+	switch (pe) {
+		/*
+		 * Events valid only on counter 0.
+		 */
+	case PMC_EV_IAP_EVENT_10H_00H:
+	case PMC_EV_IAP_EVENT_14H_00H:
+	case PMC_EV_IAP_EVENT_18H_00H:
+	case PMC_EV_IAP_EVENT_B3H_01H:
+	case PMC_EV_IAP_EVENT_B3H_02H:
+	case PMC_EV_IAP_EVENT_B3H_04H:
+	case PMC_EV_IAP_EVENT_C1H_00H:
+	case PMC_EV_IAP_EVENT_CBH_01H:
+	case PMC_EV_IAP_EVENT_CBH_02H:
+		mask = (1 << 0);
+		break;
+
+		/*
+		 * Events valid only on counter 1.
+		 */
+	case PMC_EV_IAP_EVENT_11H_00H:
+	case PMC_EV_IAP_EVENT_12H_00H:
+	case PMC_EV_IAP_EVENT_13H_00H:
+		mask = (1 << 1);
+		break;
+
+	default:
+		mask = ~0;	/* Any row index is ok. */
+	}
+
+	return (mask & (1 << ri));
+}
+
+static int
+iap_allocate_pmc(int cpu, int ri, struct pmc *pm,
+    const struct pmc_op_pmcallocate *a)
+{
+	int n;
+	enum pmc_event ev;
+	struct iap_event_descr *ie;
+	uint32_t c, caps, config, cpuflag, evsel, mask;
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[core,%d] illegal CPU %d", __LINE__, cpu));
+	KASSERT(ri >= 0 && ri < core_iap_npmc,
+	    ("[core,%d] illegal row-index value %d", __LINE__, ri));
+
+	/* check requested capabilities */
+	caps = a->pm_caps;
+	if ((IAP_PMC_CAPS & caps) != caps)
+		return (EPERM);
+
+	ev = pm->pm_event;
+
+	if (iap_architectural_event_is_unsupported(ev))
+		return (EOPNOTSUPP);
+
+	switch (core_cputype) {
+	case PMC_CPU_INTEL_COREI7:
+		if (iap_event_corei7_ok_on_counter(ev, ri) == 0)
+			return (EINVAL);
+		break;
+	case PMC_CPU_INTEL_WESTMERE:
+		if (iap_event_westmere_ok_on_counter(ev, ri) == 0)
+			return (EINVAL);
+		break;
+	default:
+		if (iap_event_ok_on_counter(ev, ri) == 0)
+			return (EINVAL);
+	}
+
+	/*
+	 * Look for an event descriptor with matching CPU and event id
+	 * fields.
+	 */
+
+	switch (core_cputype) {
+	default:
+	case PMC_CPU_INTEL_ATOM:
+		cpuflag = IAP_F_CA;
+		break;
+	case PMC_CPU_INTEL_CORE:
+		cpuflag = IAP_F_CC;
+		break;
+	case PMC_CPU_INTEL_CORE2:
+		cpuflag = IAP_F_CC2;
+		break;
+	case PMC_CPU_INTEL_CORE2EXTREME:
+		cpuflag = IAP_F_CC2 | IAP_F_CC2E;
+		break;
+	case PMC_CPU_INTEL_COREI7:
+		cpuflag = IAP_F_I7;
+		break;
+	case PMC_CPU_INTEL_WESTMERE:
+		cpuflag = IAP_F_WM;
+		break;
+	}
+
+	for (n = 0, ie = iap_events; n < niap_events; n++, ie++)
+		if (ie->iap_ev == ev && ie->iap_flags & cpuflag)
+			break;
+
+	if (n == niap_events)
+		return (EINVAL);
+
+	/*
+	 * A matching event descriptor has been found, so start
+	 * assembling the contents of the event select register.
+	 */
+	evsel = ie->iap_evcode;
+
+	config = a->pm_md.pm_iap.pm_iap_config & ~IAP_F_CMASK;
+
+	/*
+	 * If the event uses a fixed umask value, reject any umask
+	 * bits set by the user.
+	 */
+	if (ie->iap_flags & IAP_F_FM) {
+
+		if (IAP_UMASK(config) != 0)
+			return (EINVAL);
+
+		evsel |= (ie->iap_umask << 8);
+
+	} else {
+
+		/*
+		 * Otherwise, the UMASK value needs to be taken from
+		 * the MD fields of the allocation request.  Reject
+		 * requests that specify reserved bits.
+		 */
+
+		mask = 0;
+
+		if (ie->iap_umask & IAP_M_CORE) {
+			if ((c = (config & IAP_F_CORE)) != IAP_CORE_ALL &&
+			    c != IAP_CORE_THIS)
+				return (EINVAL);
+			mask |= IAP_F_CORE;
+		}
+
+		if (ie->iap_umask & IAP_M_AGENT)
+			mask |= IAP_F_AGENT;
+
+		if (ie->iap_umask & IAP_M_PREFETCH) {
+
+			if ((c = (config & IAP_F_PREFETCH)) ==
+			    IAP_PREFETCH_RESERVED)
+				return (EINVAL);
+
+			mask |= IAP_F_PREFETCH;
+		}
+
+		if (ie->iap_umask & IAP_M_MESI)
+			mask |= IAP_F_MESI;
+
+		if (ie->iap_umask & IAP_M_SNOOPRESPONSE)
+			mask |= IAP_F_SNOOPRESPONSE;
+
+		if (ie->iap_umask & IAP_M_SNOOPTYPE)
+			mask |= IAP_F_SNOOPTYPE;
+
+		if (ie->iap_umask & IAP_M_TRANSITION)
+			mask |= IAP_F_TRANSITION;
+
+		/*
+		 * If bits outside of the allowed set of umask bits
+		 * are set, reject the request.
+		 */
+		if (config & ~mask)
+			return (EINVAL);
+
+		evsel |= (config & mask);
+
+	}
+
+	/*
+	 * Only Atom CPUs support the 'ANY' qualifier.
+	 */
+	if (core_cputype == PMC_CPU_INTEL_ATOM)
+		evsel |= (config & IAP_ANY);
+	else if (config & IAP_ANY)
+		return (EINVAL);
+
+	/*
+	 * Check offcore response configuration.
+	 */
+	if (a->pm_md.pm_iap.pm_iap_rsp != 0) {
+		if (ev != PMC_EV_IAP_EVENT_B7H_01H &&
+		    ev != PMC_EV_IAP_EVENT_BBH_01H)
+			return (EINVAL);
+		if (core_cputype == PMC_CPU_INTEL_COREI7 &&
+		    ev == PMC_EV_IAP_EVENT_BBH_01H)
+			return (EINVAL);
+		if ( a->pm_md.pm_iap.pm_iap_rsp & ~IA_OFFCORE_RSP_MASK)
+			return (EINVAL);
+		pm->pm_md.pm_iap.pm_iap_rsp =
+		    a->pm_md.pm_iap.pm_iap_rsp & IA_OFFCORE_RSP_MASK;
+	}
+
+	if (caps & PMC_CAP_THRESHOLD)
+		evsel |= (a->pm_md.pm_iap.pm_iap_config & IAP_F_CMASK);
+	if (caps & PMC_CAP_USER)
+		evsel |= IAP_USR;
+	if (caps & PMC_CAP_SYSTEM)
+		evsel |= IAP_OS;
+	if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0)
+		evsel |= (IAP_OS | IAP_USR);
+	if (caps & PMC_CAP_EDGE)
+		evsel |= IAP_EDGE;
+	if (caps & PMC_CAP_INVERT)
+		evsel |= IAP_INV;
+	if (caps & PMC_CAP_INTERRUPT)
+		evsel |= IAP_INT;
+
+	pm->pm_md.pm_iap.pm_iap_evsel = evsel;
+
+	return (0);
+}
+
+static int
+iap_config_pmc(int cpu, int ri, struct pmc *pm)
+{
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[core,%d] illegal CPU %d", __LINE__, cpu));
+
+	KASSERT(ri >= 0 && ri < core_iap_npmc,
+	    ("[core,%d] illegal row-index %d", __LINE__, ri));
+
+	PMCDBG(MDP,CFG,1, "iap-config cpu=%d ri=%d pm=%p", cpu, ri, pm);
+
+	KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__,
+	    cpu));
+
+	core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc = pm;
+
+	return (0);
+}
+
+static int
+iap_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc)
+{
+	int error;
+	struct pmc_hw *phw;
+	char iap_name[PMC_NAME_MAX];
+
+	phw = &core_pcpu[cpu]->pc_corepmcs[ri];
+
+	(void) snprintf(iap_name, sizeof(iap_name), "IAP-%d", ri);
+	if ((error = copystr(iap_name, pi->pm_name, PMC_NAME_MAX,
+	    NULL)) != 0)
+		return (error);
+
+	pi->pm_class = PMC_CLASS_IAP;
+
+	if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) {
+		pi->pm_enabled = TRUE;
+		*ppmc          = phw->phw_pmc;
+	} else {
+		pi->pm_enabled = FALSE;
+		*ppmc          = NULL;
+	}
+
+	return (0);
+}
+
+static int
+iap_get_config(int cpu, int ri, struct pmc **ppm)
+{
+	*ppm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc;
+
+	return (0);
+}
+
+static int
+iap_get_msr(int ri, uint32_t *msr)
+{
+	KASSERT(ri >= 0 && ri < core_iap_npmc,
+	    ("[iap,%d] ri %d out of range", __LINE__, ri));
+
+	*msr = ri;
+
+	return (0);
+}
+
+static int
+iap_read_pmc(int cpu, int ri, pmc_value_t *v)
+{
+	struct pmc *pm;
+	pmc_value_t tmp;
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[core,%d] illegal cpu value %d", __LINE__, cpu));
+	KASSERT(ri >= 0 && ri < core_iap_npmc,
+	    ("[core,%d] illegal row-index %d", __LINE__, ri));
+
+	pm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc;
+
+	KASSERT(pm,
+	    ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu,
+		ri));
+
+	tmp = rdpmc(ri);
+	if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
+		*v = iap_perfctr_value_to_reload_count(tmp);
+	else
+		*v = tmp;
+
+	PMCDBG(MDP,REA,1, "iap-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri,
+	    ri, *v);
+
+	return (0);
+}
+
+static int
+iap_release_pmc(int cpu, int ri, struct pmc *pm)
+{
+	(void) pm;
+
+	PMCDBG(MDP,REL,1, "iap-release cpu=%d ri=%d pm=%p", cpu, ri,
+	    pm);
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[core,%d] illegal CPU value %d", __LINE__, cpu));
+	KASSERT(ri >= 0 && ri < core_iap_npmc,
+	    ("[core,%d] illegal row-index %d", __LINE__, ri));
+
+	KASSERT(core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc
+	    == NULL, ("[core,%d] PHW pmc non-NULL", __LINE__));
+
+	return (0);
+}
+
+static int
+iap_start_pmc(int cpu, int ri)
+{
+	struct pmc *pm;
+	uint32_t evsel;
+	struct core_cpu *cc;
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[core,%d] illegal CPU value %d", __LINE__, cpu));
+	KASSERT(ri >= 0 && ri < core_iap_npmc,
+	    ("[core,%d] illegal row-index %d", __LINE__, ri));
+
+	cc = core_pcpu[cpu];
+	pm = cc->pc_corepmcs[ri].phw_pmc;
+
+	KASSERT(pm,
+	    ("[core,%d] starting cpu%d,ri%d with no pmc configured",
+		__LINE__, cpu, ri));
+
+	PMCDBG(MDP,STA,1, "iap-start cpu=%d ri=%d", cpu, ri);
+
+	evsel = pm->pm_md.pm_iap.pm_iap_evsel;
+
+	PMCDBG(MDP,STA,2, "iap-start/2 cpu=%d ri=%d evselmsr=0x%x evsel=0x%x",
+	    cpu, ri, IAP_EVSEL0 + ri, evsel);
+
+	/* Event specific configuration. */
+	switch (pm->pm_event) {
+	case PMC_EV_IAP_EVENT_B7H_01H:
+		wrmsr(IA_OFFCORE_RSP0, pm->pm_md.pm_iap.pm_iap_rsp);
+		break;
+	case PMC_EV_IAP_EVENT_BBH_01H:
+		wrmsr(IA_OFFCORE_RSP1, pm->pm_md.pm_iap.pm_iap_rsp);
+		break;
+	default:
+		break;
+	}
+
+	wrmsr(IAP_EVSEL0 + ri, evsel | IAP_EN);
+
+	if (core_cputype == PMC_CPU_INTEL_CORE)
+		return (0);
+
+	do {
+		cc->pc_resync = 0;
+		cc->pc_globalctrl |= (1ULL << ri);
+		wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl);
+	} while (cc->pc_resync != 0);
+
+	return (0);
+}
+
+static int
+iap_stop_pmc(int cpu, int ri)
+{
+	struct pmc *pm;
+	struct core_cpu *cc;
+	uint64_t msr;
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[core,%d] illegal cpu value %d", __LINE__, cpu));
+	KASSERT(ri >= 0 && ri < core_iap_npmc,
+	    ("[core,%d] illegal row index %d", __LINE__, ri));
+
+	cc = core_pcpu[cpu];
+	pm = cc->pc_corepmcs[ri].phw_pmc;
+
+	KASSERT(pm,
+	    ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__,
+		cpu, ri));
+
+	PMCDBG(MDP,STO,1, "iap-stop cpu=%d ri=%d", cpu, ri);
+
+	msr = rdmsr(IAP_EVSEL0 + ri) & ~IAP_EVSEL_MASK;
+	wrmsr(IAP_EVSEL0 + ri, msr);	/* stop hw */
+
+	if (core_cputype == PMC_CPU_INTEL_CORE)
+		return (0);
+
+	msr = 0;
+	do {
+		cc->pc_resync = 0;
+		cc->pc_globalctrl &= ~(1ULL << ri);
+		msr = rdmsr(IA_GLOBAL_CTRL) & ~IA_GLOBAL_CTRL_MASK;
+		wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl);
+	} while (cc->pc_resync != 0);
+
+	return (0);
+}
+
+static int
+iap_write_pmc(int cpu, int ri, pmc_value_t v)
+{
+	struct pmc *pm;
+	struct core_cpu *cc;
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[core,%d] illegal cpu value %d", __LINE__, cpu));
+	KASSERT(ri >= 0 && ri < core_iap_npmc,
+	    ("[core,%d] illegal row index %d", __LINE__, ri));
+
+	cc = core_pcpu[cpu];
+	pm = cc->pc_corepmcs[ri].phw_pmc;
+
+	KASSERT(pm,
+	    ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__,
+		cpu, ri));
+
+	PMCDBG(MDP,WRI,1, "iap-write cpu=%d ri=%d msr=0x%x v=%jx", cpu, ri,
+	    IAP_PMC0 + ri, v);
+
+	if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
+		v = iap_reload_count_to_perfctr_value(v);
+
+	/*
+	 * Write the new value to the counter.  The counter will be in
+	 * a stopped state when the pcd_write() entry point is called.
+	 */
+
+	wrmsr(IAP_PMC0 + ri, v & ((1ULL << core_iap_width) - 1));
+
+	return (0);
+}
+
+
+static void
+iap_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth,
+    int flags)
+{
+	struct pmc_classdep *pcd;
+
+	KASSERT(md != NULL, ("[iap,%d] md is NULL", __LINE__));
+
+	PMCDBG(MDP,INI,1, "%s", "iap-initialize");
+
+	/* Remember the set of architectural events supported. */
+	core_architectural_events = ~flags;
+
+	pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP];
+
+	pcd->pcd_caps	= IAP_PMC_CAPS;
+	pcd->pcd_class	= PMC_CLASS_IAP;
+	pcd->pcd_num	= npmc;
+	pcd->pcd_ri	= md->pmd_npmc;
+	pcd->pcd_width	= pmcwidth;
+
+	pcd->pcd_allocate_pmc	= iap_allocate_pmc;
+	pcd->pcd_config_pmc	= iap_config_pmc;
+	pcd->pcd_describe	= iap_describe;
+	pcd->pcd_get_config	= iap_get_config;
+	pcd->pcd_get_msr	= iap_get_msr;
+	pcd->pcd_pcpu_fini	= core_pcpu_fini;
+	pcd->pcd_pcpu_init	= core_pcpu_init;
+	pcd->pcd_read_pmc	= iap_read_pmc;
+	pcd->pcd_release_pmc	= iap_release_pmc;
+	pcd->pcd_start_pmc	= iap_start_pmc;
+	pcd->pcd_stop_pmc	= iap_stop_pmc;
+	pcd->pcd_write_pmc	= iap_write_pmc;
+
+	md->pmd_npmc	       += npmc;
+}
+
+static int
+core_intr(int cpu, struct trapframe *tf)
+{
+	pmc_value_t v;
+	struct pmc *pm;
+	struct core_cpu *cc;
+	int error, found_interrupt, ri;
+	uint64_t msr;
+
+	PMCDBG(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf,
+	    TRAPF_USERMODE(tf));
+
+	found_interrupt = 0;
+	cc = core_pcpu[cpu];
+
+	for (ri = 0; ri < core_iap_npmc; ri++) {
+
+		if ((pm = cc->pc_corepmcs[ri].phw_pmc) == NULL ||
+		    !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
+			continue;
+
+		if (!iap_pmc_has_overflowed(ri))
+			continue;
+
+		found_interrupt = 1;
+
+		if (pm->pm_state != PMC_STATE_RUNNING)
+			continue;
+
+		error = pmc_process_interrupt(cpu, pm, tf,
+		    TRAPF_USERMODE(tf));
+
+		v = pm->pm_sc.pm_reloadcount;
+		v = iaf_reload_count_to_perfctr_value(v);
+
+		/*
+		 * Stop the counter, reload it but only restart it if
+		 * the PMC is not stalled.
+		 */
+		msr = rdmsr(IAP_EVSEL0 + ri) & ~IAP_EVSEL_MASK;
+		wrmsr(IAP_EVSEL0 + ri, msr);
+		wrmsr(IAP_PMC0 + ri, v);
+
+		if (error)
+			continue;
+
+		wrmsr(IAP_EVSEL0 + ri, msr | (pm->pm_md.pm_iap.pm_iap_evsel |
+					      IAP_EN));
+	}
+
+	if (found_interrupt)
+		lapic_reenable_pmc();
+
+	atomic_add_int(found_interrupt ? &pmc_stats.pm_intr_processed :
+	    &pmc_stats.pm_intr_ignored, 1);
+
+	return (found_interrupt);
+}
+
+static int
+core2_intr(int cpu, struct trapframe *tf)
+{
+	int error, found_interrupt, n;
+	uint64_t flag, intrstatus, intrenable, msr;
+	struct pmc *pm;
+	struct core_cpu *cc;
+	pmc_value_t v;
+
+	PMCDBG(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf,
+	    TRAPF_USERMODE(tf));
+
+	/*
+	 * The IA_GLOBAL_STATUS (MSR 0x38E) register indicates which
+	 * PMCs have a pending PMI interrupt.  We take a 'snapshot' of
+	 * the current set of interrupting PMCs and process these
+	 * after stopping them.
+	 */
+	intrstatus = rdmsr(IA_GLOBAL_STATUS);
+	intrenable = intrstatus & core_pmcmask;
+
+	PMCDBG(MDP,INT, 1, "cpu=%d intrstatus=%jx", cpu,
+	    (uintmax_t) intrstatus);
+
+	found_interrupt = 0;
+	cc = core_pcpu[cpu];
+
+	KASSERT(cc != NULL, ("[core,%d] null pcpu", __LINE__));
+
+	cc->pc_globalctrl &= ~intrenable;
+	cc->pc_resync = 1;	/* MSRs now potentially out of sync. */
+
+	/*
+	 * Stop PMCs and clear overflow status bits.
+	 */
+	msr = rdmsr(IA_GLOBAL_CTRL) & ~IA_GLOBAL_CTRL_MASK;
+	wrmsr(IA_GLOBAL_CTRL, msr);
+	wrmsr(IA_GLOBAL_OVF_CTRL, intrenable |
+	    IA_GLOBAL_STATUS_FLAG_OVFBUF |
+	    IA_GLOBAL_STATUS_FLAG_CONDCHG);
+
+	/*
+	 * Look for interrupts from fixed function PMCs.
+	 */
+	for (n = 0, flag = (1ULL << IAF_OFFSET); n < core_iaf_npmc;
+	     n++, flag <<= 1) {
+
+		if ((intrstatus & flag) == 0)
+			continue;
+
+		found_interrupt = 1;
+
+		pm = cc->pc_corepmcs[n + core_iaf_ri].phw_pmc;
+		if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING ||
+		    !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
+			continue;
+
+		error = pmc_process_interrupt(cpu, pm, tf,
+		    TRAPF_USERMODE(tf));
+		if (error)
+			intrenable &= ~flag;
+
+		v = iaf_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount);
+
+		/* Reload sampling count. */
+		wrmsr(IAF_CTR0 + n, v);
+
+		PMCDBG(MDP,INT, 1, "iaf-intr cpu=%d error=%d v=%jx(%jx)", cpu, error,
+		    (uintmax_t) v, (uintmax_t) rdpmc(IAF_RI_TO_MSR(n)));
+	}
+
+	/*
+	 * Process interrupts from the programmable counters.
+	 */
+	for (n = 0, flag = 1; n < core_iap_npmc; n++, flag <<= 1) {
+		if ((intrstatus & flag) == 0)
+			continue;
+
+		found_interrupt = 1;
+
+		pm = cc->pc_corepmcs[n].phw_pmc;
+		if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING ||
+		    !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
+			continue;
+
+		error = pmc_process_interrupt(cpu, pm, tf,
+		    TRAPF_USERMODE(tf));
+		if (error)
+			intrenable &= ~flag;
+
+		v = iap_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount);
+
+		PMCDBG(MDP,INT, 1, "iap-intr cpu=%d error=%d v=%jx", cpu, error,
+		    (uintmax_t) v);
+
+		/* Reload sampling count. */
+		wrmsr(IAP_PMC0 + n, v);
+	}
+
+	/*
+	 * Reenable all non-stalled PMCs.
+	 */
+	PMCDBG(MDP,INT, 1, "cpu=%d intrenable=%jx", cpu,
+	    (uintmax_t) intrenable);
+
+	cc->pc_globalctrl |= intrenable;
+
+	wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl & IA_GLOBAL_CTRL_MASK);
+
+	PMCDBG(MDP,INT, 1, "cpu=%d fixedctrl=%jx globalctrl=%jx status=%jx "
+	    "ovf=%jx", cpu, (uintmax_t) rdmsr(IAF_CTRL),
+	    (uintmax_t) rdmsr(IA_GLOBAL_CTRL),
+	    (uintmax_t) rdmsr(IA_GLOBAL_STATUS),
+	    (uintmax_t) rdmsr(IA_GLOBAL_OVF_CTRL));
+
+	if (found_interrupt)
+		lapic_reenable_pmc();
+
+	atomic_add_int(found_interrupt ? &pmc_stats.pm_intr_processed :
+	    &pmc_stats.pm_intr_ignored, 1);
+
+	return (found_interrupt);
+}
+
+int
+pmc_core_initialize(struct pmc_mdep *md, int maxcpu)
+{
+	int cpuid[CORE_CPUID_REQUEST_SIZE];
+	int ipa_version, flags, nflags;
+
+	do_cpuid(CORE_CPUID_REQUEST, cpuid);
+
+	ipa_version = cpuid[CORE_CPUID_EAX] & 0xFF;
+
+	PMCDBG(MDP,INI,1,"core-init cputype=%d ncpu=%d ipa-version=%d",
+	    md->pmd_cputype, maxcpu, ipa_version);
+
+	if (ipa_version < 1 || ipa_version > 3)	/* Unknown PMC architecture. */
+		return (EPROGMISMATCH);
+
+	core_cputype = md->pmd_cputype;
+
+	core_pmcmask = 0;
+
+	/*
+	 * Initialize programmable counters.
+	 */
+	KASSERT(ipa_version >= 1,
+	    ("[core,%d] ipa_version %d too small", __LINE__, ipa_version));
+
+	core_iap_npmc = (cpuid[CORE_CPUID_EAX] >> 8) & 0xFF;
+	core_iap_width = (cpuid[CORE_CPUID_EAX] >> 16) & 0xFF;
+
+	core_pmcmask |= ((1ULL << core_iap_npmc) - 1);
+
+	nflags = (cpuid[CORE_CPUID_EAX] >> 24) & 0xFF;
+	flags = cpuid[CORE_CPUID_EBX] & ((1 << nflags) - 1);
+
+	iap_initialize(md, maxcpu, core_iap_npmc, core_iap_width, flags);
+
+	/*
+	 * Initialize fixed function counters, if present.
+	 */
+	if (core_cputype != PMC_CPU_INTEL_CORE) {
+		KASSERT(ipa_version >= 2,
+		    ("[core,%d] ipa_version %d too small", __LINE__,
+			ipa_version));
+
+		core_iaf_ri = core_iap_npmc;
+		core_iaf_npmc = cpuid[CORE_CPUID_EDX] & 0x1F;
+		core_iaf_width = (cpuid[CORE_CPUID_EDX] >> 5) & 0xFF;
+
+		iaf_initialize(md, maxcpu, core_iaf_npmc, core_iaf_width);
+		core_pmcmask |= ((1ULL << core_iaf_npmc) - 1) << IAF_OFFSET;
+	}
+
+	PMCDBG(MDP,INI,1,"core-init pmcmask=0x%jx iafri=%d", core_pmcmask,
+	    core_iaf_ri);
+
+	core_pcpu = malloc(sizeof(struct core_cpu **) * maxcpu, M_PMC,
+	    M_ZERO | M_WAITOK);
+
+	/*
+	 * Choose the appropriate interrupt handler.
+	 */
+	if (ipa_version == 1)
+		md->pmd_intr = core_intr;
+	else
+		md->pmd_intr = core2_intr;
+
+	md->pmd_pcpu_fini = NULL;
+	md->pmd_pcpu_init = NULL;
+
+	return (0);
+}
+
+void
+pmc_core_finalize(struct pmc_mdep *md)
+{
+	PMCDBG(MDP,INI,1, "%s", "core-finalize");
+
+	free(core_pcpu, M_PMC);
+	core_pcpu = NULL;
+}
diff --git a/sys/dev/misc/hwpmc/hwpmc_core.h b/sys/dev/misc/hwpmc/hwpmc_core.h
new file mode 100644
index 0000000..52ac978
--- /dev/null
+++ b/sys/dev/misc/hwpmc/hwpmc_core.h
@@ -0,0 +1,190 @@
+/*-
+ * Copyright (c) 2008 Joseph Koshy
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: src/sys/dev/hwpmc/hwpmc_core.h,v 1.4 2010/07/29 17:52:23 gnn Exp $
+ */
+
+#ifndef _DEV_HWPMC_CORE_H_
+#define	_DEV_HWPMC_CORE_H_ 1
+
+/*
+ * Fixed-function PMCs.
+ */
+struct pmc_md_iaf_op_pmcallocate {
+	uint16_t	pm_iaf_flags;	/* additional flags */
+};
+
+#define	IAF_OS		0x1
+#define	IAF_USR		0x2
+#define	IAF_ANY		0x4
+#define	IAF_PMI		0x8
+
+/*
+ * Programmable PMCs.
+ */
+struct pmc_md_iap_op_pmcallocate {
+	uint32_t	pm_iap_config;
+	uint32_t	pm_iap_rsp;
+};
+
+#define	IAP_EVSEL(C)	((C) & 0xFF)
+#define	IAP_UMASK(C)	((C) & 0xFF00)
+#define	IAP_USR		(1 << 16)
+#define	IAP_OS		(1 << 17)
+#define	IAP_EDGE	(1 << 18)
+#define	IAP_INT		(1 << 20)
+#define	IAP_ANY		(1 << 21)
+#define	IAP_EN		(1 << 22)
+#define	IAP_INV		(1 << 23)
+#define	IAP_CMASK(C)	(((C) & 0xFF) << 24)
+
+#define	IA_OFFCORE_RSP_MASK	0xF7FF
+
+#ifdef	_KERNEL
+
+/*
+ * Fixed-function counters.
+ */
+
+#define	IAF_MASK				0xF
+
+#define	IAF_COUNTER_MASK			0x0000ffffffffffff
+#define	IAF_CTR0				0x309
+#define	IAF_CTR1				0x30A
+#define	IAF_CTR2				0x30B
+
+/*
+ * The IAF_CTRL MSR is laid out in the following way.
+ *
+ * Bit Position    Use
+ * 63 - 12         Reserved (do not touch)
+ * 11              Ctr 2 PMI
+ * 10              Reserved (do not touch)
+ * 9-8             Ctr 2 Enable
+ * 7               Ctr 1 PMI
+ * 6               Reserved (do not touch)
+ * 5-4             Ctr 1 Enable
+ * 3               Ctr 0 PMI
+ * 2               Reserved (do not touch)
+ * 1-0             Ctr 0 Enable (3: All Levels, 2: User, 1: OS, 0: Disable)
+ */
+
+#define	IAF_OFFSET				32
+#define	IAF_CTRL				0x38D
+#define	IAF_CTRL_MASK				0x0000000000000bbb
+
+/*
+ * Programmable counters.
+ */
+
+#define	IAP_PMC0				0x0C1
+
+/*
+ * IAP_EVSEL(n) is laid out in the following way.
+ *
+ * Bit Position    Use
+ * 63-31           Reserved (do not touch)
+ * 31-24           Counter Mask
+ * 23              Invert
+ * 22              Enable
+ * 21              Reserved (do not touch)
+ * 20              APIC Interrupt Enable
+ * 19              Pin Control
+ * 18              Edge Detect
+ * 17              OS
+ * 16              User
+ * 15-8            Unit Mask
+ * 7-0             Event Select
+ */
+
+#define	IAP_EVSEL_MASK				0x00000000ffdfffff
+#define	IAP_EVSEL0				0x186
+
+/*
+ * Simplified programming interface in Intel Performance Architecture
+ * v2 and later.
+ */
+
+#define	IA_GLOBAL_STATUS			0x38E
+#define	IA_GLOBAL_CTRL				0x38F
+
+/*
+ * IA_GLOBAL_CTRL is layed out in the following way.
+ *
+ * Bit Position    Use
+ * 63-35           Reserved (do not touch)
+ * 34              IAF Counter 2 Enable
+ * 33              IAF Counter 1 Enable
+ * 32              IAF Counter 0 Enable
+ * 31-0            Depends on programmable counters
+ */
+
+/* The mask is only for the fixed porttion of the register. */
+#define	IAF_GLOBAL_CTRL_MASK			0x0000000700000000
+
+/* The mask is only for the programmable porttion of the register. */
+#define IAP_GLOBAL_CTRL_MASK			0x00000000ffffffff
+
+/* The mask is for both the fixed and programmable porttions of the register. */
+#define IA_GLOBAL_CTRL_MASK			0x00000007ffffffff
+
+#define	IA_GLOBAL_OVF_CTRL			0x390
+
+#define	IA_GLOBAL_STATUS_FLAG_CONDCHG		(1ULL << 63)
+#define	IA_GLOBAL_STATUS_FLAG_OVFBUF		(1ULL << 62)
+
+/*
+ * Offcore response configuration.
+ */
+#define	IA_OFFCORE_RSP0				0x1A6
+#define	IA_OFFCORE_RSP1				0x1A7
+
+struct pmc_md_iaf_pmc {
+	uint64_t	pm_iaf_ctrl;
+};
+
+struct pmc_md_iap_pmc {
+	uint32_t	pm_iap_evsel;
+	uint32_t	pm_iap_rsp;
+};
+
+/*
+ * Prototypes.
+ */
+
+int	pmc_core_initialize(struct pmc_mdep *_md, int _maxcpu);
+void	pmc_core_finalize(struct pmc_mdep *_md);
+
+void	pmc_core_mark_started(int _cpu, int _pmc);
+
+int	pmc_iaf_initialize(struct pmc_mdep *_md, int _maxcpu, int _npmc, int _width);
+void	pmc_iaf_finalize(struct pmc_mdep *_md);
+
+int	pmc_iap_initialize(struct pmc_mdep *_md, int _maxcpu, int _npmc, int _width,
+	    int _flags);
+void	pmc_iap_finalize(struct pmc_mdep *_md);
+
+#endif	/* _KERNEL */
+#endif	/* _DEV_HWPMC_CORE_H */
diff --git a/sys/dev/misc/hwpmc/hwpmc_intel.c b/sys/dev/misc/hwpmc/hwpmc_intel.c
new file mode 100644
index 0000000..29d231d
--- /dev/null
+++ b/sys/dev/misc/hwpmc/hwpmc_intel.c
@@ -0,0 +1,311 @@
+/*-
+ * Copyright (c) 2008 Joseph Koshy
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * Common code for handling Intel CPUs.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: src/sys/dev/hwpmc/hwpmc_intel.c,v 1.13 2010/04/02 13:23:49 fabient Exp $");
+
+#include <sys/param.h>
+#include <sys/pmc.h>
+#include <sys/pmckern.h>
+#include <sys/systm.h>
+
+#include <machine/cpu.h>
+#include <machine/cputypes.h>
+#include <machine/md_var.h>
+#include <machine/specialreg.h>
+
+static int
+intel_switch_in(struct pmc_cpu *pc, struct pmc_process *pp)
+{
+	(void) pc;
+
+	PMCDBG(MDP,SWI,1, "pc=%p pp=%p enable-msr=%d", pc, pp,
+	    pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS);
+
+	/* allow the RDPMC instruction if needed */
+	if (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS)
+		load_cr4(rcr4() | CR4_PCE);
+
+	PMCDBG(MDP,SWI,1, "cr4=0x%jx", (uintmax_t) rcr4());
+
+	return 0;
+}
+
+static int
+intel_switch_out(struct pmc_cpu *pc, struct pmc_process *pp)
+{
+	(void) pc;
+	(void) pp;		/* can be NULL */
+
+	PMCDBG(MDP,SWO,1, "pc=%p pp=%p cr4=0x%jx", pc, pp,
+	    (uintmax_t) rcr4());
+
+	/* always turn off the RDPMC instruction */
+	load_cr4(rcr4() & ~CR4_PCE);
+
+	return 0;
+}
+
+struct pmc_mdep *
+pmc_intel_initialize(void)
+{
+	struct pmc_mdep *pmc_mdep;
+	enum pmc_cputype cputype;
+	int error, model, nclasses, ncpus;
+
+	KASSERT(cpu_vendor_id == CPU_VENDOR_INTEL,
+	    ("[intel,%d] Initializing non-intel processor", __LINE__));
+
+	PMCDBG(MDP,INI,0, "intel-initialize cpuid=0x%x", cpu_id);
+
+	cputype = -1;
+	nclasses = 2;
+
+	model = ((cpu_id & 0xF0000) >> 12) | ((cpu_id & 0xF0) >> 4);
+
+	switch (cpu_id & 0xF00) {
+#if	defined(__i386__)
+	case 0x500:		/* Pentium family processors */
+		cputype = PMC_CPU_INTEL_P5;
+		break;
+#endif
+	case 0x600:		/* Pentium Pro, Celeron, Pentium II & III */
+		switch (model) {
+#if	defined(__i386__)
+		case 0x1:
+			cputype = PMC_CPU_INTEL_P6;
+			break;
+		case 0x3: case 0x5:
+			cputype = PMC_CPU_INTEL_PII;
+			break;
+		case 0x6: case 0x16:
+			cputype = PMC_CPU_INTEL_CL;
+			break;
+		case 0x7: case 0x8: case 0xA: case 0xB:
+			cputype = PMC_CPU_INTEL_PIII;
+			break;
+		case 0x9: case 0xD:
+			cputype = PMC_CPU_INTEL_PM;
+			break;
+#endif
+		case 0xE:
+			cputype = PMC_CPU_INTEL_CORE;
+			break;
+		case 0xF:
+			cputype = PMC_CPU_INTEL_CORE2;
+			nclasses = 3;
+			break;
+		case 0x17:
+			cputype = PMC_CPU_INTEL_CORE2EXTREME;
+			nclasses = 3;
+			break;
+		case 0x1C:	/* Per Intel document 320047-002. */
+			cputype = PMC_CPU_INTEL_ATOM;
+			nclasses = 3;
+			break;
+		case 0x1A:
+		case 0x1E:	/* Per Intel document 253669-032 9/2009, pages A-2 and A-57 */
+		case 0x1F:	/* Per Intel document 253669-032 9/2009, pages A-2 and A-57 */
+		case 0x2E:
+			cputype = PMC_CPU_INTEL_COREI7;
+			nclasses = 5;
+			break;
+		case 0x25:	/* Per Intel document 253669-033US 12/2009. */
+		case 0x2C:	/* Per Intel document 253669-033US 12/2009. */
+			cputype = PMC_CPU_INTEL_WESTMERE;
+			nclasses = 5;
+			break;
+		}
+		break;
+#if	defined(__i386__) || defined(__amd64__)
+	case 0xF00:		/* P4 */
+		if (model >= 0 && model <= 6) /* known models */
+			cputype = PMC_CPU_INTEL_PIV;
+		break;
+	}
+#endif
+
+	if ((int) cputype == -1) {
+		printf("pmc: Unknown Intel CPU.\n");
+		return (NULL);
+	}
+
+	pmc_mdep = malloc(sizeof(struct pmc_mdep) + nclasses *
+	    sizeof(struct pmc_classdep), M_PMC, M_WAITOK|M_ZERO);
+
+	pmc_mdep->pmd_cputype 	 = cputype;
+	pmc_mdep->pmd_nclass	 = nclasses;
+
+	pmc_mdep->pmd_switch_in	 = intel_switch_in;
+	pmc_mdep->pmd_switch_out = intel_switch_out;
+
+	ncpus = pmc_cpu_max();
+
+	error = pmc_tsc_initialize(pmc_mdep, ncpus);
+	if (error)
+		goto error;
+
+	switch (cputype) {
+#if	defined(__i386__) || defined(__amd64__)
+		/*
+		 * Intel Core, Core 2 and Atom processors.
+		 */
+	case PMC_CPU_INTEL_ATOM:
+	case PMC_CPU_INTEL_CORE:
+	case PMC_CPU_INTEL_CORE2:
+	case PMC_CPU_INTEL_CORE2EXTREME:
+	case PMC_CPU_INTEL_COREI7:
+	case PMC_CPU_INTEL_WESTMERE:
+		error = pmc_core_initialize(pmc_mdep, ncpus);
+		break;
+
+		/*
+		 * Intel Pentium 4 Processors, and P4/EMT64 processors.
+		 */
+
+	case PMC_CPU_INTEL_PIV:
+		error = pmc_p4_initialize(pmc_mdep, ncpus);
+
+		KASSERT(pmc_mdep->pmd_npmc == TSC_NPMCS + P4_NPMCS,
+		    ("[intel,%d] incorrect npmc count %d", __LINE__,
+		    pmc_mdep->pmd_npmc));
+		break;
+#endif
+
+#if	defined(__i386__)
+		/*
+		 * P6 Family Processors
+		 */
+
+	case PMC_CPU_INTEL_P6:
+	case PMC_CPU_INTEL_CL:
+	case PMC_CPU_INTEL_PII:
+	case PMC_CPU_INTEL_PIII:
+	case PMC_CPU_INTEL_PM:
+		error = pmc_p6_initialize(pmc_mdep, ncpus);
+
+		KASSERT(pmc_mdep->pmd_npmc == TSC_NPMCS + P6_NPMCS,
+		    ("[intel,%d] incorrect npmc count %d", __LINE__,
+		    pmc_mdep->pmd_npmc));
+		break;
+
+		/*
+		 * Intel Pentium PMCs.
+		 */
+
+	case PMC_CPU_INTEL_P5:
+		error = pmc_p5_initialize(pmc_mdep, ncpus);
+
+		KASSERT(pmc_mdep->pmd_npmc == TSC_NPMCS + PENTIUM_NPMCS,
+		    ("[intel,%d] incorrect npmc count %d", __LINE__,
+		    pmc_mdep->pmd_npmc));
+		break;
+#endif
+
+	default:
+		KASSERT(0, ("[intel,%d] Unknown CPU type", __LINE__));
+	}
+
+	/*
+	 * Init the uncore class.
+	 */
+#if	defined(__i386__) || defined(__amd64__)
+	switch (cputype) {
+		/*
+		 * Intel Corei7 and Westmere processors.
+		 */
+	case PMC_CPU_INTEL_COREI7:
+	case PMC_CPU_INTEL_WESTMERE:
+		error = pmc_uncore_initialize(pmc_mdep, ncpus);
+		break;
+	default:
+		break;
+	}
+#endif
+
+  error:
+	if (error) {
+		free(pmc_mdep, M_PMC);
+		pmc_mdep = NULL;
+	}
+
+	return (pmc_mdep);
+}
+
+void
+pmc_intel_finalize(struct pmc_mdep *md)
+{
+	pmc_tsc_finalize(md);
+
+	switch (md->pmd_cputype) {
+#if	defined(__i386__) || defined(__amd64__)
+	case PMC_CPU_INTEL_ATOM:
+	case PMC_CPU_INTEL_CORE:
+	case PMC_CPU_INTEL_CORE2:
+	case PMC_CPU_INTEL_CORE2EXTREME:
+	case PMC_CPU_INTEL_COREI7:
+	case PMC_CPU_INTEL_WESTMERE:
+		pmc_core_finalize(md);
+		break;
+
+	case PMC_CPU_INTEL_PIV:
+		pmc_p4_finalize(md);
+		break;
+#endif
+#if	defined(__i386__)
+	case PMC_CPU_INTEL_P6:
+	case PMC_CPU_INTEL_CL:
+	case PMC_CPU_INTEL_PII:
+	case PMC_CPU_INTEL_PIII:
+	case PMC_CPU_INTEL_PM:
+		pmc_p6_finalize(md);
+		break;
+	case PMC_CPU_INTEL_P5:
+		pmc_p5_finalize(md);
+		break;
+#endif
+	default:
+		KASSERT(0, ("[intel,%d] unknown CPU type", __LINE__));
+	}
+
+	/*
+	 * Uncore.
+	 */
+#if	defined(__i386__) || defined(__amd64__)
+	switch (md->pmd_cputype) {
+	case PMC_CPU_INTEL_COREI7:
+	case PMC_CPU_INTEL_WESTMERE:
+		pmc_uncore_finalize(md);
+		break;
+	default:
+		break;
+	}
+#endif
+}
diff --git a/sys/dev/misc/hwpmc/hwpmc_logging.c b/sys/dev/misc/hwpmc/hwpmc_logging.c
new file mode 100644
index 0000000..ff31d5d
--- /dev/null
+++ b/sys/dev/misc/hwpmc/hwpmc_logging.c
@@ -0,0 +1,1024 @@
+/*-
+ * Copyright (c) 2005-2007 Joseph Koshy
+ * Copyright (c) 2007 The FreeBSD Foundation
+ * All rights reserved.
+ *
+ * Portions of this software were developed by A. Joseph Koshy under
+ * sponsorship from the FreeBSD Foundation and Google, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+
+/*
+ * Logging code for hwpmc(4)
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: src/sys/dev/hwpmc/hwpmc_logging.c,v 1.18 2010/03/26 14:35:48 fabient Exp $");
+
+#include <sys/param.h>
+#include <sys/file.h>
+#include <sys/kernel.h>
+#include <sys/kthread.h>
+#include <sys/lock.h>
+#include <sys/module.h>
+#include <sys/mutex.h>
+#include <sys/pmc.h>
+#include <sys/pmckern.h>
+#include <sys/pmclog.h>
+#include <sys/proc.h>
+#include <sys/signalvar.h>
+#include <sys/sysctl.h>
+#include <sys/systm.h>
+#include <sys/uio.h>
+#include <sys/unistd.h>
+#include <sys/vnode.h>
+
+/*
+ * Sysctl tunables
+ */
+
+SYSCTL_DECL(_kern_hwpmc);
+
+/*
+ * kern.hwpmc.logbuffersize -- size of the per-cpu owner buffers.
+ */
+
+static int pmclog_buffer_size = PMC_LOG_BUFFER_SIZE;
+TUNABLE_INT(PMC_SYSCTL_NAME_PREFIX "logbuffersize", &pmclog_buffer_size);
+SYSCTL_INT(_kern_hwpmc, OID_AUTO, logbuffersize, CTLFLAG_TUN|CTLFLAG_RD,
+    &pmclog_buffer_size, 0, "size of log buffers in kilobytes");
+
+/*
+ * kern.hwpmc.nbuffer -- number of global log buffers
+ */
+
+static int pmc_nlogbuffers = PMC_NLOGBUFFERS;
+TUNABLE_INT(PMC_SYSCTL_NAME_PREFIX "nbuffers", &pmc_nlogbuffers);
+SYSCTL_INT(_kern_hwpmc, OID_AUTO, nbuffers, CTLFLAG_TUN|CTLFLAG_RD,
+    &pmc_nlogbuffers, 0, "number of global log buffers");
+
+/*
+ * Global log buffer list and associated spin lock.
+ */
+
+TAILQ_HEAD(, pmclog_buffer) pmc_bufferlist =
+	TAILQ_HEAD_INITIALIZER(pmc_bufferlist);
+static struct mtx pmc_bufferlist_mtx;	/* spin lock */
+static struct mtx pmc_kthread_mtx;	/* sleep lock */
+
+#define	PMCLOG_INIT_BUFFER_DESCRIPTOR(D) do {				\
+		const int __roundup = roundup(sizeof(*D),		\
+			sizeof(uint32_t));				\
+		(D)->plb_fence = ((char *) (D)) +			\
+			 1024*pmclog_buffer_size;			\
+		(D)->plb_base  = (D)->plb_ptr = ((char *) (D)) +	\
+			__roundup;					\
+	} while (0)
+
+
+/*
+ * Log file record constructors.
+ */
+#define	_PMCLOG_TO_HEADER(T,L)						\
+	((PMCLOG_HEADER_MAGIC << 24) |					\
+	 (PMCLOG_TYPE_ ## T << 16)   |					\
+	 ((L) & 0xFFFF))
+
+/* reserve LEN bytes of space and initialize the entry header */
+#define	_PMCLOG_RESERVE(PO,TYPE,LEN,ACTION) do {			\
+		uint32_t *_le;						\
+		int _len = roundup((LEN), sizeof(uint32_t));		\
+		if ((_le = pmclog_reserve((PO), _len)) == NULL) {	\
+			ACTION;						\
+		}							\
+		*_le = _PMCLOG_TO_HEADER(TYPE,_len);			\
+		_le += 3	/* skip over timestamp */
+
+#define	PMCLOG_RESERVE(P,T,L)		_PMCLOG_RESERVE(P,T,L,return)
+#define	PMCLOG_RESERVE_WITH_ERROR(P,T,L) _PMCLOG_RESERVE(P,T,L,		\
+	error=ENOMEM;goto error)
+
+#define	PMCLOG_EMIT32(V)	do { *_le++ = (V); } while (0)
+#define	PMCLOG_EMIT64(V)	do { 					\
+		*_le++ = (uint32_t) ((V) & 0xFFFFFFFF);			\
+		*_le++ = (uint32_t) (((V) >> 32) & 0xFFFFFFFF);		\
+	} while (0)
+
+
+/* Emit a string.  Caution: does NOT update _le, so needs to be last */
+#define	PMCLOG_EMITSTRING(S,L)	do { bcopy((S), _le, (L)); } while (0)
+
+#define	PMCLOG_DESPATCH(PO)						\
+		pmclog_release((PO));					\
+	} while (0)
+
+
+/*
+ * Assertions about the log file format.
+ */
+
+CTASSERT(sizeof(struct pmclog_callchain) == 6*4 +
+    PMC_CALLCHAIN_DEPTH_MAX*sizeof(uintfptr_t));
+CTASSERT(sizeof(struct pmclog_closelog) == 3*4);
+CTASSERT(sizeof(struct pmclog_dropnotify) == 3*4);
+CTASSERT(sizeof(struct pmclog_map_in) == PATH_MAX +
+    4*4 + sizeof(uintfptr_t));
+CTASSERT(offsetof(struct pmclog_map_in,pl_pathname) ==
+    4*4 + sizeof(uintfptr_t));
+CTASSERT(sizeof(struct pmclog_map_out) == 4*4 + 2*sizeof(uintfptr_t));
+CTASSERT(sizeof(struct pmclog_pcsample) == 6*4 + sizeof(uintfptr_t));
+CTASSERT(sizeof(struct pmclog_pmcallocate) == 6*4);
+CTASSERT(sizeof(struct pmclog_pmcattach) == 5*4 + PATH_MAX);
+CTASSERT(offsetof(struct pmclog_pmcattach,pl_pathname) == 5*4);
+CTASSERT(sizeof(struct pmclog_pmcdetach) == 5*4);
+CTASSERT(sizeof(struct pmclog_proccsw) == 5*4 + 8);
+CTASSERT(sizeof(struct pmclog_procexec) == 5*4 + PATH_MAX +
+    sizeof(uintfptr_t));
+CTASSERT(offsetof(struct pmclog_procexec,pl_pathname) == 5*4 +
+    sizeof(uintfptr_t));
+CTASSERT(sizeof(struct pmclog_procexit) == 5*4 + 8);
+CTASSERT(sizeof(struct pmclog_procfork) == 5*4);
+CTASSERT(sizeof(struct pmclog_sysexit) == 4*4);
+CTASSERT(sizeof(struct pmclog_userdata) == 4*4);
+
+/*
+ * Log buffer structure
+ */
+
+struct pmclog_buffer {
+	TAILQ_ENTRY(pmclog_buffer) plb_next;
+	char 		*plb_base;
+	char		*plb_ptr;
+	char 		*plb_fence;
+};
+
+/*
+ * Prototypes
+ */
+
+static int pmclog_get_buffer(struct pmc_owner *po);
+static void pmclog_loop(void *arg);
+static void pmclog_release(struct pmc_owner *po);
+static uint32_t *pmclog_reserve(struct pmc_owner *po, int length);
+static void pmclog_schedule_io(struct pmc_owner *po);
+static void pmclog_stop_kthread(struct pmc_owner *po);
+
+/*
+ * Helper functions
+ */
+
+/*
+ * Get a log buffer
+ */
+
+static int
+pmclog_get_buffer(struct pmc_owner *po)
+{
+	struct pmclog_buffer *plb;
+
+	mtx_assert(&po->po_mtx, MA_OWNED);
+
+	KASSERT(po->po_curbuf == NULL,
+	    ("[pmclog,%d] po=%p current buffer still valid", __LINE__, po));
+
+	mtx_lock_spin(&pmc_bufferlist_mtx);
+	if ((plb = TAILQ_FIRST(&pmc_bufferlist)) != NULL)
+		TAILQ_REMOVE(&pmc_bufferlist, plb, plb_next);
+	mtx_unlock_spin(&pmc_bufferlist_mtx);
+
+	PMCDBG(LOG,GTB,1, "po=%p plb=%p", po, plb);
+
+#ifdef	DEBUG
+	if (plb)
+		KASSERT(plb->plb_ptr == plb->plb_base &&
+		    plb->plb_base < plb->plb_fence,
+		    ("[pmclog,%d] po=%p buffer invariants: ptr=%p "
+		    "base=%p fence=%p", __LINE__, po, plb->plb_ptr,
+		    plb->plb_base, plb->plb_fence));
+#endif
+
+	po->po_curbuf = plb;
+
+	/* update stats */
+	atomic_add_int(&pmc_stats.pm_buffer_requests, 1);
+	if (plb == NULL)
+		atomic_add_int(&pmc_stats.pm_buffer_requests_failed, 1);
+
+	return (plb ? 0 : ENOMEM);
+}
+
+/*
+ * Log handler loop.
+ *
+ * This function is executed by each pmc owner's helper thread.
+ */
+
+static void
+pmclog_loop(void *arg)
+{
+	int error, last_buffer;
+	struct pmc_owner *po;
+	struct pmclog_buffer *lb;
+	struct proc *p;
+	struct ucred *ownercred;
+	struct ucred *mycred;
+	struct thread *td;
+	struct uio auio;
+	struct iovec aiov;
+	size_t nbytes;
+
+	po = (struct pmc_owner *) arg;
+	p = po->po_owner;
+	td = curthread;
+	mycred = td->td_ucred;
+	last_buffer = 0;
+
+	PROC_LOCK(p);
+	ownercred = crhold(p->p_ucred);
+	PROC_UNLOCK(p);
+
+	PMCDBG(LOG,INI,1, "po=%p kt=%p", po, po->po_kthread);
+	KASSERT(po->po_kthread == curthread->td_proc,
+	    ("[pmclog,%d] proc mismatch po=%p po/kt=%p curproc=%p", __LINE__,
+		po, po->po_kthread, curthread->td_proc));
+
+	lb = NULL;
+
+
+	/*
+	 * Loop waiting for I/O requests to be added to the owner
+	 * struct's queue.  The loop is exited when the log file
+	 * is deconfigured.
+	 */
+
+	mtx_lock(&pmc_kthread_mtx);
+
+	for (;;) {
+
+		/* check if we've been asked to exit */
+		if ((po->po_flags & PMC_PO_OWNS_LOGFILE) == 0)
+			break;
+
+		if (lb == NULL) { /* look for a fresh buffer to write */
+			mtx_lock_spin(&po->po_mtx);
+			if ((lb = TAILQ_FIRST(&po->po_logbuffers)) == NULL) {
+				mtx_unlock_spin(&po->po_mtx);
+
+				(void) msleep(po, &pmc_kthread_mtx, PWAIT,
+				    "pmcloop", 0);
+				continue;
+			}
+
+			TAILQ_REMOVE(&po->po_logbuffers, lb, plb_next);
+			if (po->po_flags & PMC_PO_SHUTDOWN)
+				last_buffer = TAILQ_EMPTY(&po->po_logbuffers);
+			mtx_unlock_spin(&po->po_mtx);
+		}
+
+		mtx_unlock(&pmc_kthread_mtx);
+
+		/* process the request */
+		PMCDBG(LOG,WRI,2, "po=%p base=%p ptr=%p", po,
+		    lb->plb_base, lb->plb_ptr);
+		/* change our thread's credentials before issuing the I/O */
+
+		aiov.iov_base = lb->plb_base;
+		aiov.iov_len  = nbytes = lb->plb_ptr - lb->plb_base;
+
+		auio.uio_iov    = &aiov;
+		auio.uio_iovcnt = 1;
+		auio.uio_offset = -1;
+		auio.uio_resid  = nbytes;
+		auio.uio_rw     = UIO_WRITE;
+		auio.uio_segflg = UIO_SYSSPACE;
+		auio.uio_td     = td;
+
+		/* switch thread credentials -- see kern_ktrace.c */
+		td->td_ucred = ownercred;
+		error = fo_write(po->po_file, &auio, ownercred, 0, td);
+		td->td_ucred = mycred;
+
+		if (error) {
+			/* XXX some errors are recoverable */
+			/* send a SIGIO to the owner and exit */
+			PROC_LOCK(p);
+			psignal(p, SIGIO);
+			PROC_UNLOCK(p);
+
+			mtx_lock(&pmc_kthread_mtx);
+
+			po->po_error = error; /* save for flush log */
+
+			PMCDBG(LOG,WRI,2, "po=%p error=%d", po, error);
+
+			break;
+		}
+
+		if (last_buffer) {
+			/*
+			 * Close the file to get PMCLOG_EOF error
+			 * in pmclog(3).
+			 */
+			fo_close(po->po_file, curthread);
+		}
+
+		mtx_lock(&pmc_kthread_mtx);
+
+		/* put the used buffer back into the global pool */
+		PMCLOG_INIT_BUFFER_DESCRIPTOR(lb);
+
+		mtx_lock_spin(&pmc_bufferlist_mtx);
+		TAILQ_INSERT_HEAD(&pmc_bufferlist, lb, plb_next);
+		mtx_unlock_spin(&pmc_bufferlist_mtx);
+
+		lb = NULL;
+	}
+
+	po->po_kthread = NULL;
+
+	mtx_unlock(&pmc_kthread_mtx);
+
+	/* return the current I/O buffer to the global pool */
+	if (lb) {
+		PMCLOG_INIT_BUFFER_DESCRIPTOR(lb);
+
+		mtx_lock_spin(&pmc_bufferlist_mtx);
+		TAILQ_INSERT_HEAD(&pmc_bufferlist, lb, plb_next);
+		mtx_unlock_spin(&pmc_bufferlist_mtx);
+	}
+
+	/*
+	 * Exit this thread, signalling the waiter
+	 */
+
+	crfree(ownercred);
+
+	kproc_exit(0);
+}
+
+/*
+ * Release and log entry and schedule an I/O if needed.
+ */
+
+static void
+pmclog_release(struct pmc_owner *po)
+{
+	KASSERT(po->po_curbuf->plb_ptr >= po->po_curbuf->plb_base,
+	    ("[pmclog,%d] buffer invariants po=%p ptr=%p base=%p", __LINE__,
+		po, po->po_curbuf->plb_ptr, po->po_curbuf->plb_base));
+	KASSERT(po->po_curbuf->plb_ptr <= po->po_curbuf->plb_fence,
+	    ("[pmclog,%d] buffer invariants po=%p ptr=%p fenc=%p", __LINE__,
+		po, po->po_curbuf->plb_ptr, po->po_curbuf->plb_fence));
+
+	/* schedule an I/O if we've filled a buffer */
+	if (po->po_curbuf->plb_ptr >= po->po_curbuf->plb_fence)
+		pmclog_schedule_io(po);
+
+	mtx_unlock_spin(&po->po_mtx);
+
+	PMCDBG(LOG,REL,1, "po=%p", po);
+}
+
+
+/*
+ * Attempt to reserve 'length' bytes of space in an owner's log
+ * buffer.  The function returns a pointer to 'length' bytes of space
+ * if there was enough space or returns NULL if no space was
+ * available.  Non-null returns do so with the po mutex locked.  The
+ * caller must invoke pmclog_release() on the pmc owner structure
+ * when done.
+ */
+
+static uint32_t *
+pmclog_reserve(struct pmc_owner *po, int length)
+{
+	uintptr_t newptr, oldptr;
+	uint32_t *lh;
+	struct timespec ts;
+
+	PMCDBG(LOG,ALL,1, "po=%p len=%d", po, length);
+
+	KASSERT(length % sizeof(uint32_t) == 0,
+	    ("[pmclog,%d] length not a multiple of word size", __LINE__));
+
+	mtx_lock_spin(&po->po_mtx);
+
+	/* No more data when shutdown in progress. */
+	if (po->po_flags & PMC_PO_SHUTDOWN) {
+		mtx_unlock_spin(&po->po_mtx);
+		return (NULL);
+	}
+
+	if (po->po_curbuf == NULL)
+		if (pmclog_get_buffer(po) != 0) {
+			mtx_unlock_spin(&po->po_mtx);
+			return (NULL);
+		}
+
+	KASSERT(po->po_curbuf != NULL,
+	    ("[pmclog,%d] po=%p no current buffer", __LINE__, po));
+
+	KASSERT(po->po_curbuf->plb_ptr >= po->po_curbuf->plb_base &&
+	    po->po_curbuf->plb_ptr <= po->po_curbuf->plb_fence,
+	    ("[pmclog,%d] po=%p buffer invariants: ptr=%p base=%p fence=%p",
+		__LINE__, po, po->po_curbuf->plb_ptr, po->po_curbuf->plb_base,
+		po->po_curbuf->plb_fence));
+
+	oldptr = (uintptr_t) po->po_curbuf->plb_ptr;
+	newptr = oldptr + length;
+
+	KASSERT(oldptr != (uintptr_t) NULL,
+	    ("[pmclog,%d] po=%p Null log buffer pointer", __LINE__, po));
+
+	/*
+	 * If we have space in the current buffer, return a pointer to
+	 * available space with the PO structure locked.
+	 */
+	if (newptr <= (uintptr_t) po->po_curbuf->plb_fence) {
+		po->po_curbuf->plb_ptr = (char *) newptr;
+		goto done;
+	}
+
+	/*
+	 * Otherwise, schedule the current buffer for output and get a
+	 * fresh buffer.
+	 */
+	pmclog_schedule_io(po);
+
+	if (pmclog_get_buffer(po) != 0) {
+		mtx_unlock_spin(&po->po_mtx);
+		return (NULL);
+	}
+
+	KASSERT(po->po_curbuf != NULL,
+	    ("[pmclog,%d] po=%p no current buffer", __LINE__, po));
+
+	KASSERT(po->po_curbuf->plb_ptr != NULL,
+	    ("[pmclog,%d] null return from pmc_get_log_buffer", __LINE__));
+
+	KASSERT(po->po_curbuf->plb_ptr == po->po_curbuf->plb_base &&
+	    po->po_curbuf->plb_ptr <= po->po_curbuf->plb_fence,
+	    ("[pmclog,%d] po=%p buffer invariants: ptr=%p base=%p fence=%p",
+		__LINE__, po, po->po_curbuf->plb_ptr, po->po_curbuf->plb_base,
+		po->po_curbuf->plb_fence));
+
+	oldptr = (uintptr_t) po->po_curbuf->plb_ptr;
+
+ done:
+	lh = (uint32_t *) oldptr;
+	lh++;				/* skip header */
+	getnanotime(&ts);		/* fill in the timestamp */
+	*lh++ = ts.tv_sec & 0xFFFFFFFF;
+	*lh++ = ts.tv_nsec & 0xFFFFFFF;
+	return ((uint32_t *) oldptr);
+}
+
+/*
+ * Schedule an I/O.
+ *
+ * Transfer the current buffer to the helper kthread.
+ */
+
+static void
+pmclog_schedule_io(struct pmc_owner *po)
+{
+	KASSERT(po->po_curbuf != NULL,
+	    ("[pmclog,%d] schedule_io with null buffer po=%p", __LINE__, po));
+
+	KASSERT(po->po_curbuf->plb_ptr >= po->po_curbuf->plb_base,
+	    ("[pmclog,%d] buffer invariants po=%p ptr=%p base=%p", __LINE__,
+		po, po->po_curbuf->plb_ptr, po->po_curbuf->plb_base));
+	KASSERT(po->po_curbuf->plb_ptr <= po->po_curbuf->plb_fence,
+	    ("[pmclog,%d] buffer invariants po=%p ptr=%p fenc=%p", __LINE__,
+		po, po->po_curbuf->plb_ptr, po->po_curbuf->plb_fence));
+
+	PMCDBG(LOG,SIO, 1, "po=%p", po);
+
+	mtx_assert(&po->po_mtx, MA_OWNED);
+
+	/*
+	 * Add the current buffer to the tail of the buffer list and
+	 * wakeup the helper.
+	 */
+	TAILQ_INSERT_TAIL(&po->po_logbuffers, po->po_curbuf, plb_next);
+	po->po_curbuf = NULL;
+	wakeup_one(po);
+}
+
+/*
+ * Stop the helper kthread.
+ */
+
+static void
+pmclog_stop_kthread(struct pmc_owner *po)
+{
+	/*
+	 * Close the file to force the thread out of fo_write,
+	 * unset flag, wakeup the helper thread,
+	 * wait for it to exit
+	 */
+
+	if (po->po_file != NULL)
+		fo_close(po->po_file, curthread);
+
+	mtx_lock(&pmc_kthread_mtx);
+	po->po_flags &= ~PMC_PO_OWNS_LOGFILE;
+	wakeup_one(po);
+	if (po->po_kthread)
+		msleep(po->po_kthread, &pmc_kthread_mtx, PPAUSE, "pmckstp", 0);
+	mtx_unlock(&pmc_kthread_mtx);
+}
+
+/*
+ * Public functions
+ */
+
+/*
+ * Configure a log file for pmc owner 'po'.
+ *
+ * Parameter 'logfd' is a file handle referencing an open file in the
+ * owner process.  This file needs to have been opened for writing.
+ */
+
+int
+pmclog_configure_log(struct pmc_mdep *md, struct pmc_owner *po, int logfd)
+{
+	int error;
+	struct proc *p;
+
+	/*
+	 * As long as it is possible to get a LOR between pmc_sx lock and
+	 * proctree/allproc sx locks used for adding a new process, assure
+	 * the former is not held here.
+	 */
+	sx_assert(&pmc_sx, SA_UNLOCKED);
+	PMCDBG(LOG,CFG,1, "config po=%p logfd=%d", po, logfd);
+
+	p = po->po_owner;
+
+	/* return EBUSY if a log file was already present */
+	if (po->po_flags & PMC_PO_OWNS_LOGFILE)
+		return (EBUSY);
+
+	KASSERT(po->po_kthread == NULL,
+	    ("[pmclog,%d] po=%p kthread (%p) already present", __LINE__, po,
+		po->po_kthread));
+	KASSERT(po->po_file == NULL,
+	    ("[pmclog,%d] po=%p file (%p) already present", __LINE__, po,
+		po->po_file));
+
+	/* get a reference to the file state */
+	error = fget_write(curthread, logfd, &po->po_file);
+	if (error)
+		goto error;
+
+	/* mark process as owning a log file */
+	po->po_flags |= PMC_PO_OWNS_LOGFILE;
+	error = kproc_create(pmclog_loop, po, &po->po_kthread,
+	    RFHIGHPID, 0, "hwpmc: proc(%d)", p->p_pid);
+	if (error)
+		goto error;
+
+	/* mark process as using HWPMCs */
+	PROC_LOCK(p);
+	p->p_flag |= P_HWPMC;
+	PROC_UNLOCK(p);
+
+	/* create a log initialization entry */
+	PMCLOG_RESERVE_WITH_ERROR(po, INITIALIZE,
+	    sizeof(struct pmclog_initialize));
+	PMCLOG_EMIT32(PMC_VERSION);
+	PMCLOG_EMIT32(md->pmd_cputype);
+	PMCLOG_DESPATCH(po);
+
+	return (0);
+
+ error:
+	/* shutdown the thread */
+	if (po->po_kthread)
+		pmclog_stop_kthread(po);
+
+	KASSERT(po->po_kthread == NULL, ("[pmclog,%d] po=%p kthread not "
+	    "stopped", __LINE__, po));
+
+	if (po->po_file)
+		(void) fdrop(po->po_file, curthread);
+	po->po_file  = NULL;	/* clear file and error state */
+	po->po_error = 0;
+
+	return (error);
+}
+
+
+/*
+ * De-configure a log file.  This will throw away any buffers queued
+ * for this owner process.
+ */
+
+int
+pmclog_deconfigure_log(struct pmc_owner *po)
+{
+	int error;
+	struct pmclog_buffer *lb;
+
+	PMCDBG(LOG,CFG,1, "de-config po=%p", po);
+
+	if ((po->po_flags & PMC_PO_OWNS_LOGFILE) == 0)
+		return (EINVAL);
+
+	KASSERT(po->po_sscount == 0,
+	    ("[pmclog,%d] po=%p still owning SS PMCs", __LINE__, po));
+	KASSERT(po->po_file != NULL,
+	    ("[pmclog,%d] po=%p no log file", __LINE__, po));
+
+	/* stop the kthread, this will reset the 'OWNS_LOGFILE' flag */
+	if (po->po_kthread)
+		pmclog_stop_kthread(po);
+
+	KASSERT(po->po_kthread == NULL,
+	    ("[pmclog,%d] po=%p kthread not stopped", __LINE__, po));
+
+	/* return all queued log buffers to the global pool */
+	while ((lb = TAILQ_FIRST(&po->po_logbuffers)) != NULL) {
+		TAILQ_REMOVE(&po->po_logbuffers, lb, plb_next);
+		PMCLOG_INIT_BUFFER_DESCRIPTOR(lb);
+		mtx_lock_spin(&pmc_bufferlist_mtx);
+		TAILQ_INSERT_HEAD(&pmc_bufferlist, lb, plb_next);
+		mtx_unlock_spin(&pmc_bufferlist_mtx);
+	}
+
+	/* return the 'current' buffer to the global pool */
+	if ((lb = po->po_curbuf) != NULL) {
+		PMCLOG_INIT_BUFFER_DESCRIPTOR(lb);
+		mtx_lock_spin(&pmc_bufferlist_mtx);
+		TAILQ_INSERT_HEAD(&pmc_bufferlist, lb, plb_next);
+		mtx_unlock_spin(&pmc_bufferlist_mtx);
+	}
+
+	/* drop a reference to the fd */
+	error = fdrop(po->po_file, curthread);
+	po->po_file  = NULL;
+	po->po_error = 0;
+
+	return (error);
+}
+
+/*
+ * Flush a process' log buffer.
+ */
+
+int
+pmclog_flush(struct pmc_owner *po)
+{
+	int error;
+
+	PMCDBG(LOG,FLS,1, "po=%p", po);
+
+	/*
+	 * If there is a pending error recorded by the logger thread,
+	 * return that.
+	 */
+	if (po->po_error)
+		return (po->po_error);
+
+	error = 0;
+
+	/*
+	 * Check that we do have an active log file.
+	 */
+	mtx_lock(&pmc_kthread_mtx);
+	if ((po->po_flags & PMC_PO_OWNS_LOGFILE) == 0) {
+		error = EINVAL;
+		goto error;
+	}
+
+	/*
+	 * Schedule the current buffer if any.
+	 */
+	mtx_lock_spin(&po->po_mtx);
+	if (po->po_curbuf)
+		pmclog_schedule_io(po);
+	mtx_unlock_spin(&po->po_mtx);
+
+	/*
+	 * Initiate shutdown: no new data queued,
+	 * thread will close file on last block.
+	 */
+	po->po_flags |= PMC_PO_SHUTDOWN;
+
+ error:
+	mtx_unlock(&pmc_kthread_mtx);
+
+	return (error);
+}
+
+
+void
+pmclog_process_callchain(struct pmc *pm, struct pmc_sample *ps)
+{
+	int n, recordlen;
+	uint32_t flags;
+	struct pmc_owner *po;
+
+	PMCDBG(LOG,SAM,1,"pm=%p pid=%d n=%d", pm, ps->ps_pid,
+	    ps->ps_nsamples);
+
+	recordlen = offsetof(struct pmclog_callchain, pl_pc) +
+	    ps->ps_nsamples * sizeof(uintfptr_t);
+	po = pm->pm_owner;
+	flags = PMC_CALLCHAIN_TO_CPUFLAGS(ps->ps_cpu,ps->ps_flags);
+	PMCLOG_RESERVE(po, CALLCHAIN, recordlen);
+	PMCLOG_EMIT32(ps->ps_pid);
+	PMCLOG_EMIT32(pm->pm_id);
+	PMCLOG_EMIT32(flags);
+	for (n = 0; n < ps->ps_nsamples; n++)
+		PMCLOG_EMITADDR(ps->ps_pc[n]);
+	PMCLOG_DESPATCH(po);
+}
+
+void
+pmclog_process_closelog(struct pmc_owner *po)
+{
+	PMCLOG_RESERVE(po,CLOSELOG,sizeof(struct pmclog_closelog));
+	PMCLOG_DESPATCH(po);
+}
+
+void
+pmclog_process_dropnotify(struct pmc_owner *po)
+{
+	PMCLOG_RESERVE(po,DROPNOTIFY,sizeof(struct pmclog_dropnotify));
+	PMCLOG_DESPATCH(po);
+}
+
+void
+pmclog_process_map_in(struct pmc_owner *po, pid_t pid, uintfptr_t start,
+    const char *path)
+{
+	int pathlen, recordlen;
+
+	KASSERT(path != NULL, ("[pmclog,%d] map-in, null path", __LINE__));
+
+	pathlen = strlen(path) + 1;	/* #bytes for path name */
+	recordlen = offsetof(struct pmclog_map_in, pl_pathname) +
+	    pathlen;
+
+	PMCLOG_RESERVE(po, MAP_IN, recordlen);
+	PMCLOG_EMIT32(pid);
+	PMCLOG_EMITADDR(start);
+	PMCLOG_EMITSTRING(path,pathlen);
+	PMCLOG_DESPATCH(po);
+}
+
+void
+pmclog_process_map_out(struct pmc_owner *po, pid_t pid, uintfptr_t start,
+    uintfptr_t end)
+{
+	KASSERT(start <= end, ("[pmclog,%d] start > end", __LINE__));
+
+	PMCLOG_RESERVE(po, MAP_OUT, sizeof(struct pmclog_map_out));
+	PMCLOG_EMIT32(pid);
+	PMCLOG_EMITADDR(start);
+	PMCLOG_EMITADDR(end);
+	PMCLOG_DESPATCH(po);
+}
+
+void
+pmclog_process_pmcallocate(struct pmc *pm)
+{
+	struct pmc_owner *po;
+
+	po = pm->pm_owner;
+
+	PMCDBG(LOG,ALL,1, "pm=%p", pm);
+
+	PMCLOG_RESERVE(po, PMCALLOCATE, sizeof(struct pmclog_pmcallocate));
+	PMCLOG_EMIT32(pm->pm_id);
+	PMCLOG_EMIT32(pm->pm_event);
+	PMCLOG_EMIT32(pm->pm_flags);
+	PMCLOG_DESPATCH(po);
+}
+
+void
+pmclog_process_pmcattach(struct pmc *pm, pid_t pid, char *path)
+{
+	int pathlen, recordlen;
+	struct pmc_owner *po;
+
+	PMCDBG(LOG,ATT,1,"pm=%p pid=%d", pm, pid);
+
+	po = pm->pm_owner;
+
+	pathlen = strlen(path) + 1;	/* #bytes for the string */
+	recordlen = offsetof(struct pmclog_pmcattach, pl_pathname) + pathlen;
+
+	PMCLOG_RESERVE(po, PMCATTACH, recordlen);
+	PMCLOG_EMIT32(pm->pm_id);
+	PMCLOG_EMIT32(pid);
+	PMCLOG_EMITSTRING(path, pathlen);
+	PMCLOG_DESPATCH(po);
+}
+
+void
+pmclog_process_pmcdetach(struct pmc *pm, pid_t pid)
+{
+	struct pmc_owner *po;
+
+	PMCDBG(LOG,ATT,1,"!pm=%p pid=%d", pm, pid);
+
+	po = pm->pm_owner;
+
+	PMCLOG_RESERVE(po, PMCDETACH, sizeof(struct pmclog_pmcdetach));
+	PMCLOG_EMIT32(pm->pm_id);
+	PMCLOG_EMIT32(pid);
+	PMCLOG_DESPATCH(po);
+}
+
+/*
+ * Log a context switch event to the log file.
+ */
+
+void
+pmclog_process_proccsw(struct pmc *pm, struct pmc_process *pp, pmc_value_t v)
+{
+	struct pmc_owner *po;
+
+	KASSERT(pm->pm_flags & PMC_F_LOG_PROCCSW,
+	    ("[pmclog,%d] log-process-csw called gratuitously", __LINE__));
+
+	PMCDBG(LOG,SWO,1,"pm=%p pid=%d v=%jx", pm, pp->pp_proc->p_pid,
+	    v);
+
+	po = pm->pm_owner;
+
+	PMCLOG_RESERVE(po, PROCCSW, sizeof(struct pmclog_proccsw));
+	PMCLOG_EMIT32(pm->pm_id);
+	PMCLOG_EMIT64(v);
+	PMCLOG_EMIT32(pp->pp_proc->p_pid);
+	PMCLOG_DESPATCH(po);
+}
+
+void
+pmclog_process_procexec(struct pmc_owner *po, pmc_id_t pmid, pid_t pid,
+    uintfptr_t startaddr, char *path)
+{
+	int pathlen, recordlen;
+
+	PMCDBG(LOG,EXC,1,"po=%p pid=%d path=\"%s\"", po, pid, path);
+
+	pathlen   = strlen(path) + 1;	/* #bytes for the path */
+	recordlen = offsetof(struct pmclog_procexec, pl_pathname) + pathlen;
+
+	PMCLOG_RESERVE(po, PROCEXEC, recordlen);
+	PMCLOG_EMIT32(pid);
+	PMCLOG_EMITADDR(startaddr);
+	PMCLOG_EMIT32(pmid);
+	PMCLOG_EMITSTRING(path,pathlen);
+	PMCLOG_DESPATCH(po);
+}
+
+/*
+ * Log a process exit event (and accumulated pmc value) to the log file.
+ */
+
+void
+pmclog_process_procexit(struct pmc *pm, struct pmc_process *pp)
+{
+	int ri;
+	struct pmc_owner *po;
+
+	ri = PMC_TO_ROWINDEX(pm);
+	PMCDBG(LOG,EXT,1,"pm=%p pid=%d v=%jx", pm, pp->pp_proc->p_pid,
+	    pp->pp_pmcs[ri].pp_pmcval);
+
+	po = pm->pm_owner;
+
+	PMCLOG_RESERVE(po, PROCEXIT, sizeof(struct pmclog_procexit));
+	PMCLOG_EMIT32(pm->pm_id);
+	PMCLOG_EMIT64(pp->pp_pmcs[ri].pp_pmcval);
+	PMCLOG_EMIT32(pp->pp_proc->p_pid);
+	PMCLOG_DESPATCH(po);
+}
+
+/*
+ * Log a fork event.
+ */
+
+void
+pmclog_process_procfork(struct pmc_owner *po, pid_t oldpid, pid_t newpid)
+{
+	PMCLOG_RESERVE(po, PROCFORK, sizeof(struct pmclog_procfork));
+	PMCLOG_EMIT32(oldpid);
+	PMCLOG_EMIT32(newpid);
+	PMCLOG_DESPATCH(po);
+}
+
+/*
+ * Log a process exit event of the form suitable for system-wide PMCs.
+ */
+
+void
+pmclog_process_sysexit(struct pmc_owner *po, pid_t pid)
+{
+	PMCLOG_RESERVE(po, SYSEXIT, sizeof(struct pmclog_sysexit));
+	PMCLOG_EMIT32(pid);
+	PMCLOG_DESPATCH(po);
+}
+
+/*
+ * Write a user log entry.
+ */
+
+int
+pmclog_process_userlog(struct pmc_owner *po, struct pmc_op_writelog *wl)
+{
+	int error;
+
+	PMCDBG(LOG,WRI,1, "writelog po=%p ud=0x%x", po, wl->pm_userdata);
+
+	error = 0;
+
+	PMCLOG_RESERVE_WITH_ERROR(po, USERDATA,
+	    sizeof(struct pmclog_userdata));
+	PMCLOG_EMIT32(wl->pm_userdata);
+	PMCLOG_DESPATCH(po);
+
+ error:
+	return (error);
+}
+
+/*
+ * Initialization.
+ *
+ * Create a pool of log buffers and initialize mutexes.
+ */
+
+void
+pmclog_initialize()
+{
+	int n;
+	struct pmclog_buffer *plb;
+
+	if (pmclog_buffer_size <= 0) {
+		(void) printf("hwpmc: tunable logbuffersize=%d must be "
+		    "greater than zero.\n", pmclog_buffer_size);
+		pmclog_buffer_size = PMC_LOG_BUFFER_SIZE;
+	}
+
+	if (pmc_nlogbuffers <= 0) {
+		(void) printf("hwpmc: tunable nlogbuffers=%d must be greater "
+		    "than zero.\n", pmc_nlogbuffers);
+		pmc_nlogbuffers = PMC_NLOGBUFFERS;
+	}
+
+	/* create global pool of log buffers */
+	for (n = 0; n < pmc_nlogbuffers; n++) {
+		plb = malloc(1024 * pmclog_buffer_size, M_PMC,
+		    M_WAITOK|M_ZERO);
+		PMCLOG_INIT_BUFFER_DESCRIPTOR(plb);
+		TAILQ_INSERT_HEAD(&pmc_bufferlist, plb, plb_next);
+	}
+	mtx_init(&pmc_bufferlist_mtx, "pmc-buffer-list", "pmc-leaf",
+	    MTX_SPIN);
+	mtx_init(&pmc_kthread_mtx, "pmc-kthread", "pmc-sleep", MTX_DEF);
+}
+
+/*
+ * Shutdown logging.
+ *
+ * Destroy mutexes and release memory back the to free pool.
+ */
+
+void
+pmclog_shutdown()
+{
+	struct pmclog_buffer *plb;
+
+	mtx_destroy(&pmc_kthread_mtx);
+	mtx_destroy(&pmc_bufferlist_mtx);
+
+	while ((plb = TAILQ_FIRST(&pmc_bufferlist)) != NULL) {
+		TAILQ_REMOVE(&pmc_bufferlist, plb, plb_next);
+		free(plb, M_PMC);
+	}
+}
diff --git a/sys/dev/misc/hwpmc/hwpmc_mod.c b/sys/dev/misc/hwpmc/hwpmc_mod.c
new file mode 100644
index 0000000..53d4f63
--- /dev/null
+++ b/sys/dev/misc/hwpmc/hwpmc_mod.c
@@ -0,0 +1,4949 @@
+/*-
+ * Copyright (c) 2003-2008 Joseph Koshy
+ * Copyright (c) 2007 The FreeBSD Foundation
+ * All rights reserved.
+ *
+ * Portions of this software were developed by A. Joseph Koshy under
+ * sponsorship from the FreeBSD Foundation and Google, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: src/sys/dev/hwpmc/hwpmc_mod.c,v 1.52 2011/05/16 23:35:14 attilio Exp $");
+
+#include <sys/param.h>
+#include <sys/eventhandler.h>
+#include <sys/jail.h>
+#include <sys/kernel.h>
+#include <sys/kthread.h>
+#include <sys/limits.h>
+#include <sys/lock.h>
+#include <sys/malloc.h>
+#include <sys/module.h>
+#include <sys/mount.h>
+#include <sys/mutex.h>
+#include <sys/pmc.h>
+#include <sys/pmckern.h>
+#include <sys/pmclog.h>
+#include <sys/priv.h>
+#include <sys/proc.h>
+#include <sys/queue.h>
+#include <sys/resourcevar.h>
+#include <sys/sched.h>
+#include <sys/signalvar.h>
+#include <sys/smp.h>
+#include <sys/sx.h>
+#include <sys/sysctl.h>
+#include <sys/sysent.h>
+#include <sys/systm.h>
+#include <sys/vnode.h>
+
+#include <sys/linker.h>		/* needs to be after <sys/malloc.h> */
+
+#include <machine/atomic.h>
+#include <machine/md_var.h>
+
+#include <vm/vm.h>
+#include <vm/vm_extern.h>
+#include <vm/pmap.h>
+#include <vm/vm_map.h>
+#include <vm/vm_object.h>
+
+/*
+ * Types
+ */
+
+enum pmc_flags {
+	PMC_FLAG_NONE	  = 0x00, /* do nothing */
+	PMC_FLAG_REMOVE   = 0x01, /* atomically remove entry from hash */
+	PMC_FLAG_ALLOCATE = 0x02, /* add entry to hash if not found */
+};
+
+/*
+ * The offset in sysent where the syscall is allocated.
+ */
+
+static int pmc_syscall_num = NO_SYSCALL;
+struct pmc_cpu		**pmc_pcpu;	 /* per-cpu state */
+pmc_value_t		*pmc_pcpu_saved; /* saved PMC values: CSW handling */
+
+#define	PMC_PCPU_SAVED(C,R)	pmc_pcpu_saved[(R) + md->pmd_npmc*(C)]
+
+struct mtx_pool		*pmc_mtxpool;
+static int		*pmc_pmcdisp;	 /* PMC row dispositions */
+
+#define	PMC_ROW_DISP_IS_FREE(R)		(pmc_pmcdisp[(R)] == 0)
+#define	PMC_ROW_DISP_IS_THREAD(R)	(pmc_pmcdisp[(R)] > 0)
+#define	PMC_ROW_DISP_IS_STANDALONE(R)	(pmc_pmcdisp[(R)] < 0)
+
+#define	PMC_MARK_ROW_FREE(R) do {					  \
+	pmc_pmcdisp[(R)] = 0;						  \
+} while (0)
+
+#define	PMC_MARK_ROW_STANDALONE(R) do {					  \
+	KASSERT(pmc_pmcdisp[(R)] <= 0, ("[pmc,%d] row disposition error", \
+		    __LINE__));						  \
+	atomic_add_int(&pmc_pmcdisp[(R)], -1);				  \
+	KASSERT(pmc_pmcdisp[(R)] >= (-pmc_cpu_max_active()),		  \
+		("[pmc,%d] row disposition error", __LINE__));		  \
+} while (0)
+
+#define	PMC_UNMARK_ROW_STANDALONE(R) do { 				  \
+	atomic_add_int(&pmc_pmcdisp[(R)], 1);				  \
+	KASSERT(pmc_pmcdisp[(R)] <= 0, ("[pmc,%d] row disposition error", \
+		    __LINE__));						  \
+} while (0)
+
+#define	PMC_MARK_ROW_THREAD(R) do {					  \
+	KASSERT(pmc_pmcdisp[(R)] >= 0, ("[pmc,%d] row disposition error", \
+		    __LINE__));						  \
+	atomic_add_int(&pmc_pmcdisp[(R)], 1);				  \
+} while (0)
+
+#define	PMC_UNMARK_ROW_THREAD(R) do {					  \
+	atomic_add_int(&pmc_pmcdisp[(R)], -1);				  \
+	KASSERT(pmc_pmcdisp[(R)] >= 0, ("[pmc,%d] row disposition error", \
+		    __LINE__));						  \
+} while (0)
+
+
+/* various event handlers */
+static eventhandler_tag	pmc_exit_tag, pmc_fork_tag;
+
+/* Module statistics */
+struct pmc_op_getdriverstats pmc_stats;
+
+/* Machine/processor dependent operations */
+static struct pmc_mdep  *md;
+
+/*
+ * Hash tables mapping owner processes and target threads to PMCs.
+ */
+
+struct mtx pmc_processhash_mtx;		/* spin mutex */
+static u_long pmc_processhashmask;
+static LIST_HEAD(pmc_processhash, pmc_process)	*pmc_processhash;
+
+/*
+ * Hash table of PMC owner descriptors.  This table is protected by
+ * the shared PMC "sx" lock.
+ */
+
+static u_long pmc_ownerhashmask;
+static LIST_HEAD(pmc_ownerhash, pmc_owner)	*pmc_ownerhash;
+
+/*
+ * List of PMC owners with system-wide sampling PMCs.
+ */
+
+static LIST_HEAD(, pmc_owner)			pmc_ss_owners;
+
+
+/*
+ * A map of row indices to classdep structures.
+ */
+static struct pmc_classdep **pmc_rowindex_to_classdep;
+
+/*
+ * Prototypes
+ */
+
+#ifdef	DEBUG
+static int	pmc_debugflags_sysctl_handler(SYSCTL_HANDLER_ARGS);
+static int	pmc_debugflags_parse(char *newstr, char *fence);
+#endif
+
+static int	load(struct module *module, int cmd, void *arg);
+static int	pmc_attach_process(struct proc *p, struct pmc *pm);
+static struct pmc *pmc_allocate_pmc_descriptor(void);
+static struct pmc_owner *pmc_allocate_owner_descriptor(struct proc *p);
+static int	pmc_attach_one_process(struct proc *p, struct pmc *pm);
+static int	pmc_can_allocate_rowindex(struct proc *p, unsigned int ri,
+    int cpu);
+static int	pmc_can_attach(struct pmc *pm, struct proc *p);
+static void	pmc_capture_user_callchain(int cpu, struct trapframe *tf);
+static void	pmc_cleanup(void);
+static int	pmc_detach_process(struct proc *p, struct pmc *pm);
+static int	pmc_detach_one_process(struct proc *p, struct pmc *pm,
+    int flags);
+static void	pmc_destroy_owner_descriptor(struct pmc_owner *po);
+static struct pmc_owner *pmc_find_owner_descriptor(struct proc *p);
+static int	pmc_find_pmc(pmc_id_t pmcid, struct pmc **pm);
+static struct pmc *pmc_find_pmc_descriptor_in_process(struct pmc_owner *po,
+    pmc_id_t pmc);
+static struct pmc_process *pmc_find_process_descriptor(struct proc *p,
+    uint32_t mode);
+static void	pmc_force_context_switch(void);
+static void	pmc_link_target_process(struct pmc *pm,
+    struct pmc_process *pp);
+static void	pmc_log_all_process_mappings(struct pmc_owner *po);
+static void	pmc_log_kernel_mappings(struct pmc *pm);
+static void	pmc_log_process_mappings(struct pmc_owner *po, struct proc *p);
+static void	pmc_maybe_remove_owner(struct pmc_owner *po);
+static void	pmc_process_csw_in(struct thread *td);
+static void	pmc_process_csw_out(struct thread *td);
+static void	pmc_process_exit(void *arg, struct proc *p);
+static void	pmc_process_fork(void *arg, struct proc *p1,
+    struct proc *p2, int n);
+static void	pmc_process_samples(int cpu);
+static void	pmc_release_pmc_descriptor(struct pmc *pmc);
+static void	pmc_remove_owner(struct pmc_owner *po);
+static void	pmc_remove_process_descriptor(struct pmc_process *pp);
+static void	pmc_restore_cpu_binding(struct pmc_binding *pb);
+static void	pmc_save_cpu_binding(struct pmc_binding *pb);
+static void	pmc_select_cpu(int cpu);
+static int	pmc_start(struct pmc *pm);
+static int	pmc_stop(struct pmc *pm);
+static int	pmc_syscall_handler(struct thread *td, void *syscall_args);
+static void	pmc_unlink_target_process(struct pmc *pmc,
+    struct pmc_process *pp);
+
+/*
+ * Kernel tunables and sysctl(8) interface.
+ */
+
+SYSCTL_NODE(_kern, OID_AUTO, hwpmc, CTLFLAG_RW, 0, "HWPMC parameters");
+
+static int pmc_callchaindepth = PMC_CALLCHAIN_DEPTH;
+TUNABLE_INT(PMC_SYSCTL_NAME_PREFIX "callchaindepth", &pmc_callchaindepth);
+SYSCTL_INT(_kern_hwpmc, OID_AUTO, callchaindepth, CTLFLAG_TUN|CTLFLAG_RD,
+    &pmc_callchaindepth, 0, "depth of call chain records");
+
+#ifdef	DEBUG
+struct pmc_debugflags pmc_debugflags = PMC_DEBUG_DEFAULT_FLAGS;
+char	pmc_debugstr[PMC_DEBUG_STRSIZE];
+TUNABLE_STR(PMC_SYSCTL_NAME_PREFIX "debugflags", pmc_debugstr,
+    sizeof(pmc_debugstr));
+SYSCTL_PROC(_kern_hwpmc, OID_AUTO, debugflags,
+    CTLTYPE_STRING|CTLFLAG_RW|CTLFLAG_TUN,
+    0, 0, pmc_debugflags_sysctl_handler, "A", "debug flags");
+#endif
+
+/*
+ * kern.hwpmc.hashrows -- determines the number of rows in the
+ * of the hash table used to look up threads
+ */
+
+static int pmc_hashsize = PMC_HASH_SIZE;
+TUNABLE_INT(PMC_SYSCTL_NAME_PREFIX "hashsize", &pmc_hashsize);
+SYSCTL_INT(_kern_hwpmc, OID_AUTO, hashsize, CTLFLAG_TUN|CTLFLAG_RD,
+    &pmc_hashsize, 0, "rows in hash tables");
+
+/*
+ * kern.hwpmc.nsamples --- number of PC samples/callchain stacks per CPU
+ */
+
+static int pmc_nsamples = PMC_NSAMPLES;
+TUNABLE_INT(PMC_SYSCTL_NAME_PREFIX "nsamples", &pmc_nsamples);
+SYSCTL_INT(_kern_hwpmc, OID_AUTO, nsamples, CTLFLAG_TUN|CTLFLAG_RD,
+    &pmc_nsamples, 0, "number of PC samples per CPU");
+
+
+/*
+ * kern.hwpmc.mtxpoolsize -- number of mutexes in the mutex pool.
+ */
+
+static int pmc_mtxpool_size = PMC_MTXPOOL_SIZE;
+TUNABLE_INT(PMC_SYSCTL_NAME_PREFIX "mtxpoolsize", &pmc_mtxpool_size);
+SYSCTL_INT(_kern_hwpmc, OID_AUTO, mtxpoolsize, CTLFLAG_TUN|CTLFLAG_RD,
+    &pmc_mtxpool_size, 0, "size of spin mutex pool");
+
+
+/*
+ * security.bsd.unprivileged_syspmcs -- allow non-root processes to
+ * allocate system-wide PMCs.
+ *
+ * Allowing unprivileged processes to allocate system PMCs is convenient
+ * if system-wide measurements need to be taken concurrently with other
+ * per-process measurements.  This feature is turned off by default.
+ */
+
+static int pmc_unprivileged_syspmcs = 0;
+TUNABLE_INT("security.bsd.unprivileged_syspmcs", &pmc_unprivileged_syspmcs);
+SYSCTL_INT(_security_bsd, OID_AUTO, unprivileged_syspmcs, CTLFLAG_RW,
+    &pmc_unprivileged_syspmcs, 0,
+    "allow unprivileged process to allocate system PMCs");
+
+/*
+ * Hash function.  Discard the lower 2 bits of the pointer since
+ * these are always zero for our uses.  The hash multiplier is
+ * round((2^LONG_BIT) * ((sqrt(5)-1)/2)).
+ */
+
+#if	LONG_BIT == 64
+#define	_PMC_HM		11400714819323198486u
+#elif	LONG_BIT == 32
+#define	_PMC_HM		2654435769u
+#else
+#error 	Must know the size of 'long' to compile
+#endif
+
+#define	PMC_HASH_PTR(P,M)	((((unsigned long) (P) >> 2) * _PMC_HM) & (M))
+
+/*
+ * Syscall structures
+ */
+
+/* The `sysent' for the new syscall */
+static struct sysent pmc_sysent = {
+	2,			/* sy_narg */
+	pmc_syscall_handler	/* sy_call */
+};
+
+static struct syscall_module_data pmc_syscall_mod = {
+	load,
+	NULL,
+	&pmc_syscall_num,
+	&pmc_sysent,
+	{ 0, NULL }
+};
+
+static moduledata_t pmc_mod = {
+	PMC_MODULE_NAME,
+	syscall_module_handler,
+	&pmc_syscall_mod
+};
+
+DECLARE_MODULE(pmc, pmc_mod, SI_SUB_SMP, SI_ORDER_ANY);
+MODULE_VERSION(pmc, PMC_VERSION);
+
+#ifdef	DEBUG
+enum pmc_dbgparse_state {
+	PMCDS_WS,		/* in whitespace */
+	PMCDS_MAJOR,		/* seen a major keyword */
+	PMCDS_MINOR
+};
+
+static int
+pmc_debugflags_parse(char *newstr, char *fence)
+{
+	char c, *p, *q;
+	struct pmc_debugflags *tmpflags;
+	int error, found, *newbits, tmp;
+	size_t kwlen;
+
+	tmpflags = malloc(sizeof(*tmpflags), M_PMC, M_WAITOK|M_ZERO);
+
+	p = newstr;
+	error = 0;
+
+	for (; p < fence && (c = *p); p++) {
+
+		/* skip white space */
+		if (c == ' ' || c == '\t')
+			continue;
+
+		/* look for a keyword followed by "=" */
+		for (q = p; p < fence && (c = *p) && c != '='; p++)
+			;
+		if (c != '=') {
+			error = EINVAL;
+			goto done;
+		}
+
+		kwlen = p - q;
+		newbits = NULL;
+
+		/* lookup flag group name */
+#define	DBG_SET_FLAG_MAJ(S,F)						\
+		if (kwlen == sizeof(S)-1 && strncmp(q, S, kwlen) == 0)	\
+			newbits = &tmpflags->pdb_ ## F;
+
+		DBG_SET_FLAG_MAJ("cpu",		CPU);
+		DBG_SET_FLAG_MAJ("csw",		CSW);
+		DBG_SET_FLAG_MAJ("logging",	LOG);
+		DBG_SET_FLAG_MAJ("module",	MOD);
+		DBG_SET_FLAG_MAJ("md", 		MDP);
+		DBG_SET_FLAG_MAJ("owner",	OWN);
+		DBG_SET_FLAG_MAJ("pmc",		PMC);
+		DBG_SET_FLAG_MAJ("process",	PRC);
+		DBG_SET_FLAG_MAJ("sampling", 	SAM);
+
+		if (newbits == NULL) {
+			error = EINVAL;
+			goto done;
+		}
+
+		p++;		/* skip the '=' */
+
+		/* Now parse the individual flags */
+		tmp = 0;
+	newflag:
+		for (q = p; p < fence && (c = *p); p++)
+			if (c == ' ' || c == '\t' || c == ',')
+				break;
+
+		/* p == fence or c == ws or c == "," or c == 0 */
+
+		if ((kwlen = p - q) == 0) {
+			*newbits = tmp;
+			continue;
+		}
+
+		found = 0;
+#define	DBG_SET_FLAG_MIN(S,F)						\
+		if (kwlen == sizeof(S)-1 && strncmp(q, S, kwlen) == 0)	\
+			tmp |= found = (1 << PMC_DEBUG_MIN_ ## F)
+
+		/* a '*' denotes all possible flags in the group */
+		if (kwlen == 1 && *q == '*')
+			tmp = found = ~0;
+		/* look for individual flag names */
+		DBG_SET_FLAG_MIN("allocaterow", ALR);
+		DBG_SET_FLAG_MIN("allocate",	ALL);
+		DBG_SET_FLAG_MIN("attach",	ATT);
+		DBG_SET_FLAG_MIN("bind",	BND);
+		DBG_SET_FLAG_MIN("config",	CFG);
+		DBG_SET_FLAG_MIN("exec",	EXC);
+		DBG_SET_FLAG_MIN("exit",	EXT);
+		DBG_SET_FLAG_MIN("find",	FND);
+		DBG_SET_FLAG_MIN("flush",	FLS);
+		DBG_SET_FLAG_MIN("fork",	FRK);
+		DBG_SET_FLAG_MIN("getbuf",	GTB);
+		DBG_SET_FLAG_MIN("hook",	PMH);
+		DBG_SET_FLAG_MIN("init",	INI);
+		DBG_SET_FLAG_MIN("intr",	INT);
+		DBG_SET_FLAG_MIN("linktarget",	TLK);
+		DBG_SET_FLAG_MIN("mayberemove", OMR);
+		DBG_SET_FLAG_MIN("ops",		OPS);
+		DBG_SET_FLAG_MIN("read",	REA);
+		DBG_SET_FLAG_MIN("register",	REG);
+		DBG_SET_FLAG_MIN("release",	REL);
+		DBG_SET_FLAG_MIN("remove",	ORM);
+		DBG_SET_FLAG_MIN("sample",	SAM);
+		DBG_SET_FLAG_MIN("scheduleio",	SIO);
+		DBG_SET_FLAG_MIN("select",	SEL);
+		DBG_SET_FLAG_MIN("signal",	SIG);
+		DBG_SET_FLAG_MIN("swi",		SWI);
+		DBG_SET_FLAG_MIN("swo",		SWO);
+		DBG_SET_FLAG_MIN("start",	STA);
+		DBG_SET_FLAG_MIN("stop",	STO);
+		DBG_SET_FLAG_MIN("syscall",	PMS);
+		DBG_SET_FLAG_MIN("unlinktarget", TUL);
+		DBG_SET_FLAG_MIN("write",	WRI);
+		if (found == 0) {
+			/* unrecognized flag name */
+			error = EINVAL;
+			goto done;
+		}
+
+		if (c == 0 || c == ' ' || c == '\t') {	/* end of flag group */
+			*newbits = tmp;
+			continue;
+		}
+
+		p++;
+		goto newflag;
+	}
+
+	/* save the new flag set */
+	bcopy(tmpflags, &pmc_debugflags, sizeof(pmc_debugflags));
+
+ done:
+	free(tmpflags, M_PMC);
+	return error;
+}
+
+static int
+pmc_debugflags_sysctl_handler(SYSCTL_HANDLER_ARGS)
+{
+	char *fence, *newstr;
+	int error;
+	unsigned int n;
+
+	(void) arg1; (void) arg2; /* unused parameters */
+
+	n = sizeof(pmc_debugstr);
+	newstr = malloc(n, M_PMC, M_WAITOK|M_ZERO);
+	(void) strlcpy(newstr, pmc_debugstr, n);
+
+	error = sysctl_handle_string(oidp, newstr, n, req);
+
+	/* if there is a new string, parse and copy it */
+	if (error == 0 && req->newptr != NULL) {
+		fence = newstr + (n < req->newlen ? n : req->newlen + 1);
+		if ((error = pmc_debugflags_parse(newstr, fence)) == 0)
+			(void) strlcpy(pmc_debugstr, newstr,
+			    sizeof(pmc_debugstr));
+	}
+
+	free(newstr, M_PMC);
+
+	return error;
+}
+#endif
+
+/*
+ * Map a row index to a classdep structure and return the adjusted row
+ * index for the PMC class index.
+ */
+static struct pmc_classdep *
+pmc_ri_to_classdep(struct pmc_mdep *md, int ri, int *adjri)
+{
+	struct pmc_classdep *pcd;
+
+	(void) md;
+
+	KASSERT(ri >= 0 && ri < md->pmd_npmc,
+	    ("[pmc,%d] illegal row-index %d", __LINE__, ri));
+
+	pcd = pmc_rowindex_to_classdep[ri];
+
+	KASSERT(pcd != NULL,
+	    ("[pmc,%d] ri %d null pcd", __LINE__, ri));
+
+	*adjri = ri - pcd->pcd_ri;
+
+	KASSERT(*adjri >= 0 && *adjri < pcd->pcd_num,
+	    ("[pmc,%d] adjusted row-index %d", __LINE__, *adjri));
+
+	return (pcd);
+}
+
+/*
+ * Concurrency Control
+ *
+ * The driver manages the following data structures:
+ *
+ *   - target process descriptors, one per target process
+ *   - owner process descriptors (and attached lists), one per owner process
+ *   - lookup hash tables for owner and target processes
+ *   - PMC descriptors (and attached lists)
+ *   - per-cpu hardware state
+ *   - the 'hook' variable through which the kernel calls into
+ *     this module
+ *   - the machine hardware state (managed by the MD layer)
+ *
+ * These data structures are accessed from:
+ *
+ * - thread context-switch code
+ * - interrupt handlers (possibly on multiple cpus)
+ * - kernel threads on multiple cpus running on behalf of user
+ *   processes doing system calls
+ * - this driver's private kernel threads
+ *
+ * = Locks and Locking strategy =
+ *
+ * The driver uses four locking strategies for its operation:
+ *
+ * - The global SX lock "pmc_sx" is used to protect internal
+ *   data structures.
+ *
+ *   Calls into the module by syscall() start with this lock being
+ *   held in exclusive mode.  Depending on the requested operation,
+ *   the lock may be downgraded to 'shared' mode to allow more
+ *   concurrent readers into the module.  Calls into the module from
+ *   other parts of the kernel acquire the lock in shared mode.
+ *
+ *   This SX lock is held in exclusive mode for any operations that
+ *   modify the linkages between the driver's internal data structures.
+ *
+ *   The 'pmc_hook' function pointer is also protected by this lock.
+ *   It is only examined with the sx lock held in exclusive mode.  The
+ *   kernel module is allowed to be unloaded only with the sx lock held
+ *   in exclusive mode.  In normal syscall handling, after acquiring the
+ *   pmc_sx lock we first check that 'pmc_hook' is non-null before
+ *   proceeding.  This prevents races between the thread unloading the module
+ *   and other threads seeking to use the module.
+ *
+ * - Lookups of target process structures and owner process structures
+ *   cannot use the global "pmc_sx" SX lock because these lookups need
+ *   to happen during context switches and in other critical sections
+ *   where sleeping is not allowed.  We protect these lookup tables
+ *   with their own private spin-mutexes, "pmc_processhash_mtx" and
+ *   "pmc_ownerhash_mtx".
+ *
+ * - Interrupt handlers work in a lock free manner.  At interrupt
+ *   time, handlers look at the PMC pointer (phw->phw_pmc) configured
+ *   when the PMC was started.  If this pointer is NULL, the interrupt
+ *   is ignored after updating driver statistics.  We ensure that this
+ *   pointer is set (using an atomic operation if necessary) before the
+ *   PMC hardware is started.  Conversely, this pointer is unset atomically
+ *   only after the PMC hardware is stopped.
+ *
+ *   We ensure that everything needed for the operation of an
+ *   interrupt handler is available without it needing to acquire any
+ *   locks.  We also ensure that a PMC's software state is destroyed only
+ *   after the PMC is taken off hardware (on all CPUs).
+ *
+ * - Context-switch handling with process-private PMCs needs more
+ *   care.
+ *
+ *   A given process may be the target of multiple PMCs.  For example,
+ *   PMCATTACH and PMCDETACH may be requested by a process on one CPU
+ *   while the target process is running on another.  A PMC could also
+ *   be getting released because its owner is exiting.  We tackle
+ *   these situations in the following manner:
+ *
+ *   - each target process structure 'pmc_process' has an array
+ *     of 'struct pmc *' pointers, one for each hardware PMC.
+ *
+ *   - At context switch IN time, each "target" PMC in RUNNING state
+ *     gets started on hardware and a pointer to each PMC is copied into
+ *     the per-cpu phw array.  The 'runcount' for the PMC is
+ *     incremented.
+ *
+ *   - At context switch OUT time, all process-virtual PMCs are stopped
+ *     on hardware.  The saved value is added to the PMCs value field
+ *     only if the PMC is in a non-deleted state (the PMCs state could
+ *     have changed during the current time slice).
+ *
+ *     Note that since in-between a switch IN on a processor and a switch
+ *     OUT, the PMC could have been released on another CPU.  Therefore
+ *     context switch OUT always looks at the hardware state to turn
+ *     OFF PMCs and will update a PMC's saved value only if reachable
+ *     from the target process record.
+ *
+ *   - OP PMCRELEASE could be called on a PMC at any time (the PMC could
+ *     be attached to many processes at the time of the call and could
+ *     be active on multiple CPUs).
+ *
+ *     We prevent further scheduling of the PMC by marking it as in
+ *     state 'DELETED'.  If the runcount of the PMC is non-zero then
+ *     this PMC is currently running on a CPU somewhere.  The thread
+ *     doing the PMCRELEASE operation waits by repeatedly doing a
+ *     pause() till the runcount comes to zero.
+ *
+ * The contents of a PMC descriptor (struct pmc) are protected using
+ * a spin-mutex.  In order to save space, we use a mutex pool.
+ *
+ * In terms of lock types used by witness(4), we use:
+ * - Type "pmc-sx", used by the global SX lock.
+ * - Type "pmc-sleep", for sleep mutexes used by logger threads.
+ * - Type "pmc-per-proc", for protecting PMC owner descriptors.
+ * - Type "pmc-leaf", used for all other spin mutexes.
+ */
+
+/*
+ * save the cpu binding of the current kthread
+ */
+
+static void
+pmc_save_cpu_binding(struct pmc_binding *pb)
+{
+	PMCDBG(CPU,BND,2, "%s", "save-cpu");
+	thread_lock(curthread);
+	pb->pb_bound = sched_is_bound(curthread);
+	pb->pb_cpu   = curthread->td_oncpu;
+	thread_unlock(curthread);
+	PMCDBG(CPU,BND,2, "save-cpu cpu=%d", pb->pb_cpu);
+}
+
+/*
+ * restore the cpu binding of the current thread
+ */
+
+static void
+pmc_restore_cpu_binding(struct pmc_binding *pb)
+{
+	PMCDBG(CPU,BND,2, "restore-cpu curcpu=%d restore=%d",
+	    curthread->td_oncpu, pb->pb_cpu);
+	thread_lock(curthread);
+	if (pb->pb_bound)
+		sched_bind(curthread, pb->pb_cpu);
+	else
+		sched_unbind(curthread);
+	thread_unlock(curthread);
+	PMCDBG(CPU,BND,2, "%s", "restore-cpu done");
+}
+
+/*
+ * move execution over the specified cpu and bind it there.
+ */
+
+static void
+pmc_select_cpu(int cpu)
+{
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[pmc,%d] bad cpu number %d", __LINE__, cpu));
+
+	/* Never move to an inactive CPU. */
+	KASSERT(pmc_cpu_is_active(cpu), ("[pmc,%d] selecting inactive "
+	    "CPU %d", __LINE__, cpu));
+
+	PMCDBG(CPU,SEL,2, "select-cpu cpu=%d", cpu);
+	thread_lock(curthread);
+	sched_bind(curthread, cpu);
+	thread_unlock(curthread);
+
+	KASSERT(curthread->td_oncpu == cpu,
+	    ("[pmc,%d] CPU not bound [cpu=%d, curr=%d]", __LINE__,
+		cpu, curthread->td_oncpu));
+
+	PMCDBG(CPU,SEL,2, "select-cpu cpu=%d ok", cpu);
+}
+
+/*
+ * Force a context switch.
+ *
+ * We do this by pause'ing for 1 tick -- invoking mi_switch() is not
+ * guaranteed to force a context switch.
+ */
+
+static void
+pmc_force_context_switch(void)
+{
+
+	pause("pmcctx", 1);
+}
+
+/*
+ * Get the file name for an executable.  This is a simple wrapper
+ * around vn_fullpath(9).
+ */
+
+static void
+pmc_getfilename(struct vnode *v, char **fullpath, char **freepath)
+{
+
+	*fullpath = "unknown";
+	*freepath = NULL;
+	vn_fullpath(curthread, v, fullpath, freepath);
+}
+
+/*
+ * remove an process owning PMCs
+ */
+
+void
+pmc_remove_owner(struct pmc_owner *po)
+{
+	struct pmc *pm, *tmp;
+
+	sx_assert(&pmc_sx, SX_XLOCKED);
+
+	PMCDBG(OWN,ORM,1, "remove-owner po=%p", po);
+
+	/* Remove descriptor from the owner hash table */
+	LIST_REMOVE(po, po_next);
+
+	/* release all owned PMC descriptors */
+	LIST_FOREACH_SAFE(pm, &po->po_pmcs, pm_next, tmp) {
+		PMCDBG(OWN,ORM,2, "pmc=%p", pm);
+		KASSERT(pm->pm_owner == po,
+		    ("[pmc,%d] owner %p != po %p", __LINE__, pm->pm_owner, po));
+
+		pmc_release_pmc_descriptor(pm);	/* will unlink from the list */
+	}
+
+	KASSERT(po->po_sscount == 0,
+	    ("[pmc,%d] SS count not zero", __LINE__));
+	KASSERT(LIST_EMPTY(&po->po_pmcs),
+	    ("[pmc,%d] PMC list not empty", __LINE__));
+
+	/* de-configure the log file if present */
+	if (po->po_flags & PMC_PO_OWNS_LOGFILE)
+		pmclog_deconfigure_log(po);
+}
+
+/*
+ * remove an owner process record if all conditions are met.
+ */
+
+static void
+pmc_maybe_remove_owner(struct pmc_owner *po)
+{
+
+	PMCDBG(OWN,OMR,1, "maybe-remove-owner po=%p", po);
+
+	/*
+	 * Remove owner record if
+	 * - this process does not own any PMCs
+	 * - this process has not allocated a system-wide sampling buffer
+	 */
+
+	if (LIST_EMPTY(&po->po_pmcs) &&
+	    ((po->po_flags & PMC_PO_OWNS_LOGFILE) == 0)) {
+		pmc_remove_owner(po);
+		pmc_destroy_owner_descriptor(po);
+	}
+}
+
+/*
+ * Add an association between a target process and a PMC.
+ */
+
+static void
+pmc_link_target_process(struct pmc *pm, struct pmc_process *pp)
+{
+	int ri;
+	struct pmc_target *pt;
+
+	sx_assert(&pmc_sx, SX_XLOCKED);
+
+	KASSERT(pm != NULL && pp != NULL,
+	    ("[pmc,%d] Null pm %p or pp %p", __LINE__, pm, pp));
+	KASSERT(PMC_IS_VIRTUAL_MODE(PMC_TO_MODE(pm)),
+	    ("[pmc,%d] Attaching a non-process-virtual pmc=%p to pid=%d",
+		__LINE__, pm, pp->pp_proc->p_pid));
+	KASSERT(pp->pp_refcnt >= 0 && pp->pp_refcnt <= ((int) md->pmd_npmc - 1),
+	    ("[pmc,%d] Illegal reference count %d for process record %p",
+		__LINE__, pp->pp_refcnt, (void *) pp));
+
+	ri = PMC_TO_ROWINDEX(pm);
+
+	PMCDBG(PRC,TLK,1, "link-target pmc=%p ri=%d pmc-process=%p",
+	    pm, ri, pp);
+
+#ifdef	DEBUG
+	LIST_FOREACH(pt, &pm->pm_targets, pt_next)
+	    if (pt->pt_process == pp)
+		    KASSERT(0, ("[pmc,%d] pp %p already in pmc %p targets",
+				__LINE__, pp, pm));
+#endif
+
+	pt = malloc(sizeof(struct pmc_target), M_PMC, M_WAITOK|M_ZERO);
+	pt->pt_process = pp;
+
+	LIST_INSERT_HEAD(&pm->pm_targets, pt, pt_next);
+
+	atomic_store_rel_ptr((uintptr_t *)&pp->pp_pmcs[ri].pp_pmc,
+	    (uintptr_t)pm);
+
+	if (pm->pm_owner->po_owner == pp->pp_proc)
+		pm->pm_flags |= PMC_F_ATTACHED_TO_OWNER;
+
+	/*
+	 * Initialize the per-process values at this row index.
+	 */
+	pp->pp_pmcs[ri].pp_pmcval = PMC_TO_MODE(pm) == PMC_MODE_TS ?
+	    pm->pm_sc.pm_reloadcount : 0;
+
+	pp->pp_refcnt++;
+
+}
+
+/*
+ * Removes the association between a target process and a PMC.
+ */
+
+static void
+pmc_unlink_target_process(struct pmc *pm, struct pmc_process *pp)
+{
+	int ri;
+	struct proc *p;
+	struct pmc_target *ptgt;
+
+	sx_assert(&pmc_sx, SX_XLOCKED);
+
+	KASSERT(pm != NULL && pp != NULL,
+	    ("[pmc,%d] Null pm %p or pp %p", __LINE__, pm, pp));
+
+	KASSERT(pp->pp_refcnt >= 1 && pp->pp_refcnt <= (int) md->pmd_npmc,
+	    ("[pmc,%d] Illegal ref count %d on process record %p",
+		__LINE__, pp->pp_refcnt, (void *) pp));
+
+	ri = PMC_TO_ROWINDEX(pm);
+
+	PMCDBG(PRC,TUL,1, "unlink-target pmc=%p ri=%d pmc-process=%p",
+	    pm, ri, pp);
+
+	KASSERT(pp->pp_pmcs[ri].pp_pmc == pm,
+	    ("[pmc,%d] PMC ri %d mismatch pmc %p pp->[ri] %p", __LINE__,
+		ri, pm, pp->pp_pmcs[ri].pp_pmc));
+
+	pp->pp_pmcs[ri].pp_pmc = NULL;
+	pp->pp_pmcs[ri].pp_pmcval = (pmc_value_t) 0;
+
+	/* Remove owner-specific flags */
+	if (pm->pm_owner->po_owner == pp->pp_proc) {
+		pp->pp_flags &= ~PMC_PP_ENABLE_MSR_ACCESS;
+		pm->pm_flags &= ~PMC_F_ATTACHED_TO_OWNER;
+	}
+
+	pp->pp_refcnt--;
+
+	/* Remove the target process from the PMC structure */
+	LIST_FOREACH(ptgt, &pm->pm_targets, pt_next)
+		if (ptgt->pt_process == pp)
+			break;
+
+	KASSERT(ptgt != NULL, ("[pmc,%d] process %p (pp: %p) not found "
+		    "in pmc %p", __LINE__, pp->pp_proc, pp, pm));
+
+	LIST_REMOVE(ptgt, pt_next);
+	free(ptgt, M_PMC);
+
+	/* if the PMC now lacks targets, send the owner a SIGIO */
+	if (LIST_EMPTY(&pm->pm_targets)) {
+		p = pm->pm_owner->po_owner;
+		PROC_LOCK(p);
+		psignal(p, SIGIO);
+		PROC_UNLOCK(p);
+
+		PMCDBG(PRC,SIG,2, "signalling proc=%p signal=%d", p,
+		    SIGIO);
+	}
+}
+
+/*
+ * Check if PMC 'pm' may be attached to target process 't'.
+ */
+
+static int
+pmc_can_attach(struct pmc *pm, struct proc *t)
+{
+	struct proc *o;		/* pmc owner */
+	struct ucred *oc, *tc;	/* owner, target credentials */
+	int decline_attach, i;
+
+	/*
+	 * A PMC's owner can always attach that PMC to itself.
+	 */
+
+	if ((o = pm->pm_owner->po_owner) == t)
+		return 0;
+
+	PROC_LOCK(o);
+	oc = o->p_ucred;
+	crhold(oc);
+	PROC_UNLOCK(o);
+
+	PROC_LOCK(t);
+	tc = t->p_ucred;
+	crhold(tc);
+	PROC_UNLOCK(t);
+
+	/*
+	 * The effective uid of the PMC owner should match at least one
+	 * of the {effective,real,saved} uids of the target process.
+	 */
+
+	decline_attach = oc->cr_uid != tc->cr_uid &&
+	    oc->cr_uid != tc->cr_svuid &&
+	    oc->cr_uid != tc->cr_ruid;
+
+	/*
+	 * Every one of the target's group ids, must be in the owner's
+	 * group list.
+	 */
+	for (i = 0; !decline_attach && i < tc->cr_ngroups; i++)
+		decline_attach = !groupmember(tc->cr_groups[i], oc);
+
+	/* check the read and saved gids too */
+	if (decline_attach == 0)
+		decline_attach = !groupmember(tc->cr_rgid, oc) ||
+		    !groupmember(tc->cr_svgid, oc);
+
+	crfree(tc);
+	crfree(oc);
+
+	return !decline_attach;
+}
+
+/*
+ * Attach a process to a PMC.
+ */
+
+static int
+pmc_attach_one_process(struct proc *p, struct pmc *pm)
+{
+	int ri;
+	char *fullpath, *freepath;
+	struct pmc_process	*pp;
+
+	sx_assert(&pmc_sx, SX_XLOCKED);
+
+	PMCDBG(PRC,ATT,2, "attach-one pm=%p ri=%d proc=%p (%d, %s)", pm,
+	    PMC_TO_ROWINDEX(pm), p, p->p_pid, p->p_comm);
+
+	/*
+	 * Locate the process descriptor corresponding to process 'p',
+	 * allocating space as needed.
+	 *
+	 * Verify that rowindex 'pm_rowindex' is free in the process
+	 * descriptor.
+	 *
+	 * If not, allocate space for a descriptor and link the
+	 * process descriptor and PMC.
+	 */
+	ri = PMC_TO_ROWINDEX(pm);
+
+	if ((pp = pmc_find_process_descriptor(p, PMC_FLAG_ALLOCATE)) == NULL)
+		return ENOMEM;
+
+	if (pp->pp_pmcs[ri].pp_pmc == pm) /* already present at slot [ri] */
+		return EEXIST;
+
+	if (pp->pp_pmcs[ri].pp_pmc != NULL)
+		return EBUSY;
+
+	pmc_link_target_process(pm, pp);
+
+	if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)) &&
+	    (pm->pm_flags & PMC_F_ATTACHED_TO_OWNER) == 0)
+		pm->pm_flags |= PMC_F_NEEDS_LOGFILE;
+
+	pm->pm_flags |= PMC_F_ATTACH_DONE; /* mark as attached */
+
+	/* issue an attach event to a configured log file */
+	if (pm->pm_owner->po_flags & PMC_PO_OWNS_LOGFILE) {
+		pmc_getfilename(p->p_textvp, &fullpath, &freepath);
+		if (p->p_flag & P_KTHREAD) {
+			fullpath = kernelname;
+			freepath = NULL;
+		} else
+			pmclog_process_pmcattach(pm, p->p_pid, fullpath);
+		if (freepath)
+			free(freepath, M_TEMP);
+		if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
+			pmc_log_process_mappings(pm->pm_owner, p);
+	}
+	/* mark process as using HWPMCs */
+	PROC_LOCK(p);
+	p->p_flag |= P_HWPMC;
+	PROC_UNLOCK(p);
+
+	return 0;
+}
+
+/*
+ * Attach a process and optionally its children
+ */
+
+static int
+pmc_attach_process(struct proc *p, struct pmc *pm)
+{
+	int error;
+	struct proc *top;
+
+	sx_assert(&pmc_sx, SX_XLOCKED);
+
+	PMCDBG(PRC,ATT,1, "attach pm=%p ri=%d proc=%p (%d, %s)", pm,
+	    PMC_TO_ROWINDEX(pm), p, p->p_pid, p->p_comm);
+
+
+	/*
+	 * If this PMC successfully allowed a GETMSR operation
+	 * in the past, disallow further ATTACHes.
+	 */
+
+	if ((pm->pm_flags & PMC_PP_ENABLE_MSR_ACCESS) != 0)
+		return EPERM;
+
+	if ((pm->pm_flags & PMC_F_DESCENDANTS) == 0)
+		return pmc_attach_one_process(p, pm);
+
+	/*
+	 * Traverse all child processes, attaching them to
+	 * this PMC.
+	 */
+
+	sx_slock(&proctree_lock);
+
+	top = p;
+
+	for (;;) {
+		if ((error = pmc_attach_one_process(p, pm)) != 0)
+			break;
+		if (!LIST_EMPTY(&p->p_children))
+			p = LIST_FIRST(&p->p_children);
+		else for (;;) {
+			if (p == top)
+				goto done;
+			if (LIST_NEXT(p, p_sibling)) {
+				p = LIST_NEXT(p, p_sibling);
+				break;
+			}
+			p = p->p_pptr;
+		}
+	}
+
+	if (error)
+		(void) pmc_detach_process(top, pm);
+
+ done:
+	sx_sunlock(&proctree_lock);
+	return error;
+}
+
+/*
+ * Detach a process from a PMC.  If there are no other PMCs tracking
+ * this process, remove the process structure from its hash table.  If
+ * 'flags' contains PMC_FLAG_REMOVE, then free the process structure.
+ */
+
+static int
+pmc_detach_one_process(struct proc *p, struct pmc *pm, int flags)
+{
+	int ri;
+	struct pmc_process *pp;
+
+	sx_assert(&pmc_sx, SX_XLOCKED);
+
+	KASSERT(pm != NULL,
+	    ("[pmc,%d] null pm pointer", __LINE__));
+
+	ri = PMC_TO_ROWINDEX(pm);
+
+	PMCDBG(PRC,ATT,2, "detach-one pm=%p ri=%d proc=%p (%d, %s) flags=0x%x",
+	    pm, ri, p, p->p_pid, p->p_comm, flags);
+
+	if ((pp = pmc_find_process_descriptor(p, 0)) == NULL)
+		return ESRCH;
+
+	if (pp->pp_pmcs[ri].pp_pmc != pm)
+		return EINVAL;
+
+	pmc_unlink_target_process(pm, pp);
+
+	/* Issue a detach entry if a log file is configured */
+	if (pm->pm_owner->po_flags & PMC_PO_OWNS_LOGFILE)
+		pmclog_process_pmcdetach(pm, p->p_pid);
+
+	/*
+	 * If there are no PMCs targetting this process, we remove its
+	 * descriptor from the target hash table and unset the P_HWPMC
+	 * flag in the struct proc.
+	 */
+	KASSERT(pp->pp_refcnt >= 0 && pp->pp_refcnt <= (int) md->pmd_npmc,
+	    ("[pmc,%d] Illegal refcnt %d for process struct %p",
+		__LINE__, pp->pp_refcnt, pp));
+
+	if (pp->pp_refcnt != 0)	/* still a target of some PMC */
+		return 0;
+
+	pmc_remove_process_descriptor(pp);
+
+	if (flags & PMC_FLAG_REMOVE)
+		free(pp, M_PMC);
+
+	PROC_LOCK(p);
+	p->p_flag &= ~P_HWPMC;
+	PROC_UNLOCK(p);
+
+	return 0;
+}
+
+/*
+ * Detach a process and optionally its descendants from a PMC.
+ */
+
+static int
+pmc_detach_process(struct proc *p, struct pmc *pm)
+{
+	struct proc *top;
+
+	sx_assert(&pmc_sx, SX_XLOCKED);
+
+	PMCDBG(PRC,ATT,1, "detach pm=%p ri=%d proc=%p (%d, %s)", pm,
+	    PMC_TO_ROWINDEX(pm), p, p->p_pid, p->p_comm);
+
+	if ((pm->pm_flags & PMC_F_DESCENDANTS) == 0)
+		return pmc_detach_one_process(p, pm, PMC_FLAG_REMOVE);
+
+	/*
+	 * Traverse all children, detaching them from this PMC.  We
+	 * ignore errors since we could be detaching a PMC from a
+	 * partially attached proc tree.
+	 */
+
+	sx_slock(&proctree_lock);
+
+	top = p;
+
+	for (;;) {
+		(void) pmc_detach_one_process(p, pm, PMC_FLAG_REMOVE);
+
+		if (!LIST_EMPTY(&p->p_children))
+			p = LIST_FIRST(&p->p_children);
+		else for (;;) {
+			if (p == top)
+				goto done;
+			if (LIST_NEXT(p, p_sibling)) {
+				p = LIST_NEXT(p, p_sibling);
+				break;
+			}
+			p = p->p_pptr;
+		}
+	}
+
+ done:
+	sx_sunlock(&proctree_lock);
+
+	if (LIST_EMPTY(&pm->pm_targets))
+		pm->pm_flags &= ~PMC_F_ATTACH_DONE;
+
+	return 0;
+}
+
+
+/*
+ * Thread context switch IN
+ */
+
+static void
+pmc_process_csw_in(struct thread *td)
+{
+	int cpu;
+	unsigned int adjri, ri;
+	struct pmc *pm;
+	struct proc *p;
+	struct pmc_cpu *pc;
+	struct pmc_hw *phw;
+	pmc_value_t newvalue;
+	struct pmc_process *pp;
+	struct pmc_classdep *pcd;
+
+	p = td->td_proc;
+
+	if ((pp = pmc_find_process_descriptor(p, PMC_FLAG_NONE)) == NULL)
+		return;
+
+	KASSERT(pp->pp_proc == td->td_proc,
+	    ("[pmc,%d] not my thread state", __LINE__));
+
+	critical_enter(); /* no preemption from this point */
+
+	cpu = PCPU_GET(cpuid); /* td->td_oncpu is invalid */
+
+	PMCDBG(CSW,SWI,1, "cpu=%d proc=%p (%d, %s) pp=%p", cpu, p,
+	    p->p_pid, p->p_comm, pp);
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[pmc,%d] wierd CPU id %d", __LINE__, cpu));
+
+	pc = pmc_pcpu[cpu];
+
+	for (ri = 0; ri < md->pmd_npmc; ri++) {
+
+		if ((pm = pp->pp_pmcs[ri].pp_pmc) == NULL)
+			continue;
+
+		KASSERT(PMC_IS_VIRTUAL_MODE(PMC_TO_MODE(pm)),
+		    ("[pmc,%d] Target PMC in non-virtual mode (%d)",
+			__LINE__, PMC_TO_MODE(pm)));
+
+		KASSERT(PMC_TO_ROWINDEX(pm) == ri,
+		    ("[pmc,%d] Row index mismatch pmc %d != ri %d",
+			__LINE__, PMC_TO_ROWINDEX(pm), ri));
+
+		/*
+		 * Only PMCs that are marked as 'RUNNING' need
+		 * be placed on hardware.
+		 */
+
+		if (pm->pm_state != PMC_STATE_RUNNING)
+			continue;
+
+		/* increment PMC runcount */
+		atomic_add_rel_int(&pm->pm_runcount, 1);
+
+		/* configure the HWPMC we are going to use. */
+		pcd = pmc_ri_to_classdep(md, ri, &adjri);
+		pcd->pcd_config_pmc(cpu, adjri, pm);
+
+		phw = pc->pc_hwpmcs[ri];
+
+		KASSERT(phw != NULL,
+		    ("[pmc,%d] null hw pointer", __LINE__));
+
+		KASSERT(phw->phw_pmc == pm,
+		    ("[pmc,%d] hw->pmc %p != pmc %p", __LINE__,
+			phw->phw_pmc, pm));
+
+		/*
+		 * Write out saved value and start the PMC.
+		 *
+		 * Sampling PMCs use a per-process value, while
+		 * counting mode PMCs use a per-pmc value that is
+		 * inherited across descendants.
+		 */
+		if (PMC_TO_MODE(pm) == PMC_MODE_TS) {
+			mtx_pool_lock_spin(pmc_mtxpool, pm);
+			newvalue = PMC_PCPU_SAVED(cpu,ri) =
+			    pp->pp_pmcs[ri].pp_pmcval;
+			mtx_pool_unlock_spin(pmc_mtxpool, pm);
+		} else {
+			KASSERT(PMC_TO_MODE(pm) == PMC_MODE_TC,
+			    ("[pmc,%d] illegal mode=%d", __LINE__,
+			    PMC_TO_MODE(pm)));
+			mtx_pool_lock_spin(pmc_mtxpool, pm);
+			newvalue = PMC_PCPU_SAVED(cpu, ri) =
+			    pm->pm_gv.pm_savedvalue;
+			mtx_pool_unlock_spin(pmc_mtxpool, pm);
+		}
+
+		PMCDBG(CSW,SWI,1,"cpu=%d ri=%d new=%jd", cpu, ri, newvalue);
+
+		pcd->pcd_write_pmc(cpu, adjri, newvalue);
+		pcd->pcd_start_pmc(cpu, adjri);
+	}
+
+	/*
+	 * perform any other architecture/cpu dependent thread
+	 * switch-in actions.
+	 */
+
+	(void) (*md->pmd_switch_in)(pc, pp);
+
+	critical_exit();
+
+}
+
+/*
+ * Thread context switch OUT.
+ */
+
+static void
+pmc_process_csw_out(struct thread *td)
+{
+	int cpu;
+	int64_t tmp;
+	struct pmc *pm;
+	struct proc *p;
+	enum pmc_mode mode;
+	struct pmc_cpu *pc;
+	pmc_value_t newvalue;
+	unsigned int adjri, ri;
+	struct pmc_process *pp;
+	struct pmc_classdep *pcd;
+
+
+	/*
+	 * Locate our process descriptor; this may be NULL if
+	 * this process is exiting and we have already removed
+	 * the process from the target process table.
+	 *
+	 * Note that due to kernel preemption, multiple
+	 * context switches may happen while the process is
+	 * exiting.
+	 *
+	 * Note also that if the target process cannot be
+	 * found we still need to deconfigure any PMCs that
+	 * are currently running on hardware.
+	 */
+
+	p = td->td_proc;
+	pp = pmc_find_process_descriptor(p, PMC_FLAG_NONE);
+
+	/*
+	 * save PMCs
+	 */
+
+	critical_enter();
+
+	cpu = PCPU_GET(cpuid); /* td->td_oncpu is invalid */
+
+	PMCDBG(CSW,SWO,1, "cpu=%d proc=%p (%d, %s) pp=%p", cpu, p,
+	    p->p_pid, p->p_comm, pp);
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[pmc,%d wierd CPU id %d", __LINE__, cpu));
+
+	pc = pmc_pcpu[cpu];
+
+	/*
+	 * When a PMC gets unlinked from a target PMC, it will
+	 * be removed from the target's pp_pmc[] array.
+	 *
+	 * However, on a MP system, the target could have been
+	 * executing on another CPU at the time of the unlink.
+	 * So, at context switch OUT time, we need to look at
+	 * the hardware to determine if a PMC is scheduled on
+	 * it.
+	 */
+
+	for (ri = 0; ri < md->pmd_npmc; ri++) {
+
+		pcd = pmc_ri_to_classdep(md, ri, &adjri);
+		pm  = NULL;
+		(void) (*pcd->pcd_get_config)(cpu, adjri, &pm);
+
+		if (pm == NULL)	/* nothing at this row index */
+			continue;
+
+		mode = PMC_TO_MODE(pm);
+		if (!PMC_IS_VIRTUAL_MODE(mode))
+			continue; /* not a process virtual PMC */
+
+		KASSERT(PMC_TO_ROWINDEX(pm) == ri,
+		    ("[pmc,%d] ri mismatch pmc(%d) ri(%d)",
+			__LINE__, PMC_TO_ROWINDEX(pm), ri));
+
+		/* Stop hardware if not already stopped */
+		if (pm->pm_stalled == 0)
+			pcd->pcd_stop_pmc(cpu, adjri);
+
+		/* reduce this PMC's runcount */
+		atomic_subtract_rel_int(&pm->pm_runcount, 1);
+
+		/*
+		 * If this PMC is associated with this process,
+		 * save the reading.
+		 */
+
+		if (pp != NULL && pp->pp_pmcs[ri].pp_pmc != NULL) {
+
+			KASSERT(pm == pp->pp_pmcs[ri].pp_pmc,
+			    ("[pmc,%d] pm %p != pp_pmcs[%d] %p", __LINE__,
+				pm, ri, pp->pp_pmcs[ri].pp_pmc));
+
+			KASSERT(pp->pp_refcnt > 0,
+			    ("[pmc,%d] pp refcnt = %d", __LINE__,
+				pp->pp_refcnt));
+
+			pcd->pcd_read_pmc(cpu, adjri, &newvalue);
+
+			tmp = newvalue - PMC_PCPU_SAVED(cpu,ri);
+
+			PMCDBG(CSW,SWO,1,"cpu=%d ri=%d tmp=%jd", cpu, ri,
+			    tmp);
+
+			if (mode == PMC_MODE_TS) {
+
+				/*
+				 * For sampling process-virtual PMCs,
+				 * we expect the count to be
+				 * decreasing as the 'value'
+				 * programmed into the PMC is the
+				 * number of events to be seen till
+				 * the next sampling interrupt.
+				 */
+				if (tmp < 0)
+					tmp += pm->pm_sc.pm_reloadcount;
+				mtx_pool_lock_spin(pmc_mtxpool, pm);
+				pp->pp_pmcs[ri].pp_pmcval -= tmp;
+				if ((int64_t) pp->pp_pmcs[ri].pp_pmcval < 0)
+					pp->pp_pmcs[ri].pp_pmcval +=
+					    pm->pm_sc.pm_reloadcount;
+				mtx_pool_unlock_spin(pmc_mtxpool, pm);
+
+			} else {
+
+				/*
+				 * For counting process-virtual PMCs,
+				 * we expect the count to be
+				 * increasing monotonically, modulo a 64
+				 * bit wraparound.
+				 */
+				KASSERT((int64_t) tmp >= 0,
+				    ("[pmc,%d] negative increment cpu=%d "
+				     "ri=%d newvalue=%jx saved=%jx "
+				     "incr=%jx", __LINE__, cpu, ri,
+				     newvalue, PMC_PCPU_SAVED(cpu,ri), tmp));
+
+				mtx_pool_lock_spin(pmc_mtxpool, pm);
+				pm->pm_gv.pm_savedvalue += tmp;
+				pp->pp_pmcs[ri].pp_pmcval += tmp;
+				mtx_pool_unlock_spin(pmc_mtxpool, pm);
+
+				if (pm->pm_flags & PMC_F_LOG_PROCCSW)
+					pmclog_process_proccsw(pm, pp, tmp);
+			}
+		}
+
+		/* mark hardware as free */
+		pcd->pcd_config_pmc(cpu, adjri, NULL);
+	}
+
+	/*
+	 * perform any other architecture/cpu dependent thread
+	 * switch out functions.
+	 */
+
+	(void) (*md->pmd_switch_out)(pc, pp);
+
+	critical_exit();
+}
+
+/*
+ * Log a KLD operation.
+ */
+
+static void
+pmc_process_kld_load(struct pmckern_map_in *pkm)
+{
+	struct pmc_owner *po;
+
+	sx_assert(&pmc_sx, SX_LOCKED);
+
+	/*
+	 * Notify owners of system sampling PMCs about KLD operations.
+	 */
+
+	LIST_FOREACH(po, &pmc_ss_owners, po_ssnext)
+	    if (po->po_flags & PMC_PO_OWNS_LOGFILE)
+		pmclog_process_map_in(po, (pid_t) -1, pkm->pm_address,
+		    (char *) pkm->pm_file);
+
+	/*
+	 * TODO: Notify owners of (all) process-sampling PMCs too.
+	 */
+
+	return;
+}
+
+static void
+pmc_process_kld_unload(struct pmckern_map_out *pkm)
+{
+	struct pmc_owner *po;
+
+	sx_assert(&pmc_sx, SX_LOCKED);
+
+	LIST_FOREACH(po, &pmc_ss_owners, po_ssnext)
+	    if (po->po_flags & PMC_PO_OWNS_LOGFILE)
+		pmclog_process_map_out(po, (pid_t) -1,
+		    pkm->pm_address, pkm->pm_address + pkm->pm_size);
+
+	/*
+	 * TODO: Notify owners of process-sampling PMCs.
+	 */
+}
+
+/*
+ * A mapping change for a process.
+ */
+
+static void
+pmc_process_mmap(struct thread *td, struct pmckern_map_in *pkm)
+{
+	int ri;
+	pid_t pid;
+	char *fullpath, *freepath;
+	const struct pmc *pm;
+	struct pmc_owner *po;
+	const struct pmc_process *pp;
+
+	freepath = fullpath = NULL;
+	pmc_getfilename((struct vnode *) pkm->pm_file, &fullpath, &freepath);
+
+	pid = td->td_proc->p_pid;
+
+	/* Inform owners of all system-wide sampling PMCs. */
+	LIST_FOREACH(po, &pmc_ss_owners, po_ssnext)
+	    if (po->po_flags & PMC_PO_OWNS_LOGFILE)
+		pmclog_process_map_in(po, pid, pkm->pm_address, fullpath);
+
+	if ((pp = pmc_find_process_descriptor(td->td_proc, 0)) == NULL)
+		goto done;
+
+	/*
+	 * Inform sampling PMC owners tracking this process.
+	 */
+	for (ri = 0; ri < md->pmd_npmc; ri++)
+		if ((pm = pp->pp_pmcs[ri].pp_pmc) != NULL &&
+		    PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
+			pmclog_process_map_in(pm->pm_owner,
+			    pid, pkm->pm_address, fullpath);
+
+  done:
+	if (freepath)
+		free(freepath, M_TEMP);
+}
+
+
+/*
+ * Log an munmap request.
+ */
+
+static void
+pmc_process_munmap(struct thread *td, struct pmckern_map_out *pkm)
+{
+	int ri;
+	pid_t pid;
+	struct pmc_owner *po;
+	const struct pmc *pm;
+	const struct pmc_process *pp;
+
+	pid = td->td_proc->p_pid;
+
+	LIST_FOREACH(po, &pmc_ss_owners, po_ssnext)
+	    if (po->po_flags & PMC_PO_OWNS_LOGFILE)
+		pmclog_process_map_out(po, pid, pkm->pm_address,
+		    pkm->pm_address + pkm->pm_size);
+
+	if ((pp = pmc_find_process_descriptor(td->td_proc, 0)) == NULL)
+		return;
+
+	for (ri = 0; ri < md->pmd_npmc; ri++)
+		if ((pm = pp->pp_pmcs[ri].pp_pmc) != NULL &&
+		    PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
+			pmclog_process_map_out(pm->pm_owner, pid,
+			    pkm->pm_address, pkm->pm_address + pkm->pm_size);
+}
+
+/*
+ * Log mapping information about the kernel.
+ */
+
+static void
+pmc_log_kernel_mappings(struct pmc *pm)
+{
+	struct pmc_owner *po;
+	struct pmckern_map_in *km, *kmbase;
+
+	sx_assert(&pmc_sx, SX_LOCKED);
+	KASSERT(PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)),
+	    ("[pmc,%d] non-sampling PMC (%p) desires mapping information",
+		__LINE__, (void *) pm));
+
+	po = pm->pm_owner;
+
+	if (po->po_flags & PMC_PO_INITIAL_MAPPINGS_DONE)
+		return;
+
+	/*
+	 * Log the current set of kernel modules.
+	 */
+	kmbase = linker_hwpmc_list_objects();
+	for (km = kmbase; km->pm_file != NULL; km++) {
+		PMCDBG(LOG,REG,1,"%s %p", (char *) km->pm_file,
+		    (void *) km->pm_address);
+		pmclog_process_map_in(po, (pid_t) -1, km->pm_address,
+		    km->pm_file);
+	}
+	free(kmbase, M_LINKER);
+
+	po->po_flags |= PMC_PO_INITIAL_MAPPINGS_DONE;
+}
+
+/*
+ * Log the mappings for a single process.
+ */
+
+static void
+pmc_log_process_mappings(struct pmc_owner *po, struct proc *p)
+{
+	int locked;
+	vm_map_t map;
+	struct vnode *vp;
+	struct vmspace *vm;
+	vm_map_entry_t entry;
+	vm_offset_t last_end;
+	u_int last_timestamp;
+	struct vnode *last_vp;
+	vm_offset_t start_addr;
+	vm_object_t obj, lobj, tobj;
+	char *fullpath, *freepath;
+
+	last_vp = NULL;
+	last_end = (vm_offset_t) 0;
+	fullpath = freepath = NULL;
+
+	if ((vm = vmspace_acquire_ref(p)) == NULL)
+		return;
+
+	map = &vm->vm_map;
+	vm_map_lock_read(map);
+
+	for (entry = map->header.next; entry != &map->header; entry = entry->next) {
+
+		if (entry == NULL) {
+			PMCDBG(LOG,OPS,2, "hwpmc: vm_map entry unexpectedly "
+			    "NULL! pid=%d vm_map=%p\n", p->p_pid, map);
+			break;
+		}
+
+		/*
+		 * We only care about executable map entries.
+		 */
+		if ((entry->eflags & MAP_ENTRY_IS_SUB_MAP) ||
+		    !(entry->protection & VM_PROT_EXECUTE) ||
+		    (entry->object.vm_object == NULL)) {
+			continue;
+		}
+
+		obj = entry->object.vm_object;
+		VM_OBJECT_LOCK(obj);
+
+		/*
+		 * Walk the backing_object list to find the base
+		 * (non-shadowed) vm_object.
+		 */
+		for (lobj = tobj = obj; tobj != NULL; tobj = tobj->backing_object) {
+			if (tobj != obj)
+				VM_OBJECT_LOCK(tobj);
+			if (lobj != obj)
+				VM_OBJECT_UNLOCK(lobj);
+			lobj = tobj;
+		}
+
+		/*
+		 * At this point lobj is the base vm_object and it is locked.
+		 */
+		if (lobj == NULL) {
+			PMCDBG(LOG,OPS,2, "hwpmc: lobj unexpectedly NULL! pid=%d "
+			    "vm_map=%p vm_obj=%p\n", p->p_pid, map, obj);
+			VM_OBJECT_UNLOCK(obj);
+			continue;
+		}
+
+		if (lobj->type != OBJT_VNODE || lobj->handle == NULL) {
+			if (lobj != obj)
+				VM_OBJECT_UNLOCK(lobj);
+			VM_OBJECT_UNLOCK(obj);
+			continue;
+		}
+
+		/*
+		 * Skip contiguous regions that point to the same
+		 * vnode, so we don't emit redundant MAP-IN
+		 * directives.
+		 */
+		if (entry->start == last_end && lobj->handle == last_vp) {
+			last_end = entry->end;
+			if (lobj != obj)
+				VM_OBJECT_UNLOCK(lobj);
+			VM_OBJECT_UNLOCK(obj);
+			continue;
+		}
+
+		/*
+		 * We don't want to keep the proc's vm_map or this
+		 * vm_object locked while we walk the pathname, since
+		 * vn_fullpath() can sleep.  However, if we drop the
+		 * lock, it's possible for concurrent activity to
+		 * modify the vm_map list.  To protect against this,
+		 * we save the vm_map timestamp before we release the
+		 * lock, and check it after we reacquire the lock
+		 * below.
+		 */
+		start_addr = entry->start;
+		last_end = entry->end;
+		last_timestamp = map->timestamp;
+		vm_map_unlock_read(map);
+
+		vp = lobj->handle;
+		vref(vp);
+		if (lobj != obj)
+			VM_OBJECT_UNLOCK(lobj);
+
+		VM_OBJECT_UNLOCK(obj);
+
+		freepath = NULL;
+		pmc_getfilename(vp, &fullpath, &freepath);
+		last_vp = vp;
+
+		locked = VFS_LOCK_GIANT(vp->v_mount);
+		vrele(vp);
+		VFS_UNLOCK_GIANT(locked);
+
+		vp = NULL;
+		pmclog_process_map_in(po, p->p_pid, start_addr, fullpath);
+		if (freepath)
+			free(freepath, M_TEMP);
+
+		vm_map_lock_read(map);
+
+		/*
+		 * If our saved timestamp doesn't match, this means
+		 * that the vm_map was modified out from under us and
+		 * we can't trust our current "entry" pointer.  Do a
+		 * new lookup for this entry.  If there is no entry
+		 * for this address range, vm_map_lookup_entry() will
+		 * return the previous one, so we always want to go to
+		 * entry->next on the next loop iteration.
+		 *
+		 * There is an edge condition here that can occur if
+		 * there is no entry at or before this address.  In
+		 * this situation, vm_map_lookup_entry returns
+		 * &map->header, which would cause our loop to abort
+		 * without processing the rest of the map.  However,
+		 * in practice this will never happen for process
+		 * vm_map.  This is because the executable's text
+		 * segment is the first mapping in the proc's address
+		 * space, and this mapping is never removed until the
+		 * process exits, so there will always be a non-header
+		 * entry at or before the requested address for
+		 * vm_map_lookup_entry to return.
+		 */
+		if (map->timestamp != last_timestamp)
+			vm_map_lookup_entry(map, last_end - 1, &entry);
+	}
+
+	vm_map_unlock_read(map);
+	vmspace_free(vm);
+	return;
+}
+
+/*
+ * Log mappings for all processes in the system.
+ */
+
+static void
+pmc_log_all_process_mappings(struct pmc_owner *po)
+{
+	struct proc *p, *top;
+
+	sx_assert(&pmc_sx, SX_XLOCKED);
+
+	if ((p = pfind(1)) == NULL)
+		panic("[pmc,%d] Cannot find init", __LINE__);
+
+	PROC_UNLOCK(p);
+
+	sx_slock(&proctree_lock);
+
+	top = p;
+
+	for (;;) {
+		pmc_log_process_mappings(po, p);
+		if (!LIST_EMPTY(&p->p_children))
+			p = LIST_FIRST(&p->p_children);
+		else for (;;) {
+			if (p == top)
+				goto done;
+			if (LIST_NEXT(p, p_sibling)) {
+				p = LIST_NEXT(p, p_sibling);
+				break;
+			}
+			p = p->p_pptr;
+		}
+	}
+ done:
+	sx_sunlock(&proctree_lock);
+}
+
+/*
+ * The 'hook' invoked from the kernel proper
+ */
+
+
+#ifdef	DEBUG
+const char *pmc_hooknames[] = {
+	/* these strings correspond to PMC_FN_* in <sys/pmckern.h> */
+	"",
+	"EXEC",
+	"CSW-IN",
+	"CSW-OUT",
+	"SAMPLE",
+	"KLDLOAD",
+	"KLDUNLOAD",
+	"MMAP",
+	"MUNMAP",
+	"CALLCHAIN"
+};
+#endif
+
+static int
+pmc_hook_handler(struct thread *td, int function, void *arg)
+{
+
+	PMCDBG(MOD,PMH,1, "hook td=%p func=%d \"%s\" arg=%p", td, function,
+	    pmc_hooknames[function], arg);
+
+	switch (function)
+	{
+
+	/*
+	 * Process exec()
+	 */
+
+	case PMC_FN_PROCESS_EXEC:
+	{
+		char *fullpath, *freepath;
+		unsigned int ri;
+		int is_using_hwpmcs;
+		struct pmc *pm;
+		struct proc *p;
+		struct pmc_owner *po;
+		struct pmc_process *pp;
+		struct pmckern_procexec *pk;
+
+		sx_assert(&pmc_sx, SX_XLOCKED);
+
+		p = td->td_proc;
+		pmc_getfilename(p->p_textvp, &fullpath, &freepath);
+
+		pk = (struct pmckern_procexec *) arg;
+
+		/* Inform owners of SS mode PMCs of the exec event. */
+		LIST_FOREACH(po, &pmc_ss_owners, po_ssnext)
+		    if (po->po_flags & PMC_PO_OWNS_LOGFILE)
+			    pmclog_process_procexec(po, PMC_ID_INVALID,
+				p->p_pid, pk->pm_entryaddr, fullpath);
+
+		PROC_LOCK(p);
+		is_using_hwpmcs = p->p_flag & P_HWPMC;
+		PROC_UNLOCK(p);
+
+		if (!is_using_hwpmcs) {
+			if (freepath)
+				free(freepath, M_TEMP);
+			break;
+		}
+
+		/*
+		 * PMCs are not inherited across an exec():  remove any
+		 * PMCs that this process is the owner of.
+		 */
+
+		if ((po = pmc_find_owner_descriptor(p)) != NULL) {
+			pmc_remove_owner(po);
+			pmc_destroy_owner_descriptor(po);
+		}
+
+		/*
+		 * If the process being exec'ed is not the target of any
+		 * PMC, we are done.
+		 */
+		if ((pp = pmc_find_process_descriptor(p, 0)) == NULL) {
+			if (freepath)
+				free(freepath, M_TEMP);
+			break;
+		}
+
+		/*
+		 * Log the exec event to all monitoring owners.  Skip
+		 * owners who have already recieved the event because
+		 * they had system sampling PMCs active.
+		 */
+		for (ri = 0; ri < md->pmd_npmc; ri++)
+			if ((pm = pp->pp_pmcs[ri].pp_pmc) != NULL) {
+				po = pm->pm_owner;
+				if (po->po_sscount == 0 &&
+				    po->po_flags & PMC_PO_OWNS_LOGFILE)
+					pmclog_process_procexec(po, pm->pm_id,
+					    p->p_pid, pk->pm_entryaddr,
+					    fullpath);
+			}
+
+		if (freepath)
+			free(freepath, M_TEMP);
+
+
+		PMCDBG(PRC,EXC,1, "exec proc=%p (%d, %s) cred-changed=%d",
+		    p, p->p_pid, p->p_comm, pk->pm_credentialschanged);
+
+		if (pk->pm_credentialschanged == 0) /* no change */
+			break;
+
+		/*
+		 * If the newly exec()'ed process has a different credential
+		 * than before, allow it to be the target of a PMC only if
+		 * the PMC's owner has sufficient priviledge.
+		 */
+
+		for (ri = 0; ri < md->pmd_npmc; ri++)
+			if ((pm = pp->pp_pmcs[ri].pp_pmc) != NULL)
+				if (pmc_can_attach(pm, td->td_proc) != 0)
+					pmc_detach_one_process(td->td_proc,
+					    pm, PMC_FLAG_NONE);
+
+		KASSERT(pp->pp_refcnt >= 0 && pp->pp_refcnt <= (int) md->pmd_npmc,
+		    ("[pmc,%d] Illegal ref count %d on pp %p", __LINE__,
+			pp->pp_refcnt, pp));
+
+		/*
+		 * If this process is no longer the target of any
+		 * PMCs, we can remove the process entry and free
+		 * up space.
+		 */
+
+		if (pp->pp_refcnt == 0) {
+			pmc_remove_process_descriptor(pp);
+			free(pp, M_PMC);
+			break;
+		}
+
+	}
+	break;
+
+	case PMC_FN_CSW_IN:
+		pmc_process_csw_in(td);
+		break;
+
+	case PMC_FN_CSW_OUT:
+		pmc_process_csw_out(td);
+		break;
+
+	/*
+	 * Process accumulated PC samples.
+	 *
+	 * This function is expected to be called by hardclock() for
+	 * each CPU that has accumulated PC samples.
+	 *
+	 * This function is to be executed on the CPU whose samples
+	 * are being processed.
+	 */
+	case PMC_FN_DO_SAMPLES:
+
+		/*
+		 * Clear the cpu specific bit in the CPU mask before
+		 * do the rest of the processing.  If the NMI handler
+		 * gets invoked after the "atomic_clear_int()" call
+		 * below but before "pmc_process_samples()" gets
+		 * around to processing the interrupt, then we will
+		 * come back here at the next hardclock() tick (and
+		 * may find nothing to do if "pmc_process_samples()"
+		 * had already processed the interrupt).  We don't
+		 * lose the interrupt sample.
+		 */
+		atomic_clear_int(&pmc_cpumask, (1 << PCPU_GET(cpuid)));
+		pmc_process_samples(PCPU_GET(cpuid));
+		break;
+
+
+	case PMC_FN_KLD_LOAD:
+		sx_assert(&pmc_sx, SX_LOCKED);
+		pmc_process_kld_load((struct pmckern_map_in *) arg);
+		break;
+
+	case PMC_FN_KLD_UNLOAD:
+		sx_assert(&pmc_sx, SX_LOCKED);
+		pmc_process_kld_unload((struct pmckern_map_out *) arg);
+		break;
+
+	case PMC_FN_MMAP:
+		sx_assert(&pmc_sx, SX_LOCKED);
+		pmc_process_mmap(td, (struct pmckern_map_in *) arg);
+		break;
+
+	case PMC_FN_MUNMAP:
+		sx_assert(&pmc_sx, SX_LOCKED);
+		pmc_process_munmap(td, (struct pmckern_map_out *) arg);
+		break;
+
+	case PMC_FN_USER_CALLCHAIN:
+		/*
+		 * Record a call chain.
+		 */
+		KASSERT(td == curthread, ("[pmc,%d] td != curthread",
+		    __LINE__));
+		pmc_capture_user_callchain(PCPU_GET(cpuid),
+		    (struct trapframe *) arg);
+		td->td_pflags &= ~TDP_CALLCHAIN;
+		break;
+
+	default:
+#ifdef	DEBUG
+		KASSERT(0, ("[pmc,%d] unknown hook %d\n", __LINE__, function));
+#endif
+		break;
+
+	}
+
+	return 0;
+}
+
+/*
+ * allocate a 'struct pmc_owner' descriptor in the owner hash table.
+ */
+
+static struct pmc_owner *
+pmc_allocate_owner_descriptor(struct proc *p)
+{
+	uint32_t hindex;
+	struct pmc_owner *po;
+	struct pmc_ownerhash *poh;
+
+	hindex = PMC_HASH_PTR(p, pmc_ownerhashmask);
+	poh = &pmc_ownerhash[hindex];
+
+	/* allocate space for N pointers and one descriptor struct */
+	po = malloc(sizeof(struct pmc_owner), M_PMC, M_WAITOK|M_ZERO);
+	po->po_sscount = po->po_error = po->po_flags = po->po_logprocmaps = 0;
+	po->po_file  = NULL;
+	po->po_owner = p;
+	po->po_kthread = NULL;
+	LIST_INIT(&po->po_pmcs);
+	LIST_INSERT_HEAD(poh, po, po_next); /* insert into hash table */
+
+	TAILQ_INIT(&po->po_logbuffers);
+	mtx_init(&po->po_mtx, "pmc-owner-mtx", "pmc-per-proc", MTX_SPIN);
+
+	PMCDBG(OWN,ALL,1, "allocate-owner proc=%p (%d, %s) pmc-owner=%p",
+	    p, p->p_pid, p->p_comm, po);
+
+	return po;
+}
+
+static void
+pmc_destroy_owner_descriptor(struct pmc_owner *po)
+{
+
+	PMCDBG(OWN,REL,1, "destroy-owner po=%p proc=%p (%d, %s)",
+	    po, po->po_owner, po->po_owner->p_pid, po->po_owner->p_comm);
+
+	mtx_destroy(&po->po_mtx);
+	free(po, M_PMC);
+}
+
+/*
+ * find the descriptor corresponding to process 'p', adding or removing it
+ * as specified by 'mode'.
+ */
+
+static struct pmc_process *
+pmc_find_process_descriptor(struct proc *p, uint32_t mode)
+{
+	uint32_t hindex;
+	struct pmc_process *pp, *ppnew;
+	struct pmc_processhash *pph;
+
+	hindex = PMC_HASH_PTR(p, pmc_processhashmask);
+	pph = &pmc_processhash[hindex];
+
+	ppnew = NULL;
+
+	/*
+	 * Pre-allocate memory in the FIND_ALLOCATE case since we
+	 * cannot call malloc(9) once we hold a spin lock.
+	 */
+	if (mode & PMC_FLAG_ALLOCATE)
+		ppnew = malloc(sizeof(struct pmc_process) + md->pmd_npmc *
+		    sizeof(struct pmc_targetstate), M_PMC, M_WAITOK|M_ZERO);
+
+	mtx_lock_spin(&pmc_processhash_mtx);
+	LIST_FOREACH(pp, pph, pp_next)
+	    if (pp->pp_proc == p)
+		    break;
+
+	if ((mode & PMC_FLAG_REMOVE) && pp != NULL)
+		LIST_REMOVE(pp, pp_next);
+
+	if ((mode & PMC_FLAG_ALLOCATE) && pp == NULL &&
+	    ppnew != NULL) {
+		ppnew->pp_proc = p;
+		LIST_INSERT_HEAD(pph, ppnew, pp_next);
+		pp = ppnew;
+		ppnew = NULL;
+	}
+	mtx_unlock_spin(&pmc_processhash_mtx);
+
+	if (pp != NULL && ppnew != NULL)
+		free(ppnew, M_PMC);
+
+	return pp;
+}
+
+/*
+ * remove a process descriptor from the process hash table.
+ */
+
+static void
+pmc_remove_process_descriptor(struct pmc_process *pp)
+{
+	KASSERT(pp->pp_refcnt == 0,
+	    ("[pmc,%d] Removing process descriptor %p with count %d",
+		__LINE__, pp, pp->pp_refcnt));
+
+	mtx_lock_spin(&pmc_processhash_mtx);
+	LIST_REMOVE(pp, pp_next);
+	mtx_unlock_spin(&pmc_processhash_mtx);
+}
+
+
+/*
+ * find an owner descriptor corresponding to proc 'p'
+ */
+
+static struct pmc_owner *
+pmc_find_owner_descriptor(struct proc *p)
+{
+	uint32_t hindex;
+	struct pmc_owner *po;
+	struct pmc_ownerhash *poh;
+
+	hindex = PMC_HASH_PTR(p, pmc_ownerhashmask);
+	poh = &pmc_ownerhash[hindex];
+
+	po = NULL;
+	LIST_FOREACH(po, poh, po_next)
+	    if (po->po_owner == p)
+		    break;
+
+	PMCDBG(OWN,FND,1, "find-owner proc=%p (%d, %s) hindex=0x%x -> "
+	    "pmc-owner=%p", p, p->p_pid, p->p_comm, hindex, po);
+
+	return po;
+}
+
+/*
+ * pmc_allocate_pmc_descriptor
+ *
+ * Allocate a pmc descriptor and initialize its
+ * fields.
+ */
+
+static struct pmc *
+pmc_allocate_pmc_descriptor(void)
+{
+	struct pmc *pmc;
+
+	pmc = malloc(sizeof(struct pmc), M_PMC, M_WAITOK|M_ZERO);
+
+	if (pmc != NULL) {
+		pmc->pm_owner = NULL;
+		LIST_INIT(&pmc->pm_targets);
+	}
+
+	PMCDBG(PMC,ALL,1, "allocate-pmc -> pmc=%p", pmc);
+
+	return pmc;
+}
+
+/*
+ * Destroy a pmc descriptor.
+ */
+
+static void
+pmc_destroy_pmc_descriptor(struct pmc *pm)
+{
+	(void) pm;
+
+#ifdef	DEBUG
+	KASSERT(pm->pm_state == PMC_STATE_DELETED ||
+	    pm->pm_state == PMC_STATE_FREE,
+	    ("[pmc,%d] destroying non-deleted PMC", __LINE__));
+	KASSERT(LIST_EMPTY(&pm->pm_targets),
+	    ("[pmc,%d] destroying pmc with targets", __LINE__));
+	KASSERT(pm->pm_owner == NULL,
+	    ("[pmc,%d] destroying pmc attached to an owner", __LINE__));
+	KASSERT(pm->pm_runcount == 0,
+	    ("[pmc,%d] pmc has non-zero run count %d", __LINE__,
+		pm->pm_runcount));
+#endif
+}
+
+static void
+pmc_wait_for_pmc_idle(struct pmc *pm)
+{
+#ifdef	DEBUG
+	volatile int maxloop;
+
+	maxloop = 100 * pmc_cpu_max();
+#endif
+
+	/*
+	 * Loop (with a forced context switch) till the PMC's runcount
+	 * comes down to zero.
+	 */
+	while (atomic_load_acq_32(&pm->pm_runcount) > 0) {
+#ifdef	DEBUG
+		maxloop--;
+		KASSERT(maxloop > 0,
+		    ("[pmc,%d] (ri%d, rc%d) waiting too long for "
+			"pmc to be free", __LINE__,
+			PMC_TO_ROWINDEX(pm), pm->pm_runcount));
+#endif
+		pmc_force_context_switch();
+	}
+}
+
+/*
+ * This function does the following things:
+ *
+ *  - detaches the PMC from hardware
+ *  - unlinks all target threads that were attached to it
+ *  - removes the PMC from its owner's list
+ *  - destroy's the PMC private mutex
+ *
+ * Once this function completes, the given pmc pointer can be safely
+ * FREE'd by the caller.
+ */
+
+static void
+pmc_release_pmc_descriptor(struct pmc *pm)
+{
+	enum pmc_mode mode;
+	struct pmc_hw *phw;
+	u_int adjri, ri, cpu;
+	struct pmc_owner *po;
+	struct pmc_binding pb;
+	struct pmc_process *pp;
+	struct pmc_classdep *pcd;
+	struct pmc_target *ptgt, *tmp;
+
+	sx_assert(&pmc_sx, SX_XLOCKED);
+
+	KASSERT(pm, ("[pmc,%d] null pmc", __LINE__));
+
+	ri   = PMC_TO_ROWINDEX(pm);
+	pcd  = pmc_ri_to_classdep(md, ri, &adjri);
+	mode = PMC_TO_MODE(pm);
+
+	PMCDBG(PMC,REL,1, "release-pmc pmc=%p ri=%d mode=%d", pm, ri,
+	    mode);
+
+	/*
+	 * First, we take the PMC off hardware.
+	 */
+	cpu = 0;
+	if (PMC_IS_SYSTEM_MODE(mode)) {
+
+		/*
+		 * A system mode PMC runs on a specific CPU.  Switch
+		 * to this CPU and turn hardware off.
+		 */
+		pmc_save_cpu_binding(&pb);
+
+		cpu = PMC_TO_CPU(pm);
+
+		pmc_select_cpu(cpu);
+
+		/* switch off non-stalled CPUs */
+		if (pm->pm_state == PMC_STATE_RUNNING &&
+		    pm->pm_stalled == 0) {
+
+			phw = pmc_pcpu[cpu]->pc_hwpmcs[ri];
+
+			KASSERT(phw->phw_pmc == pm,
+			    ("[pmc, %d] pmc ptr ri(%d) hw(%p) pm(%p)",
+				__LINE__, ri, phw->phw_pmc, pm));
+			PMCDBG(PMC,REL,2, "stopping cpu=%d ri=%d", cpu, ri);
+
+			critical_enter();
+			pcd->pcd_stop_pmc(cpu, adjri);
+			critical_exit();
+		}
+
+		PMCDBG(PMC,REL,2, "decfg cpu=%d ri=%d", cpu, ri);
+
+		critical_enter();
+		pcd->pcd_config_pmc(cpu, adjri, NULL);
+		critical_exit();
+
+		/* adjust the global and process count of SS mode PMCs */
+		if (mode == PMC_MODE_SS && pm->pm_state == PMC_STATE_RUNNING) {
+			po = pm->pm_owner;
+			po->po_sscount--;
+			if (po->po_sscount == 0) {
+				atomic_subtract_rel_int(&pmc_ss_count, 1);
+				LIST_REMOVE(po, po_ssnext);
+			}
+		}
+
+		pm->pm_state = PMC_STATE_DELETED;
+
+		pmc_restore_cpu_binding(&pb);
+
+		/*
+		 * We could have references to this PMC structure in
+		 * the per-cpu sample queues.  Wait for the queue to
+		 * drain.
+		 */
+		pmc_wait_for_pmc_idle(pm);
+
+	} else if (PMC_IS_VIRTUAL_MODE(mode)) {
+
+		/*
+		 * A virtual PMC could be running on multiple CPUs at
+		 * a given instant.
+		 *
+		 * By marking its state as DELETED, we ensure that
+		 * this PMC is never further scheduled on hardware.
+		 *
+		 * Then we wait till all CPUs are done with this PMC.
+		 */
+		pm->pm_state = PMC_STATE_DELETED;
+
+
+		/* Wait for the PMCs runcount to come to zero. */
+		pmc_wait_for_pmc_idle(pm);
+
+		/*
+		 * At this point the PMC is off all CPUs and cannot be
+		 * freshly scheduled onto a CPU.  It is now safe to
+		 * unlink all targets from this PMC.  If a
+		 * process-record's refcount falls to zero, we remove
+		 * it from the hash table.  The module-wide SX lock
+		 * protects us from races.
+		 */
+		LIST_FOREACH_SAFE(ptgt, &pm->pm_targets, pt_next, tmp) {
+			pp = ptgt->pt_process;
+			pmc_unlink_target_process(pm, pp); /* frees 'ptgt' */
+
+			PMCDBG(PMC,REL,3, "pp->refcnt=%d", pp->pp_refcnt);
+
+			/*
+			 * If the target process record shows that no
+			 * PMCs are attached to it, reclaim its space.
+			 */
+
+			if (pp->pp_refcnt == 0) {
+				pmc_remove_process_descriptor(pp);
+				free(pp, M_PMC);
+			}
+		}
+
+		cpu = curthread->td_oncpu; /* setup cpu for pmd_release() */
+
+	}
+
+	/*
+	 * Release any MD resources
+	 */
+	(void) pcd->pcd_release_pmc(cpu, adjri, pm);
+
+	/*
+	 * Update row disposition
+	 */
+
+	if (PMC_IS_SYSTEM_MODE(PMC_TO_MODE(pm)))
+		PMC_UNMARK_ROW_STANDALONE(ri);
+	else
+		PMC_UNMARK_ROW_THREAD(ri);
+
+	/* unlink from the owner's list */
+	if (pm->pm_owner) {
+		LIST_REMOVE(pm, pm_next);
+		pm->pm_owner = NULL;
+	}
+
+	pmc_destroy_pmc_descriptor(pm);
+}
+
+/*
+ * Register an owner and a pmc.
+ */
+
+static int
+pmc_register_owner(struct proc *p, struct pmc *pmc)
+{
+	struct pmc_owner *po;
+
+	sx_assert(&pmc_sx, SX_XLOCKED);
+
+	if ((po = pmc_find_owner_descriptor(p)) == NULL)
+		if ((po = pmc_allocate_owner_descriptor(p)) == NULL)
+			return ENOMEM;
+
+	KASSERT(pmc->pm_owner == NULL,
+	    ("[pmc,%d] attempting to own an initialized PMC", __LINE__));
+	pmc->pm_owner  = po;
+
+	LIST_INSERT_HEAD(&po->po_pmcs, pmc, pm_next);
+
+	PROC_LOCK(p);
+	p->p_flag |= P_HWPMC;
+	PROC_UNLOCK(p);
+
+	if (po->po_flags & PMC_PO_OWNS_LOGFILE)
+		pmclog_process_pmcallocate(pmc);
+
+	PMCDBG(PMC,REG,1, "register-owner pmc-owner=%p pmc=%p",
+	    po, pmc);
+
+	return 0;
+}
+
+/*
+ * Return the current row disposition:
+ * == 0 => FREE
+ *  > 0 => PROCESS MODE
+ *  < 0 => SYSTEM MODE
+ */
+
+int
+pmc_getrowdisp(int ri)
+{
+	return pmc_pmcdisp[ri];
+}
+
+/*
+ * Check if a PMC at row index 'ri' can be allocated to the current
+ * process.
+ *
+ * Allocation can fail if:
+ *   - the current process is already being profiled by a PMC at index 'ri',
+ *     attached to it via OP_PMCATTACH.
+ *   - the current process has already allocated a PMC at index 'ri'
+ *     via OP_ALLOCATE.
+ */
+
+static int
+pmc_can_allocate_rowindex(struct proc *p, unsigned int ri, int cpu)
+{
+	enum pmc_mode mode;
+	struct pmc *pm;
+	struct pmc_owner *po;
+	struct pmc_process *pp;
+
+	PMCDBG(PMC,ALR,1, "can-allocate-rowindex proc=%p (%d, %s) ri=%d "
+	    "cpu=%d", p, p->p_pid, p->p_comm, ri, cpu);
+
+	/*
+	 * We shouldn't have already allocated a process-mode PMC at
+	 * row index 'ri'.
+	 *
+	 * We shouldn't have allocated a system-wide PMC on the same
+	 * CPU and same RI.
+	 */
+	if ((po = pmc_find_owner_descriptor(p)) != NULL)
+		LIST_FOREACH(pm, &po->po_pmcs, pm_next) {
+		    if (PMC_TO_ROWINDEX(pm) == ri) {
+			    mode = PMC_TO_MODE(pm);
+			    if (PMC_IS_VIRTUAL_MODE(mode))
+				    return EEXIST;
+			    if (PMC_IS_SYSTEM_MODE(mode) &&
+				(int) PMC_TO_CPU(pm) == cpu)
+				    return EEXIST;
+		    }
+	        }
+
+	/*
+	 * We also shouldn't be the target of any PMC at this index
+	 * since otherwise a PMC_ATTACH to ourselves will fail.
+	 */
+	if ((pp = pmc_find_process_descriptor(p, 0)) != NULL)
+		if (pp->pp_pmcs[ri].pp_pmc)
+			return EEXIST;
+
+	PMCDBG(PMC,ALR,2, "can-allocate-rowindex proc=%p (%d, %s) ri=%d ok",
+	    p, p->p_pid, p->p_comm, ri);
+
+	return 0;
+}
+
+/*
+ * Check if a given PMC at row index 'ri' can be currently used in
+ * mode 'mode'.
+ */
+
+static int
+pmc_can_allocate_row(int ri, enum pmc_mode mode)
+{
+	enum pmc_disp	disp;
+
+	sx_assert(&pmc_sx, SX_XLOCKED);
+
+	PMCDBG(PMC,ALR,1, "can-allocate-row ri=%d mode=%d", ri, mode);
+
+	if (PMC_IS_SYSTEM_MODE(mode))
+		disp = PMC_DISP_STANDALONE;
+	else
+		disp = PMC_DISP_THREAD;
+
+	/*
+	 * check disposition for PMC row 'ri':
+	 *
+	 * Expected disposition		Row-disposition		Result
+	 *
+	 * STANDALONE			STANDALONE or FREE	proceed
+	 * STANDALONE			THREAD			fail
+	 * THREAD			THREAD or FREE		proceed
+	 * THREAD			STANDALONE		fail
+	 */
+
+	if (!PMC_ROW_DISP_IS_FREE(ri) &&
+	    !(disp == PMC_DISP_THREAD && PMC_ROW_DISP_IS_THREAD(ri)) &&
+	    !(disp == PMC_DISP_STANDALONE && PMC_ROW_DISP_IS_STANDALONE(ri)))
+		return EBUSY;
+
+	/*
+	 * All OK
+	 */
+
+	PMCDBG(PMC,ALR,2, "can-allocate-row ri=%d mode=%d ok", ri, mode);
+
+	return 0;
+
+}
+
+/*
+ * Find a PMC descriptor with user handle 'pmcid' for thread 'td'.
+ */
+
+static struct pmc *
+pmc_find_pmc_descriptor_in_process(struct pmc_owner *po, pmc_id_t pmcid)
+{
+	struct pmc *pm;
+
+	KASSERT(PMC_ID_TO_ROWINDEX(pmcid) < md->pmd_npmc,
+	    ("[pmc,%d] Illegal pmc index %d (max %d)", __LINE__,
+		PMC_ID_TO_ROWINDEX(pmcid), md->pmd_npmc));
+
+	LIST_FOREACH(pm, &po->po_pmcs, pm_next)
+	    if (pm->pm_id == pmcid)
+		    return pm;
+
+	return NULL;
+}
+
+static int
+pmc_find_pmc(pmc_id_t pmcid, struct pmc **pmc)
+{
+
+	struct pmc *pm;
+	struct pmc_owner *po;
+
+	PMCDBG(PMC,FND,1, "find-pmc id=%d", pmcid);
+
+	if ((po = pmc_find_owner_descriptor(curthread->td_proc)) == NULL)
+		return ESRCH;
+
+	if ((pm = pmc_find_pmc_descriptor_in_process(po, pmcid)) == NULL)
+		return EINVAL;
+
+	PMCDBG(PMC,FND,2, "find-pmc id=%d -> pmc=%p", pmcid, pm);
+
+	*pmc = pm;
+	return 0;
+}
+
+/*
+ * Start a PMC.
+ */
+
+static int
+pmc_start(struct pmc *pm)
+{
+	enum pmc_mode mode;
+	struct pmc_owner *po;
+	struct pmc_binding pb;
+	struct pmc_classdep *pcd;
+	int adjri, error, cpu, ri;
+
+	KASSERT(pm != NULL,
+	    ("[pmc,%d] null pm", __LINE__));
+
+	mode = PMC_TO_MODE(pm);
+	ri   = PMC_TO_ROWINDEX(pm);
+	pcd  = pmc_ri_to_classdep(md, ri, &adjri);
+
+	error = 0;
+
+	PMCDBG(PMC,OPS,1, "start pmc=%p mode=%d ri=%d", pm, mode, ri);
+
+	po = pm->pm_owner;
+
+	/*
+	 * Disallow PMCSTART if a logfile is required but has not been
+	 * configured yet.
+	 */
+	if ((pm->pm_flags & PMC_F_NEEDS_LOGFILE) &&
+	    (po->po_flags & PMC_PO_OWNS_LOGFILE) == 0)
+		return (EDOOFUS);	/* programming error */
+
+	/*
+	 * If this is a sampling mode PMC, log mapping information for
+	 * the kernel modules that are currently loaded.
+	 */
+	if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
+	    pmc_log_kernel_mappings(pm);
+
+	if (PMC_IS_VIRTUAL_MODE(mode)) {
+
+		/*
+		 * If a PMCATTACH has never been done on this PMC,
+		 * attach it to its owner process.
+		 */
+
+		if (LIST_EMPTY(&pm->pm_targets))
+			error = (pm->pm_flags & PMC_F_ATTACH_DONE) ? ESRCH :
+			    pmc_attach_process(po->po_owner, pm);
+
+		/*
+		 * If the PMC is attached to its owner, then force a context
+		 * switch to ensure that the MD state gets set correctly.
+		 */
+
+		if (error == 0) {
+			pm->pm_state = PMC_STATE_RUNNING;
+			if (pm->pm_flags & PMC_F_ATTACHED_TO_OWNER)
+				pmc_force_context_switch();
+		}
+
+		return (error);
+	}
+
+
+	/*
+	 * A system-wide PMC.
+	 *
+	 * Add the owner to the global list if this is a system-wide
+	 * sampling PMC.
+	 */
+
+	if (mode == PMC_MODE_SS) {
+		if (po->po_sscount == 0) {
+			LIST_INSERT_HEAD(&pmc_ss_owners, po, po_ssnext);
+			atomic_add_rel_int(&pmc_ss_count, 1);
+			PMCDBG(PMC,OPS,1, "po=%p in global list", po);
+		}
+		po->po_sscount++;
+
+		/*
+		 * Log mapping information for all existing processes in the
+		 * system.  Subsequent mappings are logged as they happen;
+		 * see pmc_process_mmap().
+		 */
+		if (po->po_logprocmaps == 0) {
+			pmc_log_all_process_mappings(po);
+			po->po_logprocmaps = 1;
+		}
+	}
+
+	/*
+	 * Move to the CPU associated with this
+	 * PMC, and start the hardware.
+	 */
+
+	pmc_save_cpu_binding(&pb);
+
+	cpu = PMC_TO_CPU(pm);
+
+	if (!pmc_cpu_is_active(cpu))
+		return (ENXIO);
+
+	pmc_select_cpu(cpu);
+
+	/*
+	 * global PMCs are configured at allocation time
+	 * so write out the initial value and start the PMC.
+	 */
+
+	pm->pm_state = PMC_STATE_RUNNING;
+
+	critical_enter();
+	if ((error = pcd->pcd_write_pmc(cpu, adjri,
+		 PMC_IS_SAMPLING_MODE(mode) ?
+		 pm->pm_sc.pm_reloadcount :
+		 pm->pm_sc.pm_initial)) == 0)
+		error = pcd->pcd_start_pmc(cpu, adjri);
+	critical_exit();
+
+	pmc_restore_cpu_binding(&pb);
+
+	return (error);
+}
+
+/*
+ * Stop a PMC.
+ */
+
+static int
+pmc_stop(struct pmc *pm)
+{
+	struct pmc_owner *po;
+	struct pmc_binding pb;
+	struct pmc_classdep *pcd;
+	int adjri, cpu, error, ri;
+
+	KASSERT(pm != NULL, ("[pmc,%d] null pmc", __LINE__));
+
+	PMCDBG(PMC,OPS,1, "stop pmc=%p mode=%d ri=%d", pm,
+	    PMC_TO_MODE(pm), PMC_TO_ROWINDEX(pm));
+
+	pm->pm_state = PMC_STATE_STOPPED;
+
+	/*
+	 * If the PMC is a virtual mode one, changing the state to
+	 * non-RUNNING is enough to ensure that the PMC never gets
+	 * scheduled.
+	 *
+	 * If this PMC is current running on a CPU, then it will
+	 * handled correctly at the time its target process is context
+	 * switched out.
+	 */
+
+	if (PMC_IS_VIRTUAL_MODE(PMC_TO_MODE(pm)))
+		return 0;
+
+	/*
+	 * A system-mode PMC.  Move to the CPU associated with
+	 * this PMC, and stop the hardware.  We update the
+	 * 'initial count' so that a subsequent PMCSTART will
+	 * resume counting from the current hardware count.
+	 */
+
+	pmc_save_cpu_binding(&pb);
+
+	cpu = PMC_TO_CPU(pm);
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[pmc,%d] illegal cpu=%d", __LINE__, cpu));
+
+	if (!pmc_cpu_is_active(cpu))
+		return ENXIO;
+
+	pmc_select_cpu(cpu);
+
+	ri = PMC_TO_ROWINDEX(pm);
+	pcd = pmc_ri_to_classdep(md, ri, &adjri);
+
+	critical_enter();
+	if ((error = pcd->pcd_stop_pmc(cpu, adjri)) == 0)
+		error = pcd->pcd_read_pmc(cpu, adjri, &pm->pm_sc.pm_initial);
+	critical_exit();
+
+	pmc_restore_cpu_binding(&pb);
+
+	po = pm->pm_owner;
+
+	/* remove this owner from the global list of SS PMC owners */
+	if (PMC_TO_MODE(pm) == PMC_MODE_SS) {
+		po->po_sscount--;
+		if (po->po_sscount == 0) {
+			atomic_subtract_rel_int(&pmc_ss_count, 1);
+			LIST_REMOVE(po, po_ssnext);
+			PMCDBG(PMC,OPS,2,"po=%p removed from global list", po);
+		}
+	}
+
+	return (error);
+}
+
+
+#ifdef	DEBUG
+static const char *pmc_op_to_name[] = {
+#undef	__PMC_OP
+#define	__PMC_OP(N, D)	#N ,
+	__PMC_OPS()
+	NULL
+};
+#endif
+
+/*
+ * The syscall interface
+ */
+
+#define	PMC_GET_SX_XLOCK(...) do {		\
+	sx_xlock(&pmc_sx);			\
+	if (pmc_hook == NULL) {			\
+		sx_xunlock(&pmc_sx);		\
+		return __VA_ARGS__;		\
+	}					\
+} while (0)
+
+#define	PMC_DOWNGRADE_SX() do {			\
+	sx_downgrade(&pmc_sx);			\
+	is_sx_downgraded = 1;			\
+} while (0)
+
+static int
+pmc_syscall_handler(struct thread *td, void *syscall_args)
+{
+	int error, is_sx_downgraded, is_sx_locked, op;
+	struct pmc_syscall_args *c;
+	void *arg;
+
+	PMC_GET_SX_XLOCK(ENOSYS);
+
+	DROP_GIANT();
+
+	is_sx_downgraded = 0;
+	is_sx_locked = 1;
+
+	c = (struct pmc_syscall_args *) syscall_args;
+
+	op = c->pmop_code;
+	arg = c->pmop_data;
+
+	PMCDBG(MOD,PMS,1, "syscall op=%d \"%s\" arg=%p", op,
+	    pmc_op_to_name[op], arg);
+
+	error = 0;
+	atomic_add_int(&pmc_stats.pm_syscalls, 1);
+
+	switch(op)
+	{
+
+
+	/*
+	 * Configure a log file.
+	 *
+	 * XXX This OP will be reworked.
+	 */
+
+	case PMC_OP_CONFIGURELOG:
+	{
+		struct proc *p;
+		struct pmc *pm;
+		struct pmc_owner *po;
+		struct pmc_op_configurelog cl;
+
+		sx_assert(&pmc_sx, SX_XLOCKED);
+
+		if ((error = copyin(arg, &cl, sizeof(cl))) != 0)
+			break;
+
+		/* mark this process as owning a log file */
+		p = td->td_proc;
+		if ((po = pmc_find_owner_descriptor(p)) == NULL)
+			if ((po = pmc_allocate_owner_descriptor(p)) == NULL) {
+				error = ENOMEM;
+				break;
+			}
+
+		/*
+		 * If a valid fd was passed in, try to configure that,
+		 * otherwise if 'fd' was less than zero and there was
+		 * a log file configured, flush its buffers and
+		 * de-configure it.
+		 */
+		if (cl.pm_logfd >= 0) {
+			sx_xunlock(&pmc_sx);
+			is_sx_locked = 0;
+			error = pmclog_configure_log(md, po, cl.pm_logfd);
+		} else if (po->po_flags & PMC_PO_OWNS_LOGFILE) {
+			pmclog_process_closelog(po);
+			error = pmclog_flush(po);
+			if (error == 0) {
+				LIST_FOREACH(pm, &po->po_pmcs, pm_next)
+				    if (pm->pm_flags & PMC_F_NEEDS_LOGFILE &&
+					pm->pm_state == PMC_STATE_RUNNING)
+					    pmc_stop(pm);
+				error = pmclog_deconfigure_log(po);
+			}
+		} else
+			error = EINVAL;
+
+		if (error)
+			break;
+	}
+	break;
+
+
+	/*
+	 * Flush a log file.
+	 */
+
+	case PMC_OP_FLUSHLOG:
+	{
+		struct pmc_owner *po;
+
+		sx_assert(&pmc_sx, SX_XLOCKED);
+
+		if ((po = pmc_find_owner_descriptor(td->td_proc)) == NULL) {
+			error = EINVAL;
+			break;
+		}
+
+		error = pmclog_flush(po);
+	}
+	break;
+
+	/*
+	 * Retrieve hardware configuration.
+	 */
+
+	case PMC_OP_GETCPUINFO:	/* CPU information */
+	{
+		struct pmc_op_getcpuinfo gci;
+		struct pmc_classinfo *pci;
+		struct pmc_classdep *pcd;
+		int cl;
+
+		gci.pm_cputype = md->pmd_cputype;
+		gci.pm_ncpu    = pmc_cpu_max();
+		gci.pm_npmc    = md->pmd_npmc;
+		gci.pm_nclass  = md->pmd_nclass;
+		pci = gci.pm_classes;
+		pcd = md->pmd_classdep;
+		for (cl = 0; cl < md->pmd_nclass; cl++, pci++, pcd++) {
+			pci->pm_caps  = pcd->pcd_caps;
+			pci->pm_class = pcd->pcd_class;
+			pci->pm_width = pcd->pcd_width;
+			pci->pm_num   = pcd->pcd_num;
+		}
+		error = copyout(&gci, arg, sizeof(gci));
+	}
+	break;
+
+
+	/*
+	 * Get module statistics
+	 */
+
+	case PMC_OP_GETDRIVERSTATS:
+	{
+		struct pmc_op_getdriverstats gms;
+
+		bcopy(&pmc_stats, &gms, sizeof(gms));
+		error = copyout(&gms, arg, sizeof(gms));
+	}
+	break;
+
+
+	/*
+	 * Retrieve module version number
+	 */
+
+	case PMC_OP_GETMODULEVERSION:
+	{
+		uint32_t cv, modv;
+
+		/* retrieve the client's idea of the ABI version */
+		if ((error = copyin(arg, &cv, sizeof(uint32_t))) != 0)
+			break;
+		/* don't service clients newer than our driver */
+		modv = PMC_VERSION;
+		if ((cv & 0xFFFF0000) > (modv & 0xFFFF0000)) {
+			error = EPROGMISMATCH;
+			break;
+		}
+		error = copyout(&modv, arg, sizeof(int));
+	}
+	break;
+
+
+	/*
+	 * Retrieve the state of all the PMCs on a given
+	 * CPU.
+	 */
+
+	case PMC_OP_GETPMCINFO:
+	{
+		int ari;
+		struct pmc *pm;
+		size_t pmcinfo_size;
+		uint32_t cpu, n, npmc;
+		struct pmc_owner *po;
+		struct pmc_binding pb;
+		struct pmc_classdep *pcd;
+		struct pmc_info *p, *pmcinfo;
+		struct pmc_op_getpmcinfo *gpi;
+
+		PMC_DOWNGRADE_SX();
+
+		gpi = (struct pmc_op_getpmcinfo *) arg;
+
+		if ((error = copyin(&gpi->pm_cpu, &cpu, sizeof(cpu))) != 0)
+			break;
+
+		if (cpu >= pmc_cpu_max()) {
+			error = EINVAL;
+			break;
+		}
+
+		if (!pmc_cpu_is_active(cpu)) {
+			error = ENXIO;
+			break;
+		}
+
+		/* switch to CPU 'cpu' */
+		pmc_save_cpu_binding(&pb);
+		pmc_select_cpu(cpu);
+
+		npmc = md->pmd_npmc;
+
+		pmcinfo_size = npmc * sizeof(struct pmc_info);
+		pmcinfo = malloc(pmcinfo_size, M_PMC, M_WAITOK);
+
+		p = pmcinfo;
+
+		for (n = 0; n < md->pmd_npmc; n++, p++) {
+
+			pcd = pmc_ri_to_classdep(md, n, &ari);
+
+			KASSERT(pcd != NULL,
+			    ("[pmc,%d] null pcd ri=%d", __LINE__, n));
+
+			if ((error = pcd->pcd_describe(cpu, ari, p, &pm)) != 0)
+				break;
+
+			if (PMC_ROW_DISP_IS_STANDALONE(n))
+				p->pm_rowdisp = PMC_DISP_STANDALONE;
+			else if (PMC_ROW_DISP_IS_THREAD(n))
+				p->pm_rowdisp = PMC_DISP_THREAD;
+			else
+				p->pm_rowdisp = PMC_DISP_FREE;
+
+			p->pm_ownerpid = -1;
+
+			if (pm == NULL)	/* no PMC associated */
+				continue;
+
+			po = pm->pm_owner;
+
+			KASSERT(po->po_owner != NULL,
+			    ("[pmc,%d] pmc_owner had a null proc pointer",
+				__LINE__));
+
+			p->pm_ownerpid = po->po_owner->p_pid;
+			p->pm_mode     = PMC_TO_MODE(pm);
+			p->pm_event    = pm->pm_event;
+			p->pm_flags    = pm->pm_flags;
+
+			if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
+				p->pm_reloadcount =
+				    pm->pm_sc.pm_reloadcount;
+		}
+
+		pmc_restore_cpu_binding(&pb);
+
+		/* now copy out the PMC info collected */
+		if (error == 0)
+			error = copyout(pmcinfo, &gpi->pm_pmcs, pmcinfo_size);
+
+		free(pmcinfo, M_PMC);
+	}
+	break;
+
+
+	/*
+	 * Set the administrative state of a PMC.  I.e. whether
+	 * the PMC is to be used or not.
+	 */
+
+	case PMC_OP_PMCADMIN:
+	{
+		int cpu, ri;
+		enum pmc_state request;
+		struct pmc_cpu *pc;
+		struct pmc_hw *phw;
+		struct pmc_op_pmcadmin pma;
+		struct pmc_binding pb;
+
+		sx_assert(&pmc_sx, SX_XLOCKED);
+
+		KASSERT(td == curthread,
+		    ("[pmc,%d] td != curthread", __LINE__));
+
+		error = priv_check(td, PRIV_PMC_MANAGE);
+		if (error)
+			break;
+
+		if ((error = copyin(arg, &pma, sizeof(pma))) != 0)
+			break;
+
+		cpu = pma.pm_cpu;
+
+		if (cpu < 0 || cpu >= (int) pmc_cpu_max()) {
+			error = EINVAL;
+			break;
+		}
+
+		if (!pmc_cpu_is_active(cpu)) {
+			error = ENXIO;
+			break;
+		}
+
+		request = pma.pm_state;
+
+		if (request != PMC_STATE_DISABLED &&
+		    request != PMC_STATE_FREE) {
+			error = EINVAL;
+			break;
+		}
+
+		ri = pma.pm_pmc; /* pmc id == row index */
+		if (ri < 0 || ri >= (int) md->pmd_npmc) {
+			error = EINVAL;
+			break;
+		}
+
+		/*
+		 * We can't disable a PMC with a row-index allocated
+		 * for process virtual PMCs.
+		 */
+
+		if (PMC_ROW_DISP_IS_THREAD(ri) &&
+		    request == PMC_STATE_DISABLED) {
+			error = EBUSY;
+			break;
+		}
+
+		/*
+		 * otherwise, this PMC on this CPU is either free or
+		 * in system-wide mode.
+		 */
+
+		pmc_save_cpu_binding(&pb);
+		pmc_select_cpu(cpu);
+
+		pc  = pmc_pcpu[cpu];
+		phw = pc->pc_hwpmcs[ri];
+
+		/*
+		 * XXX do we need some kind of 'forced' disable?
+		 */
+
+		if (phw->phw_pmc == NULL) {
+			if (request == PMC_STATE_DISABLED &&
+			    (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED)) {
+				phw->phw_state &= ~PMC_PHW_FLAG_IS_ENABLED;
+				PMC_MARK_ROW_STANDALONE(ri);
+			} else if (request == PMC_STATE_FREE &&
+			    (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) == 0) {
+				phw->phw_state |=  PMC_PHW_FLAG_IS_ENABLED;
+				PMC_UNMARK_ROW_STANDALONE(ri);
+			}
+			/* other cases are a no-op */
+		} else
+			error = EBUSY;
+
+		pmc_restore_cpu_binding(&pb);
+	}
+	break;
+
+
+	/*
+	 * Allocate a PMC.
+	 */
+
+	case PMC_OP_PMCALLOCATE:
+	{
+		int adjri, n;
+		u_int cpu;
+		uint32_t caps;
+		struct pmc *pmc;
+		enum pmc_mode mode;
+		struct pmc_hw *phw;
+		struct pmc_binding pb;
+		struct pmc_classdep *pcd;
+		struct pmc_op_pmcallocate pa;
+
+		if ((error = copyin(arg, &pa, sizeof(pa))) != 0)
+			break;
+
+		caps = pa.pm_caps;
+		mode = pa.pm_mode;
+		cpu  = pa.pm_cpu;
+
+		if ((mode != PMC_MODE_SS  &&  mode != PMC_MODE_SC  &&
+		     mode != PMC_MODE_TS  &&  mode != PMC_MODE_TC) ||
+		    (cpu != (u_int) PMC_CPU_ANY && cpu >= pmc_cpu_max())) {
+			error = EINVAL;
+			break;
+		}
+
+		/*
+		 * Virtual PMCs should only ask for a default CPU.
+		 * System mode PMCs need to specify a non-default CPU.
+		 */
+
+		if ((PMC_IS_VIRTUAL_MODE(mode) && cpu != (u_int) PMC_CPU_ANY) ||
+		    (PMC_IS_SYSTEM_MODE(mode) && cpu == (u_int) PMC_CPU_ANY)) {
+			error = EINVAL;
+			break;
+		}
+
+		/*
+		 * Check that an inactive CPU is not being asked for.
+		 */
+
+		if (PMC_IS_SYSTEM_MODE(mode) && !pmc_cpu_is_active(cpu)) {
+			error = ENXIO;
+			break;
+		}
+
+		/*
+		 * Refuse an allocation for a system-wide PMC if this
+		 * process has been jailed, or if this process lacks
+		 * super-user credentials and the sysctl tunable
+		 * 'security.bsd.unprivileged_syspmcs' is zero.
+		 */
+
+		if (PMC_IS_SYSTEM_MODE(mode)) {
+			if (jailed(curthread->td_ucred)) {
+				error = EPERM;
+				break;
+			}
+			if (!pmc_unprivileged_syspmcs) {
+				error = priv_check(curthread,
+				    PRIV_PMC_SYSTEM);
+				if (error)
+					break;
+			}
+		}
+
+		/*
+		 * Look for valid values for 'pm_flags'
+		 */
+
+		if ((pa.pm_flags & ~(PMC_F_DESCENDANTS | PMC_F_LOG_PROCCSW |
+		    PMC_F_LOG_PROCEXIT | PMC_F_CALLCHAIN)) != 0) {
+			error = EINVAL;
+			break;
+		}
+
+		/* process logging options are not allowed for system PMCs */
+		if (PMC_IS_SYSTEM_MODE(mode) && (pa.pm_flags &
+		    (PMC_F_LOG_PROCCSW | PMC_F_LOG_PROCEXIT))) {
+			error = EINVAL;
+			break;
+		}
+
+		/*
+		 * All sampling mode PMCs need to be able to interrupt the
+		 * CPU.
+		 */
+		if (PMC_IS_SAMPLING_MODE(mode))
+			caps |= PMC_CAP_INTERRUPT;
+
+		/* A valid class specifier should have been passed in. */
+		for (n = 0; n < md->pmd_nclass; n++)
+			if (md->pmd_classdep[n].pcd_class == pa.pm_class)
+				break;
+		if (n == md->pmd_nclass) {
+			error = EINVAL;
+			break;
+		}
+
+		/* The requested PMC capabilities should be feasible. */
+		if ((md->pmd_classdep[n].pcd_caps & caps) != caps) {
+			error = EOPNOTSUPP;
+			break;
+		}
+
+		PMCDBG(PMC,ALL,2, "event=%d caps=0x%x mode=%d cpu=%d",
+		    pa.pm_ev, caps, mode, cpu);
+
+		pmc = pmc_allocate_pmc_descriptor();
+		pmc->pm_id    = PMC_ID_MAKE_ID(cpu,pa.pm_mode,pa.pm_class,
+		    PMC_ID_INVALID);
+		pmc->pm_event = pa.pm_ev;
+		pmc->pm_state = PMC_STATE_FREE;
+		pmc->pm_caps  = caps;
+		pmc->pm_flags = pa.pm_flags;
+
+		/* switch thread to CPU 'cpu' */
+		pmc_save_cpu_binding(&pb);
+
+#define	PMC_IS_SHAREABLE_PMC(cpu, n)				\
+	(pmc_pcpu[(cpu)]->pc_hwpmcs[(n)]->phw_state &		\
+	 PMC_PHW_FLAG_IS_SHAREABLE)
+#define	PMC_IS_UNALLOCATED(cpu, n)				\
+	(pmc_pcpu[(cpu)]->pc_hwpmcs[(n)]->phw_pmc == NULL)
+
+		if (PMC_IS_SYSTEM_MODE(mode)) {
+			pmc_select_cpu(cpu);
+			for (n = 0; n < (int) md->pmd_npmc; n++) {
+				pcd = pmc_ri_to_classdep(md, n, &adjri);
+				if (pmc_can_allocate_row(n, mode) == 0 &&
+				    pmc_can_allocate_rowindex(
+					    curthread->td_proc, n, cpu) == 0 &&
+				    (PMC_IS_UNALLOCATED(cpu, n) ||
+				     PMC_IS_SHAREABLE_PMC(cpu, n)) &&
+				    pcd->pcd_allocate_pmc(cpu, adjri, pmc,
+					&pa) == 0)
+					break;
+			}
+		} else {
+			/* Process virtual mode */
+			for (n = 0; n < (int) md->pmd_npmc; n++) {
+				pcd = pmc_ri_to_classdep(md, n, &adjri);
+				if (pmc_can_allocate_row(n, mode) == 0 &&
+				    pmc_can_allocate_rowindex(
+					    curthread->td_proc, n,
+					    PMC_CPU_ANY) == 0 &&
+				    pcd->pcd_allocate_pmc(curthread->td_oncpu,
+					adjri, pmc, &pa) == 0)
+					break;
+			}
+		}
+
+#undef	PMC_IS_UNALLOCATED
+#undef	PMC_IS_SHAREABLE_PMC
+
+		pmc_restore_cpu_binding(&pb);
+
+		if (n == (int) md->pmd_npmc) {
+			pmc_destroy_pmc_descriptor(pmc);
+			free(pmc, M_PMC);
+			pmc = NULL;
+			error = EINVAL;
+			break;
+		}
+
+		/* Fill in the correct value in the ID field */
+		pmc->pm_id = PMC_ID_MAKE_ID(cpu,mode,pa.pm_class,n);
+
+		PMCDBG(PMC,ALL,2, "ev=%d class=%d mode=%d n=%d -> pmcid=%x",
+		    pmc->pm_event, pa.pm_class, mode, n, pmc->pm_id);
+
+		/* Process mode PMCs with logging enabled need log files */
+		if (pmc->pm_flags & (PMC_F_LOG_PROCEXIT | PMC_F_LOG_PROCCSW))
+			pmc->pm_flags |= PMC_F_NEEDS_LOGFILE;
+
+		/* All system mode sampling PMCs require a log file */
+		if (PMC_IS_SAMPLING_MODE(mode) && PMC_IS_SYSTEM_MODE(mode))
+			pmc->pm_flags |= PMC_F_NEEDS_LOGFILE;
+
+		/*
+		 * Configure global pmc's immediately
+		 */
+
+		if (PMC_IS_SYSTEM_MODE(PMC_TO_MODE(pmc))) {
+
+			pmc_save_cpu_binding(&pb);
+			pmc_select_cpu(cpu);
+
+			phw = pmc_pcpu[cpu]->pc_hwpmcs[n];
+			pcd = pmc_ri_to_classdep(md, n, &adjri);
+
+			if ((phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) == 0 ||
+			    (error = pcd->pcd_config_pmc(cpu, adjri, pmc)) != 0) {
+				(void) pcd->pcd_release_pmc(cpu, adjri, pmc);
+				pmc_destroy_pmc_descriptor(pmc);
+				free(pmc, M_PMC);
+				pmc = NULL;
+				pmc_restore_cpu_binding(&pb);
+				error = EPERM;
+				break;
+			}
+
+			pmc_restore_cpu_binding(&pb);
+		}
+
+		pmc->pm_state    = PMC_STATE_ALLOCATED;
+
+		/*
+		 * mark row disposition
+		 */
+
+		if (PMC_IS_SYSTEM_MODE(mode))
+			PMC_MARK_ROW_STANDALONE(n);
+		else
+			PMC_MARK_ROW_THREAD(n);
+
+		/*
+		 * Register this PMC with the current thread as its owner.
+		 */
+
+		if ((error =
+		    pmc_register_owner(curthread->td_proc, pmc)) != 0) {
+			pmc_release_pmc_descriptor(pmc);
+			free(pmc, M_PMC);
+			pmc = NULL;
+			break;
+		}
+
+		/*
+		 * Return the allocated index.
+		 */
+
+		pa.pm_pmcid = pmc->pm_id;
+
+		error = copyout(&pa, arg, sizeof(pa));
+	}
+	break;
+
+
+	/*
+	 * Attach a PMC to a process.
+	 */
+
+	case PMC_OP_PMCATTACH:
+	{
+		struct pmc *pm;
+		struct proc *p;
+		struct pmc_op_pmcattach a;
+
+		sx_assert(&pmc_sx, SX_XLOCKED);
+
+		if ((error = copyin(arg, &a, sizeof(a))) != 0)
+			break;
+
+		if (a.pm_pid < 0) {
+			error = EINVAL;
+			break;
+		} else if (a.pm_pid == 0)
+			a.pm_pid = td->td_proc->p_pid;
+
+		if ((error = pmc_find_pmc(a.pm_pmc, &pm)) != 0)
+			break;
+
+		if (PMC_IS_SYSTEM_MODE(PMC_TO_MODE(pm))) {
+			error = EINVAL;
+			break;
+		}
+
+		/* PMCs may be (re)attached only when allocated or stopped */
+		if (pm->pm_state == PMC_STATE_RUNNING) {
+			error = EBUSY;
+			break;
+		} else if (pm->pm_state != PMC_STATE_ALLOCATED &&
+		    pm->pm_state != PMC_STATE_STOPPED) {
+			error = EINVAL;
+			break;
+		}
+
+		/* lookup pid */
+		if ((p = pfind(a.pm_pid)) == NULL) {
+			error = ESRCH;
+			break;
+		}
+
+		/*
+		 * Ignore processes that are working on exiting.
+		 */
+		if (p->p_flag & P_WEXIT) {
+			error = ESRCH;
+			PROC_UNLOCK(p);	/* pfind() returns a locked process */
+			break;
+		}
+
+		/*
+		 * we are allowed to attach a PMC to a process if
+		 * we can debug it.
+		 */
+		error = p_candebug(curthread, p);
+
+		PROC_UNLOCK(p);
+
+		if (error == 0)
+			error = pmc_attach_process(p, pm);
+	}
+	break;
+
+
+	/*
+	 * Detach an attached PMC from a process.
+	 */
+
+	case PMC_OP_PMCDETACH:
+	{
+		struct pmc *pm;
+		struct proc *p;
+		struct pmc_op_pmcattach a;
+
+		if ((error = copyin(arg, &a, sizeof(a))) != 0)
+			break;
+
+		if (a.pm_pid < 0) {
+			error = EINVAL;
+			break;
+		} else if (a.pm_pid == 0)
+			a.pm_pid = td->td_proc->p_pid;
+
+		if ((error = pmc_find_pmc(a.pm_pmc, &pm)) != 0)
+			break;
+
+		if ((p = pfind(a.pm_pid)) == NULL) {
+			error = ESRCH;
+			break;
+		}
+
+		/*
+		 * Treat processes that are in the process of exiting
+		 * as if they were not present.
+		 */
+
+		if (p->p_flag & P_WEXIT)
+			error = ESRCH;
+
+		PROC_UNLOCK(p);	/* pfind() returns a locked process */
+
+		if (error == 0)
+			error = pmc_detach_process(p, pm);
+	}
+	break;
+
+
+	/*
+	 * Retrieve the MSR number associated with the counter
+	 * 'pmc_id'.  This allows processes to directly use RDPMC
+	 * instructions to read their PMCs, without the overhead of a
+	 * system call.
+	 */
+
+	case PMC_OP_PMCGETMSR:
+	{
+		int adjri, ri;
+		struct pmc *pm;
+		struct pmc_target *pt;
+		struct pmc_op_getmsr gm;
+		struct pmc_classdep *pcd;
+
+		PMC_DOWNGRADE_SX();
+
+		if ((error = copyin(arg, &gm, sizeof(gm))) != 0)
+			break;
+
+		if ((error = pmc_find_pmc(gm.pm_pmcid, &pm)) != 0)
+			break;
+
+		/*
+		 * The allocated PMC has to be a process virtual PMC,
+		 * i.e., of type MODE_T[CS].  Global PMCs can only be
+		 * read using the PMCREAD operation since they may be
+		 * allocated on a different CPU than the one we could
+		 * be running on at the time of the RDPMC instruction.
+		 *
+		 * The GETMSR operation is not allowed for PMCs that
+		 * are inherited across processes.
+		 */
+
+		if (!PMC_IS_VIRTUAL_MODE(PMC_TO_MODE(pm)) ||
+		    (pm->pm_flags & PMC_F_DESCENDANTS)) {
+			error = EINVAL;
+			break;
+		}
+
+		/*
+		 * It only makes sense to use a RDPMC (or its
+		 * equivalent instruction on non-x86 architectures) on
+		 * a process that has allocated and attached a PMC to
+		 * itself.  Conversely the PMC is only allowed to have
+		 * one process attached to it -- its owner.
+		 */
+
+		if ((pt = LIST_FIRST(&pm->pm_targets)) == NULL ||
+		    LIST_NEXT(pt, pt_next) != NULL ||
+		    pt->pt_process->pp_proc != pm->pm_owner->po_owner) {
+			error = EINVAL;
+			break;
+		}
+
+		ri = PMC_TO_ROWINDEX(pm);
+		pcd = pmc_ri_to_classdep(md, ri, &adjri);
+
+		/* PMC class has no 'GETMSR' support */
+		if (pcd->pcd_get_msr == NULL) {
+			error = ENOSYS;
+			break;
+		}
+
+		if ((error = (*pcd->pcd_get_msr)(adjri, &gm.pm_msr)) < 0)
+			break;
+
+		if ((error = copyout(&gm, arg, sizeof(gm))) < 0)
+			break;
+
+		/*
+		 * Mark our process as using MSRs.  Update machine
+		 * state using a forced context switch.
+		 */
+
+		pt->pt_process->pp_flags |= PMC_PP_ENABLE_MSR_ACCESS;
+		pmc_force_context_switch();
+
+	}
+	break;
+
+	/*
+	 * Release an allocated PMC
+	 */
+
+	case PMC_OP_PMCRELEASE:
+	{
+		pmc_id_t pmcid;
+		struct pmc *pm;
+		struct pmc_owner *po;
+		struct pmc_op_simple sp;
+
+		/*
+		 * Find PMC pointer for the named PMC.
+		 *
+		 * Use pmc_release_pmc_descriptor() to switch off the
+		 * PMC, remove all its target threads, and remove the
+		 * PMC from its owner's list.
+		 *
+		 * Remove the owner record if this is the last PMC
+		 * owned.
+		 *
+		 * Free up space.
+		 */
+
+		if ((error = copyin(arg, &sp, sizeof(sp))) != 0)
+			break;
+
+		pmcid = sp.pm_pmcid;
+
+		if ((error = pmc_find_pmc(pmcid, &pm)) != 0)
+			break;
+
+		po = pm->pm_owner;
+		pmc_release_pmc_descriptor(pm);
+		pmc_maybe_remove_owner(po);
+
+		free(pm, M_PMC);
+	}
+	break;
+
+
+	/*
+	 * Read and/or write a PMC.
+	 */
+
+	case PMC_OP_PMCRW:
+	{
+		int adjri;
+		struct pmc *pm;
+		uint32_t cpu, ri;
+		pmc_value_t oldvalue;
+		struct pmc_binding pb;
+		struct pmc_op_pmcrw prw;
+		struct pmc_classdep *pcd;
+		struct pmc_op_pmcrw *pprw;
+
+		PMC_DOWNGRADE_SX();
+
+		if ((error = copyin(arg, &prw, sizeof(prw))) != 0)
+			break;
+
+		ri = 0;
+		PMCDBG(PMC,OPS,1, "rw id=%d flags=0x%x", prw.pm_pmcid,
+		    prw.pm_flags);
+
+		/* must have at least one flag set */
+		if ((prw.pm_flags & (PMC_F_OLDVALUE|PMC_F_NEWVALUE)) == 0) {
+			error = EINVAL;
+			break;
+		}
+
+		/* locate pmc descriptor */
+		if ((error = pmc_find_pmc(prw.pm_pmcid, &pm)) != 0)
+			break;
+
+		/* Can't read a PMC that hasn't been started. */
+		if (pm->pm_state != PMC_STATE_ALLOCATED &&
+		    pm->pm_state != PMC_STATE_STOPPED &&
+		    pm->pm_state != PMC_STATE_RUNNING) {
+			error = EINVAL;
+			break;
+		}
+
+		/* writing a new value is allowed only for 'STOPPED' pmcs */
+		if (pm->pm_state == PMC_STATE_RUNNING &&
+		    (prw.pm_flags & PMC_F_NEWVALUE)) {
+			error = EBUSY;
+			break;
+		}
+
+		if (PMC_IS_VIRTUAL_MODE(PMC_TO_MODE(pm))) {
+
+			/*
+			 * If this PMC is attached to its owner (i.e.,
+			 * the process requesting this operation) and
+			 * is running, then attempt to get an
+			 * upto-date reading from hardware for a READ.
+			 * Writes are only allowed when the PMC is
+			 * stopped, so only update the saved value
+			 * field.
+			 *
+			 * If the PMC is not running, or is not
+			 * attached to its owner, read/write to the
+			 * savedvalue field.
+			 */
+
+			ri = PMC_TO_ROWINDEX(pm);
+			pcd = pmc_ri_to_classdep(md, ri, &adjri);
+
+			mtx_pool_lock_spin(pmc_mtxpool, pm);
+			cpu = curthread->td_oncpu;
+
+			if (prw.pm_flags & PMC_F_OLDVALUE) {
+				if ((pm->pm_flags & PMC_F_ATTACHED_TO_OWNER) &&
+				    (pm->pm_state == PMC_STATE_RUNNING))
+					error = (*pcd->pcd_read_pmc)(cpu, adjri,
+					    &oldvalue);
+				else
+					oldvalue = pm->pm_gv.pm_savedvalue;
+			}
+			if (prw.pm_flags & PMC_F_NEWVALUE)
+				pm->pm_gv.pm_savedvalue = prw.pm_value;
+
+			mtx_pool_unlock_spin(pmc_mtxpool, pm);
+
+		} else { /* System mode PMCs */
+			cpu = PMC_TO_CPU(pm);
+			ri  = PMC_TO_ROWINDEX(pm);
+			pcd = pmc_ri_to_classdep(md, ri, &adjri);
+
+			if (!pmc_cpu_is_active(cpu)) {
+				error = ENXIO;
+				break;
+			}
+
+			/* move this thread to CPU 'cpu' */
+			pmc_save_cpu_binding(&pb);
+			pmc_select_cpu(cpu);
+
+			critical_enter();
+			/* save old value */
+			if (prw.pm_flags & PMC_F_OLDVALUE)
+				if ((error = (*pcd->pcd_read_pmc)(cpu, adjri,
+					 &oldvalue)))
+					goto error;
+			/* write out new value */
+			if (prw.pm_flags & PMC_F_NEWVALUE)
+				error = (*pcd->pcd_write_pmc)(cpu, adjri,
+				    prw.pm_value);
+		error:
+			critical_exit();
+			pmc_restore_cpu_binding(&pb);
+			if (error)
+				break;
+		}
+
+		pprw = (struct pmc_op_pmcrw *) arg;
+
+#ifdef	DEBUG
+		if (prw.pm_flags & PMC_F_NEWVALUE)
+			PMCDBG(PMC,OPS,2, "rw id=%d new %jx -> old %jx",
+			    ri, prw.pm_value, oldvalue);
+		else if (prw.pm_flags & PMC_F_OLDVALUE)
+			PMCDBG(PMC,OPS,2, "rw id=%d -> old %jx", ri, oldvalue);
+#endif
+
+		/* return old value if requested */
+		if (prw.pm_flags & PMC_F_OLDVALUE)
+			if ((error = copyout(&oldvalue, &pprw->pm_value,
+				 sizeof(prw.pm_value))))
+				break;
+
+	}
+	break;
+
+
+	/*
+	 * Set the sampling rate for a sampling mode PMC and the
+	 * initial count for a counting mode PMC.
+	 */
+
+	case PMC_OP_PMCSETCOUNT:
+	{
+		struct pmc *pm;
+		struct pmc_op_pmcsetcount sc;
+
+		PMC_DOWNGRADE_SX();
+
+		if ((error = copyin(arg, &sc, sizeof(sc))) != 0)
+			break;
+
+		if ((error = pmc_find_pmc(sc.pm_pmcid, &pm)) != 0)
+			break;
+
+		if (pm->pm_state == PMC_STATE_RUNNING) {
+			error = EBUSY;
+			break;
+		}
+
+		if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
+			pm->pm_sc.pm_reloadcount = sc.pm_count;
+		else
+			pm->pm_sc.pm_initial = sc.pm_count;
+	}
+	break;
+
+
+	/*
+	 * Start a PMC.
+	 */
+
+	case PMC_OP_PMCSTART:
+	{
+		pmc_id_t pmcid;
+		struct pmc *pm;
+		struct pmc_op_simple sp;
+
+		sx_assert(&pmc_sx, SX_XLOCKED);
+
+		if ((error = copyin(arg, &sp, sizeof(sp))) != 0)
+			break;
+
+		pmcid = sp.pm_pmcid;
+
+		if ((error = pmc_find_pmc(pmcid, &pm)) != 0)
+			break;
+
+		KASSERT(pmcid == pm->pm_id,
+		    ("[pmc,%d] pmcid %x != id %x", __LINE__,
+			pm->pm_id, pmcid));
+
+		if (pm->pm_state == PMC_STATE_RUNNING) /* already running */
+			break;
+		else if (pm->pm_state != PMC_STATE_STOPPED &&
+		    pm->pm_state != PMC_STATE_ALLOCATED) {
+			error = EINVAL;
+			break;
+		}
+
+		error = pmc_start(pm);
+	}
+	break;
+
+
+	/*
+	 * Stop a PMC.
+	 */
+
+	case PMC_OP_PMCSTOP:
+	{
+		pmc_id_t pmcid;
+		struct pmc *pm;
+		struct pmc_op_simple sp;
+
+		PMC_DOWNGRADE_SX();
+
+		if ((error = copyin(arg, &sp, sizeof(sp))) != 0)
+			break;
+
+		pmcid = sp.pm_pmcid;
+
+		/*
+		 * Mark the PMC as inactive and invoke the MD stop
+		 * routines if needed.
+		 */
+
+		if ((error = pmc_find_pmc(pmcid, &pm)) != 0)
+			break;
+
+		KASSERT(pmcid == pm->pm_id,
+		    ("[pmc,%d] pmc id %x != pmcid %x", __LINE__,
+			pm->pm_id, pmcid));
+
+		if (pm->pm_state == PMC_STATE_STOPPED) /* already stopped */
+			break;
+		else if (pm->pm_state != PMC_STATE_RUNNING) {
+			error = EINVAL;
+			break;
+		}
+
+		error = pmc_stop(pm);
+	}
+	break;
+
+
+	/*
+	 * Write a user supplied value to the log file.
+	 */
+
+	case PMC_OP_WRITELOG:
+	{
+		struct pmc_op_writelog wl;
+		struct pmc_owner *po;
+
+		PMC_DOWNGRADE_SX();
+
+		if ((error = copyin(arg, &wl, sizeof(wl))) != 0)
+			break;
+
+		if ((po = pmc_find_owner_descriptor(td->td_proc)) == NULL) {
+			error = EINVAL;
+			break;
+		}
+
+		if ((po->po_flags & PMC_PO_OWNS_LOGFILE) == 0) {
+			error = EINVAL;
+			break;
+		}
+
+		error = pmclog_process_userlog(po, &wl);
+	}
+	break;
+
+
+	default:
+		error = EINVAL;
+		break;
+	}
+
+	if (is_sx_locked != 0) {
+		if (is_sx_downgraded)
+			sx_sunlock(&pmc_sx);
+		else
+			sx_xunlock(&pmc_sx);
+	}
+
+	if (error)
+		atomic_add_int(&pmc_stats.pm_syscall_errors, 1);
+
+	PICKUP_GIANT();
+
+	return error;
+}
+
+/*
+ * Helper functions
+ */
+
+
+/*
+ * Mark the thread as needing callchain capture and post an AST.  The
+ * actual callchain capture will be done in a context where it is safe
+ * to take page faults.
+ */
+
+static void
+pmc_post_callchain_callback(void)
+{
+	struct thread *td;
+
+	td = curthread;
+
+	/*
+	 * If there is multiple PMCs for the same interrupt ignore new post
+	 */
+	if (td->td_pflags & TDP_CALLCHAIN)
+		return;
+
+	/*
+	 * Mark this thread as needing callchain capture.
+	 * `td->td_pflags' will be safe to touch because this thread
+	 * was in user space when it was interrupted.
+	 */
+	td->td_pflags |= TDP_CALLCHAIN;
+
+	/*
+	 * Don't let this thread migrate between CPUs until callchain
+	 * capture completes.
+	 */
+	sched_pin();
+
+	return;
+}
+
+/*
+ * Interrupt processing.
+ *
+ * Find a free slot in the per-cpu array of samples and capture the
+ * current callchain there.  If a sample was successfully added, a bit
+ * is set in mask 'pmc_cpumask' denoting that the DO_SAMPLES hook
+ * needs to be invoked from the clock handler.
+ *
+ * This function is meant to be called from an NMI handler.  It cannot
+ * use any of the locking primitives supplied by the OS.
+ */
+
+int
+pmc_process_interrupt(int cpu, struct pmc *pm, struct trapframe *tf,
+    int inuserspace)
+{
+	int error, callchaindepth;
+	struct thread *td;
+	struct pmc_sample *ps;
+	struct pmc_samplebuffer *psb;
+
+	error = 0;
+
+	/*
+	 * Allocate space for a sample buffer.
+	 */
+	psb = pmc_pcpu[cpu]->pc_sb;
+
+	ps = psb->ps_write;
+	if (ps->ps_nsamples) {	/* in use, reader hasn't caught up */
+		pm->pm_stalled = 1;
+		atomic_add_int(&pmc_stats.pm_intr_bufferfull, 1);
+		PMCDBG(SAM,INT,1,"(spc) cpu=%d pm=%p tf=%p um=%d wr=%d rd=%d",
+		    cpu, pm, (void *) tf, inuserspace,
+		    (int) (psb->ps_write - psb->ps_samples),
+		    (int) (psb->ps_read - psb->ps_samples));
+		error = ENOMEM;
+		goto done;
+	}
+
+
+	/* Fill in entry. */
+	PMCDBG(SAM,INT,1,"cpu=%d pm=%p tf=%p um=%d wr=%d rd=%d", cpu, pm,
+	    (void *) tf, inuserspace,
+	    (int) (psb->ps_write - psb->ps_samples),
+	    (int) (psb->ps_read - psb->ps_samples));
+
+	KASSERT(pm->pm_runcount >= 0,
+	    ("[pmc,%d] pm=%p runcount %d", __LINE__, (void *) pm,
+		pm->pm_runcount));
+
+	atomic_add_rel_int(&pm->pm_runcount, 1);	/* hold onto PMC */
+	ps->ps_pmc = pm;
+	if ((td = curthread) && td->td_proc)
+		ps->ps_pid = td->td_proc->p_pid;
+	else
+		ps->ps_pid = -1;
+	ps->ps_cpu = cpu;
+	ps->ps_td = td;
+	ps->ps_flags = inuserspace ? PMC_CC_F_USERSPACE : 0;
+
+	callchaindepth = (pm->pm_flags & PMC_F_CALLCHAIN) ?
+	    pmc_callchaindepth : 1;
+
+	if (callchaindepth == 1)
+		ps->ps_pc[0] = PMC_TRAPFRAME_TO_PC(tf);
+	else {
+		/*
+		 * Kernel stack traversals can be done immediately,
+		 * while we defer to an AST for user space traversals.
+		 */
+		if (!inuserspace)
+			callchaindepth =
+			    pmc_save_kernel_callchain(ps->ps_pc,
+				callchaindepth, tf);
+		else {
+			pmc_post_callchain_callback();
+			callchaindepth = PMC_SAMPLE_INUSE;
+		}
+	}
+
+	ps->ps_nsamples = callchaindepth;	/* mark entry as in use */
+
+	/* increment write pointer, modulo ring buffer size */
+	ps++;
+	if (ps == psb->ps_fence)
+		psb->ps_write = psb->ps_samples;
+	else
+		psb->ps_write = ps;
+
+ done:
+	/* mark CPU as needing processing */
+	atomic_set_int(&pmc_cpumask, (1 << cpu));
+
+	return (error);
+}
+
+/*
+ * Capture a user call chain.  This function will be called from ast()
+ * before control returns to userland and before the process gets
+ * rescheduled.
+ */
+
+static void
+pmc_capture_user_callchain(int cpu, struct trapframe *tf)
+{
+	int i;
+	struct pmc *pm;
+	struct thread *td;
+	struct pmc_sample *ps;
+	struct pmc_samplebuffer *psb;
+#ifdef	INVARIANTS
+	int ncallchains;
+#endif
+
+	sched_unpin();	/* Can migrate safely now. */
+
+	psb = pmc_pcpu[cpu]->pc_sb;
+	td = curthread;
+
+	KASSERT(td->td_pflags & TDP_CALLCHAIN,
+	    ("[pmc,%d] Retrieving callchain for thread that doesn't want it",
+		__LINE__));
+
+#ifdef	INVARIANTS
+	ncallchains = 0;
+#endif
+
+	/*
+	 * Iterate through all deferred callchain requests.
+	 */
+
+	ps = psb->ps_samples;
+	for (i = 0; i < pmc_nsamples; i++, ps++) {
+
+		if (ps->ps_nsamples != PMC_SAMPLE_INUSE)
+			continue;
+		if (ps->ps_td != td)
+			continue;
+
+		KASSERT(ps->ps_cpu == cpu,
+		    ("[pmc,%d] cpu mismatch ps_cpu=%d pcpu=%d", __LINE__,
+			ps->ps_cpu, PCPU_GET(cpuid)));
+
+		pm = ps->ps_pmc;
+
+		KASSERT(pm->pm_flags & PMC_F_CALLCHAIN,
+		    ("[pmc,%d] Retrieving callchain for PMC that doesn't "
+			"want it", __LINE__));
+
+		KASSERT(pm->pm_runcount > 0,
+		    ("[pmc,%d] runcount %d", __LINE__, pm->pm_runcount));
+
+		/*
+		 * Retrieve the callchain and mark the sample buffer
+		 * as 'processable' by the timer tick sweep code.
+		 */
+		ps->ps_nsamples = pmc_save_user_callchain(ps->ps_pc,
+		    pmc_callchaindepth, tf);
+
+#ifdef	INVARIANTS
+		ncallchains++;
+#endif
+
+	}
+
+	KASSERT(ncallchains > 0,
+	    ("[pmc,%d] cpu %d didn't find a sample to collect", __LINE__,
+		cpu));
+
+	return;
+}
+
+
+/*
+ * Process saved PC samples.
+ */
+
+static void
+pmc_process_samples(int cpu)
+{
+	struct pmc *pm;
+	int adjri, n;
+	struct thread *td;
+	struct pmc_owner *po;
+	struct pmc_sample *ps;
+	struct pmc_classdep *pcd;
+	struct pmc_samplebuffer *psb;
+
+	KASSERT(PCPU_GET(cpuid) == cpu,
+	    ("[pmc,%d] not on the correct CPU pcpu=%d cpu=%d", __LINE__,
+		PCPU_GET(cpuid), cpu));
+
+	psb = pmc_pcpu[cpu]->pc_sb;
+
+	for (n = 0; n < pmc_nsamples; n++) { /* bound on #iterations */
+
+		ps = psb->ps_read;
+		if (ps->ps_nsamples == PMC_SAMPLE_FREE)
+			break;
+		if (ps->ps_nsamples == PMC_SAMPLE_INUSE) {
+			/* Need a rescan at a later time. */
+			atomic_set_int(&pmc_cpumask, (1 << cpu));
+			break;
+		}
+
+		pm = ps->ps_pmc;
+
+		KASSERT(pm->pm_runcount > 0,
+		    ("[pmc,%d] pm=%p runcount %d", __LINE__, (void *) pm,
+			pm->pm_runcount));
+
+		po = pm->pm_owner;
+
+		KASSERT(PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)),
+		    ("[pmc,%d] pmc=%p non-sampling mode=%d", __LINE__,
+			pm, PMC_TO_MODE(pm)));
+
+		/* Ignore PMCs that have been switched off */
+		if (pm->pm_state != PMC_STATE_RUNNING)
+			goto entrydone;
+
+		PMCDBG(SAM,OPS,1,"cpu=%d pm=%p n=%d fl=%x wr=%d rd=%d", cpu,
+		    pm, ps->ps_nsamples, ps->ps_flags,
+		    (int) (psb->ps_write - psb->ps_samples),
+		    (int) (psb->ps_read - psb->ps_samples));
+
+		/*
+		 * If this is a process-mode PMC that is attached to
+		 * its owner, and if the PC is in user mode, update
+		 * profiling statistics like timer-based profiling
+		 * would have done.
+		 */
+		if (pm->pm_flags & PMC_F_ATTACHED_TO_OWNER) {
+			if (ps->ps_flags & PMC_CC_F_USERSPACE) {
+				td = FIRST_THREAD_IN_PROC(po->po_owner);
+				addupc_intr(td, ps->ps_pc[0], 1);
+			}
+			goto entrydone;
+		}
+
+		/*
+		 * Otherwise, this is either a sampling mode PMC that
+		 * is attached to a different process than its owner,
+		 * or a system-wide sampling PMC.  Dispatch a log
+		 * entry to the PMC's owner process.
+		 */
+
+		pmclog_process_callchain(pm, ps);
+
+	entrydone:
+		ps->ps_nsamples = 0;	/* mark entry as free */
+		atomic_subtract_rel_int(&pm->pm_runcount, 1);
+
+		/* increment read pointer, modulo sample size */
+		if (++ps == psb->ps_fence)
+			psb->ps_read = psb->ps_samples;
+		else
+			psb->ps_read = ps;
+	}
+
+	atomic_add_int(&pmc_stats.pm_log_sweeps, 1);
+
+	/* Do not re-enable stalled PMCs if we failed to process any samples */
+	if (n == 0)
+		return;
+
+	/*
+	 * Restart any stalled sampling PMCs on this CPU.
+	 *
+	 * If the NMI handler sets the pm_stalled field of a PMC after
+	 * the check below, we'll end up processing the stalled PMC at
+	 * the next hardclock tick.
+	 */
+	for (n = 0; n < md->pmd_npmc; n++) {
+		pcd = pmc_ri_to_classdep(md, n, &adjri);
+		KASSERT(pcd != NULL,
+		    ("[pmc,%d] null pcd ri=%d", __LINE__, n));
+		(void) (*pcd->pcd_get_config)(cpu,adjri,&pm);
+
+		if (pm == NULL ||			 /* !cfg'ed */
+		    pm->pm_state != PMC_STATE_RUNNING || /* !active */
+		    !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)) || /* !sampling */
+		    pm->pm_stalled == 0) /* !stalled */
+			continue;
+
+		pm->pm_stalled = 0;
+		(*pcd->pcd_start_pmc)(cpu, adjri);
+	}
+}
+
+/*
+ * Event handlers.
+ */
+
+/*
+ * Handle a process exit.
+ *
+ * Remove this process from all hash tables.  If this process
+ * owned any PMCs, turn off those PMCs and deallocate them,
+ * removing any associations with target processes.
+ *
+ * This function will be called by the last 'thread' of a
+ * process.
+ *
+ * XXX This eventhandler gets called early in the exit process.
+ * Consider using a 'hook' invocation from thread_exit() or equivalent
+ * spot.  Another negative is that kse_exit doesn't seem to call
+ * exit1() [??].
+ *
+ */
+
+static void
+pmc_process_exit(void *arg __unused, struct proc *p)
+{
+	struct pmc *pm;
+	int adjri, cpu;
+	unsigned int ri;
+	int is_using_hwpmcs;
+	struct pmc_owner *po;
+	struct pmc_process *pp;
+	struct pmc_classdep *pcd;
+	pmc_value_t newvalue, tmp;
+
+	PROC_LOCK(p);
+	is_using_hwpmcs = p->p_flag & P_HWPMC;
+	PROC_UNLOCK(p);
+
+	/*
+	 * Log a sysexit event to all SS PMC owners.
+	 */
+	LIST_FOREACH(po, &pmc_ss_owners, po_ssnext)
+	    if (po->po_flags & PMC_PO_OWNS_LOGFILE)
+		    pmclog_process_sysexit(po, p->p_pid);
+
+	if (!is_using_hwpmcs)
+		return;
+
+	PMC_GET_SX_XLOCK();
+	PMCDBG(PRC,EXT,1,"process-exit proc=%p (%d, %s)", p, p->p_pid,
+	    p->p_comm);
+
+	/*
+	 * Since this code is invoked by the last thread in an exiting
+	 * process, we would have context switched IN at some prior
+	 * point.  However, with PREEMPTION, kernel mode context
+	 * switches may happen any time, so we want to disable a
+	 * context switch OUT till we get any PMCs targetting this
+	 * process off the hardware.
+	 *
+	 * We also need to atomically remove this process'
+	 * entry from our target process hash table, using
+	 * PMC_FLAG_REMOVE.
+	 */
+	PMCDBG(PRC,EXT,1, "process-exit proc=%p (%d, %s)", p, p->p_pid,
+	    p->p_comm);
+
+	critical_enter(); /* no preemption */
+
+	cpu = curthread->td_oncpu;
+
+	if ((pp = pmc_find_process_descriptor(p,
+		 PMC_FLAG_REMOVE)) != NULL) {
+
+		PMCDBG(PRC,EXT,2,
+		    "process-exit proc=%p pmc-process=%p", p, pp);
+
+		/*
+		 * The exiting process could the target of
+		 * some PMCs which will be running on
+		 * currently executing CPU.
+		 *
+		 * We need to turn these PMCs off like we
+		 * would do at context switch OUT time.
+		 */
+		for (ri = 0; ri < md->pmd_npmc; ri++) {
+
+			/*
+			 * Pick up the pmc pointer from hardware
+			 * state similar to the CSW_OUT code.
+			 */
+			pm = NULL;
+
+			pcd = pmc_ri_to_classdep(md, ri, &adjri);
+
+			(void) (*pcd->pcd_get_config)(cpu, adjri, &pm);
+
+			PMCDBG(PRC,EXT,2, "ri=%d pm=%p", ri, pm);
+
+			if (pm == NULL ||
+			    !PMC_IS_VIRTUAL_MODE(PMC_TO_MODE(pm)))
+				continue;
+
+			PMCDBG(PRC,EXT,2, "ppmcs[%d]=%p pm=%p "
+			    "state=%d", ri, pp->pp_pmcs[ri].pp_pmc,
+			    pm, pm->pm_state);
+
+			KASSERT(PMC_TO_ROWINDEX(pm) == ri,
+			    ("[pmc,%d] ri mismatch pmc(%d) ri(%d)",
+				__LINE__, PMC_TO_ROWINDEX(pm), ri));
+
+			KASSERT(pm == pp->pp_pmcs[ri].pp_pmc,
+			    ("[pmc,%d] pm %p != pp_pmcs[%d] %p",
+				__LINE__, pm, ri, pp->pp_pmcs[ri].pp_pmc));
+
+			(void) pcd->pcd_stop_pmc(cpu, adjri);
+
+			KASSERT(pm->pm_runcount > 0,
+			    ("[pmc,%d] bad runcount ri %d rc %d",
+				__LINE__, ri, pm->pm_runcount));
+
+			/* Stop hardware only if it is actually running */
+			if (pm->pm_state == PMC_STATE_RUNNING &&
+			    pm->pm_stalled == 0) {
+				pcd->pcd_read_pmc(cpu, adjri, &newvalue);
+				tmp = newvalue -
+				    PMC_PCPU_SAVED(cpu,ri);
+
+				mtx_pool_lock_spin(pmc_mtxpool, pm);
+				pm->pm_gv.pm_savedvalue += tmp;
+				pp->pp_pmcs[ri].pp_pmcval += tmp;
+				mtx_pool_unlock_spin(pmc_mtxpool, pm);
+			}
+
+			atomic_subtract_rel_int(&pm->pm_runcount,1);
+
+			KASSERT((int) pm->pm_runcount >= 0,
+			    ("[pmc,%d] runcount is %d", __LINE__, ri));
+
+			(void) pcd->pcd_config_pmc(cpu, adjri, NULL);
+		}
+
+		/*
+		 * Inform the MD layer of this pseudo "context switch
+		 * out"
+		 */
+		(void) md->pmd_switch_out(pmc_pcpu[cpu], pp);
+
+		critical_exit(); /* ok to be pre-empted now */
+
+		/*
+		 * Unlink this process from the PMCs that are
+		 * targetting it.  This will send a signal to
+		 * all PMC owner's whose PMCs are orphaned.
+		 *
+		 * Log PMC value at exit time if requested.
+		 */
+		for (ri = 0; ri < md->pmd_npmc; ri++)
+			if ((pm = pp->pp_pmcs[ri].pp_pmc) != NULL) {
+				if (pm->pm_flags & PMC_F_NEEDS_LOGFILE &&
+				    PMC_IS_COUNTING_MODE(PMC_TO_MODE(pm)))
+					pmclog_process_procexit(pm, pp);
+				pmc_unlink_target_process(pm, pp);
+			}
+		free(pp, M_PMC);
+
+	} else
+		critical_exit(); /* pp == NULL */
+
+
+	/*
+	 * If the process owned PMCs, free them up and free up
+	 * memory.
+	 */
+	if ((po = pmc_find_owner_descriptor(p)) != NULL) {
+		pmc_remove_owner(po);
+		pmc_destroy_owner_descriptor(po);
+	}
+
+	sx_xunlock(&pmc_sx);
+}
+
+/*
+ * Handle a process fork.
+ *
+ * If the parent process 'p1' is under HWPMC monitoring, then copy
+ * over any attached PMCs that have 'do_descendants' semantics.
+ */
+
+static void
+pmc_process_fork(void *arg __unused, struct proc *p1, struct proc *newproc,
+    int flags)
+{
+	int is_using_hwpmcs;
+	unsigned int ri;
+	uint32_t do_descendants;
+	struct pmc *pm;
+	struct pmc_owner *po;
+	struct pmc_process *ppnew, *ppold;
+
+	(void) flags;		/* unused parameter */
+
+	PROC_LOCK(p1);
+	is_using_hwpmcs = p1->p_flag & P_HWPMC;
+	PROC_UNLOCK(p1);
+
+	/*
+	 * If there are system-wide sampling PMCs active, we need to
+	 * log all fork events to their owner's logs.
+	 */
+
+	LIST_FOREACH(po, &pmc_ss_owners, po_ssnext)
+	    if (po->po_flags & PMC_PO_OWNS_LOGFILE)
+		    pmclog_process_procfork(po, p1->p_pid, newproc->p_pid);
+
+	if (!is_using_hwpmcs)
+		return;
+
+	PMC_GET_SX_XLOCK();
+	PMCDBG(PMC,FRK,1, "process-fork proc=%p (%d, %s) -> %p", p1,
+	    p1->p_pid, p1->p_comm, newproc);
+
+	/*
+	 * If the parent process (curthread->td_proc) is a
+	 * target of any PMCs, look for PMCs that are to be
+	 * inherited, and link these into the new process
+	 * descriptor.
+	 */
+	if ((ppold = pmc_find_process_descriptor(curthread->td_proc,
+		 PMC_FLAG_NONE)) == NULL)
+		goto done;		/* nothing to do */
+
+	do_descendants = 0;
+	for (ri = 0; ri < md->pmd_npmc; ri++)
+		if ((pm = ppold->pp_pmcs[ri].pp_pmc) != NULL)
+			do_descendants |= pm->pm_flags & PMC_F_DESCENDANTS;
+	if (do_descendants == 0) /* nothing to do */
+		goto done;
+
+	/* allocate a descriptor for the new process  */
+	if ((ppnew = pmc_find_process_descriptor(newproc,
+		 PMC_FLAG_ALLOCATE)) == NULL)
+		goto done;
+
+	/*
+	 * Run through all PMCs that were targeting the old process
+	 * and which specified F_DESCENDANTS and attach them to the
+	 * new process.
+	 *
+	 * Log the fork event to all owners of PMCs attached to this
+	 * process, if not already logged.
+	 */
+	for (ri = 0; ri < md->pmd_npmc; ri++)
+		if ((pm = ppold->pp_pmcs[ri].pp_pmc) != NULL &&
+		    (pm->pm_flags & PMC_F_DESCENDANTS)) {
+			pmc_link_target_process(pm, ppnew);
+			po = pm->pm_owner;
+			if (po->po_sscount == 0 &&
+			    po->po_flags & PMC_PO_OWNS_LOGFILE)
+				pmclog_process_procfork(po, p1->p_pid,
+				    newproc->p_pid);
+		}
+
+	/*
+	 * Now mark the new process as being tracked by this driver.
+	 */
+	PROC_LOCK(newproc);
+	newproc->p_flag |= P_HWPMC;
+	PROC_UNLOCK(newproc);
+
+ done:
+	sx_xunlock(&pmc_sx);
+}
+
+
+/*
+ * initialization
+ */
+
+static const char *pmc_name_of_pmcclass[] = {
+#undef	__PMC_CLASS
+#define	__PMC_CLASS(N) #N ,
+	__PMC_CLASSES()
+};
+
+static int
+pmc_initialize(void)
+{
+	int c, cpu, error, n, ri;
+	unsigned int maxcpu;
+	struct pmc_binding pb;
+	struct pmc_sample *ps;
+	struct pmc_classdep *pcd;
+	struct pmc_samplebuffer *sb;
+
+	md = NULL;
+	error = 0;
+
+#ifdef	DEBUG
+	/* parse debug flags first */
+	if (TUNABLE_STR_FETCH(PMC_SYSCTL_NAME_PREFIX "debugflags",
+		pmc_debugstr, sizeof(pmc_debugstr)))
+		pmc_debugflags_parse(pmc_debugstr,
+		    pmc_debugstr+strlen(pmc_debugstr));
+#endif
+
+	PMCDBG(MOD,INI,0, "PMC Initialize (version %x)", PMC_VERSION);
+
+	/* check kernel version */
+	if (pmc_kernel_version != PMC_VERSION) {
+		if (pmc_kernel_version == 0)
+			printf("hwpmc: this kernel has not been compiled with "
+			    "'options HWPMC_HOOKS'.\n");
+		else
+			printf("hwpmc: kernel version (0x%x) does not match "
+			    "module version (0x%x).\n", pmc_kernel_version,
+			    PMC_VERSION);
+		return EPROGMISMATCH;
+	}
+
+	/*
+	 * check sysctl parameters
+	 */
+
+	if (pmc_hashsize <= 0) {
+		(void) printf("hwpmc: tunable \"hashsize\"=%d must be "
+		    "greater than zero.\n", pmc_hashsize);
+		pmc_hashsize = PMC_HASH_SIZE;
+	}
+
+	if (pmc_nsamples <= 0 || pmc_nsamples > 65535) {
+		(void) printf("hwpmc: tunable \"nsamples\"=%d out of "
+		    "range.\n", pmc_nsamples);
+		pmc_nsamples = PMC_NSAMPLES;
+	}
+
+	if (pmc_callchaindepth <= 0 ||
+	    pmc_callchaindepth > PMC_CALLCHAIN_DEPTH_MAX) {
+		(void) printf("hwpmc: tunable \"callchaindepth\"=%d out of "
+		    "range.\n", pmc_callchaindepth);
+		pmc_callchaindepth = PMC_CALLCHAIN_DEPTH;
+	}
+
+	md = pmc_md_initialize();
+
+	if (md == NULL)
+		return (ENOSYS);
+
+	KASSERT(md->pmd_nclass >= 1 && md->pmd_npmc >= 1,
+	    ("[pmc,%d] no classes or pmcs", __LINE__));
+
+	/* Compute the map from row-indices to classdep pointers. */
+	pmc_rowindex_to_classdep = malloc(sizeof(struct pmc_classdep *) *
+	    md->pmd_npmc, M_PMC, M_WAITOK|M_ZERO);
+
+	for (n = 0; n < md->pmd_npmc; n++)
+		pmc_rowindex_to_classdep[n] = NULL;
+	for (ri = c = 0; c < md->pmd_nclass; c++) {
+		pcd = &md->pmd_classdep[c];
+		for (n = 0; n < pcd->pcd_num; n++, ri++)
+			pmc_rowindex_to_classdep[ri] = pcd;
+	}
+
+	KASSERT(ri == md->pmd_npmc,
+	    ("[pmc,%d] npmc miscomputed: ri=%d, md->npmc=%d", __LINE__,
+	    ri, md->pmd_npmc));
+
+	maxcpu = pmc_cpu_max();
+
+	/* allocate space for the per-cpu array */
+	pmc_pcpu = malloc(maxcpu * sizeof(struct pmc_cpu *), M_PMC,
+	    M_WAITOK|M_ZERO);
+
+	/* per-cpu 'saved values' for managing process-mode PMCs */
+	pmc_pcpu_saved = malloc(sizeof(pmc_value_t) * maxcpu * md->pmd_npmc,
+	    M_PMC, M_WAITOK);
+
+	/* Perform CPU-dependent initialization. */
+	pmc_save_cpu_binding(&pb);
+	error = 0;
+	for (cpu = 0; error == 0 && cpu < maxcpu; cpu++) {
+		if (!pmc_cpu_is_active(cpu))
+			continue;
+		pmc_select_cpu(cpu);
+		pmc_pcpu[cpu] = malloc(sizeof(struct pmc_cpu) +
+		    md->pmd_npmc * sizeof(struct pmc_hw *), M_PMC,
+		    M_WAITOK|M_ZERO);
+		if (md->pmd_pcpu_init)
+			error = md->pmd_pcpu_init(md, cpu);
+		for (n = 0; error == 0 && n < md->pmd_nclass; n++)
+			error = md->pmd_classdep[n].pcd_pcpu_init(md, cpu);
+	}
+	pmc_restore_cpu_binding(&pb);
+
+	if (error)
+		return (error);
+
+	/* allocate space for the sample array */
+	for (cpu = 0; cpu < maxcpu; cpu++) {
+		if (!pmc_cpu_is_active(cpu))
+			continue;
+
+		sb = malloc(sizeof(struct pmc_samplebuffer) +
+		    pmc_nsamples * sizeof(struct pmc_sample), M_PMC,
+		    M_WAITOK|M_ZERO);
+		sb->ps_read = sb->ps_write = sb->ps_samples;
+		sb->ps_fence = sb->ps_samples + pmc_nsamples;
+
+		KASSERT(pmc_pcpu[cpu] != NULL,
+		    ("[pmc,%d] cpu=%d Null per-cpu data", __LINE__, cpu));
+
+		sb->ps_callchains = malloc(pmc_callchaindepth * pmc_nsamples *
+		    sizeof(uintptr_t), M_PMC, M_WAITOK|M_ZERO);
+
+		for (n = 0, ps = sb->ps_samples; n < pmc_nsamples; n++, ps++)
+			ps->ps_pc = sb->ps_callchains +
+			    (n * pmc_callchaindepth);
+
+		pmc_pcpu[cpu]->pc_sb = sb;
+	}
+
+	/* allocate space for the row disposition array */
+	pmc_pmcdisp = malloc(sizeof(enum pmc_mode) * md->pmd_npmc,
+	    M_PMC, M_WAITOK|M_ZERO);
+
+	KASSERT(pmc_pmcdisp != NULL,
+	    ("[pmc,%d] pmcdisp allocation returned NULL", __LINE__));
+
+	/* mark all PMCs as available */
+	for (n = 0; n < (int) md->pmd_npmc; n++)
+		PMC_MARK_ROW_FREE(n);
+
+	/* allocate thread hash tables */
+	pmc_ownerhash = hashinit(pmc_hashsize, M_PMC,
+	    &pmc_ownerhashmask);
+
+	pmc_processhash = hashinit(pmc_hashsize, M_PMC,
+	    &pmc_processhashmask);
+	mtx_init(&pmc_processhash_mtx, "pmc-process-hash", "pmc-leaf",
+	    MTX_SPIN);
+
+	LIST_INIT(&pmc_ss_owners);
+	pmc_ss_count = 0;
+
+	/* allocate a pool of spin mutexes */
+	pmc_mtxpool = mtx_pool_create("pmc-leaf", pmc_mtxpool_size,
+	    MTX_SPIN);
+
+	PMCDBG(MOD,INI,1, "pmc_ownerhash=%p, mask=0x%lx "
+	    "targethash=%p mask=0x%lx", pmc_ownerhash, pmc_ownerhashmask,
+	    pmc_processhash, pmc_processhashmask);
+
+	/* register process {exit,fork,exec} handlers */
+	pmc_exit_tag = EVENTHANDLER_REGISTER(process_exit,
+	    pmc_process_exit, NULL, EVENTHANDLER_PRI_ANY);
+	pmc_fork_tag = EVENTHANDLER_REGISTER(process_fork,
+	    pmc_process_fork, NULL, EVENTHANDLER_PRI_ANY);
+
+	/* initialize logging */
+	pmclog_initialize();
+
+	/* set hook functions */
+	pmc_intr = md->pmd_intr;
+	pmc_hook = pmc_hook_handler;
+
+	if (error == 0) {
+		printf(PMC_MODULE_NAME ":");
+		for (n = 0; n < (int) md->pmd_nclass; n++) {
+			pcd = &md->pmd_classdep[n];
+			printf(" %s/%d/%d/0x%b",
+			    pmc_name_of_pmcclass[pcd->pcd_class],
+			    pcd->pcd_num,
+			    pcd->pcd_width,
+			    pcd->pcd_caps,
+			    "\20"
+			    "\1INT\2USR\3SYS\4EDG\5THR"
+			    "\6REA\7WRI\10INV\11QUA\12PRC"
+			    "\13TAG\14CSC");
+		}
+		printf("\n");
+	}
+
+	return (error);
+}
+
+/* prepare to be unloaded */
+static void
+pmc_cleanup(void)
+{
+	int c, cpu;
+	unsigned int maxcpu;
+	struct pmc_ownerhash *ph;
+	struct pmc_owner *po, *tmp;
+	struct pmc_binding pb;
+#ifdef	DEBUG
+	struct pmc_processhash *prh;
+#endif
+
+	PMCDBG(MOD,INI,0, "%s", "cleanup");
+
+	/* switch off sampling */
+	pmc_cpumask = 0;
+	pmc_intr = NULL;
+
+	sx_xlock(&pmc_sx);
+	if (pmc_hook == NULL) {	/* being unloaded already */
+		sx_xunlock(&pmc_sx);
+		return;
+	}
+
+	pmc_hook = NULL; /* prevent new threads from entering module */
+
+	/* deregister event handlers */
+	EVENTHANDLER_DEREGISTER(process_fork, pmc_fork_tag);
+	EVENTHANDLER_DEREGISTER(process_exit, pmc_exit_tag);
+
+	/* send SIGBUS to all owner threads, free up allocations */
+	if (pmc_ownerhash)
+		for (ph = pmc_ownerhash;
+		     ph <= &pmc_ownerhash[pmc_ownerhashmask];
+		     ph++) {
+			LIST_FOREACH_SAFE(po, ph, po_next, tmp) {
+				pmc_remove_owner(po);
+
+				/* send SIGBUS to owner processes */
+				PMCDBG(MOD,INI,2, "cleanup signal proc=%p "
+				    "(%d, %s)", po->po_owner,
+				    po->po_owner->p_pid,
+				    po->po_owner->p_comm);
+
+				PROC_LOCK(po->po_owner);
+				psignal(po->po_owner, SIGBUS);
+				PROC_UNLOCK(po->po_owner);
+
+				pmc_destroy_owner_descriptor(po);
+			}
+		}
+
+	/* reclaim allocated data structures */
+	if (pmc_mtxpool)
+		mtx_pool_destroy(&pmc_mtxpool);
+
+	mtx_destroy(&pmc_processhash_mtx);
+	if (pmc_processhash) {
+#ifdef	DEBUG
+		struct pmc_process *pp;
+
+		PMCDBG(MOD,INI,3, "%s", "destroy process hash");
+		for (prh = pmc_processhash;
+		     prh <= &pmc_processhash[pmc_processhashmask];
+		     prh++)
+			LIST_FOREACH(pp, prh, pp_next)
+			    PMCDBG(MOD,INI,3, "pid=%d", pp->pp_proc->p_pid);
+#endif
+
+		hashdestroy(pmc_processhash, M_PMC, pmc_processhashmask);
+		pmc_processhash = NULL;
+	}
+
+	if (pmc_ownerhash) {
+		PMCDBG(MOD,INI,3, "%s", "destroy owner hash");
+		hashdestroy(pmc_ownerhash, M_PMC, pmc_ownerhashmask);
+		pmc_ownerhash = NULL;
+	}
+
+	KASSERT(LIST_EMPTY(&pmc_ss_owners),
+	    ("[pmc,%d] Global SS owner list not empty", __LINE__));
+	KASSERT(pmc_ss_count == 0,
+	    ("[pmc,%d] Global SS count not empty", __LINE__));
+
+	/* do processor and pmc-class dependent cleanup */
+	maxcpu = pmc_cpu_max();
+
+	PMCDBG(MOD,INI,3, "%s", "md cleanup");
+	if (md) {
+		pmc_save_cpu_binding(&pb);
+		for (cpu = 0; cpu < maxcpu; cpu++) {
+			PMCDBG(MOD,INI,1,"pmc-cleanup cpu=%d pcs=%p",
+			    cpu, pmc_pcpu[cpu]);
+			if (!pmc_cpu_is_active(cpu) || pmc_pcpu[cpu] == NULL)
+				continue;
+			pmc_select_cpu(cpu);
+			for (c = 0; c < md->pmd_nclass; c++)
+				md->pmd_classdep[c].pcd_pcpu_fini(md, cpu);
+			if (md->pmd_pcpu_fini)
+				md->pmd_pcpu_fini(md, cpu);
+		}
+
+		pmc_md_finalize(md);
+
+		free(md, M_PMC);
+		md = NULL;
+		pmc_restore_cpu_binding(&pb);
+	}
+
+	/* Free per-cpu descriptors. */
+	for (cpu = 0; cpu < maxcpu; cpu++) {
+		if (!pmc_cpu_is_active(cpu))
+			continue;
+		KASSERT(pmc_pcpu[cpu]->pc_sb != NULL,
+		    ("[pmc,%d] Null cpu sample buffer cpu=%d", __LINE__,
+			cpu));
+		free(pmc_pcpu[cpu]->pc_sb->ps_callchains, M_PMC);
+		free(pmc_pcpu[cpu]->pc_sb, M_PMC);
+		free(pmc_pcpu[cpu], M_PMC);
+	}
+
+	free(pmc_pcpu, M_PMC);
+	pmc_pcpu = NULL;
+
+	free(pmc_pcpu_saved, M_PMC);
+	pmc_pcpu_saved = NULL;
+
+	if (pmc_pmcdisp) {
+		free(pmc_pmcdisp, M_PMC);
+		pmc_pmcdisp = NULL;
+	}
+
+	if (pmc_rowindex_to_classdep) {
+		free(pmc_rowindex_to_classdep, M_PMC);
+		pmc_rowindex_to_classdep = NULL;
+	}
+
+	pmclog_shutdown();
+
+	sx_xunlock(&pmc_sx); 	/* we are done */
+}
+
+/*
+ * The function called at load/unload.
+ */
+
+static int
+load (struct module *module __unused, int cmd, void *arg __unused)
+{
+	int error;
+
+	error = 0;
+
+	switch (cmd) {
+	case MOD_LOAD :
+		/* initialize the subsystem */
+		error = pmc_initialize();
+		if (error != 0)
+			break;
+		PMCDBG(MOD,INI,1, "syscall=%d maxcpu=%d",
+		    pmc_syscall_num, pmc_cpu_max());
+		break;
+
+
+	case MOD_UNLOAD :
+	case MOD_SHUTDOWN:
+		pmc_cleanup();
+		PMCDBG(MOD,INI,1, "%s", "unloaded");
+		break;
+
+	default :
+		error = EINVAL;	/* XXX should panic(9) */
+		break;
+	}
+
+	return error;
+}
+
+/* memory pool */
+MALLOC_DEFINE(M_PMC, "pmc", "Memory space for the PMC module");
diff --git a/sys/dev/misc/hwpmc/hwpmc_pentium.c b/sys/dev/misc/hwpmc/hwpmc_pentium.c
new file mode 100644
index 0000000..ba679ea
--- /dev/null
+++ b/sys/dev/misc/hwpmc/hwpmc_pentium.c
@@ -0,0 +1,57 @@
+/*-
+ * Copyright (c) 2003-2005 Joseph Koshy
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: src/sys/dev/hwpmc/hwpmc_pentium.c,v 1.5 2008/11/09 17:37:54 jkoshy Exp $");
+
+#include <sys/param.h>
+#include <sys/lock.h>
+#include <sys/mutex.h>
+#include <sys/pmc.h>
+#include <sys/pmckern.h>
+#include <sys/smp.h>
+#include <sys/systm.h>
+
+#include <machine/cpufunc.h>
+#include <machine/md_var.h>
+#include <machine/pmc_mdep.h>
+
+/*
+ * Intel Pentium PMCs
+ */
+
+int
+pmc_p5_initialize(struct pmc_mdep *pmc_mdep, int ncpus)
+{
+	(void) pmc_mdep; (void) ncpus;
+	return (ENOSYS);		/* nothing here yet */
+}
+
+void
+pmc_p5_finalize(struct pmc_mdep *pmc_mdep)
+{
+	(void) pmc_mdep;
+}
diff --git a/sys/dev/misc/hwpmc/hwpmc_pentium.h b/sys/dev/misc/hwpmc/hwpmc_pentium.h
new file mode 100644
index 0000000..e395cea
--- /dev/null
+++ b/sys/dev/misc/hwpmc/hwpmc_pentium.h
@@ -0,0 +1,73 @@
+/*-
+ * Copyright (c) 2005, Joseph Koshy
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: src/sys/dev/hwpmc/hwpmc_pentium.h,v 1.2 2008/11/09 17:37:54 jkoshy Exp $
+ */
+
+/* Machine dependent interfaces */
+
+#ifndef _DEV_HWPMC_PENTIUM_H_
+#define	_DEV_HWPMC_PENTIUM_H_ 1
+
+/* Intel Pentium PMCs */
+
+#define	PENTIUM_NPMCS	2
+#define	PENTIUM_CESR_PC1		(1 << 25)
+#define	PENTIUM_CESR_CC1_MASK		0x01C00000
+#define	PENTIUM_CESR_TO_CC1(C)		(((C) & 0x07) << 22)
+#define	PENTIUM_CESR_ES1_MASK		0x003F0000
+#define	PENTIUM_CESR_TO_ES1(E)		(((E) & 0x3F) << 16)
+#define	PENTIUM_CESR_PC0		(1 << 9)
+#define	PENTIUM_CESR_CC0_MASK		0x000001C0
+#define	PENTIUM_CESR_TO_CC0(C)		(((C) & 0x07) << 6)
+#define	PENTIUM_CESR_ES0_MASK		0x0000003F
+#define	PENTIUM_CESR_TO_ES0(E)		((E) & 0x3F)
+#define	PENTIUM_CESR_RESERVED		0xFC00FC00
+
+#define	PENTIUM_MSR_CESR		0x11
+#define	PENTIUM_MSR_CTR0		0x12
+#define	PENTIUM_MSR_CTR1		0x13
+
+struct pmc_md_pentium_op_pmcallocate {
+	uint32_t	pm_pentium_config;
+};
+
+#ifdef _KERNEL
+
+/* MD extension for 'struct pmc' */
+struct pmc_md_pentium_pmc {
+	uint32_t	pm_pentium_cesr;
+};
+
+
+/*
+ * Prototypes
+ */
+
+int	pmc_p5_initialize(struct pmc_mdep *_md, int _ncpus);
+void	pmc_p5_finalize(struct pmc_mdep *_md);
+
+#endif /* _KERNEL */
+#endif /* _DEV_HWPMC_PENTIUM_H_ */
diff --git a/sys/dev/misc/hwpmc/hwpmc_piv.c b/sys/dev/misc/hwpmc/hwpmc_piv.c
new file mode 100644
index 0000000..5d74cdb
--- /dev/null
+++ b/sys/dev/misc/hwpmc/hwpmc_piv.c
@@ -0,0 +1,1698 @@
+/*-
+ * Copyright (c) 2003-2007 Joseph Koshy
+ * Copyright (c) 2007 The FreeBSD Foundation
+ * All rights reserved.
+ *
+ * Portions of this software were developed by A. Joseph Koshy under
+ * sponsorship from the FreeBSD Foundation and Google, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: src/sys/dev/hwpmc/hwpmc_piv.c,v 1.21 2009/08/14 21:05:08 jhb Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/lock.h>
+#include <sys/mutex.h>
+#include <sys/pmc.h>
+#include <sys/pmckern.h>
+#include <sys/smp.h>
+#include <sys/systm.h>
+
+#include <machine/intr_machdep.h>
+#include <machine/apicvar.h>
+#include <machine/cpu.h>
+#include <machine/cpufunc.h>
+#include <machine/cputypes.h>
+#include <machine/md_var.h>
+#include <machine/specialreg.h>
+
+/*
+ * PENTIUM 4 SUPPORT
+ *
+ * The P4 has 18 PMCs, divided into 4 groups with 4,4,4 and 6 PMCs
+ * respectively.  Each PMC comprises of two model specific registers:
+ * a counter configuration control register (CCCR) and a counter
+ * register that holds the actual event counts.
+ *
+ * Configuring an event requires the use of one of 45 event selection
+ * control registers (ESCR).  Events are associated with specific
+ * ESCRs.  Each PMC group has a set of ESCRs it can use.
+ *
+ * - The BPU counter group (4 PMCs) can use the 16 ESCRs:
+ *   BPU_ESCR{0,1}, IS_ESCR{0,1}, MOB_ESCR{0,1}, ITLB_ESCR{0,1},
+ *   PMH_ESCR{0,1}, IX_ESCR{0,1}, FSB_ESCR{0,}, BSU_ESCR{0,1}.
+ *
+ * - The MS counter group (4 PMCs) can use the 6 ESCRs: MS_ESCR{0,1},
+ *   TC_ESCR{0,1}, TBPU_ESCR{0,1}.
+ *
+ * - The FLAME counter group (4 PMCs) can use the 10 ESCRs:
+ *   FLAME_ESCR{0,1}, FIRM_ESCR{0,1}, SAAT_ESCR{0,1}, U2L_ESCR{0,1},
+ *   DAC_ESCR{0,1}.
+ *
+ * - The IQ counter group (6 PMCs) can use the 13 ESCRs: IQ_ESCR{0,1},
+ *   ALF_ESCR{0,1}, RAT_ESCR{0,1}, SSU_ESCR0, CRU_ESCR{0,1,2,3,4,5}.
+ *
+ * Even-numbered ESCRs can be used with counters 0, 1 and 4 (if
+ * present) of a counter group.  Odd-numbers ESCRs can be used with
+ * counters 2, 3 and 5 (if present) of a counter group.  The
+ * 'p4_escrs[]' table describes these restrictions in a form that
+ * function 'p4_allocate()' uses for making allocation decisions.
+ *
+ * SYSTEM-MODE AND THREAD-MODE ALLOCATION
+ *
+ * In addition to remembering the state of PMC rows
+ * ('FREE','STANDALONE', or 'THREAD'), we similar need to track the
+ * state of ESCR rows.  If an ESCR is allocated to a system-mode PMC
+ * on a CPU we cannot allocate this to a thread-mode PMC.  On a
+ * multi-cpu (multiple physical CPUs) system, ESCR allocation on each
+ * CPU is tracked by the pc_escrs[] array.
+ *
+ * Each system-mode PMC that is using an ESCR records its row-index in
+ * the appropriate entry and system-mode allocation attempts check
+ * that an ESCR is available using this array.  Process-mode PMCs do
+ * not use the pc_escrs[] array, since ESCR row itself would have been
+ * marked as in 'THREAD' mode.
+ *
+ * HYPERTHREADING SUPPORT
+ *
+ * When HTT is enabled, the FreeBSD kernel treats the two 'logical'
+ * cpus as independent CPUs and can schedule kernel threads on them
+ * independently.  However, the two logical CPUs share the same set of
+ * PMC resources.  We need to ensure that:
+ * - PMCs that use the PMC_F_DESCENDANTS semantics are handled correctly,
+ *   and,
+ * - Threads of multi-threaded processes that get scheduled on the same
+ *   physical CPU are handled correctly.
+ *
+ * HTT Detection
+ *
+ * Not all HTT capable systems will have HTT enabled.  We detect the
+ * presence of HTT by detecting if 'p4_init()' was called for a secondary
+ * CPU in a HTT pair.
+ *
+ * Note that hwpmc(4) cannot currently deal with a change in HTT status once
+ * loaded.
+ *
+ * Handling HTT READ / WRITE / START / STOP
+ *
+ * PMC resources are shared across the CPUs in an HTT pair.  We
+ * designate the lower numbered CPU in a HTT pair as the 'primary'
+ * CPU.  In each primary CPU's state we keep track of a 'runcount'
+ * which reflects the number of PMC-using processes that have been
+ * scheduled on its secondary CPU.  Process-mode PMC operations will
+ * actually 'start' or 'stop' hardware only if these are the first or
+ * last processes respectively to use the hardware.  PMC values
+ * written by a 'write' operation are saved and are transferred to
+ * hardware at PMC 'start' time if the runcount is 0.  If the runcount
+ * is greater than 0 at the time of a 'start' operation, we keep track
+ * of the actual hardware value at the time of the 'start' operation
+ * and use this to adjust the final readings at PMC 'stop' or 'read'
+ * time.
+ *
+ * Execution sequences:
+ *
+ * Case 1:   CPUx   +...-		(no overlap)
+ *	     CPUy         +...-
+ *           RC   0 1   0 1   0
+ *
+ * Case 2:   CPUx   +........-		(partial overlap)
+ * 	     CPUy       +........-
+ *           RC   0 1   2    1   0
+ *
+ * Case 3:   CPUx   +..............-	(fully overlapped)
+ *	     CPUy       +.....-
+ *	     RC   0 1   2     1    0
+ *
+ *     Key:
+ *     'CPU[xy]' : one of the two logical processors on a HTT CPU.
+ *     'RC'      : run count (#threads per physical core).
+ *     '+'       : point in time when a thread is put on a CPU.
+ *     '-'       : point in time where a thread is taken off a CPU.
+ *
+ * Handling HTT CONFIG
+ *
+ * Different processes attached to the same PMC may get scheduled on
+ * the two logical processors in the package.  We keep track of config
+ * and de-config operations using the CFGFLAGS fields of the per-physical
+ * cpu state.
+ */
+
+#define	P4_PMCS()				\
+	P4_PMC(BPU_COUNTER0)			\
+	P4_PMC(BPU_COUNTER1)			\
+	P4_PMC(BPU_COUNTER2)			\
+	P4_PMC(BPU_COUNTER3)			\
+	P4_PMC(MS_COUNTER0)			\
+	P4_PMC(MS_COUNTER1)			\
+	P4_PMC(MS_COUNTER2)			\
+	P4_PMC(MS_COUNTER3)			\
+	P4_PMC(FLAME_COUNTER0)			\
+	P4_PMC(FLAME_COUNTER1)			\
+	P4_PMC(FLAME_COUNTER2)			\
+	P4_PMC(FLAME_COUNTER3)			\
+	P4_PMC(IQ_COUNTER0)			\
+	P4_PMC(IQ_COUNTER1)			\
+	P4_PMC(IQ_COUNTER2)			\
+	P4_PMC(IQ_COUNTER3)			\
+	P4_PMC(IQ_COUNTER4)			\
+	P4_PMC(IQ_COUNTER5)			\
+	P4_PMC(NONE)
+
+enum pmc_p4pmc {
+#undef	P4_PMC
+#define	P4_PMC(N)	P4_PMC_##N ,
+	P4_PMCS()
+};
+
+/*
+ * P4 ESCR descriptors
+ */
+
+#define	P4_ESCRS()							\
+    P4_ESCR(BSU_ESCR0,	0x3A0, BPU_COUNTER0, BPU_COUNTER1, NONE)	\
+    P4_ESCR(BSU_ESCR1,	0x3A1, BPU_COUNTER2, BPU_COUNTER3, NONE)	\
+    P4_ESCR(FSB_ESCR0,	0x3A2, BPU_COUNTER0, BPU_COUNTER1, NONE)	\
+    P4_ESCR(FSB_ESCR1,	0x3A3, BPU_COUNTER2, BPU_COUNTER3, NONE)	\
+    P4_ESCR(FIRM_ESCR0,	0x3A4, FLAME_COUNTER0, FLAME_COUNTER1, NONE)	\
+    P4_ESCR(FIRM_ESCR1,	0x3A5, FLAME_COUNTER2, FLAME_COUNTER3, NONE)	\
+    P4_ESCR(FLAME_ESCR0, 0x3A6, FLAME_COUNTER0, FLAME_COUNTER1, NONE)	\
+    P4_ESCR(FLAME_ESCR1, 0x3A7, FLAME_COUNTER2, FLAME_COUNTER3, NONE)	\
+    P4_ESCR(DAC_ESCR0,	0x3A8, FLAME_COUNTER0, FLAME_COUNTER1, NONE)	\
+    P4_ESCR(DAC_ESCR1,	0x3A9, FLAME_COUNTER2, FLAME_COUNTER3, NONE)	\
+    P4_ESCR(MOB_ESCR0,	0x3AA, BPU_COUNTER0, BPU_COUNTER1, NONE)	\
+    P4_ESCR(MOB_ESCR1,	0x3AB, BPU_COUNTER2, BPU_COUNTER3, NONE)	\
+    P4_ESCR(PMH_ESCR0,	0x3AC, BPU_COUNTER0, BPU_COUNTER1, NONE)	\
+    P4_ESCR(PMH_ESCR1,	0x3AD, BPU_COUNTER2, BPU_COUNTER3, NONE)	\
+    P4_ESCR(SAAT_ESCR0,	0x3AE, FLAME_COUNTER0, FLAME_COUNTER1, NONE)	\
+    P4_ESCR(SAAT_ESCR1,	0x3AF, FLAME_COUNTER2, FLAME_COUNTER3, NONE)	\
+    P4_ESCR(U2L_ESCR0,	0x3B0, FLAME_COUNTER0, FLAME_COUNTER1, NONE)	\
+    P4_ESCR(U2L_ESCR1,	0x3B1, FLAME_COUNTER2, FLAME_COUNTER3, NONE)	\
+    P4_ESCR(BPU_ESCR0,	0x3B2, BPU_COUNTER0, BPU_COUNTER1, NONE)	\
+    P4_ESCR(BPU_ESCR1,	0x3B3, BPU_COUNTER2, BPU_COUNTER3, NONE)	\
+    P4_ESCR(IS_ESCR0,	0x3B4, BPU_COUNTER0, BPU_COUNTER1, NONE)	\
+    P4_ESCR(IS_ESCR1,	0x3B5, BPU_COUNTER2, BPU_COUNTER3, NONE)	\
+    P4_ESCR(ITLB_ESCR0,	0x3B6, BPU_COUNTER0, BPU_COUNTER1, NONE)	\
+    P4_ESCR(ITLB_ESCR1,	0x3B7, BPU_COUNTER2, BPU_COUNTER3, NONE)	\
+    P4_ESCR(CRU_ESCR0,	0x3B8, IQ_COUNTER0, IQ_COUNTER1, IQ_COUNTER4)	\
+    P4_ESCR(CRU_ESCR1,	0x3B9, IQ_COUNTER2, IQ_COUNTER3, IQ_COUNTER5)	\
+    P4_ESCR(IQ_ESCR0,	0x3BA, IQ_COUNTER0, IQ_COUNTER1, IQ_COUNTER4)	\
+    P4_ESCR(IQ_ESCR1,	0x3BB, IQ_COUNTER1, IQ_COUNTER3, IQ_COUNTER5)	\
+    P4_ESCR(RAT_ESCR0,	0x3BC, IQ_COUNTER0, IQ_COUNTER1, IQ_COUNTER4)	\
+    P4_ESCR(RAT_ESCR1,	0x3BD, IQ_COUNTER2, IQ_COUNTER3, IQ_COUNTER5)	\
+    P4_ESCR(SSU_ESCR0,	0x3BE, IQ_COUNTER0, IQ_COUNTER2, IQ_COUNTER4)	\
+    P4_ESCR(MS_ESCR0,	0x3C0, MS_COUNTER0, MS_COUNTER1, NONE)		\
+    P4_ESCR(MS_ESCR1,	0x3C1, MS_COUNTER2, MS_COUNTER3, NONE)		\
+    P4_ESCR(TBPU_ESCR0,	0x3C2, MS_COUNTER0, MS_COUNTER1, NONE)		\
+    P4_ESCR(TBPU_ESCR1,	0x3C3, MS_COUNTER2, MS_COUNTER3, NONE)		\
+    P4_ESCR(TC_ESCR0,	0x3C4, MS_COUNTER0, MS_COUNTER1, NONE)		\
+    P4_ESCR(TC_ESCR1,	0x3C5, MS_COUNTER2, MS_COUNTER3, NONE)		\
+    P4_ESCR(IX_ESCR0,	0x3C8, BPU_COUNTER0, BPU_COUNTER1, NONE)	\
+    P4_ESCR(IX_ESCR1,	0x3C9, BPU_COUNTER2, BPU_COUNTER3, NONE)	\
+    P4_ESCR(ALF_ESCR0,	0x3CA, IQ_COUNTER0, IQ_COUNTER1, IQ_COUNTER4)	\
+    P4_ESCR(ALF_ESCR1,	0x3CB, IQ_COUNTER2, IQ_COUNTER3, IQ_COUNTER5)	\
+    P4_ESCR(CRU_ESCR2,	0x3CC, IQ_COUNTER0, IQ_COUNTER1, IQ_COUNTER4)	\
+    P4_ESCR(CRU_ESCR3,	0x3CD, IQ_COUNTER2, IQ_COUNTER3, IQ_COUNTER5)	\
+    P4_ESCR(CRU_ESCR4,	0x3E0, IQ_COUNTER0, IQ_COUNTER1, IQ_COUNTER4)	\
+    P4_ESCR(CRU_ESCR5,	0x3E1, IQ_COUNTER2, IQ_COUNTER3, IQ_COUNTER5)	\
+    P4_ESCR(NONE,		~0,    NONE, NONE, NONE)
+
+enum pmc_p4escr {
+#define	P4_ESCR(N, MSR, P1, P2, P3)	P4_ESCR_##N ,
+	P4_ESCRS()
+#undef	P4_ESCR
+};
+
+struct pmc_p4escr_descr {
+	const char	pm_escrname[PMC_NAME_MAX];
+	u_short		pm_escr_msr;
+	const enum pmc_p4pmc pm_pmcs[P4_MAX_PMC_PER_ESCR];
+};
+
+static struct pmc_p4escr_descr p4_escrs[] =
+{
+#define	P4_ESCR(N, MSR, P1, P2, P3)		\
+	{					\
+		.pm_escrname = #N,		\
+		.pm_escr_msr = (MSR),		\
+		.pm_pmcs =			\
+		{				\
+			P4_PMC_##P1,		\
+			P4_PMC_##P2,		\
+			P4_PMC_##P3		\
+		}				\
+	} ,
+
+	P4_ESCRS()
+
+#undef	P4_ESCR
+};
+
+/*
+ * P4 Event descriptor
+ */
+
+struct p4_event_descr {
+	const enum pmc_event pm_event;
+	const uint32_t	pm_escr_eventselect;
+	const uint32_t	pm_cccr_select;
+	const char	pm_is_ti_event;
+	enum pmc_p4escr	pm_escrs[P4_MAX_ESCR_PER_EVENT];
+};
+
+static struct p4_event_descr p4_events[] = {
+
+#define	P4_EVDESCR(NAME, ESCREVENTSEL, CCCRSEL, TI_EVENT, ESCR0, ESCR1)	\
+	{								\
+		.pm_event            = PMC_EV_P4_##NAME,		\
+		.pm_escr_eventselect = (ESCREVENTSEL),			\
+		.pm_cccr_select      = (CCCRSEL),			\
+		.pm_is_ti_event	     = (TI_EVENT),			\
+		.pm_escrs            =					\
+		{							\
+			P4_ESCR_##ESCR0,				\
+			P4_ESCR_##ESCR1					\
+		}							\
+	}
+
+P4_EVDESCR(TC_DELIVER_MODE,	0x01, 0x01, TRUE,  TC_ESCR0,	TC_ESCR1),
+P4_EVDESCR(BPU_FETCH_REQUEST,	0x03, 0x00, FALSE, BPU_ESCR0,	BPU_ESCR1),
+P4_EVDESCR(ITLB_REFERENCE,	0x18, 0x03, FALSE, ITLB_ESCR0,	ITLB_ESCR1),
+P4_EVDESCR(MEMORY_CANCEL,	0x02, 0x05, FALSE, DAC_ESCR0,	DAC_ESCR1),
+P4_EVDESCR(MEMORY_COMPLETE,	0x08, 0x02, FALSE, SAAT_ESCR0,	SAAT_ESCR1),
+P4_EVDESCR(LOAD_PORT_REPLAY,	0x04, 0x02, FALSE, SAAT_ESCR0,	SAAT_ESCR1),
+P4_EVDESCR(STORE_PORT_REPLAY,	0x05, 0x02, FALSE, SAAT_ESCR0,	SAAT_ESCR1),
+P4_EVDESCR(MOB_LOAD_REPLAY,	0x03, 0x02, FALSE, MOB_ESCR0,	MOB_ESCR1),
+P4_EVDESCR(PAGE_WALK_TYPE,	0x01, 0x04, TRUE,  PMH_ESCR0,	PMH_ESCR1),
+P4_EVDESCR(BSQ_CACHE_REFERENCE,	0x0C, 0x07, FALSE, BSU_ESCR0,	BSU_ESCR1),
+P4_EVDESCR(IOQ_ALLOCATION,	0x03, 0x06, FALSE, FSB_ESCR0,	FSB_ESCR1),
+P4_EVDESCR(IOQ_ACTIVE_ENTRIES,	0x1A, 0x06, FALSE, FSB_ESCR1,	NONE),
+P4_EVDESCR(FSB_DATA_ACTIVITY,	0x17, 0x06, TRUE,  FSB_ESCR0,	FSB_ESCR1),
+P4_EVDESCR(BSQ_ALLOCATION,	0x05, 0x07, FALSE, BSU_ESCR0,	NONE),
+P4_EVDESCR(BSQ_ACTIVE_ENTRIES,	0x06, 0x07, FALSE, BSU_ESCR1,	NONE),
+	/* BSQ_ACTIVE_ENTRIES inherits CPU specificity from BSQ_ALLOCATION */
+P4_EVDESCR(SSE_INPUT_ASSIST,	0x34, 0x01, TRUE,  FIRM_ESCR0,	FIRM_ESCR1),
+P4_EVDESCR(PACKED_SP_UOP,	0x08, 0x01, TRUE,  FIRM_ESCR0,	FIRM_ESCR1),
+P4_EVDESCR(PACKED_DP_UOP,	0x0C, 0x01, TRUE,  FIRM_ESCR0,	FIRM_ESCR1),
+P4_EVDESCR(SCALAR_SP_UOP,	0x0A, 0x01, TRUE,  FIRM_ESCR0,	FIRM_ESCR1),
+P4_EVDESCR(SCALAR_DP_UOP,	0x0E, 0x01, TRUE,  FIRM_ESCR0,	FIRM_ESCR1),
+P4_EVDESCR(64BIT_MMX_UOP,	0x02, 0x01, TRUE,  FIRM_ESCR0,	FIRM_ESCR1),
+P4_EVDESCR(128BIT_MMX_UOP,	0x1A, 0x01, TRUE,  FIRM_ESCR0,	FIRM_ESCR1),
+P4_EVDESCR(X87_FP_UOP,		0x04, 0x01, TRUE,  FIRM_ESCR0,	FIRM_ESCR1),
+P4_EVDESCR(X87_SIMD_MOVES_UOP,	0x2E, 0x01, TRUE,  FIRM_ESCR0,	FIRM_ESCR1),
+P4_EVDESCR(GLOBAL_POWER_EVENTS,	0x13, 0x06, FALSE, FSB_ESCR0,	FSB_ESCR1),
+P4_EVDESCR(TC_MS_XFER,		0x05, 0x00, FALSE, MS_ESCR0,	MS_ESCR1),
+P4_EVDESCR(UOP_QUEUE_WRITES,	0x09, 0x00, FALSE, MS_ESCR0,	MS_ESCR1),
+P4_EVDESCR(RETIRED_MISPRED_BRANCH_TYPE,
+				0x05, 0x02, FALSE, TBPU_ESCR0,	TBPU_ESCR1),
+P4_EVDESCR(RETIRED_BRANCH_TYPE,	0x04, 0x02, FALSE, TBPU_ESCR0,	TBPU_ESCR1),
+P4_EVDESCR(RESOURCE_STALL,	0x01, 0x01, FALSE, ALF_ESCR0,	ALF_ESCR1),
+P4_EVDESCR(WC_BUFFER,		0x05, 0x05, TRUE,  DAC_ESCR0,	DAC_ESCR1),
+P4_EVDESCR(B2B_CYCLES,		0x16, 0x03, TRUE,  FSB_ESCR0,	FSB_ESCR1),
+P4_EVDESCR(BNR,			0x08, 0x03, TRUE,  FSB_ESCR0,	FSB_ESCR1),
+P4_EVDESCR(SNOOP,		0x06, 0x03, TRUE,  FSB_ESCR0,	FSB_ESCR1),
+P4_EVDESCR(RESPONSE,		0x04, 0x03, TRUE,  FSB_ESCR0,	FSB_ESCR1),
+P4_EVDESCR(FRONT_END_EVENT,	0x08, 0x05, FALSE, CRU_ESCR2,	CRU_ESCR3),
+P4_EVDESCR(EXECUTION_EVENT,	0x0C, 0x05, FALSE, CRU_ESCR2,	CRU_ESCR3),
+P4_EVDESCR(REPLAY_EVENT, 	0x09, 0x05, FALSE, CRU_ESCR2,	CRU_ESCR3),
+P4_EVDESCR(INSTR_RETIRED,	0x02, 0x04, FALSE, CRU_ESCR0,	CRU_ESCR1),
+P4_EVDESCR(UOPS_RETIRED,	0x01, 0x04, FALSE, CRU_ESCR0,	CRU_ESCR1),
+P4_EVDESCR(UOP_TYPE,		0x02, 0x02, FALSE, RAT_ESCR0,	RAT_ESCR1),
+P4_EVDESCR(BRANCH_RETIRED,	0x06, 0x05, FALSE, CRU_ESCR2,	CRU_ESCR3),
+P4_EVDESCR(MISPRED_BRANCH_RETIRED, 0x03, 0x04, FALSE, CRU_ESCR0, CRU_ESCR1),
+P4_EVDESCR(X87_ASSIST,		0x03, 0x05, FALSE, CRU_ESCR2,	CRU_ESCR3),
+P4_EVDESCR(MACHINE_CLEAR,	0x02, 0x05, FALSE, CRU_ESCR2,	CRU_ESCR3)
+
+#undef	P4_EVDESCR
+};
+
+#define	P4_EVENT_IS_TI(E) ((E)->pm_is_ti_event == TRUE)
+
+#define	P4_NEVENTS	(PMC_EV_P4_LAST - PMC_EV_P4_FIRST + 1)
+
+/*
+ * P4 PMC descriptors
+ */
+
+struct p4pmc_descr {
+	struct pmc_descr pm_descr; 	/* common information */
+	enum pmc_p4pmc	pm_pmcnum;	/* PMC number */
+	uint32_t	pm_pmc_msr; 	/* PERFCTR MSR address */
+	uint32_t	pm_cccr_msr;  	/* CCCR MSR address */
+};
+
+static struct p4pmc_descr p4_pmcdesc[P4_NPMCS] = {
+#define	P4_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_USER | PMC_CAP_SYSTEM |  \
+	PMC_CAP_EDGE | PMC_CAP_THRESHOLD | PMC_CAP_READ | PMC_CAP_WRITE | \
+	PMC_CAP_INVERT | PMC_CAP_QUALIFIER | PMC_CAP_PRECISE |            \
+	PMC_CAP_TAGGING | PMC_CAP_CASCADE)
+
+#define	P4_PMCDESCR(N, PMC, CCCR)			\
+	{						\
+		.pm_descr =				\
+		{					\
+			.pd_name = #N,			\
+			.pd_class = PMC_CLASS_P4,	\
+			.pd_caps = P4_PMC_CAPS,		\
+			.pd_width = 40			\
+		},					\
+		.pm_pmcnum      = P4_PMC_##N,		\
+		.pm_cccr_msr 	= (CCCR),		\
+		.pm_pmc_msr	= (PMC)			\
+	}
+
+	P4_PMCDESCR(BPU_COUNTER0,	0x300,	0x360),
+	P4_PMCDESCR(BPU_COUNTER1,	0x301,	0x361),
+	P4_PMCDESCR(BPU_COUNTER2,	0x302,	0x362),
+	P4_PMCDESCR(BPU_COUNTER3,	0x303,	0x363),
+	P4_PMCDESCR(MS_COUNTER0,	0x304,	0x364),
+	P4_PMCDESCR(MS_COUNTER1,	0x305,	0x365),
+	P4_PMCDESCR(MS_COUNTER2,	0x306,	0x366),
+	P4_PMCDESCR(MS_COUNTER3,	0x307,	0x367),
+	P4_PMCDESCR(FLAME_COUNTER0,	0x308,	0x368),
+	P4_PMCDESCR(FLAME_COUNTER1,	0x309,	0x369),
+	P4_PMCDESCR(FLAME_COUNTER2,	0x30A,	0x36A),
+	P4_PMCDESCR(FLAME_COUNTER3,	0x30B,	0x36B),
+	P4_PMCDESCR(IQ_COUNTER0,	0x30C,	0x36C),
+	P4_PMCDESCR(IQ_COUNTER1,	0x30D,	0x36D),
+	P4_PMCDESCR(IQ_COUNTER2,	0x30E,	0x36E),
+	P4_PMCDESCR(IQ_COUNTER3,	0x30F,	0x36F),
+	P4_PMCDESCR(IQ_COUNTER4,	0x310,	0x370),
+	P4_PMCDESCR(IQ_COUNTER5,	0x311,	0x371),
+
+#undef	P4_PMCDESCR
+};
+
+/* HTT support */
+#define	P4_NHTT					2 /* logical processors/chip */
+
+static int p4_system_has_htt;
+
+/*
+ * Per-CPU data structure for P4 class CPUs
+ *
+ * [19 struct pmc_hw structures]
+ * [45 ESCRs status bytes]
+ * [per-cpu spin mutex]
+ * [19 flag fields for holding config flags and a runcount]
+ * [19*2 hw value fields]	(Thread mode PMC support)
+ *    or
+ * [19*2 EIP values]		(Sampling mode PMCs)
+ * [19*2 pmc value fields]	(Thread mode PMC support))
+ */
+
+struct p4_cpu {
+	struct pmc_hw	pc_p4pmcs[P4_NPMCS];
+	char		pc_escrs[P4_NESCR];
+	struct mtx	pc_mtx;		/* spin lock */
+	uint32_t	pc_intrflag;	/* NMI handler flags */
+	unsigned int	pc_intrlock;	/* NMI handler spin lock */
+	unsigned char	pc_flags[P4_NPMCS]; /* 4 bits each: {cfg,run}count */
+	union {
+		pmc_value_t pc_hw[P4_NPMCS * P4_NHTT];
+		uintptr_t   pc_ip[P4_NPMCS * P4_NHTT];
+	}		pc_si;
+	pmc_value_t	pc_pmc_values[P4_NPMCS * P4_NHTT];
+};
+
+static struct p4_cpu **p4_pcpu;
+
+#define	P4_PCPU_PMC_VALUE(PC,RI,CPU) 	(PC)->pc_pmc_values[(RI)*((CPU) & 1)]
+#define	P4_PCPU_HW_VALUE(PC,RI,CPU)	(PC)->pc_si.pc_hw[(RI)*((CPU) & 1)]
+#define	P4_PCPU_SAVED_IP(PC,RI,CPU)	(PC)->pc_si.pc_ip[(RI)*((CPU) & 1)]
+
+#define	P4_PCPU_GET_FLAGS(PC,RI,MASK)	((PC)->pc_flags[(RI)] & (MASK))
+#define	P4_PCPU_SET_FLAGS(PC,RI,MASK,VAL)	do {	\
+	char _tmp;					\
+	_tmp = (PC)->pc_flags[(RI)];			\
+	_tmp &= ~(MASK);				\
+	_tmp |= (VAL) & (MASK);				\
+	(PC)->pc_flags[(RI)] = _tmp;			\
+} while (0)
+
+#define	P4_PCPU_GET_RUNCOUNT(PC,RI)	P4_PCPU_GET_FLAGS(PC,RI,0x0F)
+#define	P4_PCPU_SET_RUNCOUNT(PC,RI,V)	P4_PCPU_SET_FLAGS(PC,RI,0x0F,V)
+
+#define	P4_PCPU_GET_CFGFLAGS(PC,RI)	(P4_PCPU_GET_FLAGS(PC,RI,0xF0) >> 4)
+#define	P4_PCPU_SET_CFGFLAGS(PC,RI,C)	P4_PCPU_SET_FLAGS(PC,RI,0xF0,((C) <<4))
+
+#define	P4_CPU_TO_FLAG(C)		(P4_CPU_IS_HTT_SECONDARY(cpu) ? 0x2 : 0x1)
+
+#define	P4_PCPU_GET_INTRFLAG(PC,I)	((PC)->pc_intrflag & (1 << (I)))
+#define	P4_PCPU_SET_INTRFLAG(PC,I,V)	do {		\
+		uint32_t __mask;			\
+		__mask = 1 << (I);			\
+		if ((V))				\
+			(PC)->pc_intrflag |= __mask;	\
+		else					\
+			(PC)->pc_intrflag &= ~__mask;	\
+	} while (0)
+
+/*
+ * A minimal spin lock implementation for use inside the NMI handler.
+ *
+ * We don't want to use a regular spin lock here, because curthread
+ * may not be consistent at the time the handler is invoked.
+ */
+#define	P4_PCPU_ACQ_INTR_SPINLOCK(PC) do {				\
+		while (!atomic_cmpset_acq_int(&pc->pc_intrlock, 0, 1))	\
+			ia32_pause();					\
+	} while (0)
+#define	P4_PCPU_REL_INTR_SPINLOCK(PC) 					\
+	atomic_store_rel_int(&pc->pc_intrlock, 0);
+
+/* ESCR row disposition */
+static int p4_escrdisp[P4_NESCR];
+
+#define	P4_ESCR_ROW_DISP_IS_THREAD(E)		(p4_escrdisp[(E)] > 0)
+#define	P4_ESCR_ROW_DISP_IS_STANDALONE(E)	(p4_escrdisp[(E)] < 0)
+#define	P4_ESCR_ROW_DISP_IS_FREE(E)		(p4_escrdisp[(E)] == 0)
+
+#define	P4_ESCR_MARK_ROW_STANDALONE(E) do {				\
+	KASSERT(p4_escrdisp[(E)] <= 0, ("[p4,%d] row disposition error",\
+		    __LINE__));						\
+	atomic_add_int(&p4_escrdisp[(E)], -1);				\
+	KASSERT(p4_escrdisp[(E)] >= (-pmc_cpu_max_active()), 		\
+		("[p4,%d] row disposition error", __LINE__));		\
+} while (0)
+
+#define	P4_ESCR_UNMARK_ROW_STANDALONE(E) do {				\
+	atomic_add_int(&p4_escrdisp[(E)], 1);				\
+	KASSERT(p4_escrdisp[(E)] <= 0, ("[p4,%d] row disposition error",\
+		    __LINE__));						\
+} while (0)
+
+#define	P4_ESCR_MARK_ROW_THREAD(E) do {					 \
+	KASSERT(p4_escrdisp[(E)] >= 0, ("[p4,%d] row disposition error", \
+		    __LINE__));						 \
+	atomic_add_int(&p4_escrdisp[(E)], 1);				 \
+} while (0)
+
+#define	P4_ESCR_UNMARK_ROW_THREAD(E) do {				 \
+	atomic_add_int(&p4_escrdisp[(E)], -1);				 \
+	KASSERT(p4_escrdisp[(E)] >= 0, ("[p4,%d] row disposition error", \
+		    __LINE__));						 \
+} while (0)
+
+#define	P4_PMC_IS_STOPPED(cccr)	((rdmsr(cccr) & P4_CCCR_ENABLE) == 0)
+
+#define	P4_CPU_IS_HTT_SECONDARY(cpu)					\
+	(p4_system_has_htt ? ((cpu) & 1) : 0)
+#define	P4_TO_HTT_PRIMARY(cpu) 						\
+	(p4_system_has_htt ? ((cpu) & ~1) : (cpu))
+
+#define	P4_CCCR_Tx_MASK	(~(P4_CCCR_OVF_PMI_T0|P4_CCCR_OVF_PMI_T1|	\
+			     P4_CCCR_ENABLE|P4_CCCR_OVF))
+#define	P4_ESCR_Tx_MASK	(~(P4_ESCR_T0_OS|P4_ESCR_T0_USR|P4_ESCR_T1_OS|	\
+			     P4_ESCR_T1_USR))
+
+/*
+ * support routines
+ */
+
+static struct p4_event_descr *
+p4_find_event(enum pmc_event ev)
+{
+	int n;
+
+	for (n = 0; n < P4_NEVENTS; n++)
+		if (p4_events[n].pm_event == ev)
+			break;
+	if (n == P4_NEVENTS)
+		return (NULL);
+	return (&p4_events[n]);
+}
+
+/*
+ * Initialize per-cpu state
+ */
+
+static int
+p4_pcpu_init(struct pmc_mdep *md, int cpu)
+{
+	char *pescr;
+	int n, first_ri, phycpu;
+	struct pmc_hw *phw;
+	struct p4_cpu *p4c;
+	struct pmc_cpu *pc, *plc;
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[p4,%d] insane cpu number %d", __LINE__, cpu));
+
+	PMCDBG(MDP,INI,0, "p4-init cpu=%d is-primary=%d", cpu,
+	    pmc_cpu_is_primary(cpu) != 0);
+
+	first_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_P4].pcd_ri;
+
+	/*
+	 * The two CPUs in an HT pair share their per-cpu state.
+	 *
+	 * For HT capable CPUs, we assume that the two logical
+	 * processors in the HT pair get two consecutive CPU ids
+	 * starting with an even id #.
+	 *
+	 * The primary CPU (the even numbered CPU of the pair) would
+	 * have been initialized prior to the initialization for the
+	 * secondary.
+	 */
+
+	if (!pmc_cpu_is_primary(cpu) && (cpu & 1)) {
+
+		p4_system_has_htt = 1;
+
+		phycpu = P4_TO_HTT_PRIMARY(cpu);
+		pc = pmc_pcpu[phycpu];
+		plc = pmc_pcpu[cpu];
+
+		KASSERT(plc != pc, ("[p4,%d] per-cpu config error", __LINE__));
+
+		PMCDBG(MDP,INI,1, "p4-init cpu=%d phycpu=%d pc=%p", cpu,
+		    phycpu, pc);
+		KASSERT(pc, ("[p4,%d] Null Per-Cpu state cpu=%d phycpu=%d",
+		    __LINE__, cpu, phycpu));
+
+		/* PMCs are shared with the physical CPU. */
+		for (n = 0; n < P4_NPMCS; n++)
+			plc->pc_hwpmcs[n + first_ri] =
+			    pc->pc_hwpmcs[n + first_ri];
+
+		return (0);
+	}
+
+	p4c = malloc(sizeof(struct p4_cpu), M_PMC, M_WAITOK|M_ZERO);
+
+	if (p4c == NULL)
+		return (ENOMEM);
+
+	pc = pmc_pcpu[cpu];
+
+	KASSERT(pc != NULL, ("[p4,%d] cpu %d null per-cpu", __LINE__, cpu));
+
+	p4_pcpu[cpu] = p4c;
+	phw = p4c->pc_p4pmcs;
+
+	for (n = 0; n < P4_NPMCS; n++, phw++) {
+		phw->phw_state   = PMC_PHW_FLAG_IS_ENABLED |
+		    PMC_PHW_CPU_TO_STATE(cpu) | PMC_PHW_INDEX_TO_STATE(n);
+		phw->phw_pmc     = NULL;
+		pc->pc_hwpmcs[n + first_ri] = phw;
+	}
+
+	pescr = p4c->pc_escrs;
+	for (n = 0; n < P4_NESCR; n++)
+		*pescr++ = P4_INVALID_PMC_INDEX;
+
+	mtx_init(&p4c->pc_mtx, "p4-pcpu", "pmc-leaf", MTX_SPIN);
+
+	return (0);
+}
+
+/*
+ * Destroy per-cpu state.
+ */
+
+static int
+p4_pcpu_fini(struct pmc_mdep *md, int cpu)
+{
+	int first_ri, i;
+	struct p4_cpu *p4c;
+	struct pmc_cpu *pc;
+
+	PMCDBG(MDP,INI,0, "p4-cleanup cpu=%d", cpu);
+
+	pc = pmc_pcpu[cpu];
+	first_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_P4].pcd_ri;
+
+	for (i = 0; i < P4_NPMCS; i++)
+		pc->pc_hwpmcs[i + first_ri] = NULL;
+
+	if (!pmc_cpu_is_primary(cpu) && (cpu & 1))
+		return (0);
+
+	p4c = p4_pcpu[cpu];
+
+	KASSERT(p4c != NULL, ("[p4,%d] NULL pcpu", __LINE__));
+
+	/* Turn off all PMCs on this CPU */
+	for (i = 0; i < P4_NPMCS - 1; i++)
+		wrmsr(P4_CCCR_MSR_FIRST + i,
+		    rdmsr(P4_CCCR_MSR_FIRST + i) & ~P4_CCCR_ENABLE);
+
+	mtx_destroy(&p4c->pc_mtx);
+
+	free(p4c, M_PMC);
+
+	p4_pcpu[cpu] = NULL;
+
+	return (0);
+}
+
+/*
+ * Read a PMC
+ */
+
+static int
+p4_read_pmc(int cpu, int ri, pmc_value_t *v)
+{
+	struct pmc *pm;
+	pmc_value_t tmp;
+	struct p4_cpu *pc;
+	enum pmc_mode mode;
+	struct p4pmc_descr *pd;
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[p4,%d] illegal CPU value %d", __LINE__, cpu));
+	KASSERT(ri >= 0 && ri < P4_NPMCS,
+	    ("[p4,%d] illegal row-index %d", __LINE__, ri));
+
+	pc = p4_pcpu[P4_TO_HTT_PRIMARY(cpu)];
+	pm = pc->pc_p4pmcs[ri].phw_pmc;
+	pd = &p4_pmcdesc[ri];
+
+	KASSERT(pm != NULL,
+	    ("[p4,%d] No owner for HWPMC [cpu%d,pmc%d]", __LINE__, cpu, ri));
+
+	KASSERT(pd->pm_descr.pd_class == PMC_TO_CLASS(pm),
+	    ("[p4,%d] class mismatch pd %d != id class %d", __LINE__,
+	    pd->pm_descr.pd_class, PMC_TO_CLASS(pm)));
+
+	mode = PMC_TO_MODE(pm);
+
+	PMCDBG(MDP,REA,1, "p4-read cpu=%d ri=%d mode=%d", cpu, ri, mode);
+
+	KASSERT(pd->pm_descr.pd_class == PMC_CLASS_P4,
+	    ("[p4,%d] unknown PMC class %d", __LINE__, pd->pm_descr.pd_class));
+
+	tmp = rdmsr(p4_pmcdesc[ri].pm_pmc_msr);
+
+	if (PMC_IS_VIRTUAL_MODE(mode)) {
+		if (tmp < P4_PCPU_HW_VALUE(pc,ri,cpu)) /* 40 bit overflow */
+			tmp += (P4_PERFCTR_MASK + 1) -
+			    P4_PCPU_HW_VALUE(pc,ri,cpu);
+		else
+			tmp -= P4_PCPU_HW_VALUE(pc,ri,cpu);
+		tmp += P4_PCPU_PMC_VALUE(pc,ri,cpu);
+	}
+
+	if (PMC_IS_SAMPLING_MODE(mode)) /* undo transformation */
+		*v = P4_PERFCTR_VALUE_TO_RELOAD_COUNT(tmp);
+	else
+		*v = tmp;
+
+	PMCDBG(MDP,REA,2, "p4-read -> %jx", *v);
+
+	return (0);
+}
+
+/*
+ * Write a PMC
+ */
+
+static int
+p4_write_pmc(int cpu, int ri, pmc_value_t v)
+{
+	enum pmc_mode mode;
+	struct pmc *pm;
+	struct p4_cpu *pc;
+	const struct pmc_hw *phw;
+	const struct p4pmc_descr *pd;
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[amd,%d] illegal CPU value %d", __LINE__, cpu));
+	KASSERT(ri >= 0 && ri < P4_NPMCS,
+	    ("[amd,%d] illegal row-index %d", __LINE__, ri));
+
+	pc  = p4_pcpu[P4_TO_HTT_PRIMARY(cpu)];
+	phw = &pc->pc_p4pmcs[ri];
+	pm  = phw->phw_pmc;
+	pd  = &p4_pmcdesc[ri];
+
+	KASSERT(pm != NULL,
+	    ("[p4,%d] No owner for HWPMC [cpu%d,pmc%d]", __LINE__,
+		cpu, ri));
+
+	mode = PMC_TO_MODE(pm);
+
+	PMCDBG(MDP,WRI,1, "p4-write cpu=%d ri=%d mode=%d v=%jx", cpu, ri,
+	    mode, v);
+
+	/*
+	 * write the PMC value to the register/saved value: for
+	 * sampling mode PMCs, the value to be programmed into the PMC
+	 * counter is -(C+1) where 'C' is the requested sample rate.
+	 */
+	if (PMC_IS_SAMPLING_MODE(mode))
+		v = P4_RELOAD_COUNT_TO_PERFCTR_VALUE(v);
+
+	if (PMC_IS_SYSTEM_MODE(mode))
+		wrmsr(pd->pm_pmc_msr, v);
+	else
+		P4_PCPU_PMC_VALUE(pc,ri,cpu) = v;
+
+	return (0);
+}
+
+/*
+ * Configure a PMC 'pm' on the given CPU and row-index.
+ *
+ * 'pm' may be NULL to indicate de-configuration.
+ *
+ * On HTT systems, a PMC may get configured twice, once for each
+ * "logical" CPU.  We track this using the CFGFLAGS field of the
+ * per-cpu state; this field is a bit mask with one bit each for
+ * logical CPUs 0 & 1.
+ */
+
+static int
+p4_config_pmc(int cpu, int ri, struct pmc *pm)
+{
+	struct pmc_hw *phw;
+	struct p4_cpu *pc;
+	int cfgflags, cpuflag;
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[p4,%d] illegal CPU %d", __LINE__, cpu));
+
+	KASSERT(ri >= 0 && ri < P4_NPMCS,
+	    ("[p4,%d] illegal row-index %d", __LINE__, ri));
+
+	PMCDBG(MDP,CFG,1, "cpu=%d ri=%d pm=%p", cpu, ri, pm);
+
+	pc  = p4_pcpu[P4_TO_HTT_PRIMARY(cpu)];
+	phw = &pc->pc_p4pmcs[ri];
+
+	KASSERT(pm == NULL || phw->phw_pmc == NULL ||
+	    (p4_system_has_htt && phw->phw_pmc == pm),
+	    ("[p4,%d] hwpmc not unconfigured before re-config", __LINE__));
+
+	mtx_lock_spin(&pc->pc_mtx);
+	cfgflags = P4_PCPU_GET_CFGFLAGS(pc,ri);
+
+	KASSERT(cfgflags >= 0 || cfgflags <= 3,
+	    ("[p4,%d] illegal cfgflags cfg=%d on cpu=%d ri=%d", __LINE__,
+		cfgflags, cpu, ri));
+
+	KASSERT(cfgflags == 0 || phw->phw_pmc,
+	    ("[p4,%d] cpu=%d ri=%d pmc configured with zero cfg count",
+		__LINE__, cpu, ri));
+
+	cpuflag = P4_CPU_TO_FLAG(cpu);
+
+	if (pm) {		/* config */
+		if (cfgflags == 0)
+			phw->phw_pmc = pm;
+
+		KASSERT(phw->phw_pmc == pm,
+		    ("[p4,%d] cpu=%d ri=%d config %p != hw %p",
+			__LINE__, cpu, ri, pm, phw->phw_pmc));
+
+		cfgflags |= cpuflag;
+	} else {		/* unconfig */
+		cfgflags &= ~cpuflag;
+
+		if (cfgflags == 0)
+			phw->phw_pmc = NULL;
+	}
+
+	KASSERT(cfgflags >= 0 || cfgflags <= 3,
+	    ("[p4,%d] illegal runcount cfg=%d on cpu=%d ri=%d", __LINE__,
+		cfgflags, cpu, ri));
+
+	P4_PCPU_SET_CFGFLAGS(pc,ri,cfgflags);
+
+	mtx_unlock_spin(&pc->pc_mtx);
+
+	return (0);
+}
+
+/*
+ * Retrieve a configured PMC pointer from hardware state.
+ */
+
+static int
+p4_get_config(int cpu, int ri, struct pmc **ppm)
+{
+	int cfgflags;
+	struct p4_cpu *pc;
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[p4,%d] illegal CPU %d", __LINE__, cpu));
+	KASSERT(ri >= 0 && ri < P4_NPMCS,
+	    ("[p4,%d] illegal row-index %d", __LINE__, ri));
+
+	pc = p4_pcpu[P4_TO_HTT_PRIMARY(cpu)];
+
+	mtx_lock_spin(&pc->pc_mtx);
+	cfgflags = P4_PCPU_GET_CFGFLAGS(pc,ri);
+	mtx_unlock_spin(&pc->pc_mtx);
+
+	if (cfgflags & P4_CPU_TO_FLAG(cpu))
+		*ppm = pc->pc_p4pmcs[ri].phw_pmc; /* PMC config'ed on this CPU */
+	else
+		*ppm = NULL;
+
+	return 0;
+}
+
+/*
+ * Allocate a PMC.
+ *
+ * The allocation strategy differs between HTT and non-HTT systems.
+ *
+ * The non-HTT case:
+ *   - Given the desired event and the PMC row-index, lookup the
+ *   list of valid ESCRs for the event.
+ *   - For each valid ESCR:
+ *     - Check if the ESCR is free and the ESCR row is in a compatible
+ *       mode (i.e., system or process))
+ *     - Check if the ESCR is usable with a P4 PMC at the desired row-index.
+ *   If everything matches, we determine the appropriate bit values for the
+ *   ESCR and CCCR registers.
+ *
+ * The HTT case:
+ *
+ * - Process mode PMCs require special care.  The FreeBSD scheduler could
+ *   schedule any two processes on the same physical CPU.  We need to ensure
+ *   that a given PMC row-index is never allocated to two different
+ *   PMCs owned by different user-processes.
+ *   This is ensured by always allocating a PMC from a 'FREE' PMC row
+ *   if the system has HTT active.
+ * - A similar check needs to be done for ESCRs; we do not want two PMCs
+ *   using the same ESCR to be scheduled at the same time.  Thus ESCR
+ *   allocation is also restricted to FREE rows if the system has HTT
+ *   enabled.
+ * - Thirdly, some events are 'thread-independent' terminology, i.e.,
+ *   the PMC hardware cannot distinguish between events caused by
+ *   different logical CPUs.  This makes it impossible to assign events
+ *   to a given thread of execution.  If the system has HTT enabled,
+ *   these events are not allowed for process-mode PMCs.
+ */
+
+static int
+p4_allocate_pmc(int cpu, int ri, struct pmc *pm,
+    const struct pmc_op_pmcallocate *a)
+{
+	int found, n, m;
+	uint32_t caps, cccrvalue, escrvalue, tflags;
+	enum pmc_p4escr escr;
+	struct p4_cpu *pc;
+	struct p4_event_descr *pevent;
+	const struct p4pmc_descr *pd;
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[p4,%d] illegal CPU %d", __LINE__, cpu));
+	KASSERT(ri >= 0 && ri < P4_NPMCS,
+	    ("[p4,%d] illegal row-index value %d", __LINE__, ri));
+
+	pd = &p4_pmcdesc[ri];
+
+	PMCDBG(MDP,ALL,1, "p4-allocate ri=%d class=%d pmccaps=0x%x "
+	    "reqcaps=0x%x", ri, pd->pm_descr.pd_class, pd->pm_descr.pd_caps,
+	    pm->pm_caps);
+
+	/* check class */
+	if (pd->pm_descr.pd_class != a->pm_class)
+		return (EINVAL);
+
+	/* check requested capabilities */
+	caps = a->pm_caps;
+	if ((pd->pm_descr.pd_caps & caps) != caps)
+		return (EPERM);
+
+	/*
+	 * If the system has HTT enabled, and the desired allocation
+	 * mode is process-private, and the PMC row disposition is not
+	 * FREE (0), decline the allocation.
+	 */
+
+	if (p4_system_has_htt &&
+	    PMC_IS_VIRTUAL_MODE(PMC_TO_MODE(pm)) &&
+	    pmc_getrowdisp(ri) != 0)
+		return (EBUSY);
+
+	KASSERT(pd->pm_descr.pd_class == PMC_CLASS_P4,
+	    ("[p4,%d] unknown PMC class %d", __LINE__,
+		pd->pm_descr.pd_class));
+
+	if (pm->pm_event < PMC_EV_P4_FIRST ||
+	    pm->pm_event > PMC_EV_P4_LAST)
+		return (EINVAL);
+
+	if ((pevent = p4_find_event(pm->pm_event)) == NULL)
+		return (ESRCH);
+
+	PMCDBG(MDP,ALL,2, "pevent={ev=%d,escrsel=0x%x,cccrsel=0x%x,isti=%d}",
+	    pevent->pm_event, pevent->pm_escr_eventselect,
+	    pevent->pm_cccr_select, pevent->pm_is_ti_event);
+
+	/*
+	 * Some PMC events are 'thread independent'and therefore
+	 * cannot be used for process-private modes if HTT is being
+	 * used.
+	 */
+
+	if (P4_EVENT_IS_TI(pevent) &&
+	    PMC_IS_VIRTUAL_MODE(PMC_TO_MODE(pm)) &&
+	    p4_system_has_htt)
+		return (EINVAL);
+
+	pc = p4_pcpu[P4_TO_HTT_PRIMARY(cpu)];
+
+	found   = 0;
+
+	/* look for a suitable ESCR for this event */
+	for (n = 0; n < P4_MAX_ESCR_PER_EVENT && !found; n++) {
+		if ((escr = pevent->pm_escrs[n]) == P4_ESCR_NONE)
+			break;	/* out of ESCRs */
+		/*
+		 * Check ESCR row disposition.
+		 *
+		 * If the request is for a system-mode PMC, then the
+		 * ESCR row should not be in process-virtual mode, and
+		 * should also be free on the current CPU.
+		 */
+
+		if (PMC_IS_SYSTEM_MODE(PMC_TO_MODE(pm))) {
+		    if (P4_ESCR_ROW_DISP_IS_THREAD(escr) ||
+			pc->pc_escrs[escr] != P4_INVALID_PMC_INDEX)
+			    continue;
+		}
+
+		/*
+		 * If the request is for a process-virtual PMC, and if
+		 * HTT is not enabled, we can use an ESCR row that is
+		 * either FREE or already in process mode.
+		 *
+		 * If HTT is enabled, then we need to ensure that a
+		 * given ESCR is never allocated to two PMCS that
+		 * could run simultaneously on the two logical CPUs of
+		 * a CPU package.  We ensure this be only allocating
+		 * ESCRs from rows marked as 'FREE'.
+		 */
+
+		if (PMC_IS_VIRTUAL_MODE(PMC_TO_MODE(pm))) {
+			if (p4_system_has_htt) {
+				if (!P4_ESCR_ROW_DISP_IS_FREE(escr))
+					continue;
+			} else
+				if (P4_ESCR_ROW_DISP_IS_STANDALONE(escr))
+					continue;
+		}
+
+		/*
+		 * We found a suitable ESCR for this event.  Now check if
+		 * this escr can work with the PMC at row-index 'ri'.
+		 */
+
+		for (m = 0; m < P4_MAX_PMC_PER_ESCR; m++)
+			if (p4_escrs[escr].pm_pmcs[m] == pd->pm_pmcnum) {
+				found = 1;
+				break;
+			}
+	}
+
+	if (found == 0)
+		return (ESRCH);
+
+	KASSERT((int) escr >= 0 && escr < P4_NESCR,
+	    ("[p4,%d] illegal ESCR value %d", __LINE__, escr));
+
+	/* mark ESCR row mode */
+	if (PMC_IS_SYSTEM_MODE(PMC_TO_MODE(pm))) {
+		pc->pc_escrs[escr] = ri; /* mark ESCR as in use on this cpu */
+		P4_ESCR_MARK_ROW_STANDALONE(escr);
+	} else {
+		KASSERT(pc->pc_escrs[escr] == P4_INVALID_PMC_INDEX,
+		    ("[p4,%d] escr[%d] already in use", __LINE__, escr));
+		P4_ESCR_MARK_ROW_THREAD(escr);
+	}
+
+	pm->pm_md.pm_p4.pm_p4_escrmsr   = p4_escrs[escr].pm_escr_msr;
+	pm->pm_md.pm_p4.pm_p4_escr      = escr;
+
+	cccrvalue = P4_CCCR_TO_ESCR_SELECT(pevent->pm_cccr_select);
+	escrvalue = P4_ESCR_TO_EVENT_SELECT(pevent->pm_escr_eventselect);
+
+	/* CCCR fields */
+	if (caps & PMC_CAP_THRESHOLD)
+		cccrvalue |= (a->pm_md.pm_p4.pm_p4_cccrconfig &
+		    P4_CCCR_THRESHOLD_MASK) | P4_CCCR_COMPARE;
+
+	if (caps & PMC_CAP_EDGE)
+		cccrvalue |= P4_CCCR_EDGE;
+
+	if (caps & PMC_CAP_INVERT)
+		cccrvalue |= P4_CCCR_COMPLEMENT;
+
+	if (p4_system_has_htt)
+		cccrvalue |= a->pm_md.pm_p4.pm_p4_cccrconfig &
+		    P4_CCCR_ACTIVE_THREAD_MASK;
+	else			/* no HTT; thread field should be '11b' */
+		cccrvalue |= P4_CCCR_TO_ACTIVE_THREAD(0x3);
+
+	if (caps & PMC_CAP_CASCADE)
+		cccrvalue |= P4_CCCR_CASCADE;
+
+	/* On HTT systems the PMI T0 field may get moved to T1 at pmc start */
+	if (caps & PMC_CAP_INTERRUPT)
+		cccrvalue |= P4_CCCR_OVF_PMI_T0;
+
+	/* ESCR fields */
+	if (caps & PMC_CAP_QUALIFIER)
+		escrvalue |= a->pm_md.pm_p4.pm_p4_escrconfig &
+		    P4_ESCR_EVENT_MASK_MASK;
+	if (caps & PMC_CAP_TAGGING)
+		escrvalue |= (a->pm_md.pm_p4.pm_p4_escrconfig &
+		    P4_ESCR_TAG_VALUE_MASK) | P4_ESCR_TAG_ENABLE;
+	if (caps & PMC_CAP_QUALIFIER)
+		escrvalue |= (a->pm_md.pm_p4.pm_p4_escrconfig &
+		    P4_ESCR_EVENT_MASK_MASK);
+
+	/* HTT: T0_{OS,USR} bits may get moved to T1 at pmc start */
+	tflags = 0;
+	if (caps & PMC_CAP_SYSTEM)
+		tflags |= P4_ESCR_T0_OS;
+	if (caps & PMC_CAP_USER)
+		tflags |= P4_ESCR_T0_USR;
+	if (tflags == 0)
+		tflags = (P4_ESCR_T0_OS|P4_ESCR_T0_USR);
+	escrvalue |= tflags;
+
+	pm->pm_md.pm_p4.pm_p4_cccrvalue = cccrvalue;
+	pm->pm_md.pm_p4.pm_p4_escrvalue = escrvalue;
+
+	PMCDBG(MDP,ALL,2, "p4-allocate cccrsel=0x%x cccrval=0x%x "
+	    "escr=%d escrmsr=0x%x escrval=0x%x", pevent->pm_cccr_select,
+	    cccrvalue, escr, pm->pm_md.pm_p4.pm_p4_escrmsr, escrvalue);
+
+	return (0);
+}
+
+/*
+ * release a PMC.
+ */
+
+static int
+p4_release_pmc(int cpu, int ri, struct pmc *pm)
+{
+	enum pmc_p4escr escr;
+	struct p4_cpu *pc;
+
+	KASSERT(ri >= 0 && ri < P4_NPMCS,
+	    ("[p4,%d] illegal row-index %d", __LINE__, ri));
+
+	escr = pm->pm_md.pm_p4.pm_p4_escr;
+
+	PMCDBG(MDP,REL,1, "p4-release cpu=%d ri=%d escr=%d", cpu, ri, escr);
+
+	if (PMC_IS_SYSTEM_MODE(PMC_TO_MODE(pm))) {
+		pc  = p4_pcpu[P4_TO_HTT_PRIMARY(cpu)];
+
+		KASSERT(pc->pc_p4pmcs[ri].phw_pmc == NULL,
+		    ("[p4,%d] releasing configured PMC ri=%d", __LINE__, ri));
+
+		P4_ESCR_UNMARK_ROW_STANDALONE(escr);
+		KASSERT(pc->pc_escrs[escr] == ri,
+		    ("[p4,%d] escr[%d] not allocated to ri %d", __LINE__,
+			escr, ri));
+	        pc->pc_escrs[escr] = P4_INVALID_PMC_INDEX; /* mark as free */
+	} else
+		P4_ESCR_UNMARK_ROW_THREAD(escr);
+
+	return (0);
+}
+
+/*
+ * Start a PMC
+ */
+
+static int
+p4_start_pmc(int cpu, int ri)
+{
+	int rc;
+	struct pmc *pm;
+	struct p4_cpu *pc;
+	struct p4pmc_descr *pd;
+	uint32_t cccrvalue, cccrtbits, escrvalue, escrmsr, escrtbits;
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[p4,%d] illegal CPU value %d", __LINE__, cpu));
+	KASSERT(ri >= 0 && ri < P4_NPMCS,
+	    ("[p4,%d] illegal row-index %d", __LINE__, ri));
+
+	pc = p4_pcpu[P4_TO_HTT_PRIMARY(cpu)];
+	pm = pc->pc_p4pmcs[ri].phw_pmc;
+	pd = &p4_pmcdesc[ri];
+
+	KASSERT(pm != NULL,
+	    ("[p4,%d] starting cpu%d,pmc%d with null pmc", __LINE__, cpu, ri));
+
+	PMCDBG(MDP,STA,1, "p4-start cpu=%d ri=%d", cpu, ri);
+
+	KASSERT(pd->pm_descr.pd_class == PMC_CLASS_P4,
+	    ("[p4,%d] wrong PMC class %d", __LINE__,
+		pd->pm_descr.pd_class));
+
+	/* retrieve the desired CCCR/ESCR values from the PMC */
+	cccrvalue = pm->pm_md.pm_p4.pm_p4_cccrvalue;
+	escrvalue = pm->pm_md.pm_p4.pm_p4_escrvalue;
+	escrmsr   = pm->pm_md.pm_p4.pm_p4_escrmsr;
+
+	/* extract and zero the logical processor selection bits */
+	cccrtbits = cccrvalue & P4_CCCR_OVF_PMI_T0;
+	escrtbits = escrvalue & (P4_ESCR_T0_OS|P4_ESCR_T0_USR);
+	cccrvalue &= ~P4_CCCR_OVF_PMI_T0;
+	escrvalue &= ~(P4_ESCR_T0_OS|P4_ESCR_T0_USR);
+
+	if (P4_CPU_IS_HTT_SECONDARY(cpu)) { /* shift T0 bits to T1 position */
+		cccrtbits <<= 1;
+		escrtbits >>= 2;
+	}
+
+	/* start system mode PMCs directly */
+	if (PMC_IS_SYSTEM_MODE(PMC_TO_MODE(pm))) {
+		wrmsr(escrmsr, escrvalue | escrtbits);
+		wrmsr(pd->pm_cccr_msr, cccrvalue | cccrtbits | P4_CCCR_ENABLE);
+		return 0;
+	}
+
+	/*
+	 * Thread mode PMCs
+	 *
+	 * On HTT machines, the same PMC could be scheduled on the
+	 * same physical CPU twice (once for each logical CPU), for
+	 * example, if two threads of a multi-threaded process get
+	 * scheduled on the same CPU.
+	 *
+	 */
+
+	mtx_lock_spin(&pc->pc_mtx);
+
+	rc = P4_PCPU_GET_RUNCOUNT(pc,ri);
+	KASSERT(rc == 0 || rc == 1,
+	    ("[p4,%d] illegal runcount cpu=%d ri=%d rc=%d", __LINE__, cpu, ri,
+		rc));
+
+	if (rc == 0) {		/* 1st CPU and the non-HTT case */
+
+		KASSERT(P4_PMC_IS_STOPPED(pd->pm_cccr_msr),
+		    ("[p4,%d] cpu=%d ri=%d cccr=0x%x not stopped", __LINE__,
+			cpu, ri, pd->pm_cccr_msr));
+
+		/* write out the low 40 bits of the saved value to hardware */
+		wrmsr(pd->pm_pmc_msr,
+		    P4_PCPU_PMC_VALUE(pc,ri,cpu) & P4_PERFCTR_MASK);
+
+	} else if (rc == 1) {		/* 2nd CPU */
+
+		/*
+		 * Stop the PMC and retrieve the CCCR and ESCR values
+		 * from their MSRs, and turn on the additional T[0/1]
+		 * bits for the 2nd CPU.
+		 */
+
+		cccrvalue = rdmsr(pd->pm_cccr_msr);
+		wrmsr(pd->pm_cccr_msr, cccrvalue & ~P4_CCCR_ENABLE);
+
+		/* check that the configuration bits read back match the PMC */
+		KASSERT((cccrvalue & P4_CCCR_Tx_MASK) ==
+		    (pm->pm_md.pm_p4.pm_p4_cccrvalue & P4_CCCR_Tx_MASK),
+		    ("[p4,%d] Extra CCCR bits cpu=%d rc=%d ri=%d "
+			"cccr=0x%x PMC=0x%x", __LINE__, cpu, rc, ri,
+			cccrvalue & P4_CCCR_Tx_MASK,
+			pm->pm_md.pm_p4.pm_p4_cccrvalue & P4_CCCR_Tx_MASK));
+		KASSERT(cccrvalue & P4_CCCR_ENABLE,
+		    ("[p4,%d] 2nd cpu rc=%d cpu=%d ri=%d not running",
+			__LINE__, rc, cpu, ri));
+		KASSERT((cccrvalue & cccrtbits) == 0,
+		    ("[p4,%d] CCCR T0/T1 mismatch rc=%d cpu=%d ri=%d"
+		     "cccrvalue=0x%x tbits=0x%x", __LINE__, rc, cpu, ri,
+			cccrvalue, cccrtbits));
+
+		escrvalue = rdmsr(escrmsr);
+
+		KASSERT((escrvalue & P4_ESCR_Tx_MASK) ==
+		    (pm->pm_md.pm_p4.pm_p4_escrvalue & P4_ESCR_Tx_MASK),
+		    ("[p4,%d] Extra ESCR bits cpu=%d rc=%d ri=%d "
+			"escr=0x%x pm=0x%x", __LINE__, cpu, rc, ri,
+			escrvalue & P4_ESCR_Tx_MASK,
+			pm->pm_md.pm_p4.pm_p4_escrvalue & P4_ESCR_Tx_MASK));
+		KASSERT((escrvalue & escrtbits) == 0,
+		    ("[p4,%d] ESCR T0/T1 mismatch rc=%d cpu=%d ri=%d "
+		     "escrmsr=0x%x escrvalue=0x%x tbits=0x%x", __LINE__,
+			rc, cpu, ri, escrmsr, escrvalue, escrtbits));
+	}
+
+	/* Enable the correct bits for this CPU. */
+	escrvalue |= escrtbits;
+	cccrvalue |= cccrtbits | P4_CCCR_ENABLE;
+
+	/* Save HW value at the time of starting hardware */
+	P4_PCPU_HW_VALUE(pc,ri,cpu) = rdmsr(pd->pm_pmc_msr);
+
+	/* Program the ESCR and CCCR and start the PMC */
+	wrmsr(escrmsr, escrvalue);
+	wrmsr(pd->pm_cccr_msr, cccrvalue);
+
+	++rc;
+	P4_PCPU_SET_RUNCOUNT(pc,ri,rc);
+
+	mtx_unlock_spin(&pc->pc_mtx);
+
+	PMCDBG(MDP,STA,2,"p4-start cpu=%d rc=%d ri=%d escr=%d "
+	    "escrmsr=0x%x escrvalue=0x%x cccr_config=0x%x v=%jx", cpu, rc,
+	    ri, pm->pm_md.pm_p4.pm_p4_escr, escrmsr, escrvalue,
+	    cccrvalue, P4_PCPU_HW_VALUE(pc,ri,cpu));
+
+	return (0);
+}
+
+/*
+ * Stop a PMC.
+ */
+
+static int
+p4_stop_pmc(int cpu, int ri)
+{
+	int rc;
+	uint32_t cccrvalue, cccrtbits, escrvalue, escrmsr, escrtbits;
+	struct pmc *pm;
+	struct p4_cpu *pc;
+	struct p4pmc_descr *pd;
+	pmc_value_t tmp;
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[p4,%d] illegal CPU value %d", __LINE__, cpu));
+	KASSERT(ri >= 0 && ri < P4_NPMCS,
+	    ("[p4,%d] illegal row index %d", __LINE__, ri));
+
+	pd = &p4_pmcdesc[ri];
+	pc = p4_pcpu[P4_TO_HTT_PRIMARY(cpu)];
+	pm = pc->pc_p4pmcs[ri].phw_pmc;
+
+	KASSERT(pm != NULL,
+	    ("[p4,%d] null pmc for cpu%d, ri%d", __LINE__, cpu, ri));
+
+	PMCDBG(MDP,STO,1, "p4-stop cpu=%d ri=%d", cpu, ri);
+
+	if (PMC_IS_SYSTEM_MODE(PMC_TO_MODE(pm))) {
+		wrmsr(pd->pm_cccr_msr,
+		    pm->pm_md.pm_p4.pm_p4_cccrvalue & ~P4_CCCR_ENABLE);
+		return (0);
+	}
+
+	/*
+	 * Thread mode PMCs.
+	 *
+	 * On HTT machines, this PMC may be in use by two threads
+	 * running on two logical CPUS.  Thus we look at the
+	 * 'runcount' field and only turn off the appropriate TO/T1
+	 * bits (and keep the PMC running) if two logical CPUs were
+	 * using the PMC.
+	 *
+	 */
+
+	/* bits to mask */
+	cccrtbits = P4_CCCR_OVF_PMI_T0;
+	escrtbits = P4_ESCR_T0_OS | P4_ESCR_T0_USR;
+	if (P4_CPU_IS_HTT_SECONDARY(cpu)) {
+		cccrtbits <<= 1;
+		escrtbits >>= 2;
+	}
+
+	mtx_lock_spin(&pc->pc_mtx);
+
+	rc = P4_PCPU_GET_RUNCOUNT(pc,ri);
+
+	KASSERT(rc == 2 || rc == 1,
+	    ("[p4,%d] illegal runcount cpu=%d ri=%d rc=%d", __LINE__, cpu, ri,
+		rc));
+
+	--rc;
+
+	P4_PCPU_SET_RUNCOUNT(pc,ri,rc);
+
+	/* Stop this PMC */
+	cccrvalue = rdmsr(pd->pm_cccr_msr);
+	wrmsr(pd->pm_cccr_msr, cccrvalue & ~P4_CCCR_ENABLE);
+
+	escrmsr   = pm->pm_md.pm_p4.pm_p4_escrmsr;
+	escrvalue = rdmsr(escrmsr);
+
+	/* The current CPU should be running on this PMC */
+	KASSERT(escrvalue & escrtbits,
+	    ("[p4,%d] ESCR T0/T1 mismatch cpu=%d rc=%d ri=%d escrmsr=0x%x "
+		"escrvalue=0x%x tbits=0x%x", __LINE__, cpu, rc, ri, escrmsr,
+		escrvalue, escrtbits));
+	KASSERT(PMC_IS_COUNTING_MODE(PMC_TO_MODE(pm)) ||
+	    (cccrvalue & cccrtbits),
+	    ("[p4,%d] CCCR T0/T1 mismatch cpu=%d ri=%d cccrvalue=0x%x "
+		"tbits=0x%x", __LINE__, cpu, ri, cccrvalue, cccrtbits));
+
+	/* get the current hardware reading */
+	tmp = rdmsr(pd->pm_pmc_msr);
+
+	if (rc == 1) {		/* need to keep the PMC running */
+		escrvalue &= ~escrtbits;
+		cccrvalue &= ~cccrtbits;
+		wrmsr(escrmsr, escrvalue);
+		wrmsr(pd->pm_cccr_msr, cccrvalue);
+	}
+
+	mtx_unlock_spin(&pc->pc_mtx);
+
+	PMCDBG(MDP,STO,2, "p4-stop cpu=%d rc=%d ri=%d escrmsr=0x%x "
+	    "escrval=0x%x cccrval=0x%x v=%jx", cpu, rc, ri, escrmsr,
+	    escrvalue, cccrvalue, tmp);
+
+	if (tmp < P4_PCPU_HW_VALUE(pc,ri,cpu)) /* 40 bit counter overflow */
+		tmp += (P4_PERFCTR_MASK + 1) - P4_PCPU_HW_VALUE(pc,ri,cpu);
+	else
+		tmp -= P4_PCPU_HW_VALUE(pc,ri,cpu);
+
+	P4_PCPU_PMC_VALUE(pc,ri,cpu) += tmp;
+
+	return 0;
+}
+
+/*
+ * Handle an interrupt.
+ *
+ * The hardware sets the CCCR_OVF whenever a counter overflow occurs,
+ * so the handler examines all the 18 CCCR registers, processing the
+ * counters that have overflowed.
+ *
+ * On HTT machines, the CCCR register is shared and will interrupt
+ * both logical processors if so configured.  Thus multiple logical
+ * CPUs could enter the NMI service routine at the same time.  These
+ * will get serialized using a per-cpu spinlock dedicated for use in
+ * the NMI handler.
+ */
+
+static int
+p4_intr(int cpu, struct trapframe *tf)
+{
+	uint32_t cccrval, ovf_mask, ovf_partner;
+	int did_interrupt, error, ri;
+	struct p4_cpu *pc;
+	struct pmc *pm;
+	pmc_value_t v;
+
+	PMCDBG(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf,
+	    TRAPF_USERMODE(tf));
+
+	pc = p4_pcpu[P4_TO_HTT_PRIMARY(cpu)];
+
+	ovf_mask = P4_CPU_IS_HTT_SECONDARY(cpu) ?
+	    P4_CCCR_OVF_PMI_T1 : P4_CCCR_OVF_PMI_T0;
+	ovf_mask |= P4_CCCR_OVF;
+	if (p4_system_has_htt)
+		ovf_partner = P4_CPU_IS_HTT_SECONDARY(cpu) ?
+		    P4_CCCR_OVF_PMI_T0 : P4_CCCR_OVF_PMI_T1;
+	else
+		ovf_partner = 0;
+	did_interrupt = 0;
+
+	if (p4_system_has_htt)
+		P4_PCPU_ACQ_INTR_SPINLOCK(pc);
+
+	/*
+	 * Loop through all CCCRs, looking for ones that have
+	 * interrupted this CPU.
+	 */
+	for (ri = 0; ri < P4_NPMCS; ri++) {
+
+		/*
+		 * Check if our partner logical CPU has already marked
+		 * this PMC has having interrupted it.  If so, reset
+		 * the flag and process the interrupt, but leave the
+		 * hardware alone.
+		 */
+		if (p4_system_has_htt && P4_PCPU_GET_INTRFLAG(pc,ri)) {
+			P4_PCPU_SET_INTRFLAG(pc,ri,0);
+			did_interrupt = 1;
+
+			/*
+			 * Ignore de-configured or stopped PMCs.
+			 * Ignore PMCs not in sampling mode.
+			 */
+			pm = pc->pc_p4pmcs[ri].phw_pmc;
+			if (pm == NULL ||
+			    pm->pm_state != PMC_STATE_RUNNING ||
+			    !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) {
+				continue;
+			}
+			(void) pmc_process_interrupt(cpu, pm, tf,
+			    TRAPF_USERMODE(tf));
+			continue;
+		}
+
+		/*
+		 * Fresh interrupt.  Look for the CCCR_OVF bit
+		 * and the OVF_Tx bit for this logical
+		 * processor being set.
+		 */
+		cccrval = rdmsr(P4_CCCR_MSR_FIRST + ri);
+
+		if ((cccrval & ovf_mask) != ovf_mask)
+			continue;
+
+		/*
+		 * If the other logical CPU would also have been
+		 * interrupted due to the PMC being shared, record
+		 * this fact in the per-cpu saved interrupt flag
+		 * bitmask.
+		 */
+		if (p4_system_has_htt && (cccrval & ovf_partner))
+			P4_PCPU_SET_INTRFLAG(pc, ri, 1);
+
+		v = rdmsr(P4_PERFCTR_MSR_FIRST + ri);
+
+		PMCDBG(MDP,INT, 2, "ri=%d v=%jx", ri, v);
+
+		/* Stop the counter, and reset the overflow  bit */
+		cccrval &= ~(P4_CCCR_OVF | P4_CCCR_ENABLE);
+		wrmsr(P4_CCCR_MSR_FIRST + ri, cccrval);
+
+		did_interrupt = 1;
+
+		/*
+		 * Ignore de-configured or stopped PMCs.  Ignore PMCs
+		 * not in sampling mode.
+		 */
+		pm = pc->pc_p4pmcs[ri].phw_pmc;
+
+		if (pm == NULL ||
+		    pm->pm_state != PMC_STATE_RUNNING ||
+		    !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) {
+			continue;
+		}
+
+		/*
+		 * Process the interrupt.  Re-enable the PMC if
+		 * processing was successful.
+		 */
+		error = pmc_process_interrupt(cpu, pm, tf,
+		    TRAPF_USERMODE(tf));
+
+		/*
+		 * Only the first processor executing the NMI handler
+		 * in a HTT pair will restart a PMC, and that too
+		 * only if there were no errors.
+		 */
+		v = P4_RELOAD_COUNT_TO_PERFCTR_VALUE(
+			pm->pm_sc.pm_reloadcount);
+		wrmsr(P4_PERFCTR_MSR_FIRST + ri, v);
+		if (error == 0)
+			wrmsr(P4_CCCR_MSR_FIRST + ri,
+			    cccrval | P4_CCCR_ENABLE);
+	}
+
+	/* allow the other CPU to proceed */
+	if (p4_system_has_htt)
+		P4_PCPU_REL_INTR_SPINLOCK(pc);
+
+	/*
+	 * On Intel P4 CPUs, the PMC 'pcint' entry in the LAPIC gets
+	 * masked when a PMC interrupts the CPU.  We need to unmask
+	 * the interrupt source explicitly.
+	 */
+
+	if (did_interrupt)
+		lapic_reenable_pmc();
+
+	atomic_add_int(did_interrupt ? &pmc_stats.pm_intr_processed :
+	    &pmc_stats.pm_intr_ignored, 1);
+
+	return (did_interrupt);
+}
+
+/*
+ * Describe a CPU's PMC state.
+ */
+
+static int
+p4_describe(int cpu, int ri, struct pmc_info *pi,
+    struct pmc **ppmc)
+{
+	int error;
+	size_t copied;
+	const struct p4pmc_descr *pd;
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[p4,%d] illegal CPU %d", __LINE__, cpu));
+	KASSERT(ri >= 0 && ri < P4_NPMCS,
+	    ("[p4,%d] row-index %d out of range", __LINE__, ri));
+
+	PMCDBG(MDP,OPS,1,"p4-describe cpu=%d ri=%d", cpu, ri);
+
+	if (P4_CPU_IS_HTT_SECONDARY(cpu))
+		return (EINVAL);
+
+	pd  = &p4_pmcdesc[ri];
+
+	if ((error = copystr(pd->pm_descr.pd_name, pi->pm_name,
+	    PMC_NAME_MAX, &copied)) != 0)
+		return (error);
+
+	pi->pm_class = pd->pm_descr.pd_class;
+
+	if (p4_pcpu[cpu]->pc_p4pmcs[ri].phw_state & PMC_PHW_FLAG_IS_ENABLED) {
+		pi->pm_enabled = TRUE;
+		*ppmc          = p4_pcpu[cpu]->pc_p4pmcs[ri].phw_pmc;
+	} else {
+		pi->pm_enabled = FALSE;
+		*ppmc          = NULL;
+	}
+
+	return (0);
+}
+
+/*
+ * Get MSR# for use with RDPMC.
+ */
+
+static int
+p4_get_msr(int ri, uint32_t *msr)
+{
+	KASSERT(ri >= 0 && ri < P4_NPMCS,
+	    ("[p4,%d] ri %d out of range", __LINE__, ri));
+
+	*msr = p4_pmcdesc[ri].pm_pmc_msr - P4_PERFCTR_MSR_FIRST;
+
+	PMCDBG(MDP,OPS, 1, "ri=%d getmsr=0x%x", ri, *msr);
+
+	return 0;
+}
+
+
+int
+pmc_p4_initialize(struct pmc_mdep *md, int ncpus)
+{
+	struct pmc_classdep *pcd;
+	struct p4_event_descr *pe;
+
+	KASSERT(md != NULL, ("[p4,%d] md is NULL", __LINE__));
+	KASSERT(cpu_vendor_id == CPU_VENDOR_INTEL,
+	    ("[p4,%d] Initializing non-intel processor", __LINE__));
+
+	PMCDBG(MDP,INI,1, "%s", "p4-initialize");
+
+	/* Allocate space for pointers to per-cpu descriptors. */
+	p4_pcpu = malloc(sizeof(struct p4_cpu **) * ncpus, M_PMC,
+	    M_ZERO|M_WAITOK);
+
+	/* Fill in the class dependent descriptor. */
+	pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_P4];
+
+	switch (md->pmd_cputype) {
+	case PMC_CPU_INTEL_PIV:
+
+		pcd->pcd_caps		= P4_PMC_CAPS;
+		pcd->pcd_class		= PMC_CLASS_P4;
+		pcd->pcd_num		= P4_NPMCS;
+		pcd->pcd_ri		= md->pmd_npmc;
+		pcd->pcd_width		= 40;
+
+		pcd->pcd_allocate_pmc	= p4_allocate_pmc;
+		pcd->pcd_config_pmc	= p4_config_pmc;
+		pcd->pcd_describe	= p4_describe;
+		pcd->pcd_get_config	= p4_get_config;
+		pcd->pcd_get_msr	= p4_get_msr;
+		pcd->pcd_pcpu_fini 	= p4_pcpu_fini;
+		pcd->pcd_pcpu_init    	= p4_pcpu_init;
+		pcd->pcd_read_pmc	= p4_read_pmc;
+		pcd->pcd_release_pmc	= p4_release_pmc;
+		pcd->pcd_start_pmc	= p4_start_pmc;
+		pcd->pcd_stop_pmc	= p4_stop_pmc;
+		pcd->pcd_write_pmc	= p4_write_pmc;
+
+		md->pmd_pcpu_fini	= NULL;
+		md->pmd_pcpu_init	= NULL;
+		md->pmd_intr	    	= p4_intr;
+		md->pmd_npmc	       += P4_NPMCS;
+
+		/* model specific configuration */
+		if ((cpu_id & 0xFFF) < 0xF27) {
+
+			/*
+			 * On P4 and Xeon with CPUID < (Family 15,
+			 * Model 2, Stepping 7), only one ESCR is
+			 * available for the IOQ_ALLOCATION event.
+			 */
+
+			pe = p4_find_event(PMC_EV_P4_IOQ_ALLOCATION);
+			pe->pm_escrs[1] = P4_ESCR_NONE;
+		}
+
+		break;
+
+	default:
+		KASSERT(0,("[p4,%d] Unknown CPU type", __LINE__));
+		return ENOSYS;
+	}
+
+	return (0);
+}
+
+void
+pmc_p4_finalize(struct pmc_mdep *md)
+{
+#if	defined(INVARIANTS)
+	int i, ncpus;
+#endif
+
+	KASSERT(p4_pcpu != NULL,
+	    ("[p4,%d] NULL p4_pcpu", __LINE__));
+
+#if	defined(INVARIANTS)
+	ncpus = pmc_cpu_max();
+	for (i = 0; i < ncpus; i++)
+		KASSERT(p4_pcpu[i] == NULL, ("[p4,%d] non-null pcpu %d",
+		    __LINE__, i));
+#endif
+
+	free(p4_pcpu, M_PMC);
+	p4_pcpu = NULL;
+}
diff --git a/sys/dev/misc/hwpmc/hwpmc_piv.h b/sys/dev/misc/hwpmc/hwpmc_piv.h
new file mode 100644
index 0000000..83b00c0
--- /dev/null
+++ b/sys/dev/misc/hwpmc/hwpmc_piv.h
@@ -0,0 +1,125 @@
+/*-
+ * Copyright (c) 2005, Joseph Koshy
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: src/sys/dev/hwpmc/hwpmc_piv.h,v 1.2 2008/11/09 17:37:54 jkoshy Exp $
+ */
+
+/* Machine dependent interfaces */
+
+#ifndef _DEV_HWPMC_PIV_H_
+#define	_DEV_HWPMC_PIV_H_ 1
+
+/* Intel P4 PMCs */
+
+#define	P4_NPMCS		18
+#define	P4_NESCR		45
+#define	P4_INVALID_PMC_INDEX	-1
+#define	P4_MAX_ESCR_PER_EVENT	2
+#define	P4_MAX_PMC_PER_ESCR	3
+
+#define	P4_CCCR_OVF			(1 << 31)
+#define	P4_CCCR_CASCADE			(1 << 30)
+#define	P4_CCCR_OVF_PMI_T1		(1 << 27)
+#define	P4_CCCR_OVF_PMI_T0		(1 << 26)
+#define	P4_CCCR_FORCE_OVF		(1 << 25)
+#define	P4_CCCR_EDGE			(1 << 24)
+#define	P4_CCCR_THRESHOLD_SHIFT		20
+#define	P4_CCCR_THRESHOLD_MASK		0x00F00000
+#define	P4_CCCR_TO_THRESHOLD(C)		(((C) << P4_CCCR_THRESHOLD_SHIFT) & \
+	P4_CCCR_THRESHOLD_MASK)
+#define	P4_CCCR_COMPLEMENT		(1 << 19)
+#define	P4_CCCR_COMPARE			(1 << 18)
+#define	P4_CCCR_ACTIVE_THREAD_SHIFT	16
+#define	P4_CCCR_ACTIVE_THREAD_MASK	0x00030000
+#define	P4_CCCR_TO_ACTIVE_THREAD(T)	(((T) << P4_CCCR_ACTIVE_THREAD_SHIFT) & \
+	P4_CCCR_ACTIVE_THREAD_MASK)
+#define	P4_CCCR_ESCR_SELECT_SHIFT	13
+#define	P4_CCCR_ESCR_SELECT_MASK	0x0000E000
+#define	P4_CCCR_TO_ESCR_SELECT(E)	(((E) << P4_CCCR_ESCR_SELECT_SHIFT) & \
+	P4_CCCR_ESCR_SELECT_MASK)
+#define	P4_CCCR_ENABLE			(1 << 12)
+#define	P4_CCCR_VALID_BITS		(P4_CCCR_OVF | P4_CCCR_CASCADE | \
+    P4_CCCR_OVF_PMI_T1 | P4_CCCR_OVF_PMI_T0 | P4_CCCR_FORCE_OVF | 	 \
+    P4_CCCR_EDGE | P4_CCCR_THRESHOLD_MASK | P4_CCCR_COMPLEMENT |	 \
+    P4_CCCR_COMPARE | P4_CCCR_ESCR_SELECT_MASK | P4_CCCR_ENABLE)
+
+#define	P4_ESCR_EVENT_SELECT_SHIFT	25
+#define	P4_ESCR_EVENT_SELECT_MASK	0x7E000000
+#define	P4_ESCR_TO_EVENT_SELECT(E)	(((E) << P4_ESCR_EVENT_SELECT_SHIFT) & \
+	P4_ESCR_EVENT_SELECT_MASK)
+#define	P4_ESCR_EVENT_MASK_SHIFT	9
+#define	P4_ESCR_EVENT_MASK_MASK		0x01FFFE00
+#define	P4_ESCR_TO_EVENT_MASK(M)	(((M) << P4_ESCR_EVENT_MASK_SHIFT) & \
+	P4_ESCR_EVENT_MASK_MASK)
+#define	P4_ESCR_TAG_VALUE_SHIFT		5
+#define	P4_ESCR_TAG_VALUE_MASK		0x000001E0
+#define	P4_ESCR_TO_TAG_VALUE(T)		(((T) << P4_ESCR_TAG_VALUE_SHIFT) & \
+	P4_ESCR_TAG_VALUE_MASK)
+#define	P4_ESCR_TAG_ENABLE 		0x00000010
+#define	P4_ESCR_T0_OS			0x00000008
+#define	P4_ESCR_T0_USR			0x00000004
+#define	P4_ESCR_T1_OS			0x00000002
+#define	P4_ESCR_T1_USR			0x00000001
+#define	P4_ESCR_OS			P4_ESCR_T0_OS
+#define	P4_ESCR_USR			P4_ESCR_T0_USR
+#define	P4_ESCR_VALID_BITS		(P4_ESCR_EVENT_SELECT_MASK |	\
+    P4_ESCR_EVENT_MASK_MASK | P4_ESCR_TAG_VALUE_MASK | 			\
+    P4_ESCR_TAG_ENABLE | P4_ESCR_T0_OS | P4_ESCR_T0_USR | P4_ESCR_T1_OS \
+    P4_ESCR_T1_USR)
+
+#define	P4_PERFCTR_MASK			0xFFFFFFFFFFLL /* 40 bits */
+#define	P4_PERFCTR_OVERFLOWED(PMC)	((rdpmc(PMC) & (1LL << 39)) == 0)
+
+#define	P4_CCCR_MSR_FIRST		0x360 /* MSR_BPU_CCCR0 */
+#define	P4_PERFCTR_MSR_FIRST		0x300 /* MSR_BPU_COUNTER0 */
+
+#define	P4_RELOAD_COUNT_TO_PERFCTR_VALUE(V)	(1 - (V))
+#define	P4_PERFCTR_VALUE_TO_RELOAD_COUNT(P)	(1 - (P))
+
+struct pmc_md_p4_op_pmcallocate {
+	uint32_t	pm_p4_cccrconfig;
+	uint32_t	pm_p4_escrconfig;
+};
+
+#ifdef _KERNEL
+
+/* MD extension for 'struct pmc' */
+struct pmc_md_p4_pmc {
+	uint32_t	pm_p4_cccrvalue;
+	uint32_t	pm_p4_escrvalue;
+	uint32_t	pm_p4_escr;
+	uint32_t	pm_p4_escrmsr;
+};
+
+
+/*
+ * Prototypes
+ */
+
+int	pmc_p4_initialize(struct pmc_mdep *_md, int _ncpus);
+void	pmc_p4_finalize(struct pmc_mdep *md);
+
+#endif /* _KERNEL */
+#endif /* _DEV_HWPMC_PIV_H_ */
diff --git a/sys/dev/misc/hwpmc/hwpmc_ppro.c b/sys/dev/misc/hwpmc/hwpmc_ppro.c
new file mode 100644
index 0000000..84d301e
--- /dev/null
+++ b/sys/dev/misc/hwpmc/hwpmc_ppro.c
@@ -0,0 +1,866 @@
+/*-
+ * Copyright (c) 2003-2005,2008 Joseph Koshy
+ * Copyright (c) 2007 The FreeBSD Foundation
+ * All rights reserved.
+ *
+ * Portions of this software were developed by A. Joseph Koshy under
+ * sponsorship from the FreeBSD Foundation and Google, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: src/sys/dev/hwpmc/hwpmc_ppro.c,v 1.17 2009/08/14 21:05:08 jhb Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/lock.h>
+#include <sys/mutex.h>
+#include <sys/pmc.h>
+#include <sys/pmckern.h>
+#include <sys/smp.h>
+#include <sys/systm.h>
+
+#include <machine/intr_machdep.h>
+#include <machine/apicvar.h>
+#include <machine/cpu.h>
+#include <machine/cpufunc.h>
+#include <machine/cputypes.h>
+#include <machine/md_var.h>
+#include <machine/pmc_mdep.h>
+#include <machine/specialreg.h>
+
+/*
+ * PENTIUM PRO SUPPORT
+ *
+ * Quirks:
+ *
+ * - Both PMCs are enabled by a single bit P6_EVSEL_EN in performance
+ *   counter '0'.  This bit needs to be '1' if any of the two
+ *   performance counters are in use.  Perf counters can also be
+ *   switched off by writing zeros to their EVSEL register.
+ *
+ * - While the width of these counters is 40 bits, we do not appear to
+ *   have a way of writing 40 bits to the counter MSRs.  A WRMSR
+ *   instruction will sign extend bit 31 of the value being written to
+ *   the perf counter -- a value of 0x80000000 written to an perf
+ *   counter register will be sign extended to 0xFF80000000.
+ *
+ *   This quirk primarily affects thread-mode PMCs in counting mode, as
+ *   these PMCs read and write PMC registers at every context switch.
+ */
+
+struct p6pmc_descr {
+	struct pmc_descr pm_descr; /* common information */
+	uint32_t	pm_pmc_msr;
+	uint32_t	pm_evsel_msr;
+};
+
+static struct p6pmc_descr p6_pmcdesc[P6_NPMCS] = {
+
+#define	P6_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_USER | PMC_CAP_SYSTEM | \
+    PMC_CAP_EDGE | PMC_CAP_THRESHOLD | PMC_CAP_READ | PMC_CAP_WRITE |	 \
+    PMC_CAP_INVERT | PMC_CAP_QUALIFIER)
+
+	/* PMC 0 */
+	{
+		.pm_descr =
+		{
+			.pd_name  ="P6-0",
+			.pd_class = PMC_CLASS_P6,
+			.pd_caps  = P6_PMC_CAPS,
+			.pd_width = 40
+		},
+		.pm_pmc_msr   = P6_MSR_PERFCTR0,
+		.pm_evsel_msr = P6_MSR_EVSEL0
+	},
+
+	/* PMC 1 */
+	{
+		.pm_descr =
+		{
+			.pd_name  ="P6-1",
+			.pd_class = PMC_CLASS_P6,
+			.pd_caps  = P6_PMC_CAPS,
+			.pd_width = 40
+		},
+		.pm_pmc_msr   = P6_MSR_PERFCTR1,
+		.pm_evsel_msr = P6_MSR_EVSEL1
+	}
+};
+
+static enum pmc_cputype p6_cputype;
+
+/*
+ * P6 Event descriptor
+ *
+ * The 'pm_flags' field has the following structure:
+ * - The upper 4 bits are used to track which counter an event is valid on.
+ * - The lower bits form a bitmask of flags indicating support for the event
+ *   on a given CPU.
+ */
+
+struct p6_event_descr {
+	const enum pmc_event pm_event;
+	uint32_t	     pm_evsel;
+	uint32_t	     pm_flags;
+	uint32_t	     pm_unitmask;
+};
+
+#define	P6F_CTR(C)	(1 << (28 + (C)))
+#define	P6F_CTR0	P6F_CTR(0)
+#define	P6F_CTR1	P6F_CTR(1)
+#define	P6F(CPU)	(1 << ((CPU) - PMC_CPU_INTEL_P6))
+#define	_P6F(C)		P6F(PMC_CPU_INTEL_##C)
+#define	P6F_P6		_P6F(P6)
+#define	P6F_CL		_P6F(CL)
+#define	P6F_PII		_P6F(PII)
+#define	P6F_PIII	_P6F(PIII)
+#define	P6F_PM		_P6F(PM)
+#define	P6F_ALL_CPUS	(P6F_P6 | P6F_PII | P6F_CL | P6F_PIII | P6F_PM)
+#define	P6F_ALL_CTRS	(P6F_CTR0 | P6F_CTR1)
+#define	P6F_ALL		(P6F_ALL_CPUS | P6F_ALL_CTRS)
+
+#define	P6_EVENT_VALID_FOR_CPU(P,CPU)	((P)->pm_flags & P6F(CPU))
+#define	P6_EVENT_VALID_FOR_CTR(P,CTR)	((P)->pm_flags & P6F_CTR(CTR))
+
+static const struct p6_event_descr p6_events[] = {
+
+#define	P6_EVDESCR(NAME, EVSEL, FLAGS, UMASK)	\
+	{					\
+		.pm_event = PMC_EV_P6_##NAME,	\
+		.pm_evsel = (EVSEL),		\
+		.pm_flags = (FLAGS),		\
+		.pm_unitmask = (UMASK)		\
+	}
+
+P6_EVDESCR(DATA_MEM_REFS,		0x43, P6F_ALL, 0x00),
+P6_EVDESCR(DCU_LINES_IN,		0x45, P6F_ALL, 0x00),
+P6_EVDESCR(DCU_M_LINES_IN,		0x46, P6F_ALL, 0x00),
+P6_EVDESCR(DCU_M_LINES_OUT,		0x47, P6F_ALL, 0x00),
+P6_EVDESCR(DCU_MISS_OUTSTANDING,	0x47, P6F_ALL, 0x00),
+P6_EVDESCR(IFU_FETCH,			0x80, P6F_ALL, 0x00),
+P6_EVDESCR(IFU_FETCH_MISS,		0x81, P6F_ALL, 0x00),
+P6_EVDESCR(ITLB_MISS,			0x85, P6F_ALL, 0x00),
+P6_EVDESCR(IFU_MEM_STALL,		0x86, P6F_ALL, 0x00),
+P6_EVDESCR(ILD_STALL,			0x87, P6F_ALL, 0x00),
+P6_EVDESCR(L2_IFETCH,			0x28, P6F_ALL, 0x0F),
+P6_EVDESCR(L2_LD,			0x29, P6F_ALL, 0x0F),
+P6_EVDESCR(L2_ST,			0x2A, P6F_ALL, 0x0F),
+P6_EVDESCR(L2_LINES_IN,			0x24, P6F_ALL, 0x0F),
+P6_EVDESCR(L2_LINES_OUT,		0x26, P6F_ALL, 0x0F),
+P6_EVDESCR(L2_M_LINES_INM,		0x25, P6F_ALL, 0x00),
+P6_EVDESCR(L2_M_LINES_OUTM,		0x27, P6F_ALL, 0x0F),
+P6_EVDESCR(L2_RQSTS,			0x2E, P6F_ALL, 0x0F),
+P6_EVDESCR(L2_ADS,			0x21, P6F_ALL, 0x00),
+P6_EVDESCR(L2_DBUS_BUSY,		0x22, P6F_ALL, 0x00),
+P6_EVDESCR(L2_DBUS_BUSY_RD,		0x23, P6F_ALL, 0x00),
+P6_EVDESCR(BUS_DRDY_CLOCKS,		0x62, P6F_ALL, 0x20),
+P6_EVDESCR(BUS_LOCK_CLOCKS,		0x63, P6F_ALL, 0x20),
+P6_EVDESCR(BUS_REQ_OUTSTANDING,		0x60, P6F_ALL, 0x00),
+P6_EVDESCR(BUS_TRAN_BRD,		0x65, P6F_ALL, 0x20),
+P6_EVDESCR(BUS_TRAN_RFO,		0x66, P6F_ALL, 0x20),
+P6_EVDESCR(BUS_TRANS_WB,		0x67, P6F_ALL, 0x20),
+P6_EVDESCR(BUS_TRAN_IFETCH,		0x68, P6F_ALL, 0x20),
+P6_EVDESCR(BUS_TRAN_INVAL,		0x69, P6F_ALL, 0x20),
+P6_EVDESCR(BUS_TRAN_PWR,		0x6A, P6F_ALL, 0x20),
+P6_EVDESCR(BUS_TRANS_P,			0x6B, P6F_ALL, 0x20),
+P6_EVDESCR(BUS_TRANS_IO,		0x6C, P6F_ALL, 0x20),
+P6_EVDESCR(BUS_TRAN_DEF,		0x6D, P6F_ALL, 0x20),
+P6_EVDESCR(BUS_TRAN_BURST,		0x6E, P6F_ALL, 0x20),
+P6_EVDESCR(BUS_TRAN_ANY,		0x70, P6F_ALL, 0x20),
+P6_EVDESCR(BUS_TRAN_MEM,		0x6F, P6F_ALL, 0x20),
+P6_EVDESCR(BUS_DATA_RCV,		0x64, P6F_ALL, 0x00),
+P6_EVDESCR(BUS_BNR_DRV,			0x61, P6F_ALL, 0x00),
+P6_EVDESCR(BUS_HIT_DRV,			0x7A, P6F_ALL, 0x00),
+P6_EVDESCR(BUS_HITM_DRV,		0x7B, P6F_ALL, 0x00),
+P6_EVDESCR(BUS_SNOOP_STALL,		0x7E, P6F_ALL, 0x00),
+P6_EVDESCR(FLOPS,			0xC1, P6F_ALL_CPUS | P6F_CTR0, 0x00),
+P6_EVDESCR(FP_COMPS_OPS_EXE,		0x10, P6F_ALL_CPUS | P6F_CTR0, 0x00),
+P6_EVDESCR(FP_ASSIST,			0x11, P6F_ALL_CPUS | P6F_CTR1, 0x00),
+P6_EVDESCR(MUL,				0x12, P6F_ALL_CPUS | P6F_CTR1, 0x00),
+P6_EVDESCR(DIV,				0x13, P6F_ALL_CPUS | P6F_CTR1, 0x00),
+P6_EVDESCR(CYCLES_DIV_BUSY,		0x14, P6F_ALL_CPUS | P6F_CTR0, 0x00),
+P6_EVDESCR(LD_BLOCKS,			0x03, P6F_ALL, 0x00),
+P6_EVDESCR(SB_DRAINS,			0x04, P6F_ALL, 0x00),
+P6_EVDESCR(MISALIGN_MEM_REF,		0x05, P6F_ALL, 0x00),
+P6_EVDESCR(EMON_KNI_PREF_DISPATCHED,	0x07, P6F_PIII | P6F_ALL_CTRS, 0x03),
+P6_EVDESCR(EMON_KNI_PREF_MISS,		0x4B, P6F_PIII | P6F_ALL_CTRS, 0x03),
+P6_EVDESCR(INST_RETIRED,		0xC0, P6F_ALL, 0x00),
+P6_EVDESCR(UOPS_RETIRED,		0xC2, P6F_ALL, 0x00),
+P6_EVDESCR(INST_DECODED,		0xD0, P6F_ALL, 0x00),
+P6_EVDESCR(EMON_KNI_INST_RETIRED,	0xD8, P6F_PIII | P6F_ALL_CTRS, 0x01),
+P6_EVDESCR(EMON_KNI_COMP_INST_RET,	0xD9, P6F_PIII | P6F_ALL_CTRS, 0x01),
+P6_EVDESCR(HW_INT_RX,			0xC8, P6F_ALL, 0x00),
+P6_EVDESCR(CYCLES_INT_MASKED,		0xC6, P6F_ALL, 0x00),
+P6_EVDESCR(CYCLES_INT_PENDING_AND_MASKED, 0xC7, P6F_ALL, 0x00),
+P6_EVDESCR(BR_INST_RETIRED,		0xC4, P6F_ALL, 0x00),
+P6_EVDESCR(BR_MISS_PRED_RETIRED,	0xC5, P6F_ALL, 0x00),
+P6_EVDESCR(BR_TAKEN_RETIRED,		0xC9, P6F_ALL, 0x00),
+P6_EVDESCR(BR_MISS_PRED_TAKEN_RET, 	0xCA, P6F_ALL, 0x00),
+P6_EVDESCR(BR_INST_DECODED,		0xE0, P6F_ALL, 0x00),
+P6_EVDESCR(BTB_MISSES,			0xE2, P6F_ALL, 0x00),
+P6_EVDESCR(BR_BOGUS,			0xE4, P6F_ALL, 0x00),
+P6_EVDESCR(BACLEARS,			0xE6, P6F_ALL, 0x00),
+P6_EVDESCR(RESOURCE_STALLS,		0xA2, P6F_ALL, 0x00),
+P6_EVDESCR(PARTIAL_RAT_STALLS,		0xD2, P6F_ALL, 0x00),
+P6_EVDESCR(SEGMENT_REG_LOADS,		0x06, P6F_ALL, 0x00),
+P6_EVDESCR(CPU_CLK_UNHALTED,		0x79, P6F_ALL, 0x00),
+P6_EVDESCR(MMX_INSTR_EXEC,		0xB0,
+			P6F_ALL_CTRS | P6F_CL | P6F_PII, 0x00),
+P6_EVDESCR(MMX_SAT_INSTR_EXEC,		0xB1,
+			P6F_ALL_CTRS | P6F_PII | P6F_PIII, 0x00),
+P6_EVDESCR(MMX_UOPS_EXEC,		0xB2,
+			P6F_ALL_CTRS | P6F_PII | P6F_PIII, 0x0F),
+P6_EVDESCR(MMX_INSTR_TYPE_EXEC,		0xB3,
+			P6F_ALL_CTRS | P6F_PII | P6F_PIII, 0x3F),
+P6_EVDESCR(FP_MMX_TRANS,		0xCC,
+			P6F_ALL_CTRS | P6F_PII | P6F_PIII, 0x01),
+P6_EVDESCR(MMX_ASSIST,			0xCD,
+			P6F_ALL_CTRS | P6F_PII | P6F_PIII, 0x00),
+P6_EVDESCR(MMX_INSTR_RET,		0xCE, P6F_ALL_CTRS | P6F_PII, 0x00),
+P6_EVDESCR(SEG_RENAME_STALLS,		0xD4,
+			P6F_ALL_CTRS | P6F_PII | P6F_PIII, 0x0F),
+P6_EVDESCR(SEG_REG_RENAMES,		0xD5,
+			P6F_ALL_CTRS | P6F_PII | P6F_PIII, 0x0F),
+P6_EVDESCR(RET_SEG_RENAMES,		0xD6,
+			P6F_ALL_CTRS | P6F_PII | P6F_PIII, 0x00),
+P6_EVDESCR(EMON_EST_TRANS,		0x58, P6F_ALL_CTRS | P6F_PM, 0x02),
+P6_EVDESCR(EMON_THERMAL_TRIP,		0x59, P6F_ALL_CTRS | P6F_PM, 0x00),
+P6_EVDESCR(BR_INST_EXEC,		0x88, P6F_ALL_CTRS | P6F_PM, 0x00),
+P6_EVDESCR(BR_MISSP_EXEC,		0x89, P6F_ALL_CTRS | P6F_PM, 0x00),
+P6_EVDESCR(BR_BAC_MISSP_EXEC,		0x8A, P6F_ALL_CTRS | P6F_PM, 0x00),
+P6_EVDESCR(BR_CND_EXEC,			0x8B, P6F_ALL_CTRS | P6F_PM, 0x00),
+P6_EVDESCR(BR_CND_MISSP_EXEC,		0x8C, P6F_ALL_CTRS | P6F_PM, 0x00),
+P6_EVDESCR(BR_IND_EXEC,			0x8D, P6F_ALL_CTRS | P6F_PM, 0x00),
+P6_EVDESCR(BR_IND_MISSP_EXEC,		0x8E, P6F_ALL_CTRS | P6F_PM, 0x00),
+P6_EVDESCR(BR_RET_EXEC,			0x8F, P6F_ALL_CTRS | P6F_PM, 0x00),
+P6_EVDESCR(BR_RET_MISSP_EXEC,		0x90, P6F_ALL_CTRS | P6F_PM, 0x00),
+P6_EVDESCR(BR_RET_BAC_MISSP_EXEC,	0x91, P6F_ALL_CTRS | P6F_PM, 0x00),
+P6_EVDESCR(BR_CALL_EXEC,		0x92, P6F_ALL_CTRS | P6F_PM, 0x00),
+P6_EVDESCR(BR_CALL_MISSP_EXEC,		0x93, P6F_ALL_CTRS | P6F_PM, 0x00),
+P6_EVDESCR(BR_IND_CALL_EXEC,		0x94, P6F_ALL_CTRS | P6F_PM, 0x00),
+P6_EVDESCR(EMON_SIMD_INSTR_RETIRED,	0xCE, P6F_ALL_CTRS | P6F_PM, 0x00),
+P6_EVDESCR(EMON_SYNCH_UOPS,		0xD3, P6F_ALL_CTRS | P6F_PM, 0x00),
+P6_EVDESCR(EMON_ESP_UOPS,		0xD7, P6F_ALL_CTRS | P6F_PM, 0x00),
+P6_EVDESCR(EMON_FUSED_UOPS_RET,		0xDA, P6F_ALL_CTRS | P6F_PM, 0x03),
+P6_EVDESCR(EMON_UNFUSION,		0xDB, P6F_ALL_CTRS | P6F_PM, 0x00),
+P6_EVDESCR(EMON_PREF_RQSTS_UP,		0xF0, P6F_ALL_CTRS | P6F_PM, 0x00),
+P6_EVDESCR(EMON_PREF_RQSTS_DN,		0xD8, P6F_ALL_CTRS | P6F_PM, 0x00),
+P6_EVDESCR(EMON_SSE_SSE2_INST_RETIRED,	0xD8, P6F_ALL_CTRS | P6F_PM, 0x03),
+P6_EVDESCR(EMON_SSE_SSE2_COMP_INST_RETIRED, 0xD9, P6F_ALL_CTRS | P6F_PM, 0x03)
+
+#undef	P6_EVDESCR
+};
+
+#define	P6_NEVENTS	(PMC_EV_P6_LAST - PMC_EV_P6_FIRST + 1)
+
+static const struct p6_event_descr *
+p6_find_event(enum pmc_event ev)
+{
+	int n;
+
+	for (n = 0; n < P6_NEVENTS; n++)
+		if (p6_events[n].pm_event == ev)
+			break;
+	if (n == P6_NEVENTS)
+		return NULL;
+	return &p6_events[n];
+}
+
+/*
+ * Per-CPU data structure for P6 class CPUs
+ *
+ * [common stuff]
+ * [flags for maintaining PMC start/stop state]
+ * [3 struct pmc_hw pointers]
+ * [3 struct pmc_hw structures]
+ */
+
+struct p6_cpu {
+	struct pmc_hw	pc_p6pmcs[P6_NPMCS];
+	uint32_t	pc_state;
+};
+
+static struct p6_cpu **p6_pcpu;
+
+/*
+ * If CTR1 is active, we need to keep the 'EN' bit if CTR0 set,
+ * with the rest of CTR0 being zero'ed out.
+ */
+#define	P6_SYNC_CTR_STATE(PC) do {				\
+		uint32_t _config, _enable;			\
+		_enable = 0;					\
+		if ((PC)->pc_state & 0x02)			\
+			_enable |= P6_EVSEL_EN;			\
+		if ((PC)->pc_state & 0x01)			\
+			_config = rdmsr(P6_MSR_EVSEL0) | 	\
+			    P6_EVSEL_EN;			\
+		else						\
+			_config = 0;				\
+		wrmsr(P6_MSR_EVSEL0, _config | _enable);	\
+	} while (0)
+
+#define	P6_MARK_STARTED(PC,RI) do {				\
+		(PC)->pc_state |= (1 << ((RI)-1));		\
+	} while (0)
+
+#define	P6_MARK_STOPPED(PC,RI) do {				\
+		(PC)->pc_state &= ~(1<< ((RI)-1));		\
+	} while (0)
+
+static int
+p6_pcpu_init(struct pmc_mdep *md, int cpu)
+{
+	int first_ri, n;
+	struct p6_cpu *p6c;
+	struct pmc_cpu *pc;
+	struct pmc_hw *phw;
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[p6,%d] bad cpu %d", __LINE__, cpu));
+
+	PMCDBG(MDP,INI,0,"p6-init cpu=%d", cpu);
+
+	p6c = malloc(sizeof (struct p6_cpu), M_PMC, M_WAITOK|M_ZERO);
+	pc = pmc_pcpu[cpu];
+
+	KASSERT(pc != NULL, ("[p6,%d] cpu %d null per-cpu", __LINE__, cpu));
+
+	phw = p6c->pc_p6pmcs;
+	p6_pcpu[cpu] = p6c;
+
+	first_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_P6].pcd_ri;
+
+	for (n = 0; n < P6_NPMCS; n++, phw++) {
+		phw->phw_state   = PMC_PHW_FLAG_IS_ENABLED |
+		    PMC_PHW_CPU_TO_STATE(cpu) | PMC_PHW_INDEX_TO_STATE(n);
+		phw->phw_pmc     = NULL;
+		pc->pc_hwpmcs[n + first_ri] = phw;
+	}
+
+	return (0);
+}
+
+static int
+p6_pcpu_fini(struct pmc_mdep *md, int cpu)
+{
+	int first_ri, n;
+	struct p6_cpu *p6c;
+	struct pmc_cpu *pc;
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[p6,%d] bad cpu %d", __LINE__, cpu));
+
+	PMCDBG(MDP,INI,0,"p6-cleanup cpu=%d", cpu);
+
+	p6c = p6_pcpu[cpu];
+	p6_pcpu[cpu] = NULL;
+
+	KASSERT(p6c != NULL, ("[p6,%d] null pcpu", __LINE__));
+
+	free(p6c, M_PMC);
+
+	first_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_P6].pcd_ri;
+	pc = pmc_pcpu[cpu];
+	for (n = 0; n < P6_NPMCS; n++)
+		pc->pc_hwpmcs[n + first_ri] = NULL;
+
+	return (0);
+}
+
+static int
+p6_read_pmc(int cpu, int ri, pmc_value_t *v)
+{
+	struct pmc *pm;
+	struct p6pmc_descr *pd;
+	pmc_value_t tmp;
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[p6,%d] illegal cpu value %d", __LINE__, cpu));
+	KASSERT(ri >= 0 && ri < P6_NPMCS,
+	    ("[p6,%d] illegal row-index %d", __LINE__, ri));
+
+	pm = p6_pcpu[cpu]->pc_p6pmcs[ri].phw_pmc;
+	pd = &p6_pmcdesc[ri];
+
+	KASSERT(pm,
+	    ("[p6,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, ri));
+
+	tmp = rdmsr(pd->pm_pmc_msr) & P6_PERFCTR_READ_MASK;
+	if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
+		*v = P6_PERFCTR_VALUE_TO_RELOAD_COUNT(tmp);
+	else
+		*v = tmp;
+
+	PMCDBG(MDP,REA,1, "p6-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri,
+	    pd->pm_pmc_msr, *v);
+
+	return (0);
+}
+
+static int
+p6_write_pmc(int cpu, int ri, pmc_value_t v)
+{
+	struct pmc *pm;
+	struct p6pmc_descr *pd;
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[p6,%d] illegal cpu value %d", __LINE__, cpu));
+	KASSERT(ri >= 0 && ri < P6_NPMCS,
+	    ("[p6,%d] illegal row-index %d", __LINE__, ri));
+
+	pm = p6_pcpu[cpu]->pc_p6pmcs[ri].phw_pmc;
+	pd = &p6_pmcdesc[ri];
+
+	KASSERT(pm,
+	    ("[p6,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, ri));
+
+	PMCDBG(MDP,WRI,1, "p6-write cpu=%d ri=%d msr=0x%x v=%jx", cpu, ri,
+	    pd->pm_pmc_msr, v);
+
+	if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
+		v = P6_RELOAD_COUNT_TO_PERFCTR_VALUE(v);
+
+	wrmsr(pd->pm_pmc_msr, v & P6_PERFCTR_WRITE_MASK);
+
+	return (0);
+}
+
+static int
+p6_config_pmc(int cpu, int ri, struct pmc *pm)
+{
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[p6,%d] illegal CPU %d", __LINE__, cpu));
+
+	KASSERT(ri >= 0 && ri < P6_NPMCS,
+	    ("[p6,%d] illegal row-index %d", __LINE__, ri));
+
+	PMCDBG(MDP,CFG,1, "p6-config cpu=%d ri=%d pm=%p", cpu, ri, pm);
+
+	KASSERT(p6_pcpu[cpu] != NULL, ("[p6,%d] null per-cpu %d", __LINE__,
+	    cpu));
+
+	p6_pcpu[cpu]->pc_p6pmcs[ri].phw_pmc = pm;
+
+	return (0);
+}
+
+/*
+ * Retrieve a configured PMC pointer from hardware state.
+ */
+
+static int
+p6_get_config(int cpu, int ri, struct pmc **ppm)
+{
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[p6,%d] illegal CPU %d", __LINE__, cpu));
+	KASSERT(ri >= 0 && ri < P6_NPMCS,
+	    ("[p6,%d] illegal row-index %d", __LINE__, ri));
+
+	*ppm = p6_pcpu[cpu]->pc_p6pmcs[ri].phw_pmc;
+
+	return (0);
+}
+
+
+/*
+ * A pmc may be allocated to a given row index if:
+ * - the event is valid for this CPU
+ * - the event is valid for this counter index
+ */
+
+static int
+p6_allocate_pmc(int cpu, int ri, struct pmc *pm,
+    const struct pmc_op_pmcallocate *a)
+{
+	uint32_t allowed_unitmask, caps, config, unitmask;
+	const struct p6pmc_descr *pd;
+	const struct p6_event_descr *pevent;
+	enum pmc_event ev;
+
+	(void) cpu;
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[p6,%d] illegal CPU %d", __LINE__, cpu));
+	KASSERT(ri >= 0 && ri < P6_NPMCS,
+	    ("[p6,%d] illegal row-index value %d", __LINE__, ri));
+
+	pd = &p6_pmcdesc[ri];
+
+	PMCDBG(MDP,ALL,1, "p6-allocate ri=%d class=%d pmccaps=0x%x "
+	    "reqcaps=0x%x", ri, pd->pm_descr.pd_class, pd->pm_descr.pd_caps,
+	    pm->pm_caps);
+
+	/* check class */
+	if (pd->pm_descr.pd_class != a->pm_class)
+		return (EINVAL);
+
+	/* check requested capabilities */
+	caps = a->pm_caps;
+	if ((pd->pm_descr.pd_caps & caps) != caps)
+		return (EPERM);
+
+	ev = pm->pm_event;
+
+	if (ev < PMC_EV_P6_FIRST || ev > PMC_EV_P6_LAST)
+		return (EINVAL);
+
+	if ((pevent = p6_find_event(ev)) == NULL)
+		return (ESRCH);
+
+	if (!P6_EVENT_VALID_FOR_CPU(pevent, p6_cputype) ||
+	    !P6_EVENT_VALID_FOR_CTR(pevent, (ri-1)))
+		return (EINVAL);
+
+	/* For certain events, Pentium M differs from the stock P6 */
+	allowed_unitmask = 0;
+	if (p6_cputype == PMC_CPU_INTEL_PM) {
+		if (ev == PMC_EV_P6_L2_LD || ev == PMC_EV_P6_L2_LINES_IN ||
+		    ev == PMC_EV_P6_L2_LINES_OUT)
+			allowed_unitmask = P6_EVSEL_TO_UMASK(0x3F);
+		else if (ev == PMC_EV_P6_L2_M_LINES_OUTM)
+			allowed_unitmask = P6_EVSEL_TO_UMASK(0x30);
+	} else
+		allowed_unitmask = P6_EVSEL_TO_UMASK(pevent->pm_unitmask);
+
+	unitmask = a->pm_md.pm_ppro.pm_ppro_config & P6_EVSEL_UMASK_MASK;
+	if (unitmask & ~allowed_unitmask) /* disallow reserved bits */
+		return (EINVAL);
+
+	if (ev == PMC_EV_P6_MMX_UOPS_EXEC) /* hardcoded mask */
+		unitmask = P6_EVSEL_TO_UMASK(0x0F);
+
+	config = 0;
+
+	config |= P6_EVSEL_EVENT_SELECT(pevent->pm_evsel);
+
+	if (unitmask & (caps & PMC_CAP_QUALIFIER))
+		config |= unitmask;
+
+	if (caps & PMC_CAP_THRESHOLD)
+		config |= a->pm_md.pm_ppro.pm_ppro_config &
+		    P6_EVSEL_CMASK_MASK;
+
+	/* set at least one of the 'usr' or 'os' caps */
+	if (caps & PMC_CAP_USER)
+		config |= P6_EVSEL_USR;
+	if (caps & PMC_CAP_SYSTEM)
+		config |= P6_EVSEL_OS;
+	if ((caps & (PMC_CAP_USER|PMC_CAP_SYSTEM)) == 0)
+		config |= (P6_EVSEL_USR|P6_EVSEL_OS);
+
+	if (caps & PMC_CAP_EDGE)
+		config |= P6_EVSEL_E;
+	if (caps & PMC_CAP_INVERT)
+		config |= P6_EVSEL_INV;
+	if (caps & PMC_CAP_INTERRUPT)
+		config |= P6_EVSEL_INT;
+
+	pm->pm_md.pm_ppro.pm_ppro_evsel = config;
+
+	PMCDBG(MDP,ALL,2, "p6-allocate config=0x%x", config);
+
+	return (0);
+}
+
+static int
+p6_release_pmc(int cpu, int ri, struct pmc *pm)
+{
+	(void) pm;
+
+	PMCDBG(MDP,REL,1, "p6-release cpu=%d ri=%d pm=%p", cpu, ri, pm);
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[p6,%d] illegal CPU value %d", __LINE__, cpu));
+	KASSERT(ri >= 0 && ri < P6_NPMCS,
+	    ("[p6,%d] illegal row-index %d", __LINE__, ri));
+
+	KASSERT(p6_pcpu[cpu]->pc_p6pmcs[ri].phw_pmc == NULL,
+	    ("[p6,%d] PHW pmc non-NULL", __LINE__));
+
+	return (0);
+}
+
+static int
+p6_start_pmc(int cpu, int ri)
+{
+	uint32_t config;
+	struct pmc *pm;
+	struct p6_cpu *pc;
+	const struct p6pmc_descr *pd;
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[p6,%d] illegal CPU value %d", __LINE__, cpu));
+	KASSERT(ri >= 0 && ri < P6_NPMCS,
+	    ("[p6,%d] illegal row-index %d", __LINE__, ri));
+
+	pc = p6_pcpu[cpu];
+	pm = pc->pc_p6pmcs[ri].phw_pmc;
+	pd = &p6_pmcdesc[ri];
+
+	KASSERT(pm,
+	    ("[p6,%d] starting cpu%d,ri%d with no pmc configured",
+		__LINE__, cpu, ri));
+
+	PMCDBG(MDP,STA,1, "p6-start cpu=%d ri=%d", cpu, ri);
+
+	config = pm->pm_md.pm_ppro.pm_ppro_evsel;
+
+	PMCDBG(MDP,STA,2, "p6-start/2 cpu=%d ri=%d evselmsr=0x%x config=0x%x",
+	    cpu, ri, pd->pm_evsel_msr, config);
+
+	P6_MARK_STARTED(pc, ri);
+	wrmsr(pd->pm_evsel_msr, config);
+
+	P6_SYNC_CTR_STATE(pc);
+
+	return (0);
+}
+
+static int
+p6_stop_pmc(int cpu, int ri)
+{
+	struct pmc *pm;
+	struct p6_cpu *pc;
+	struct p6pmc_descr *pd;
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[p6,%d] illegal cpu value %d", __LINE__, cpu));
+	KASSERT(ri >= 0 && ri < P6_NPMCS,
+	    ("[p6,%d] illegal row index %d", __LINE__, ri));
+
+	pc = p6_pcpu[cpu];
+	pm = pc->pc_p6pmcs[ri].phw_pmc;
+	pd = &p6_pmcdesc[ri];
+
+	KASSERT(pm,
+	    ("[p6,%d] cpu%d ri%d no configured PMC to stop", __LINE__,
+		cpu, ri));
+
+	PMCDBG(MDP,STO,1, "p6-stop cpu=%d ri=%d", cpu, ri);
+
+	wrmsr(pd->pm_evsel_msr, 0);	/* stop hw */
+	P6_MARK_STOPPED(pc, ri);	/* update software state */
+
+	P6_SYNC_CTR_STATE(pc);		/* restart CTR1 if need be */
+
+	PMCDBG(MDP,STO,2, "p6-stop/2 cpu=%d ri=%d", cpu, ri);
+
+	return (0);
+}
+
+static int
+p6_intr(int cpu, struct trapframe *tf)
+{
+	int error, retval, ri;
+	uint32_t perf0cfg;
+	struct pmc *pm;
+	struct p6_cpu *pc;
+	pmc_value_t v;
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[p6,%d] CPU %d out of range", __LINE__, cpu));
+
+	retval = 0;
+	pc = p6_pcpu[cpu];
+
+	/* stop both PMCs */
+	perf0cfg = rdmsr(P6_MSR_EVSEL0);
+	wrmsr(P6_MSR_EVSEL0, perf0cfg & ~P6_EVSEL_EN);
+
+	for (ri = 0; ri < P6_NPMCS; ri++) {
+
+		if ((pm = pc->pc_p6pmcs[ri].phw_pmc) == NULL ||
+		    !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) {
+			continue;
+		}
+
+		if (!P6_PMC_HAS_OVERFLOWED(ri))
+			continue;
+
+		retval = 1;
+
+		if (pm->pm_state != PMC_STATE_RUNNING)
+			continue;
+
+		error = pmc_process_interrupt(cpu, pm, tf,
+		    TRAPF_USERMODE(tf));
+		if (error)
+			P6_MARK_STOPPED(pc,ri);
+
+		/* reload sampling count */
+		v = pm->pm_sc.pm_reloadcount;
+		wrmsr(P6_MSR_PERFCTR0 + ri,
+		    P6_RELOAD_COUNT_TO_PERFCTR_VALUE(v));
+
+	}
+
+	/*
+	 * On P6 processors, the LAPIC needs to have its PMC interrupt
+	 * unmasked after a PMC interrupt.
+	 */
+	if (retval)
+		lapic_reenable_pmc();
+
+	atomic_add_int(retval ? &pmc_stats.pm_intr_processed :
+	    &pmc_stats.pm_intr_ignored, 1);
+
+	/* restart counters that can be restarted */
+	P6_SYNC_CTR_STATE(pc);
+
+	return (retval);
+}
+
+static int
+p6_describe(int cpu, int ri, struct pmc_info *pi,
+    struct pmc **ppmc)
+{
+	int error;
+	size_t copied;
+	struct pmc_hw *phw;
+	struct p6pmc_descr *pd;
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[p6,%d] illegal CPU %d", __LINE__, cpu));
+	KASSERT(ri >= 0 && ri < P6_NPMCS,
+	    ("[p6,%d] row-index %d out of range", __LINE__, ri));
+
+	phw = pmc_pcpu[cpu]->pc_hwpmcs[ri];
+	pd  = &p6_pmcdesc[ri];
+
+	KASSERT(phw == &p6_pcpu[cpu]->pc_p6pmcs[ri],
+	    ("[p6,%d] phw mismatch", __LINE__));
+
+	if ((error = copystr(pd->pm_descr.pd_name, pi->pm_name,
+		 PMC_NAME_MAX, &copied)) != 0)
+		return (error);
+
+	pi->pm_class = pd->pm_descr.pd_class;
+
+	if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) {
+		pi->pm_enabled = TRUE;
+		*ppmc          = phw->phw_pmc;
+	} else {
+		pi->pm_enabled = FALSE;
+		*ppmc          = NULL;
+	}
+
+	return (0);
+}
+
+static int
+p6_get_msr(int ri, uint32_t *msr)
+{
+	KASSERT(ri >= 0 && ri < P6_NPMCS,
+	    ("[p6,%d ri %d out of range", __LINE__, ri));
+
+	*msr = p6_pmcdesc[ri].pm_pmc_msr - P6_MSR_PERFCTR0;
+
+	return (0);
+}
+
+int
+pmc_p6_initialize(struct pmc_mdep *md, int ncpus)
+{
+	struct pmc_classdep *pcd;
+
+	KASSERT(cpu_vendor_id == CPU_VENDOR_INTEL,
+	    ("[p6,%d] Initializing non-intel processor", __LINE__));
+
+	PMCDBG(MDP,INI,1, "%s", "p6-initialize");
+
+	/* Allocate space for pointers to per-cpu descriptors. */
+	p6_pcpu = malloc(sizeof(struct p6_cpu **) * ncpus, M_PMC,
+	    M_ZERO|M_WAITOK);
+
+	/* Fill in the class dependent descriptor. */
+	pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_P6];
+
+	switch (md->pmd_cputype) {
+
+		/*
+		 * P6 Family Processors
+		 */
+	case PMC_CPU_INTEL_P6:
+	case PMC_CPU_INTEL_CL:
+	case PMC_CPU_INTEL_PII:
+	case PMC_CPU_INTEL_PIII:
+	case PMC_CPU_INTEL_PM:
+
+		p6_cputype = md->pmd_cputype;
+
+		pcd->pcd_caps		= P6_PMC_CAPS;
+		pcd->pcd_class		= PMC_CLASS_P6;
+		pcd->pcd_num		= P6_NPMCS;
+		pcd->pcd_ri		= md->pmd_npmc;
+		pcd->pcd_width		= 40;
+
+		pcd->pcd_allocate_pmc	= p6_allocate_pmc;
+		pcd->pcd_config_pmc	= p6_config_pmc;
+		pcd->pcd_describe	= p6_describe;
+		pcd->pcd_get_config	= p6_get_config;
+		pcd->pcd_get_msr	= p6_get_msr;
+		pcd->pcd_pcpu_fini	= p6_pcpu_fini;
+		pcd->pcd_pcpu_init	= p6_pcpu_init;
+		pcd->pcd_read_pmc	= p6_read_pmc;
+		pcd->pcd_release_pmc	= p6_release_pmc;
+		pcd->pcd_start_pmc	= p6_start_pmc;
+		pcd->pcd_stop_pmc	= p6_stop_pmc;
+		pcd->pcd_write_pmc	= p6_write_pmc;
+
+		md->pmd_pcpu_fini	= NULL;
+		md->pmd_pcpu_init	= NULL;
+		md->pmd_intr		= p6_intr;
+
+		md->pmd_npmc	       += P6_NPMCS;
+
+		break;
+
+	default:
+		KASSERT(0,("[p6,%d] Unknown CPU type", __LINE__));
+		return ENOSYS;
+	}
+
+	return (0);
+}
+
+void
+pmc_p6_finalize(struct pmc_mdep *md)
+{
+#if	defined(INVARIANTS)
+	int i, ncpus;
+#endif
+
+	KASSERT(p6_pcpu != NULL, ("[p6,%d] NULL p6_pcpu", __LINE__));
+
+#if	defined(INVARIANTS)
+	ncpus = pmc_cpu_max();
+	for (i = 0; i < ncpus; i++)
+		KASSERT(p6_pcpu[i] == NULL, ("[p6,%d] non-null pcpu %d",
+		    __LINE__, i));
+#endif
+
+	free(p6_pcpu, M_PMC);
+	p6_pcpu = NULL;
+}
diff --git a/sys/dev/misc/hwpmc/hwpmc_ppro.h b/sys/dev/misc/hwpmc/hwpmc_ppro.h
new file mode 100644
index 0000000..cc7da92
--- /dev/null
+++ b/sys/dev/misc/hwpmc/hwpmc_ppro.h
@@ -0,0 +1,84 @@
+/*-
+ * Copyright (c) 2005, Joseph Koshy
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: src/sys/dev/hwpmc/hwpmc_ppro.h,v 1.2 2008/11/09 17:37:54 jkoshy Exp $
+ */
+
+/* Machine dependent interfaces */
+
+#ifndef _DEV_HWPMC_PPRO_H_
+#define	_DEV_HWPMC_PPRO_H_
+
+/* Intel PPro, Celeron, P-II, P-III, Pentium-M PMCS */
+
+#define	P6_NPMCS	2		/* 2 PMCs */
+
+#define	P6_EVSEL_CMASK_MASK		0xFF000000
+#define	P6_EVSEL_TO_CMASK(C)		(((C) & 0xFF) << 24)
+#define	P6_EVSEL_INV			(1 << 23)
+#define	P6_EVSEL_EN			(1 << 22)
+#define	P6_EVSEL_INT			(1 << 20)
+#define	P6_EVSEL_PC			(1 << 19)
+#define	P6_EVSEL_E			(1 << 18)
+#define	P6_EVSEL_OS			(1 << 17)
+#define	P6_EVSEL_USR			(1 << 16)
+#define	P6_EVSEL_UMASK_MASK		0x0000FF00
+#define	P6_EVSEL_TO_UMASK(U)		(((U) & 0xFF) << 8)
+#define	P6_EVSEL_EVENT_SELECT(ES)	((ES) & 0xFF)
+#define	P6_EVSEL_RESERVED		(1 << 21)
+
+#define	P6_MSR_EVSEL0			0x0186
+#define	P6_MSR_EVSEL1			0x0187
+#define	P6_MSR_PERFCTR0			0x00C1
+#define	P6_MSR_PERFCTR1			0x00C2
+
+#define	P6_PERFCTR_READ_MASK		0xFFFFFFFFFFLL	/* 40 bits */
+#define	P6_PERFCTR_WRITE_MASK		0xFFFFFFFFU	/* 32 bits */
+
+#define	P6_RELOAD_COUNT_TO_PERFCTR_VALUE(R)	(-(R))
+#define	P6_PERFCTR_VALUE_TO_RELOAD_COUNT(P)	(-(P))
+
+#define	P6_PMC_HAS_OVERFLOWED(P)	((rdpmc(P) & (1LL << 39)) == 0)
+
+struct pmc_md_ppro_op_pmcallocate {
+	uint32_t	pm_ppro_config;
+};
+
+#ifdef _KERNEL
+
+/* MD extension for 'struct pmc' */
+struct pmc_md_ppro_pmc {
+	uint32_t	pm_ppro_evsel;
+};
+
+/*
+ * Prototypes
+ */
+
+int	pmc_p6_initialize(struct pmc_mdep *_md, int _ncpus);
+void	pmc_p6_finalize(struct pmc_mdep *_md);
+
+#endif /* _KERNEL */
+#endif /* _DEV_HWPMC_PPRO_H_ */
diff --git a/sys/dev/misc/hwpmc/hwpmc_tsc.c b/sys/dev/misc/hwpmc/hwpmc_tsc.c
new file mode 100644
index 0000000..bb3c00e
--- /dev/null
+++ b/sys/dev/misc/hwpmc/hwpmc_tsc.c
@@ -0,0 +1,388 @@
+/*-
+ * Copyright (c) 2008 Joseph Koshy
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: src/sys/dev/hwpmc/hwpmc_tsc.c,v 1.1 2008/11/09 17:37:54 jkoshy Exp $");
+
+#include <sys/param.h>
+#include <sys/pmc.h>
+#include <sys/pmckern.h>
+#include <sys/systm.h>
+
+#include <machine/specialreg.h>
+
+/*
+ * TSC support.
+ */
+
+#define	TSC_CAPS	PMC_CAP_READ
+
+struct tsc_descr {
+	struct pmc_descr pm_descr;  /* "base class" */
+};
+
+static struct tsc_descr tsc_pmcdesc[TSC_NPMCS] =
+{
+    {
+	.pm_descr =
+	{
+		.pd_name  = "TSC",
+		.pd_class = PMC_CLASS_TSC,
+		.pd_caps  = TSC_CAPS,
+		.pd_width = 64
+	}
+    }
+};
+
+/*
+ * Per-CPU data structure for TSCs.
+ */
+
+struct tsc_cpu {
+	struct pmc_hw	tc_hw;
+};
+
+static struct tsc_cpu **tsc_pcpu;
+
+static int
+tsc_allocate_pmc(int cpu, int ri, struct pmc *pm,
+    const struct pmc_op_pmcallocate *a)
+{
+	(void) cpu;
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[tsc,%d] illegal CPU value %d", __LINE__, cpu));
+	KASSERT(ri >= 0 && ri < TSC_NPMCS,
+	    ("[tsc,%d] illegal row index %d", __LINE__, ri));
+
+	if (a->pm_class != PMC_CLASS_TSC)
+		return (EINVAL);
+
+	if ((pm->pm_caps & TSC_CAPS) == 0)
+		return (EINVAL);
+
+	if ((pm->pm_caps & ~TSC_CAPS) != 0)
+		return (EPERM);
+
+	if (a->pm_ev != PMC_EV_TSC_TSC ||
+	    a->pm_mode != PMC_MODE_SC)
+		return (EINVAL);
+
+	return (0);
+}
+
+static int
+tsc_config_pmc(int cpu, int ri, struct pmc *pm)
+{
+	struct pmc_hw *phw;
+
+	PMCDBG(MDP,CFG,1, "cpu=%d ri=%d pm=%p", cpu, ri, pm);
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[tsc,%d] illegal CPU value %d", __LINE__, cpu));
+	KASSERT(ri == 0, ("[tsc,%d] illegal row-index %d", __LINE__, ri));
+
+	phw = &tsc_pcpu[cpu]->tc_hw;
+
+	KASSERT(pm == NULL || phw->phw_pmc == NULL,
+	    ("[tsc,%d] pm=%p phw->pm=%p hwpmc not unconfigured", __LINE__,
+	    pm, phw->phw_pmc));
+
+	phw->phw_pmc = pm;
+
+	return (0);
+}
+
+static int
+tsc_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc)
+{
+	int error;
+	size_t copied;
+	const struct tsc_descr *pd;
+	struct pmc_hw *phw;
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[tsc,%d] illegal CPU %d", __LINE__, cpu));
+	KASSERT(ri == 0, ("[tsc,%d] illegal row-index %d", __LINE__, ri));
+
+	phw = &tsc_pcpu[cpu]->tc_hw;
+	pd  = &tsc_pmcdesc[ri];
+
+	if ((error = copystr(pd->pm_descr.pd_name, pi->pm_name,
+	    PMC_NAME_MAX, &copied)) != 0)
+		return (error);
+
+	pi->pm_class = pd->pm_descr.pd_class;
+
+	if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) {
+		pi->pm_enabled = TRUE;
+		*ppmc          = phw->phw_pmc;
+	} else {
+		pi->pm_enabled = FALSE;
+		*ppmc          = NULL;
+	}
+
+	return (0);
+}
+
+static int
+tsc_get_config(int cpu, int ri, struct pmc **ppm)
+{
+	(void) ri;
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[tsc,%d] illegal CPU %d", __LINE__, cpu));
+	KASSERT(ri == 0, ("[tsc,%d] illegal row-index %d", __LINE__, ri));
+
+	*ppm = tsc_pcpu[cpu]->tc_hw.phw_pmc;
+
+	return (0);
+}
+
+static int
+tsc_get_msr(int ri, uint32_t *msr)
+{
+	(void) ri;
+
+	KASSERT(ri >= 0 && ri < TSC_NPMCS,
+	    ("[tsc,%d] ri %d out of range", __LINE__, ri));
+
+	*msr = MSR_TSC;
+
+	return (0);
+}
+
+static int
+tsc_pcpu_fini(struct pmc_mdep *md, int cpu)
+{
+	int ri;
+	struct pmc_cpu *pc;
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[tsc,%d] illegal cpu %d", __LINE__, cpu));
+	KASSERT(tsc_pcpu[cpu] != NULL, ("[tsc,%d] null pcpu", __LINE__));
+
+	free(tsc_pcpu[cpu], M_PMC);
+	tsc_pcpu[cpu] = NULL;
+
+	ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_TSC].pcd_ri;
+
+	KASSERT(ri == 0 && ri < TSC_NPMCS, ("[tsc,%d] ri=%d", __LINE__,
+	    ri));
+
+	pc = pmc_pcpu[cpu];
+	pc->pc_hwpmcs[ri] = NULL;
+
+	return (0);
+}
+
+static int
+tsc_pcpu_init(struct pmc_mdep *md, int cpu)
+{
+	int ri;
+	struct pmc_cpu *pc;
+	struct tsc_cpu *tsc_pc;
+
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[tsc,%d] illegal cpu %d", __LINE__, cpu));
+	KASSERT(tsc_pcpu, ("[tsc,%d] null pcpu", __LINE__));
+	KASSERT(tsc_pcpu[cpu] == NULL, ("[tsc,%d] non-null per-cpu",
+	    __LINE__));
+
+	tsc_pc = malloc(sizeof(struct tsc_cpu), M_PMC, M_WAITOK|M_ZERO);
+
+	tsc_pc->tc_hw.phw_state = PMC_PHW_FLAG_IS_ENABLED |
+	    PMC_PHW_CPU_TO_STATE(cpu) | PMC_PHW_INDEX_TO_STATE(0) |
+	    PMC_PHW_FLAG_IS_SHAREABLE;
+
+	tsc_pcpu[cpu] = tsc_pc;
+
+	ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_TSC].pcd_ri;
+
+	KASSERT(pmc_pcpu, ("[tsc,%d] null generic pcpu", __LINE__));
+
+	pc = pmc_pcpu[cpu];
+
+	KASSERT(pc, ("[tsc,%d] null generic per-cpu", __LINE__));
+
+	pc->pc_hwpmcs[ri] = &tsc_pc->tc_hw;
+
+	return (0);
+}
+
+static int
+tsc_read_pmc(int cpu, int ri, pmc_value_t *v)
+{
+	struct pmc *pm;
+	enum pmc_mode mode;
+	const struct pmc_hw *phw;
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[tsc,%d] illegal CPU value %d", __LINE__, cpu));
+	KASSERT(ri == 0, ("[tsc,%d] illegal ri %d", __LINE__, ri));
+
+	phw = &tsc_pcpu[cpu]->tc_hw;
+	pm  = phw->phw_pmc;
+
+	KASSERT(pm != NULL,
+	    ("[tsc,%d] no owner for PHW [cpu%d,pmc%d]", __LINE__, cpu, ri));
+
+	mode = PMC_TO_MODE(pm);
+
+	KASSERT(mode == PMC_MODE_SC,
+	    ("[tsc,%d] illegal pmc mode %d", __LINE__, mode));
+
+	PMCDBG(MDP,REA,1,"tsc-read id=%d", ri);
+
+	*v = rdtsc();
+
+	return (0);
+}
+
+static int
+tsc_release_pmc(int cpu, int ri, struct pmc *pmc)
+{
+	struct pmc_hw *phw;
+
+	(void) pmc;
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[tsc,%d] illegal CPU value %d", __LINE__, cpu));
+	KASSERT(ri == 0,
+	    ("[tsc,%d] illegal row-index %d", __LINE__, ri));
+
+	phw = &tsc_pcpu[cpu]->tc_hw;
+
+	KASSERT(phw->phw_pmc == NULL,
+	    ("[tsc,%d] PHW pmc %p non-NULL", __LINE__, phw->phw_pmc));
+
+	/*
+	 * Nothing to do.
+	 */
+	return (0);
+}
+
+static int
+tsc_start_pmc(int cpu, int ri)
+{
+	(void) cpu;
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[tsc,%d] illegal CPU value %d", __LINE__, cpu));
+	KASSERT(ri == 0, ("[tsc,%d] illegal row-index %d", __LINE__, ri));
+
+	return (0);	/* TSCs are always running. */
+}
+
+static int
+tsc_stop_pmc(int cpu, int ri)
+{
+	(void) cpu; (void) ri;
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[tsc,%d] illegal CPU value %d", __LINE__, cpu));
+	KASSERT(ri == 0, ("[tsc,%d] illegal row-index %d", __LINE__, ri));
+
+	return (0);	/* Cannot actually stop a TSC. */
+}
+
+static int
+tsc_write_pmc(int cpu, int ri, pmc_value_t v)
+{
+	(void) cpu; (void) ri; (void) v;
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[tsc,%d] illegal CPU value %d", __LINE__, cpu));
+	KASSERT(ri == 0, ("[tsc,%d] illegal row-index %d", __LINE__, ri));
+
+	/*
+	 * The TSCs are used as timecounters by the kernel, so even
+	 * though some i386 CPUs support writeable TSCs, we don't
+	 * support writing changing TSC values through the HWPMC API.
+	 */
+	return (0);
+}
+
+int
+pmc_tsc_initialize(struct pmc_mdep *md, int maxcpu)
+{
+	struct pmc_classdep *pcd;
+
+	KASSERT(md != NULL, ("[tsc,%d] md is NULL", __LINE__));
+	KASSERT(md->pmd_nclass >= 1, ("[tsc,%d] dubious md->nclass %d",
+	    __LINE__, md->pmd_nclass));
+
+	tsc_pcpu = malloc(sizeof(struct tsc_cpu *) * maxcpu, M_PMC,
+	    M_ZERO|M_WAITOK);
+
+	pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_TSC];
+
+	pcd->pcd_caps	= PMC_CAP_READ;
+	pcd->pcd_class	= PMC_CLASS_TSC;
+	pcd->pcd_num	= TSC_NPMCS;
+	pcd->pcd_ri	= md->pmd_npmc;
+	pcd->pcd_width	= 64;
+
+	pcd->pcd_allocate_pmc = tsc_allocate_pmc;
+	pcd->pcd_config_pmc   = tsc_config_pmc;
+	pcd->pcd_describe     = tsc_describe;
+	pcd->pcd_get_config   = tsc_get_config;
+	pcd->pcd_get_msr      = tsc_get_msr;
+	pcd->pcd_pcpu_init    = tsc_pcpu_init;
+	pcd->pcd_pcpu_fini    = tsc_pcpu_fini;
+	pcd->pcd_read_pmc     = tsc_read_pmc;
+	pcd->pcd_release_pmc  = tsc_release_pmc;
+	pcd->pcd_start_pmc    = tsc_start_pmc;
+	pcd->pcd_stop_pmc     = tsc_stop_pmc;
+	pcd->pcd_write_pmc    = tsc_write_pmc;
+
+	md->pmd_npmc += TSC_NPMCS;
+
+	return (0);
+}
+
+void
+pmc_tsc_finalize(struct pmc_mdep *md)
+{
+#ifdef	INVARIANTS
+	int i, ncpus;
+
+	ncpus = pmc_cpu_max();
+	for (i = 0; i < ncpus; i++)
+		KASSERT(tsc_pcpu[i] == NULL, ("[tsc,%d] non-null pcpu cpu %d",
+		    __LINE__, i));
+
+	KASSERT(md->pmd_classdep[PMC_MDEP_CLASS_INDEX_TSC].pcd_class ==
+	    PMC_CLASS_TSC, ("[tsc,%d] class mismatch", __LINE__));
+
+#else
+	(void) md;
+#endif
+
+	free(tsc_pcpu, M_PMC);
+	tsc_pcpu = NULL;
+}
diff --git a/sys/dev/misc/hwpmc/hwpmc_tsc.h b/sys/dev/misc/hwpmc/hwpmc_tsc.h
new file mode 100644
index 0000000..539a71b
--- /dev/null
+++ b/sys/dev/misc/hwpmc/hwpmc_tsc.h
@@ -0,0 +1,43 @@
+/*-
+ * Copyright (c) 2008 Joseph Koshy
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: src/sys/dev/hwpmc/hwpmc_tsc.h,v 1.1 2008/11/09 17:37:54 jkoshy Exp $
+ */
+
+#ifndef _DEV_HWPMC_TSC_H_
+#define	_DEV_HWPMC_TSC_H_ 1
+
+#ifdef	_KERNEL
+
+#define	TSC_NPMCS	1
+
+/*
+ * Prototypes.
+ */
+
+int	pmc_tsc_initialize(struct pmc_mdep *_md, int _maxcpu);
+void	pmc_tsc_finalize(struct pmc_mdep *_md);
+#endif	/* _KERNEL */
+#endif	/* _DEV_HWPMC_TSC_H */
diff --git a/sys/dev/misc/hwpmc/hwpmc_uncore.c b/sys/dev/misc/hwpmc/hwpmc_uncore.c
new file mode 100644
index 0000000..ff3a2f2
--- /dev/null
+++ b/sys/dev/misc/hwpmc/hwpmc_uncore.c
@@ -0,0 +1,1121 @@
+/*-
+ * Copyright (c) 2010 Fabien Thomas
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * Intel Uncore PMCs.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: src/sys/dev/hwpmc/hwpmc_uncore.c,v 1.1 2010/04/02 13:23:49 fabient Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/pmc.h>
+#include <sys/pmckern.h>
+#include <sys/systm.h>
+
+#include <machine/intr_machdep.h>
+#include <machine/apicvar.h>
+#include <machine/cpu.h>
+#include <machine/cpufunc.h>
+#include <machine/specialreg.h>
+
+#define	UCF_PMC_CAPS \
+	(PMC_CAP_READ | PMC_CAP_WRITE)
+
+#define	UCP_PMC_CAPS \
+    (PMC_CAP_EDGE | PMC_CAP_THRESHOLD | PMC_CAP_READ | PMC_CAP_WRITE | \
+    PMC_CAP_INVERT | PMC_CAP_QUALIFIER | PMC_CAP_PRECISE)
+
+static enum pmc_cputype	uncore_cputype;
+
+struct uncore_cpu {
+	volatile uint32_t	pc_resync;
+	volatile uint32_t	pc_ucfctrl;	/* Fixed function control. */
+	volatile uint64_t	pc_globalctrl;	/* Global control register. */
+	struct pmc_hw		pc_uncorepmcs[];
+};
+
+static struct uncore_cpu **uncore_pcpu;
+
+static uint64_t uncore_pmcmask;
+
+static int uncore_ucf_ri;		/* relative index of fixed counters */
+static int uncore_ucf_width;
+static int uncore_ucf_npmc;
+
+static int uncore_ucp_width;
+static int uncore_ucp_npmc;
+
+static int
+uncore_pcpu_noop(struct pmc_mdep *md, int cpu)
+{
+	(void) md;
+	(void) cpu;
+	return (0);
+}
+
+static int
+uncore_pcpu_init(struct pmc_mdep *md, int cpu)
+{
+	struct pmc_cpu *pc;
+	struct uncore_cpu *cc;
+	struct pmc_hw *phw;
+	int uncore_ri, n, npmc;
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[ucf,%d] insane cpu number %d", __LINE__, cpu));
+
+	PMCDBG(MDP,INI,1,"uncore-init cpu=%d", cpu);
+
+	uncore_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCP].pcd_ri;
+	npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCP].pcd_num;
+	npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCF].pcd_num;
+
+	cc = malloc(sizeof(struct uncore_cpu) + npmc * sizeof(struct pmc_hw),
+	    M_PMC, M_WAITOK | M_ZERO);
+
+	uncore_pcpu[cpu] = cc;
+	pc = pmc_pcpu[cpu];
+
+	KASSERT(pc != NULL && cc != NULL,
+	    ("[uncore,%d] NULL per-cpu structures cpu=%d", __LINE__, cpu));
+
+	for (n = 0, phw = cc->pc_uncorepmcs; n < npmc; n++, phw++) {
+		phw->phw_state 	  = PMC_PHW_FLAG_IS_ENABLED |
+		    PMC_PHW_CPU_TO_STATE(cpu) |
+		    PMC_PHW_INDEX_TO_STATE(n + uncore_ri);
+		phw->phw_pmc	  = NULL;
+		pc->pc_hwpmcs[n + uncore_ri]  = phw;
+	}
+
+	return (0);
+}
+
+static int
+uncore_pcpu_fini(struct pmc_mdep *md, int cpu)
+{
+	int uncore_ri, n, npmc;
+	struct pmc_cpu *pc;
+	struct uncore_cpu *cc;
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[uncore,%d] insane cpu number (%d)", __LINE__, cpu));
+
+	PMCDBG(MDP,INI,1,"uncore-pcpu-fini cpu=%d", cpu);
+
+	if ((cc = uncore_pcpu[cpu]) == NULL)
+		return (0);
+
+	uncore_pcpu[cpu] = NULL;
+
+	pc = pmc_pcpu[cpu];
+
+	KASSERT(pc != NULL, ("[uncore,%d] NULL per-cpu %d state", __LINE__,
+		cpu));
+
+	npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCP].pcd_num;
+	uncore_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCP].pcd_ri;
+
+	for (n = 0; n < npmc; n++)
+		wrmsr(UCP_EVSEL0 + n, 0);
+
+	wrmsr(UCF_CTRL, 0);
+	npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCF].pcd_num;
+
+	for (n = 0; n < npmc; n++)
+		pc->pc_hwpmcs[n + uncore_ri] = NULL;
+
+	free(cc, M_PMC);
+
+	return (0);
+}
+
+/*
+ * Fixed function counters.
+ */
+
+static pmc_value_t
+ucf_perfctr_value_to_reload_count(pmc_value_t v)
+{
+	v &= (1ULL << uncore_ucf_width) - 1;
+	return (1ULL << uncore_ucf_width) - v;
+}
+
+static pmc_value_t
+ucf_reload_count_to_perfctr_value(pmc_value_t rlc)
+{
+	return (1ULL << uncore_ucf_width) - rlc;
+}
+
+static int
+ucf_allocate_pmc(int cpu, int ri, struct pmc *pm,
+    const struct pmc_op_pmcallocate *a)
+{
+	enum pmc_event ev;
+	uint32_t caps, flags;
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[uncore,%d] illegal CPU %d", __LINE__, cpu));
+
+	PMCDBG(MDP,ALL,1, "ucf-allocate ri=%d reqcaps=0x%x", ri, pm->pm_caps);
+
+	if (ri < 0 || ri > uncore_ucf_npmc)
+		return (EINVAL);
+
+	caps = a->pm_caps;
+
+	if (a->pm_class != PMC_CLASS_UCF ||
+	    (caps & UCF_PMC_CAPS) != caps)
+		return (EINVAL);
+
+	ev = pm->pm_event;
+	if (ev < PMC_EV_UCF_FIRST || ev > PMC_EV_UCF_LAST)
+		return (EINVAL);
+
+	flags = UCF_EN;
+
+	pm->pm_md.pm_ucf.pm_ucf_ctrl = (flags << (ri * 4));
+
+	PMCDBG(MDP,ALL,2, "ucf-allocate config=0x%jx",
+	    (uintmax_t) pm->pm_md.pm_ucf.pm_ucf_ctrl);
+
+	return (0);
+}
+
+static int
+ucf_config_pmc(int cpu, int ri, struct pmc *pm)
+{
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[uncore,%d] illegal CPU %d", __LINE__, cpu));
+
+	KASSERT(ri >= 0 && ri < uncore_ucf_npmc,
+	    ("[uncore,%d] illegal row-index %d", __LINE__, ri));
+
+	PMCDBG(MDP,CFG,1, "ucf-config cpu=%d ri=%d pm=%p", cpu, ri, pm);
+
+	KASSERT(uncore_pcpu[cpu] != NULL, ("[uncore,%d] null per-cpu %d", __LINE__,
+	    cpu));
+
+	uncore_pcpu[cpu]->pc_uncorepmcs[ri + uncore_ucf_ri].phw_pmc = pm;
+
+	return (0);
+}
+
+static int
+ucf_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc)
+{
+	int error;
+	struct pmc_hw *phw;
+	char ucf_name[PMC_NAME_MAX];
+
+	phw = &uncore_pcpu[cpu]->pc_uncorepmcs[ri + uncore_ucf_ri];
+
+	(void) snprintf(ucf_name, sizeof(ucf_name), "UCF-%d", ri);
+	if ((error = copystr(ucf_name, pi->pm_name, PMC_NAME_MAX,
+	    NULL)) != 0)
+		return (error);
+
+	pi->pm_class = PMC_CLASS_UCF;
+
+	if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) {
+		pi->pm_enabled = TRUE;
+		*ppmc          = phw->phw_pmc;
+	} else {
+		pi->pm_enabled = FALSE;
+		*ppmc          = NULL;
+	}
+
+	return (0);
+}
+
+static int
+ucf_get_config(int cpu, int ri, struct pmc **ppm)
+{
+	*ppm = uncore_pcpu[cpu]->pc_uncorepmcs[ri + uncore_ucf_ri].phw_pmc;
+
+	return (0);
+}
+
+static int
+ucf_read_pmc(int cpu, int ri, pmc_value_t *v)
+{
+	struct pmc *pm;
+	pmc_value_t tmp;
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[uncore,%d] illegal cpu value %d", __LINE__, cpu));
+	KASSERT(ri >= 0 && ri < uncore_ucf_npmc,
+	    ("[uncore,%d] illegal row-index %d", __LINE__, ri));
+
+	pm = uncore_pcpu[cpu]->pc_uncorepmcs[ri + uncore_ucf_ri].phw_pmc;
+
+	KASSERT(pm,
+	    ("[uncore,%d] cpu %d ri %d(%d) pmc not configured", __LINE__, cpu,
+		ri, ri + uncore_ucf_ri));
+
+	tmp = rdmsr(UCF_CTR0 + ri);
+
+	if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
+		*v = ucf_perfctr_value_to_reload_count(tmp);
+	else
+		*v = tmp;
+
+	PMCDBG(MDP,REA,1, "ucf-read cpu=%d ri=%d -> v=%jx", cpu, ri, *v);
+
+	return (0);
+}
+
+static int
+ucf_release_pmc(int cpu, int ri, struct pmc *pmc)
+{
+	PMCDBG(MDP,REL,1, "ucf-release cpu=%d ri=%d pm=%p", cpu, ri, pmc);
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[uncore,%d] illegal CPU value %d", __LINE__, cpu));
+	KASSERT(ri >= 0 && ri < uncore_ucf_npmc,
+	    ("[uncore,%d] illegal row-index %d", __LINE__, ri));
+
+	KASSERT(uncore_pcpu[cpu]->pc_uncorepmcs[ri + uncore_ucf_ri].phw_pmc == NULL,
+	    ("[uncore,%d] PHW pmc non-NULL", __LINE__));
+
+	return (0);
+}
+
+static int
+ucf_start_pmc(int cpu, int ri)
+{
+	struct pmc *pm;
+	struct uncore_cpu *ucfc;
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[uncore,%d] illegal CPU value %d", __LINE__, cpu));
+	KASSERT(ri >= 0 && ri < uncore_ucf_npmc,
+	    ("[uncore,%d] illegal row-index %d", __LINE__, ri));
+
+	PMCDBG(MDP,STA,1,"ucf-start cpu=%d ri=%d", cpu, ri);
+
+	ucfc = uncore_pcpu[cpu];
+	pm = ucfc->pc_uncorepmcs[ri + uncore_ucf_ri].phw_pmc;
+
+	ucfc->pc_ucfctrl |= pm->pm_md.pm_ucf.pm_ucf_ctrl;
+
+	wrmsr(UCF_CTRL, ucfc->pc_ucfctrl);
+
+	do {
+		ucfc->pc_resync = 0;
+		ucfc->pc_globalctrl |= (1ULL << (ri + UCF_OFFSET));
+		wrmsr(UC_GLOBAL_CTRL, ucfc->pc_globalctrl);
+	} while (ucfc->pc_resync != 0);
+
+	PMCDBG(MDP,STA,1,"ucfctrl=%x(%x) globalctrl=%jx(%jx)",
+	    ucfc->pc_ucfctrl, (uint32_t) rdmsr(UCF_CTRL),
+	    ucfc->pc_globalctrl, rdmsr(UC_GLOBAL_CTRL));
+
+	return (0);
+}
+
+static int
+ucf_stop_pmc(int cpu, int ri)
+{
+	uint32_t fc;
+	struct uncore_cpu *ucfc;
+
+	PMCDBG(MDP,STO,1,"ucf-stop cpu=%d ri=%d", cpu, ri);
+
+	ucfc = uncore_pcpu[cpu];
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[uncore,%d] illegal CPU value %d", __LINE__, cpu));
+	KASSERT(ri >= 0 && ri < uncore_ucf_npmc,
+	    ("[uncore,%d] illegal row-index %d", __LINE__, ri));
+
+	fc = (UCF_MASK << (ri * 4));
+
+	ucfc->pc_ucfctrl &= ~fc;
+
+	PMCDBG(MDP,STO,1,"ucf-stop ucfctrl=%x", ucfc->pc_ucfctrl);
+	wrmsr(UCF_CTRL, ucfc->pc_ucfctrl);
+
+	do {
+		ucfc->pc_resync = 0;
+		ucfc->pc_globalctrl &= ~(1ULL << (ri + UCF_OFFSET));
+		wrmsr(UC_GLOBAL_CTRL, ucfc->pc_globalctrl);
+	} while (ucfc->pc_resync != 0);
+
+	PMCDBG(MDP,STO,1,"ucfctrl=%x(%x) globalctrl=%jx(%jx)",
+	    ucfc->pc_ucfctrl, (uint32_t) rdmsr(UCF_CTRL),
+	    ucfc->pc_globalctrl, rdmsr(UC_GLOBAL_CTRL));
+
+	return (0);
+}
+
+static int
+ucf_write_pmc(int cpu, int ri, pmc_value_t v)
+{
+	struct uncore_cpu *cc;
+	struct pmc *pm;
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[uncore,%d] illegal cpu value %d", __LINE__, cpu));
+	KASSERT(ri >= 0 && ri < uncore_ucf_npmc,
+	    ("[uncore,%d] illegal row-index %d", __LINE__, ri));
+
+	cc = uncore_pcpu[cpu];
+	pm = cc->pc_uncorepmcs[ri + uncore_ucf_ri].phw_pmc;
+
+	KASSERT(pm,
+	    ("[uncore,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, ri));
+
+	if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
+		v = ucf_reload_count_to_perfctr_value(v);
+
+	wrmsr(UCF_CTRL, 0);	/* Turn off fixed counters */
+	wrmsr(UCF_CTR0 + ri, v);
+	wrmsr(UCF_CTRL, cc->pc_ucfctrl);
+
+	PMCDBG(MDP,WRI,1, "ucf-write cpu=%d ri=%d v=%jx ucfctrl=%jx ",
+	    cpu, ri, v, (uintmax_t) rdmsr(UCF_CTRL));
+
+	return (0);
+}
+
+
+static void
+ucf_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth)
+{
+	struct pmc_classdep *pcd;
+
+	KASSERT(md != NULL, ("[ucf,%d] md is NULL", __LINE__));
+
+	PMCDBG(MDP,INI,1, "%s", "ucf-initialize");
+
+	pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCF];
+
+	pcd->pcd_caps	= UCF_PMC_CAPS;
+	pcd->pcd_class	= PMC_CLASS_UCF;
+	pcd->pcd_num	= npmc;
+	pcd->pcd_ri	= md->pmd_npmc;
+	pcd->pcd_width	= pmcwidth;
+
+	pcd->pcd_allocate_pmc	= ucf_allocate_pmc;
+	pcd->pcd_config_pmc	= ucf_config_pmc;
+	pcd->pcd_describe	= ucf_describe;
+	pcd->pcd_get_config	= ucf_get_config;
+	pcd->pcd_get_msr	= NULL;
+	pcd->pcd_pcpu_fini	= uncore_pcpu_noop;
+	pcd->pcd_pcpu_init	= uncore_pcpu_noop;
+	pcd->pcd_read_pmc	= ucf_read_pmc;
+	pcd->pcd_release_pmc	= ucf_release_pmc;
+	pcd->pcd_start_pmc	= ucf_start_pmc;
+	pcd->pcd_stop_pmc	= ucf_stop_pmc;
+	pcd->pcd_write_pmc	= ucf_write_pmc;
+
+	md->pmd_npmc	       += npmc;
+}
+
+/*
+ * Intel programmable PMCs.
+ */
+
+/*
+ * Event descriptor tables.
+ *
+ * For each event id, we track:
+ *
+ * 1. The CPUs that the event is valid for.
+ *
+ * 2. If the event uses a fixed UMASK, the value of the umask field.
+ *    If the event doesn't use a fixed UMASK, a mask of legal bits
+ *    to check against.
+ */
+
+struct ucp_event_descr {
+	enum pmc_event	ucp_ev;
+	unsigned char	ucp_evcode;
+	unsigned char	ucp_umask;
+	unsigned char	ucp_flags;
+};
+
+#define	UCP_F_I7	(1 << 0)	/* CPU: Core i7 */
+#define	UCP_F_WM	(1 << 1)	/* CPU: Westmere */
+#define	UCP_F_FM	(1 << 2)	/* Fixed mask */
+
+#define	UCP_F_ALLCPUS					\
+    (UCP_F_I7 | UCP_F_WM)
+
+#define	UCP_F_CMASK		0xFF000000
+
+static struct ucp_event_descr ucp_events[] = {
+#undef UCPDESCR
+#define	UCPDESCR(N,EV,UM,FLAGS) {					\
+	.ucp_ev = PMC_EV_UCP_EVENT_##N,					\
+	.ucp_evcode = (EV),						\
+	.ucp_umask = (UM),						\
+	.ucp_flags = (FLAGS)						\
+	}
+
+    UCPDESCR(00H_01H, 0x00, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(00H_02H, 0x00, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(00H_04H, 0x00, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+
+    UCPDESCR(01H_01H, 0x01, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(01H_02H, 0x01, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(01H_04H, 0x01, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+
+    UCPDESCR(02H_01H, 0x02, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(03H_01H, 0x03, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(03H_02H, 0x03, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(03H_04H, 0x03, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(03H_08H, 0x03, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(03H_10H, 0x03, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(03H_20H, 0x03, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(03H_40H, 0x03, 0x40, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+
+    UCPDESCR(04H_01H, 0x04, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(04H_02H, 0x04, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(04H_04H, 0x04, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(04H_08H, 0x04, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(04H_10H, 0x04, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+
+    UCPDESCR(05H_01H, 0x05, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(05H_02H, 0x05, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(05H_04H, 0x05, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+
+    UCPDESCR(06H_01H, 0x06, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(06H_02H, 0x06, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(06H_04H, 0x06, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(06H_08H, 0x06, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(06H_10H, 0x06, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(06H_20H, 0x06, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+
+    UCPDESCR(07H_01H, 0x07, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(07H_02H, 0x07, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(07H_04H, 0x07, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(07H_08H, 0x07, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(07H_10H, 0x07, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(07H_20H, 0x07, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(07H_24H, 0x07, 0x24, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+
+    UCPDESCR(08H_01H, 0x08, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(08H_02H, 0x08, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(08H_04H, 0x08, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(08H_03H, 0x08, 0x03, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+
+    UCPDESCR(09H_01H, 0x09, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(09H_02H, 0x09, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(09H_04H, 0x09, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(09H_03H, 0x09, 0x03, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+
+    UCPDESCR(0AH_01H, 0x0A, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(0AH_02H, 0x0A, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(0AH_04H, 0x0A, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(0AH_08H, 0x0A, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(0AH_0FH, 0x0A, 0x0F, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+
+    UCPDESCR(0BH_01H, 0x0B, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(0BH_02H, 0x0B, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(0BH_04H, 0x0B, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(0BH_08H, 0x0B, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(0BH_10H, 0x0B, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(0BH_1FH, 0x0B, 0x1F, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+
+    UCPDESCR(0CH_01H, 0x0C, 0x01, UCP_F_FM | UCP_F_WM),
+    UCPDESCR(0CH_02H, 0x0C, 0x02, UCP_F_FM | UCP_F_WM),
+    UCPDESCR(0CH_04H, 0x0C, 0x04, UCP_F_FM | UCP_F_WM),
+    UCPDESCR(0CH_08H, 0x0C, 0x08, UCP_F_FM | UCP_F_WM),
+
+    UCPDESCR(20H_01H, 0x20, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(20H_02H, 0x20, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(20H_04H, 0x20, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(20H_08H, 0x20, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(20H_10H, 0x20, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(20H_20H, 0x20, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+
+    UCPDESCR(21H_01H, 0x21, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(21H_02H, 0x21, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(21H_04H, 0x21, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+
+    UCPDESCR(22H_01H, 0x22, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(22H_02H, 0x22, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(22H_04H, 0x22, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+
+    UCPDESCR(23H_01H, 0x23, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(23H_02H, 0x23, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(23H_04H, 0x23, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+
+    UCPDESCR(24H_02H, 0x24, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(24H_04H, 0x24, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+
+    UCPDESCR(25H_01H, 0x25, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(25H_02H, 0x25, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(25H_04H, 0x25, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+
+    UCPDESCR(26H_01H, 0x26, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+
+    UCPDESCR(27H_01H, 0x27, 0x01, UCP_F_FM | UCP_F_I7),
+    UCPDESCR(27H_02H, 0x27, 0x02, UCP_F_FM | UCP_F_I7),
+    UCPDESCR(27H_04H, 0x27, 0x04, UCP_F_FM | UCP_F_I7),
+    UCPDESCR(27H_08H, 0x27, 0x08, UCP_F_FM | UCP_F_I7),
+    UCPDESCR(27H_10H, 0x27, 0x10, UCP_F_FM | UCP_F_I7),
+    UCPDESCR(27H_20H, 0x27, 0x20, UCP_F_FM | UCP_F_I7),
+
+    UCPDESCR(28H_01H, 0x28, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(28H_02H, 0x28, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(28H_04H, 0x28, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(28H_08H, 0x28, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(28H_10H, 0x28, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(28H_20H, 0x28, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+
+    UCPDESCR(29H_01H, 0x29, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(29H_02H, 0x29, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(29H_04H, 0x29, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(29H_08H, 0x29, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(29H_10H, 0x29, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(29H_20H, 0x29, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+
+    UCPDESCR(2AH_01H, 0x2A, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(2AH_02H, 0x2A, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(2AH_04H, 0x2A, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(2AH_07H, 0x2A, 0x07, UCP_F_FM | UCP_F_WM),
+
+    UCPDESCR(2BH_01H, 0x2B, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(2BH_02H, 0x2B, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(2BH_04H, 0x2B, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(2BH_07H, 0x2B, 0x07, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+
+    UCPDESCR(2CH_01H, 0x2C, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(2CH_02H, 0x2C, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(2CH_04H, 0x2C, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(2CH_07H, 0x2C, 0x07, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+
+    UCPDESCR(2DH_01H, 0x2D, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(2DH_02H, 0x2D, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(2DH_04H, 0x2D, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(2DH_07H, 0x2D, 0x07, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+
+    UCPDESCR(2EH_01H, 0x2E, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(2EH_02H, 0x2E, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(2EH_04H, 0x2E, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(2EH_07H, 0x2E, 0x07, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+
+    UCPDESCR(2FH_01H, 0x2F, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(2FH_02H, 0x2F, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(2FH_04H, 0x2F, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(2FH_07H, 0x2F, 0x07, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(2FH_08H, 0x2F, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(2FH_10H, 0x2F, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(2FH_20H, 0x2F, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(2FH_38H, 0x2F, 0x38, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+
+    UCPDESCR(30H_01H, 0x30, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(30H_02H, 0x30, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(30H_04H, 0x30, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(30H_07H, 0x30, 0x07, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+
+    UCPDESCR(31H_01H, 0x31, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(31H_02H, 0x31, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(31H_04H, 0x31, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(31H_07H, 0x31, 0x07, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+
+    UCPDESCR(32H_01H, 0x32, 0x01, UCP_F_FM | UCP_F_WM),
+    UCPDESCR(32H_02H, 0x32, 0x02, UCP_F_FM | UCP_F_WM),
+    UCPDESCR(32H_04H, 0x32, 0x04, UCP_F_FM | UCP_F_WM),
+    UCPDESCR(32H_07H, 0x32, 0x07, UCP_F_FM | UCP_F_WM),
+
+    UCPDESCR(33H_01H, 0x33, 0x01, UCP_F_FM | UCP_F_WM),
+    UCPDESCR(33H_02H, 0x33, 0x02, UCP_F_FM | UCP_F_WM),
+    UCPDESCR(33H_04H, 0x33, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(33H_07H, 0x33, 0x07, UCP_F_FM | UCP_F_WM),
+
+    UCPDESCR(34H_01H, 0x34, 0x01, UCP_F_FM | UCP_F_WM),
+    UCPDESCR(34H_02H, 0x34, 0x02, UCP_F_FM | UCP_F_WM),
+    UCPDESCR(34H_04H, 0x34, 0x04, UCP_F_FM | UCP_F_WM),
+    UCPDESCR(34H_08H, 0x34, 0x08, UCP_F_FM | UCP_F_WM),
+    UCPDESCR(34H_10H, 0x34, 0x10, UCP_F_FM | UCP_F_WM),
+    UCPDESCR(34H_20H, 0x34, 0x20, UCP_F_FM | UCP_F_WM),
+
+    UCPDESCR(35H_01H, 0x35, 0x01, UCP_F_FM | UCP_F_WM),
+    UCPDESCR(35H_02H, 0x35, 0x02, UCP_F_FM | UCP_F_WM),
+    UCPDESCR(35H_04H, 0x35, 0x04, UCP_F_FM | UCP_F_WM),
+
+    UCPDESCR(40H_01H, 0x40, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(40H_02H, 0x40, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(40H_04H, 0x40, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(40H_08H, 0x40, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(40H_10H, 0x40, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(40H_20H, 0x40, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(40H_07H, 0x40, 0x07, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(40H_38H, 0x40, 0x38, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+
+    UCPDESCR(41H_01H, 0x41, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(41H_02H, 0x41, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(41H_04H, 0x41, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(41H_08H, 0x41, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(41H_10H, 0x41, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(41H_20H, 0x41, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(41H_07H, 0x41, 0x07, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(41H_38H, 0x41, 0x38, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+
+    UCPDESCR(42H_01H, 0x42, 0x01, UCP_F_FM | UCP_F_WM),
+    UCPDESCR(42H_02H, 0x42, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(42H_04H, 0x42, 0x04, UCP_F_FM | UCP_F_WM),
+    UCPDESCR(42H_08H, 0x42, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+
+    UCPDESCR(43H_01H, 0x43, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(43H_02H, 0x43, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+
+    UCPDESCR(60H_01H, 0x60, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(60H_02H, 0x60, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(60H_04H, 0x60, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+
+    UCPDESCR(61H_01H, 0x61, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(61H_02H, 0x61, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(61H_04H, 0x61, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+
+    UCPDESCR(62H_01H, 0x62, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(62H_02H, 0x62, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(62H_04H, 0x62, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+
+    UCPDESCR(63H_01H, 0x63, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(63H_02H, 0x63, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(63H_04H, 0x63, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(63H_08H, 0x63, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(63H_10H, 0x63, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(63H_20H, 0x63, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+
+    UCPDESCR(64H_01H, 0x64, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(64H_02H, 0x64, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(64H_04H, 0x64, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(64H_08H, 0x64, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(64H_10H, 0x64, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(64H_20H, 0x64, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+
+    UCPDESCR(65H_01H, 0x65, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(65H_02H, 0x65, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(65H_04H, 0x65, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+
+    UCPDESCR(66H_01H, 0x66, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(66H_02H, 0x66, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(66H_04H, 0x66, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+
+    UCPDESCR(67H_01H, 0x67, 0x01, UCP_F_FM | UCP_F_WM),
+    UCPDESCR(80H_01H, 0x80, 0x01, UCP_F_FM | UCP_F_WM),
+    UCPDESCR(80H_02H, 0x80, 0x02, UCP_F_FM | UCP_F_WM),
+    UCPDESCR(80H_04H, 0x80, 0x04, UCP_F_FM | UCP_F_WM),
+    UCPDESCR(80H_08H, 0x80, 0x08, UCP_F_FM | UCP_F_WM),
+    UCPDESCR(81H_01H, 0x81, 0x01, UCP_F_FM | UCP_F_WM),
+    UCPDESCR(81H_02H, 0x81, 0x02, UCP_F_FM | UCP_F_WM),
+    UCPDESCR(81H_04H, 0x81, 0x04, UCP_F_FM | UCP_F_WM),
+    UCPDESCR(81H_08H, 0x81, 0x08, UCP_F_FM | UCP_F_WM),
+    UCPDESCR(82H_01H, 0x82, 0x01, UCP_F_FM | UCP_F_WM),
+    UCPDESCR(83H_01H, 0x83, 0x01, UCP_F_FM | UCP_F_WM),
+    UCPDESCR(83H_02H, 0x83, 0x02, UCP_F_FM | UCP_F_WM),
+    UCPDESCR(83H_04H, 0x83, 0x04, UCP_F_FM | UCP_F_WM),
+    UCPDESCR(83H_08H, 0x83, 0x08, UCP_F_FM | UCP_F_WM),
+    UCPDESCR(84H_01H, 0x84, 0x01, UCP_F_FM | UCP_F_WM),
+    UCPDESCR(84H_02H, 0x84, 0x02, UCP_F_FM | UCP_F_WM),
+    UCPDESCR(84H_04H, 0x84, 0x04, UCP_F_FM | UCP_F_WM),
+    UCPDESCR(84H_08H, 0x84, 0x08, UCP_F_FM | UCP_F_WM),
+    UCPDESCR(85H_02H, 0x85, 0x02, UCP_F_FM | UCP_F_WM),
+    UCPDESCR(86H_01H, 0x86, 0x01, UCP_F_FM | UCP_F_WM)
+};
+
+static const int nucp_events = sizeof(ucp_events) / sizeof(ucp_events[0]);
+
+static pmc_value_t
+ucp_perfctr_value_to_reload_count(pmc_value_t v)
+{
+	v &= (1ULL << uncore_ucp_width) - 1;
+	return (1ULL << uncore_ucp_width) - v;
+}
+
+static pmc_value_t
+ucp_reload_count_to_perfctr_value(pmc_value_t rlc)
+{
+	return (1ULL << uncore_ucp_width) - rlc;
+}
+
+static int
+ucp_allocate_pmc(int cpu, int ri, struct pmc *pm,
+    const struct pmc_op_pmcallocate *a)
+{
+	int n;
+	enum pmc_event ev;
+	struct ucp_event_descr *ie;
+	uint32_t caps, config, cpuflag, evsel;
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[uncore,%d] illegal CPU %d", __LINE__, cpu));
+	KASSERT(ri >= 0 && ri < uncore_ucp_npmc,
+	    ("[uncore,%d] illegal row-index value %d", __LINE__, ri));
+
+	/* check requested capabilities */
+	caps = a->pm_caps;
+	if ((UCP_PMC_CAPS & caps) != caps)
+		return (EPERM);
+
+	ev = pm->pm_event;
+
+	/*
+	 * Look for an event descriptor with matching CPU and event id
+	 * fields.
+	 */
+
+	switch (uncore_cputype) {
+	case PMC_CPU_INTEL_COREI7:
+		cpuflag = UCP_F_I7;
+		break;
+	case PMC_CPU_INTEL_WESTMERE:
+		cpuflag = UCP_F_WM;
+		break;
+	default:
+		return (EINVAL);
+	}
+
+	for (n = 0, ie = ucp_events; n < nucp_events; n++, ie++)
+		if (ie->ucp_ev == ev && ie->ucp_flags & cpuflag)
+			break;
+
+	if (n == nucp_events)
+		return (EINVAL);
+
+	/*
+	 * A matching event descriptor has been found, so start
+	 * assembling the contents of the event select register.
+	 */
+	evsel = ie->ucp_evcode | UCP_EN;
+
+	config = a->pm_md.pm_ucp.pm_ucp_config & ~UCP_F_CMASK;
+
+	/*
+	 * If the event uses a fixed umask value, reject any umask
+	 * bits set by the user.
+	 */
+	if (ie->ucp_flags & UCP_F_FM) {
+
+		if (UCP_UMASK(config) != 0)
+			return (EINVAL);
+
+		evsel |= (ie->ucp_umask << 8);
+
+	} else
+		return (EINVAL);
+
+	if (caps & PMC_CAP_THRESHOLD)
+		evsel |= (a->pm_md.pm_ucp.pm_ucp_config & UCP_F_CMASK);
+	if (caps & PMC_CAP_EDGE)
+		evsel |= UCP_EDGE;
+	if (caps & PMC_CAP_INVERT)
+		evsel |= UCP_INV;
+
+	pm->pm_md.pm_ucp.pm_ucp_evsel = evsel;
+
+	return (0);
+}
+
+static int
+ucp_config_pmc(int cpu, int ri, struct pmc *pm)
+{
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[uncore,%d] illegal CPU %d", __LINE__, cpu));
+
+	KASSERT(ri >= 0 && ri < uncore_ucp_npmc,
+	    ("[uncore,%d] illegal row-index %d", __LINE__, ri));
+
+	PMCDBG(MDP,CFG,1, "ucp-config cpu=%d ri=%d pm=%p", cpu, ri, pm);
+
+	KASSERT(uncore_pcpu[cpu] != NULL, ("[uncore,%d] null per-cpu %d", __LINE__,
+	    cpu));
+
+	uncore_pcpu[cpu]->pc_uncorepmcs[ri].phw_pmc = pm;
+
+	return (0);
+}
+
+static int
+ucp_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc)
+{
+	int error;
+	struct pmc_hw *phw;
+	char ucp_name[PMC_NAME_MAX];
+
+	phw = &uncore_pcpu[cpu]->pc_uncorepmcs[ri];
+
+	(void) snprintf(ucp_name, sizeof(ucp_name), "UCP-%d", ri);
+	if ((error = copystr(ucp_name, pi->pm_name, PMC_NAME_MAX,
+	    NULL)) != 0)
+		return (error);
+
+	pi->pm_class = PMC_CLASS_UCP;
+
+	if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) {
+		pi->pm_enabled = TRUE;
+		*ppmc          = phw->phw_pmc;
+	} else {
+		pi->pm_enabled = FALSE;
+		*ppmc          = NULL;
+	}
+
+	return (0);
+}
+
+static int
+ucp_get_config(int cpu, int ri, struct pmc **ppm)
+{
+	*ppm = uncore_pcpu[cpu]->pc_uncorepmcs[ri].phw_pmc;
+
+	return (0);
+}
+
+static int
+ucp_read_pmc(int cpu, int ri, pmc_value_t *v)
+{
+	struct pmc *pm;
+	pmc_value_t tmp;
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[uncore,%d] illegal cpu value %d", __LINE__, cpu));
+	KASSERT(ri >= 0 && ri < uncore_ucp_npmc,
+	    ("[uncore,%d] illegal row-index %d", __LINE__, ri));
+
+	pm = uncore_pcpu[cpu]->pc_uncorepmcs[ri].phw_pmc;
+
+	KASSERT(pm,
+	    ("[uncore,%d] cpu %d ri %d pmc not configured", __LINE__, cpu,
+		ri));
+
+	tmp = rdmsr(UCP_PMC0 + ri);
+	if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
+		*v = ucp_perfctr_value_to_reload_count(tmp);
+	else
+		*v = tmp;
+
+	PMCDBG(MDP,REA,1, "ucp-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri,
+	    ri, *v);
+
+	return (0);
+}
+
+static int
+ucp_release_pmc(int cpu, int ri, struct pmc *pm)
+{
+	(void) pm;
+
+	PMCDBG(MDP,REL,1, "ucp-release cpu=%d ri=%d pm=%p", cpu, ri,
+	    pm);
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[uncore,%d] illegal CPU value %d", __LINE__, cpu));
+	KASSERT(ri >= 0 && ri < uncore_ucp_npmc,
+	    ("[uncore,%d] illegal row-index %d", __LINE__, ri));
+
+	KASSERT(uncore_pcpu[cpu]->pc_uncorepmcs[ri].phw_pmc
+	    == NULL, ("[uncore,%d] PHW pmc non-NULL", __LINE__));
+
+	return (0);
+}
+
+static int
+ucp_start_pmc(int cpu, int ri)
+{
+	struct pmc *pm;
+	uint32_t evsel;
+	struct uncore_cpu *cc;
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[uncore,%d] illegal CPU value %d", __LINE__, cpu));
+	KASSERT(ri >= 0 && ri < uncore_ucp_npmc,
+	    ("[uncore,%d] illegal row-index %d", __LINE__, ri));
+
+	cc = uncore_pcpu[cpu];
+	pm = cc->pc_uncorepmcs[ri].phw_pmc;
+
+	KASSERT(pm,
+	    ("[uncore,%d] starting cpu%d,ri%d with no pmc configured",
+		__LINE__, cpu, ri));
+
+	PMCDBG(MDP,STA,1, "ucp-start cpu=%d ri=%d", cpu, ri);
+
+	evsel = pm->pm_md.pm_ucp.pm_ucp_evsel;
+
+	PMCDBG(MDP,STA,2, "ucp-start/2 cpu=%d ri=%d evselmsr=0x%x evsel=0x%x",
+	    cpu, ri, UCP_EVSEL0 + ri, evsel);
+
+	wrmsr(UCP_EVSEL0 + ri, evsel);
+
+	do {
+		cc->pc_resync = 0;
+		cc->pc_globalctrl |= (1ULL << ri);
+		wrmsr(UC_GLOBAL_CTRL, cc->pc_globalctrl);
+	} while (cc->pc_resync != 0);
+
+	return (0);
+}
+
+static int
+ucp_stop_pmc(int cpu, int ri)
+{
+	struct pmc *pm;
+	struct uncore_cpu *cc;
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[uncore,%d] illegal cpu value %d", __LINE__, cpu));
+	KASSERT(ri >= 0 && ri < uncore_ucp_npmc,
+	    ("[uncore,%d] illegal row index %d", __LINE__, ri));
+
+	cc = uncore_pcpu[cpu];
+	pm = cc->pc_uncorepmcs[ri].phw_pmc;
+
+	KASSERT(pm,
+	    ("[uncore,%d] cpu%d ri%d no configured PMC to stop", __LINE__,
+		cpu, ri));
+
+	PMCDBG(MDP,STO,1, "ucp-stop cpu=%d ri=%d", cpu, ri);
+
+	wrmsr(UCP_EVSEL0 + ri, 0);	/* stop hw */
+
+	do {
+		cc->pc_resync = 0;
+		cc->pc_globalctrl &= ~(1ULL << ri);
+		wrmsr(UC_GLOBAL_CTRL, cc->pc_globalctrl);
+	} while (cc->pc_resync != 0);
+
+	return (0);
+}
+
+static int
+ucp_write_pmc(int cpu, int ri, pmc_value_t v)
+{
+	struct pmc *pm;
+	struct uncore_cpu *cc;
+
+	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
+	    ("[uncore,%d] illegal cpu value %d", __LINE__, cpu));
+	KASSERT(ri >= 0 && ri < uncore_ucp_npmc,
+	    ("[uncore,%d] illegal row index %d", __LINE__, ri));
+
+	cc = uncore_pcpu[cpu];
+	pm = cc->pc_uncorepmcs[ri].phw_pmc;
+
+	KASSERT(pm,
+	    ("[uncore,%d] cpu%d ri%d no configured PMC to stop", __LINE__,
+		cpu, ri));
+
+	PMCDBG(MDP,WRI,1, "ucp-write cpu=%d ri=%d msr=0x%x v=%jx", cpu, ri,
+	    UCP_PMC0 + ri, v);
+
+	if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
+		v = ucp_reload_count_to_perfctr_value(v);
+
+	/*
+	 * Write the new value to the counter.  The counter will be in
+	 * a stopped state when the pcd_write() entry point is called.
+	 */
+
+	wrmsr(UCP_PMC0 + ri, v);
+
+	return (0);
+}
+
+
+static void
+ucp_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth)
+{
+	struct pmc_classdep *pcd;
+
+	KASSERT(md != NULL, ("[ucp,%d] md is NULL", __LINE__));
+
+	PMCDBG(MDP,INI,1, "%s", "ucp-initialize");
+
+	pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCP];
+
+	pcd->pcd_caps	= UCP_PMC_CAPS;
+	pcd->pcd_class	= PMC_CLASS_UCP;
+	pcd->pcd_num	= npmc;
+	pcd->pcd_ri	= md->pmd_npmc;
+	pcd->pcd_width	= pmcwidth;
+
+	pcd->pcd_allocate_pmc	= ucp_allocate_pmc;
+	pcd->pcd_config_pmc	= ucp_config_pmc;
+	pcd->pcd_describe	= ucp_describe;
+	pcd->pcd_get_config	= ucp_get_config;
+	pcd->pcd_get_msr	= NULL;
+	pcd->pcd_pcpu_fini	= uncore_pcpu_fini;
+	pcd->pcd_pcpu_init	= uncore_pcpu_init;
+	pcd->pcd_read_pmc	= ucp_read_pmc;
+	pcd->pcd_release_pmc	= ucp_release_pmc;
+	pcd->pcd_start_pmc	= ucp_start_pmc;
+	pcd->pcd_stop_pmc	= ucp_stop_pmc;
+	pcd->pcd_write_pmc	= ucp_write_pmc;
+
+	md->pmd_npmc	       += npmc;
+}
+
+int
+pmc_uncore_initialize(struct pmc_mdep *md, int maxcpu)
+{
+	uncore_cputype = md->pmd_cputype;
+	uncore_pmcmask = 0;
+
+	/*
+	 * Initialize programmable counters.
+	 */
+
+	uncore_ucp_npmc  = 8;
+	uncore_ucp_width = 48;
+
+	uncore_pmcmask |= ((1ULL << uncore_ucp_npmc) - 1);
+
+	ucp_initialize(md, maxcpu, uncore_ucp_npmc, uncore_ucp_width);
+
+	/*
+	 * Initialize fixed function counters, if present.
+	 */
+	uncore_ucf_ri = uncore_ucp_npmc;
+	uncore_ucf_npmc  = 1;
+	uncore_ucf_width = 48;
+
+	ucf_initialize(md, maxcpu, uncore_ucf_npmc, uncore_ucf_width);
+	uncore_pmcmask |= ((1ULL << uncore_ucf_npmc) - 1) << UCF_OFFSET;
+
+	PMCDBG(MDP,INI,1,"uncore-init pmcmask=0x%jx ucfri=%d", uncore_pmcmask,
+	    uncore_ucf_ri);
+
+	uncore_pcpu = malloc(sizeof(struct uncore_cpu **) * maxcpu, M_PMC,
+	    M_ZERO | M_WAITOK);
+
+	return (0);
+}
+
+void
+pmc_uncore_finalize(struct pmc_mdep *md)
+{
+	PMCDBG(MDP,INI,1, "%s", "uncore-finalize");
+
+	free(uncore_pcpu, M_PMC);
+	uncore_pcpu = NULL;
+}
diff --git a/sys/dev/misc/hwpmc/hwpmc_uncore.h b/sys/dev/misc/hwpmc/hwpmc_uncore.h
new file mode 100644
index 0000000..da482e8
--- /dev/null
+++ b/sys/dev/misc/hwpmc/hwpmc_uncore.h
@@ -0,0 +1,120 @@
+/*-
+ * Copyright (c) 2010 Fabien Thomas
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: src/sys/dev/hwpmc/hwpmc_uncore.h,v 1.1 2010/04/02 13:23:49 fabient Exp $
+ */
+
+#ifndef _DEV_HWPMC_UNCORE_H_
+#define	_DEV_HWPMC_UNCORE_H_ 1
+
+/*
+ * Fixed-function PMCs.
+ */
+struct pmc_md_ucf_op_pmcallocate {
+	uint16_t	pm_ucf_flags;	/* additional flags */
+};
+
+#define	UCF_EN		0x1
+#define	UCF_PMI		0x4
+
+/*
+ * Programmable PMCs.
+ */
+struct pmc_md_ucp_op_pmcallocate {
+	uint32_t	pm_ucp_config;
+};
+
+#define	UCP_EVSEL(C)	((C) & 0xFF)
+#define	UCP_UMASK(C)	((C) & 0xFF00)
+#define	UCP_CTRR	(1 << 17)
+#define	UCP_EDGE	(1 << 18)
+#define	UCP_INT		(1 << 20)
+#define	UCP_EN		(1 << 22)
+#define	UCP_INV		(1 << 23)
+#define	UCP_CMASK(C)	(((C) & 0xFF) << 24)
+
+#ifdef	_KERNEL
+
+#define	DCTL_FLAG_UNC_PMI	(1ULL << 13)
+
+/*
+ * Fixed-function counters.
+ */
+
+#define	UCF_MASK				0xF
+
+#define	UCF_CTR0				0x394
+
+#define	UCF_OFFSET				32
+#define	UCF_CTRL				0x395
+
+/*
+ * Programmable counters.
+ */
+
+#define	UCP_PMC0				0x3B0
+#define	UCP_EVSEL0				0x3C0
+#define UCP_OPCODE_MATCH			0x396
+
+/*
+ * Simplified programming interface in Intel Performance Architecture
+ * v2 and later.
+ */
+
+#define	UC_GLOBAL_STATUS			0x392
+#define	UC_GLOBAL_CTRL				0x391
+#define	UC_GLOBAL_OVF_CTRL			0x393
+
+#define	UC_GLOBAL_STATUS_FLAG_CLRCHG		(1ULL << 63)
+#define	UC_GLOBAL_STATUS_FLAG_OVFPMI		(1ULL << 61)
+#define	UC_GLOBAL_CTRL_FLAG_FRZ			(1ULL << 63)
+#define	UC_GLOBAL_CTRL_FLAG_ENPMICORE0		(1ULL << 48)
+
+struct pmc_md_ucf_pmc {
+	uint64_t	pm_ucf_ctrl;
+};
+
+struct pmc_md_ucp_pmc {
+	uint32_t	pm_ucp_evsel;
+};
+
+/*
+ * Prototypes.
+ */
+
+int	pmc_uncore_initialize(struct pmc_mdep *_md, int _maxcpu);
+void	pmc_uncore_finalize(struct pmc_mdep *_md);
+
+void	pmc_uncore_mark_started(int _cpu, int _pmc);
+
+int	pmc_ucf_initialize(struct pmc_mdep *_md, int _maxcpu, int _npmc, int _width);
+void	pmc_ucf_finalize(struct pmc_mdep *_md);
+
+int	pmc_ucp_initialize(struct pmc_mdep *_md, int _maxcpu, int _npmc, int _width,
+	    int _flags);
+void	pmc_ucp_finalize(struct pmc_mdep *_md);
+
+#endif	/* _KERNEL */
+#endif	/* _DEV_HWPMC_UNCORE_H */
diff --git a/sys/dev/misc/hwpmc/hwpmc_x86.c b/sys/dev/misc/hwpmc/hwpmc_x86.c
new file mode 100644
index 0000000..c77d6e3
--- /dev/null
+++ b/sys/dev/misc/hwpmc/hwpmc_x86.c
@@ -0,0 +1,271 @@
+/*-
+ * Copyright (c) 2005,2008 Joseph Koshy
+ * Copyright (c) 2007 The FreeBSD Foundation
+ * All rights reserved.
+ *
+ * Portions of this software were developed by A. Joseph Koshy under
+ * sponsorship from the FreeBSD Foundation and Google, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: src/sys/dev/hwpmc/hwpmc_x86.c,v 1.14 2009/12/03 14:59:42 jkoshy Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/pmc.h>
+#include <sys/proc.h>
+#include <sys/systm.h>
+
+#include <machine/cpu.h>
+#include <machine/cputypes.h>
+#include <machine/intr_machdep.h>
+#include <machine/apicvar.h>
+#include <machine/pmc_mdep.h>
+#include <machine/md_var.h>
+
+#include <vm/vm.h>
+#include <vm/vm_param.h>
+#include <vm/pmap.h>
+
+/*
+ * Attempt to walk a user call stack using a too-simple algorithm.
+ * In the general case we need unwind information associated with
+ * the executable to be able to walk the user stack.
+ *
+ * We are handed a trap frame laid down at the time the PMC interrupt
+ * was taken.  If the application is using frame pointers, the saved
+ * PC value could be:
+ * a. at the beginning of a function before the stack frame is laid
+ *    down,
+ * b. just before a 'ret', after the stack frame has been taken off,
+ * c. somewhere else in the function with a valid stack frame being
+ *    present,
+ *
+ * If the application is not using frame pointers, this algorithm will
+ * fail to yield an interesting call chain.
+ *
+ * TODO: figure out a way to use unwind information.
+ */
+
+int
+pmc_save_user_callchain(uintptr_t *cc, int nframes, struct trapframe *tf)
+{
+	int n;
+	uint32_t instr;
+	uintptr_t fp, oldfp, pc, r, sp;
+
+	KASSERT(TRAPF_USERMODE(tf), ("[x86,%d] Not a user trap frame tf=%p",
+	    __LINE__, (void *) tf));
+
+	pc = PMC_TRAPFRAME_TO_PC(tf);
+	oldfp = fp = PMC_TRAPFRAME_TO_FP(tf);
+	sp = PMC_TRAPFRAME_TO_USER_SP(tf);
+
+	*cc++ = pc; n = 1;
+
+	r = fp + sizeof(uintptr_t); /* points to return address */
+
+	if (!PMC_IN_USERSPACE(pc))
+		return (n);
+
+	if (copyin((void *) pc, &instr, sizeof(instr)) != 0)
+		return (n);
+
+	if (PMC_AT_FUNCTION_PROLOGUE_PUSH_BP(instr) ||
+	    PMC_AT_FUNCTION_EPILOGUE_RET(instr)) { /* ret */
+		if (copyin((void *) sp, &pc, sizeof(pc)) != 0)
+			return (n);
+	} else if (PMC_AT_FUNCTION_PROLOGUE_MOV_SP_BP(instr)) {
+		sp += sizeof(uintptr_t);
+		if (copyin((void *) sp, &pc, sizeof(pc)) != 0)
+			return (n);
+	} else if (copyin((void *) r, &pc, sizeof(pc)) != 0 ||
+	    copyin((void *) fp, &fp, sizeof(fp)) != 0)
+		return (n);
+
+	for (; n < nframes;) {
+		if (pc == 0 || !PMC_IN_USERSPACE(pc))
+			break;
+
+		*cc++ = pc; n++;
+
+		if (fp < oldfp)
+			break;
+
+		r = fp + sizeof(uintptr_t); /* address of return address */
+		oldfp = fp;
+
+		if (copyin((void *) r, &pc, sizeof(pc)) != 0 ||
+		    copyin((void *) fp, &fp, sizeof(fp)) != 0)
+			break;
+	}
+
+	return (n);
+}
+
+/*
+ * Walking the kernel call stack.
+ *
+ * We are handed the trap frame laid down at the time the PMC
+ * interrupt was taken.  The saved PC could be:
+ * a. in the lowlevel trap handler, meaning that there isn't a C stack
+ *    to traverse,
+ * b. at the beginning of a function before the stack frame is laid
+ *    down,
+ * c. just before a 'ret', after the stack frame has been taken off,
+ * d. somewhere else in a function with a valid stack frame being
+ *    present.
+ *
+ * In case (d), the previous frame pointer is at [%ebp]/[%rbp] and
+ * the return address is at [%ebp+4]/[%rbp+8].
+ *
+ * For cases (b) and (c), the return address is at [%esp]/[%rsp] and
+ * the frame pointer doesn't need to be changed when going up one
+ * level in the stack.
+ *
+ * For case (a), we check if the PC lies in low-level trap handling
+ * code, and if so we terminate our trace.
+ */
+
+int
+pmc_save_kernel_callchain(uintptr_t *cc, int nframes, struct trapframe *tf)
+{
+	int n;
+	uint32_t instr;
+	uintptr_t fp, pc, r, sp, stackstart, stackend;
+	struct thread *td;
+
+	KASSERT(TRAPF_USERMODE(tf) == 0,("[x86,%d] not a kernel backtrace",
+	    __LINE__));
+
+	pc = PMC_TRAPFRAME_TO_PC(tf);
+	fp = PMC_TRAPFRAME_TO_FP(tf);
+	sp = PMC_TRAPFRAME_TO_KERNEL_SP(tf);
+
+	*cc++ = pc;
+	r = fp + sizeof(uintptr_t); /* points to return address */
+
+	if ((td = curthread) == NULL)
+		return (1);
+
+	if (nframes <= 1)
+		return (1);
+
+	stackstart = (uintptr_t) td->td_kstack;
+	stackend = (uintptr_t) td->td_kstack + td->td_kstack_pages * PAGE_SIZE;
+
+	if (PMC_IN_TRAP_HANDLER(pc) ||
+	    !PMC_IN_KERNEL(pc) ||
+	    !PMC_IN_KERNEL_STACK(r, stackstart, stackend) ||
+	    !PMC_IN_KERNEL_STACK(sp, stackstart, stackend) ||
+	    !PMC_IN_KERNEL_STACK(fp, stackstart, stackend))
+		return (1);
+
+	instr = *(uint32_t *) pc;
+
+	/*
+	 * Determine whether the interrupted function was in the
+	 * processing of either laying down its stack frame or taking
+	 * it off.
+	 *
+	 * If we haven't started laying down a stack frame, or are
+	 * just about to return, then our caller's address is at
+	 * *sp, and we don't have a frame to unwind.
+	 */
+	if (PMC_AT_FUNCTION_PROLOGUE_PUSH_BP(instr) ||
+	    PMC_AT_FUNCTION_EPILOGUE_RET(instr))
+		pc = *(uintptr_t *) sp;
+	else if (PMC_AT_FUNCTION_PROLOGUE_MOV_SP_BP(instr)) {
+		/*
+		 * The code was midway through laying down a frame.
+		 * At this point sp[0] has a frame back pointer,
+		 * and the caller's address is therefore at sp[1].
+		 */
+		sp += sizeof(uintptr_t);
+		if (!PMC_IN_KERNEL_STACK(sp, stackstart, stackend))
+			return (1);
+		pc = *(uintptr_t *) sp;
+	} else {
+		/*
+		 * Not in the function prologue or epilogue.
+		 */
+		pc = *(uintptr_t *) r;
+		fp = *(uintptr_t *) fp;
+	}
+
+	for (n = 1; n < nframes; n++) {
+		*cc++ = pc;
+
+		if (PMC_IN_TRAP_HANDLER(pc))
+			break;
+
+		r = fp + sizeof(uintptr_t);
+		if (!PMC_IN_KERNEL_STACK(fp, stackstart, stackend) ||
+		    !PMC_IN_KERNEL_STACK(r, stackstart, stackend))
+			break;
+		pc = *(uintptr_t *) r;
+		fp = *(uintptr_t *) fp;
+	}
+
+	return (n);
+}
+
+/*
+ * Machine dependent initialization for x86 class platforms.
+ */
+
+struct pmc_mdep *
+pmc_md_initialize()
+{
+	int i;
+	struct pmc_mdep *md;
+
+	/* determine the CPU kind */
+	if (cpu_vendor_id == CPU_VENDOR_AMD)
+		md = pmc_amd_initialize();
+	else if (cpu_vendor_id == CPU_VENDOR_INTEL)
+		md = pmc_intel_initialize();
+	else
+		return (NULL);
+
+	/* disallow sampling if we do not have an LAPIC */
+	if (!lapic_enable_pmc())
+		for (i = 1; i < md->pmd_nclass; i++)
+			md->pmd_classdep[i].pcd_caps &= ~PMC_CAP_INTERRUPT;
+
+	return (md);
+}
+
+void
+pmc_md_finalize(struct pmc_mdep *md)
+{
+
+	lapic_disable_pmc();
+	if (cpu_vendor_id == CPU_VENDOR_AMD)
+		pmc_amd_finalize(md);
+	else if (cpu_vendor_id == CPU_VENDOR_INTEL)
+		pmc_intel_finalize(md);
+	else
+		KASSERT(0, ("[x86,%d] Unknown vendor", __LINE__));
+}
diff --git a/sys/dev/misc/hwpmc/pmc_events.h b/sys/dev/misc/hwpmc/pmc_events.h
new file mode 100644
index 0000000..499c7cd
--- /dev/null
+++ b/sys/dev/misc/hwpmc/pmc_events.h
@@ -0,0 +1,3145 @@
+/*-
+ * Copyright (c) 2005  Joseph Koshy
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: src/sys/dev/hwpmc/pmc_events.h,v 1.16 2010/10/04 17:22:18 gnn Exp $
+ */
+
+#ifndef _DEV_HWPMC_PMC_EVENTS_H_
+#define	_DEV_HWPMC_PMC_EVENTS_H_
+
+/*
+ * Note: Documentation on adding events can be found both in
+ * the source tree at src/share/doc/papers/hwpmc/hwpmc.ms
+ * as well as on-line at:
+ *
+ * http://wiki.freebsd.org/PmcTools/PmcHardwareHowTo
+ *
+ * Please refer to those resources before you attempt to modify
+ * this file or the hwpmc driver/subsystem.
+ */
+
+/* * PMC event codes.
+ *
+ * __PMC_EV(CLASS, SYMBOLIC-NAME)
+ *
+ */
+
+/*
+ * AMD K7 Events, from "The AMD Athlon(tm) Processor x86 Code
+ * Optimization Guide" [Doc#22007K, Feb 2002]
+ */
+
+#define	__PMC_EV_K7()					\
+__PMC_EV(K7, DC_ACCESSES)				\
+__PMC_EV(K7, DC_MISSES)					\
+__PMC_EV(K7, DC_REFILLS_FROM_L2)			\
+__PMC_EV(K7, DC_REFILLS_FROM_SYSTEM)			\
+__PMC_EV(K7, DC_WRITEBACKS)				\
+__PMC_EV(K7, L1_DTLB_MISS_AND_L2_DTLB_HITS)		\
+__PMC_EV(K7, L1_AND_L2_DTLB_MISSES)			\
+__PMC_EV(K7, MISALIGNED_REFERENCES)			\
+__PMC_EV(K7, IC_FETCHES)				\
+__PMC_EV(K7, IC_MISSES)					\
+__PMC_EV(K7, L1_ITLB_MISSES)				\
+__PMC_EV(K7, L1_L2_ITLB_MISSES)				\
+__PMC_EV(K7, RETIRED_INSTRUCTIONS)			\
+__PMC_EV(K7, RETIRED_OPS)				\
+__PMC_EV(K7, RETIRED_BRANCHES)				\
+__PMC_EV(K7, RETIRED_BRANCHES_MISPREDICTED)		\
+__PMC_EV(K7, RETIRED_TAKEN_BRANCHES)			\
+__PMC_EV(K7, RETIRED_TAKEN_BRANCHES_MISPREDICTED)	\
+__PMC_EV(K7, RETIRED_FAR_CONTROL_TRANSFERS)		\
+__PMC_EV(K7, RETIRED_RESYNC_BRANCHES)			\
+__PMC_EV(K7, INTERRUPTS_MASKED_CYCLES)			\
+__PMC_EV(K7, INTERRUPTS_MASKED_WHILE_PENDING_CYCLES)	\
+__PMC_EV(K7, HARDWARE_INTERRUPTS)
+
+#define	PMC_EV_K7_FIRST	PMC_EV_K7_DC_ACCESSES
+#define	PMC_EV_K7_LAST	PMC_EV_K7_HARDWARE_INTERRUPTS
+
+
+/*
+ * Intel P4 Events, from "IA-32 Intel(r) Architecture Software
+ * Developer's Manual, Volume 3: System Programming Guide" [245472-012]
+ */
+
+#define	__PMC_EV_P4()				\
+__PMC_EV(P4, TC_DELIVER_MODE)			\
+__PMC_EV(P4, BPU_FETCH_REQUEST)			\
+__PMC_EV(P4, ITLB_REFERENCE)			\
+__PMC_EV(P4, MEMORY_CANCEL)			\
+__PMC_EV(P4, MEMORY_COMPLETE)			\
+__PMC_EV(P4, LOAD_PORT_REPLAY)			\
+__PMC_EV(P4, STORE_PORT_REPLAY)			\
+__PMC_EV(P4, MOB_LOAD_REPLAY)			\
+__PMC_EV(P4, PAGE_WALK_TYPE)			\
+__PMC_EV(P4, BSQ_CACHE_REFERENCE)		\
+__PMC_EV(P4, IOQ_ALLOCATION)			\
+__PMC_EV(P4, IOQ_ACTIVE_ENTRIES)		\
+__PMC_EV(P4, FSB_DATA_ACTIVITY)			\
+__PMC_EV(P4, BSQ_ALLOCATION)			\
+__PMC_EV(P4, BSQ_ACTIVE_ENTRIES)		\
+__PMC_EV(P4, SSE_INPUT_ASSIST)			\
+__PMC_EV(P4, PACKED_SP_UOP)			\
+__PMC_EV(P4, PACKED_DP_UOP)			\
+__PMC_EV(P4, SCALAR_SP_UOP)			\
+__PMC_EV(P4, SCALAR_DP_UOP)			\
+__PMC_EV(P4, 64BIT_MMX_UOP)			\
+__PMC_EV(P4, 128BIT_MMX_UOP)			\
+__PMC_EV(P4, X87_FP_UOP)			\
+__PMC_EV(P4, X87_SIMD_MOVES_UOP)		\
+__PMC_EV(P4, GLOBAL_POWER_EVENTS)		\
+__PMC_EV(P4, TC_MS_XFER)			\
+__PMC_EV(P4, UOP_QUEUE_WRITES)			\
+__PMC_EV(P4, RETIRED_MISPRED_BRANCH_TYPE)	\
+__PMC_EV(P4, RETIRED_BRANCH_TYPE)		\
+__PMC_EV(P4, RESOURCE_STALL)			\
+__PMC_EV(P4, WC_BUFFER)				\
+__PMC_EV(P4, B2B_CYCLES)			\
+__PMC_EV(P4, BNR)				\
+__PMC_EV(P4, SNOOP)				\
+__PMC_EV(P4, RESPONSE)				\
+__PMC_EV(P4, FRONT_END_EVENT)			\
+__PMC_EV(P4, EXECUTION_EVENT)			\
+__PMC_EV(P4, REPLAY_EVENT)			\
+__PMC_EV(P4, INSTR_RETIRED)			\
+__PMC_EV(P4, UOPS_RETIRED)			\
+__PMC_EV(P4, UOP_TYPE)				\
+__PMC_EV(P4, BRANCH_RETIRED)			\
+__PMC_EV(P4, MISPRED_BRANCH_RETIRED)		\
+__PMC_EV(P4, X87_ASSIST)			\
+__PMC_EV(P4, MACHINE_CLEAR)
+
+#define	PMC_EV_P4_FIRST PMC_EV_P4_TC_DELIVER_MODE
+#define	PMC_EV_P4_LAST	PMC_EV_P4_MACHINE_CLEAR
+
+/* Intel Pentium Pro, P-II, P-III and Pentium-M style events */
+
+#define	__PMC_EV_P6()				\
+__PMC_EV(P6, DATA_MEM_REFS)			\
+__PMC_EV(P6, DCU_LINES_IN)			\
+__PMC_EV(P6, DCU_M_LINES_IN)			\
+__PMC_EV(P6, DCU_M_LINES_OUT)			\
+__PMC_EV(P6, DCU_MISS_OUTSTANDING)		\
+__PMC_EV(P6, IFU_FETCH)				\
+__PMC_EV(P6, IFU_FETCH_MISS)			\
+__PMC_EV(P6, ITLB_MISS)				\
+__PMC_EV(P6, IFU_MEM_STALL)			\
+__PMC_EV(P6, ILD_STALL)				\
+__PMC_EV(P6, L2_IFETCH)				\
+__PMC_EV(P6, L2_LD)				\
+__PMC_EV(P6, L2_ST)				\
+__PMC_EV(P6, L2_LINES_IN)			\
+__PMC_EV(P6, L2_LINES_OUT)			\
+__PMC_EV(P6, L2_M_LINES_INM)			\
+__PMC_EV(P6, L2_M_LINES_OUTM)			\
+__PMC_EV(P6, L2_RQSTS)				\
+__PMC_EV(P6, L2_ADS)				\
+__PMC_EV(P6, L2_DBUS_BUSY)			\
+__PMC_EV(P6, L2_DBUS_BUSY_RD)			\
+__PMC_EV(P6, BUS_DRDY_CLOCKS)			\
+__PMC_EV(P6, BUS_LOCK_CLOCKS)			\
+__PMC_EV(P6, BUS_REQ_OUTSTANDING)		\
+__PMC_EV(P6, BUS_TRAN_BRD)			\
+__PMC_EV(P6, BUS_TRAN_RFO)			\
+__PMC_EV(P6, BUS_TRANS_WB)			\
+__PMC_EV(P6, BUS_TRAN_IFETCH)			\
+__PMC_EV(P6, BUS_TRAN_INVAL)			\
+__PMC_EV(P6, BUS_TRAN_PWR)			\
+__PMC_EV(P6, BUS_TRANS_P)			\
+__PMC_EV(P6, BUS_TRANS_IO)			\
+__PMC_EV(P6, BUS_TRAN_DEF)			\
+__PMC_EV(P6, BUS_TRAN_BURST)			\
+__PMC_EV(P6, BUS_TRAN_ANY)			\
+__PMC_EV(P6, BUS_TRAN_MEM)			\
+__PMC_EV(P6, BUS_DATA_RCV)			\
+__PMC_EV(P6, BUS_BNR_DRV)			\
+__PMC_EV(P6, BUS_HIT_DRV)			\
+__PMC_EV(P6, BUS_HITM_DRV)			\
+__PMC_EV(P6, BUS_SNOOP_STALL)			\
+__PMC_EV(P6, FLOPS)				\
+__PMC_EV(P6, FP_COMPS_OPS_EXE)			\
+__PMC_EV(P6, FP_ASSIST)				\
+__PMC_EV(P6, MUL)				\
+__PMC_EV(P6, DIV)				\
+__PMC_EV(P6, CYCLES_DIV_BUSY)			\
+__PMC_EV(P6, LD_BLOCKS)				\
+__PMC_EV(P6, SB_DRAINS)				\
+__PMC_EV(P6, MISALIGN_MEM_REF)			\
+__PMC_EV(P6, EMON_KNI_PREF_DISPATCHED)		\
+__PMC_EV(P6, EMON_KNI_PREF_MISS)		\
+__PMC_EV(P6, INST_RETIRED)			\
+__PMC_EV(P6, UOPS_RETIRED)			\
+__PMC_EV(P6, INST_DECODED)			\
+__PMC_EV(P6, EMON_KNI_INST_RETIRED)		\
+__PMC_EV(P6, EMON_KNI_COMP_INST_RET)		\
+__PMC_EV(P6, HW_INT_RX)				\
+__PMC_EV(P6, CYCLES_INT_MASKED)			\
+__PMC_EV(P6, CYCLES_INT_PENDING_AND_MASKED)	\
+__PMC_EV(P6, BR_INST_RETIRED)			\
+__PMC_EV(P6, BR_MISS_PRED_RETIRED)		\
+__PMC_EV(P6, BR_TAKEN_RETIRED)			\
+__PMC_EV(P6, BR_MISS_PRED_TAKEN_RET)		\
+__PMC_EV(P6, BR_INST_DECODED)			\
+__PMC_EV(P6, BTB_MISSES)			\
+__PMC_EV(P6, BR_BOGUS)				\
+__PMC_EV(P6, BACLEARS)				\
+__PMC_EV(P6, RESOURCE_STALLS)			\
+__PMC_EV(P6, PARTIAL_RAT_STALLS)		\
+__PMC_EV(P6, SEGMENT_REG_LOADS)			\
+__PMC_EV(P6, CPU_CLK_UNHALTED)			\
+__PMC_EV(P6, MMX_INSTR_EXEC)			\
+__PMC_EV(P6, MMX_SAT_INSTR_EXEC)		\
+__PMC_EV(P6, MMX_UOPS_EXEC)			\
+__PMC_EV(P6, MMX_INSTR_TYPE_EXEC)		\
+__PMC_EV(P6, FP_MMX_TRANS)			\
+__PMC_EV(P6, MMX_ASSIST)			\
+__PMC_EV(P6, MMX_INSTR_RET)			\
+__PMC_EV(P6, SEG_RENAME_STALLS)			\
+__PMC_EV(P6, SEG_REG_RENAMES)			\
+__PMC_EV(P6, RET_SEG_RENAMES)			\
+__PMC_EV(P6, EMON_EST_TRANS)			\
+__PMC_EV(P6, EMON_THERMAL_TRIP)			\
+__PMC_EV(P6, BR_INST_EXEC)			\
+__PMC_EV(P6, BR_MISSP_EXEC)			\
+__PMC_EV(P6, BR_BAC_MISSP_EXEC)			\
+__PMC_EV(P6, BR_CND_EXEC)			\
+__PMC_EV(P6, BR_CND_MISSP_EXEC)			\
+__PMC_EV(P6, BR_IND_EXEC)			\
+__PMC_EV(P6, BR_IND_MISSP_EXEC)			\
+__PMC_EV(P6, BR_RET_EXEC)			\
+__PMC_EV(P6, BR_RET_MISSP_EXEC)			\
+__PMC_EV(P6, BR_RET_BAC_MISSP_EXEC)		\
+__PMC_EV(P6, BR_CALL_EXEC)			\
+__PMC_EV(P6, BR_CALL_MISSP_EXEC)		\
+__PMC_EV(P6, BR_IND_CALL_EXEC)			\
+__PMC_EV(P6, EMON_SIMD_INSTR_RETIRED)		\
+__PMC_EV(P6, EMON_SYNCH_UOPS)			\
+__PMC_EV(P6, EMON_ESP_UOPS)			\
+__PMC_EV(P6, EMON_FUSED_UOPS_RET)		\
+__PMC_EV(P6, EMON_UNFUSION)			\
+__PMC_EV(P6, EMON_PREF_RQSTS_UP)		\
+__PMC_EV(P6, EMON_PREF_RQSTS_DN)		\
+__PMC_EV(P6, EMON_SSE_SSE2_INST_RETIRED)	\
+__PMC_EV(P6, EMON_SSE_SSE2_COMP_INST_RETIRED)
+
+
+#define	PMC_EV_P6_FIRST	PMC_EV_P6_DATA_MEM_REFS
+#define	PMC_EV_P6_LAST	PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED
+
+/* AMD K8 PMCs */
+
+#define	__PMC_EV_K8()							\
+__PMC_EV(K8, FP_DISPATCHED_FPU_OPS)					\
+__PMC_EV(K8, FP_CYCLES_WITH_NO_FPU_OPS_RETIRED)				\
+__PMC_EV(K8, FP_DISPATCHED_FPU_FAST_FLAG_OPS)				\
+__PMC_EV(K8, LS_SEGMENT_REGISTER_LOAD)					\
+__PMC_EV(K8, LS_MICROARCHITECTURAL_RESYNC_BY_SELF_MODIFYING_CODE)	\
+__PMC_EV(K8, LS_MICROARCHITECTURAL_RESYNC_BY_SNOOP)			\
+__PMC_EV(K8, LS_BUFFER2_FULL)						\
+__PMC_EV(K8, LS_LOCKED_OPERATION)					\
+__PMC_EV(K8, LS_MICROARCHITECTURAL_LATE_CANCEL)				\
+__PMC_EV(K8, LS_RETIRED_CFLUSH_INSTRUCTIONS)				\
+__PMC_EV(K8, LS_RETIRED_CPUID_INSTRUCTIONS)				\
+__PMC_EV(K8, DC_ACCESS)							\
+__PMC_EV(K8, DC_MISS)							\
+__PMC_EV(K8, DC_REFILL_FROM_L2)						\
+__PMC_EV(K8, DC_REFILL_FROM_SYSTEM)					\
+__PMC_EV(K8, DC_COPYBACK)						\
+__PMC_EV(K8, DC_L1_DTLB_MISS_AND_L2_DTLB_HIT)				\
+__PMC_EV(K8, DC_L1_DTLB_MISS_AND_L2_DTLB_MISS)				\
+__PMC_EV(K8, DC_MISALIGNED_DATA_REFERENCE)				\
+__PMC_EV(K8, DC_MICROARCHITECTURAL_LATE_CANCEL)				\
+__PMC_EV(K8, DC_MICROARCHITECTURAL_EARLY_CANCEL)			\
+__PMC_EV(K8, DC_ONE_BIT_ECC_ERROR)					\
+__PMC_EV(K8, DC_DISPATCHED_PREFETCH_INSTRUCTIONS)			\
+__PMC_EV(K8, DC_DCACHE_ACCESSES_BY_LOCKS)				\
+__PMC_EV(K8, BU_CPU_CLK_UNHALTED)					\
+__PMC_EV(K8, BU_INTERNAL_L2_REQUEST)					\
+__PMC_EV(K8, BU_FILL_REQUEST_L2_MISS)					\
+__PMC_EV(K8, BU_FILL_INTO_L2)						\
+__PMC_EV(K8, IC_FETCH)							\
+__PMC_EV(K8, IC_MISS)							\
+__PMC_EV(K8, IC_REFILL_FROM_L2)						\
+__PMC_EV(K8, IC_REFILL_FROM_SYSTEM)					\
+__PMC_EV(K8, IC_L1_ITLB_MISS_AND_L2_ITLB_HIT)				\
+__PMC_EV(K8, IC_L1_ITLB_MISS_AND_L2_ITLB_MISS)				\
+__PMC_EV(K8, IC_MICROARCHITECTURAL_RESYNC_BY_SNOOP)			\
+__PMC_EV(K8, IC_INSTRUCTION_FETCH_STALL)				\
+__PMC_EV(K8, IC_RETURN_STACK_HIT)					\
+__PMC_EV(K8, IC_RETURN_STACK_OVERFLOW)					\
+__PMC_EV(K8, FR_RETIRED_X86_INSTRUCTIONS)				\
+__PMC_EV(K8, FR_RETIRED_UOPS)						\
+__PMC_EV(K8, FR_RETIRED_BRANCHES)					\
+__PMC_EV(K8, FR_RETIRED_BRANCHES_MISPREDICTED)				\
+__PMC_EV(K8, FR_RETIRED_TAKEN_BRANCHES)					\
+__PMC_EV(K8, FR_RETIRED_TAKEN_BRANCHES_MISPREDICTED)			\
+__PMC_EV(K8, FR_RETIRED_FAR_CONTROL_TRANSFERS)				\
+__PMC_EV(K8, FR_RETIRED_RESYNCS)					\
+__PMC_EV(K8, FR_RETIRED_NEAR_RETURNS)					\
+__PMC_EV(K8, FR_RETIRED_NEAR_RETURNS_MISPREDICTED)			\
+__PMC_EV(K8, FR_RETIRED_TAKEN_BRANCHES_MISPREDICTED_BY_ADDR_MISCOMPARE)	\
+__PMC_EV(K8, FR_RETIRED_FPU_INSTRUCTIONS)				\
+__PMC_EV(K8, FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS)		\
+__PMC_EV(K8, FR_INTERRUPTS_MASKED_CYCLES)				\
+__PMC_EV(K8, FR_INTERRUPTS_MASKED_WHILE_PENDING_CYCLES)			\
+__PMC_EV(K8, FR_TAKEN_HARDWARE_INTERRUPTS)				\
+__PMC_EV(K8, FR_DECODER_EMPTY)						\
+__PMC_EV(K8, FR_DISPATCH_STALLS)					\
+__PMC_EV(K8, FR_DISPATCH_STALL_FROM_BRANCH_ABORT_TO_RETIRE)		\
+__PMC_EV(K8, FR_DISPATCH_STALL_FOR_SERIALIZATION)			\
+__PMC_EV(K8, FR_DISPATCH_STALL_FOR_SEGMENT_LOAD)			\
+__PMC_EV(K8, FR_DISPATCH_STALL_WHEN_REORDER_BUFFER_IS_FULL)		\
+__PMC_EV(K8, FR_DISPATCH_STALL_WHEN_RESERVATION_STATIONS_ARE_FULL)	\
+__PMC_EV(K8, FR_DISPATCH_STALL_WHEN_FPU_IS_FULL)			\
+__PMC_EV(K8, FR_DISPATCH_STALL_WHEN_LS_IS_FULL)				\
+__PMC_EV(K8, FR_DISPATCH_STALL_WHEN_WAITING_FOR_ALL_TO_BE_QUIET)	\
+__PMC_EV(K8, FR_DISPATCH_STALL_WHEN_FAR_XFER_OR_RESYNC_BRANCH_PENDING)	\
+__PMC_EV(K8, FR_FPU_EXCEPTIONS)						\
+__PMC_EV(K8, FR_NUMBER_OF_BREAKPOINTS_FOR_DR0)				\
+__PMC_EV(K8, FR_NUMBER_OF_BREAKPOINTS_FOR_DR1)				\
+__PMC_EV(K8, FR_NUMBER_OF_BREAKPOINTS_FOR_DR2)				\
+__PMC_EV(K8, FR_NUMBER_OF_BREAKPOINTS_FOR_DR3)				\
+__PMC_EV(K8, NB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENT)			\
+__PMC_EV(K8, NB_MEMORY_CONTROLLER_PAGE_TABLE_OVERFLOW)			\
+__PMC_EV(K8, NB_MEMORY_CONTROLLER_DRAM_COMMAND_SLOTS_MISSED)		\
+__PMC_EV(K8, NB_MEMORY_CONTROLLER_TURNAROUND)				\
+__PMC_EV(K8, NB_MEMORY_CONTROLLER_BYPASS_SATURATION)			\
+__PMC_EV(K8, NB_SIZED_COMMANDS)						\
+__PMC_EV(K8, NB_PROBE_RESULT)						\
+__PMC_EV(K8, NB_HT_BUS0_BANDWIDTH)					\
+__PMC_EV(K8, NB_HT_BUS1_BANDWIDTH)					\
+__PMC_EV(K8, NB_HT_BUS2_BANDWIDTH)
+
+#define	PMC_EV_K8_FIRST		PMC_EV_K8_FP_DISPATCHED_FPU_OPS
+#define	PMC_EV_K8_LAST		PMC_EV_K8_NB_HT_BUS2_BANDWIDTH
+
+
+/*
+ * Intel Pentium and Pentium MMX events, from the "Intel 64 and IA-32
+ * Architectures Software Developer's Manual, Volume 3B: System Programming
+ * Guide, Part 2, August 2007".
+ */
+#define	__PMC_EV_P5()							\
+__PMC_EV(P5, DATA_READ)							\
+__PMC_EV(P5, DATA_WRITE)						\
+__PMC_EV(P5, DATA_TLB_MISS)						\
+__PMC_EV(P5, DATA_READ_MISS)						\
+__PMC_EV(P5, DATA_WRITE_MISS)						\
+__PMC_EV(P5, WRITE_HIT_TO_M_OR_E_STATE_LINES)				\
+__PMC_EV(P5, DATA_CACHE_LINES_WRITTEN_BACK)				\
+__PMC_EV(P5, EXTERNAL_SNOOPS)						\
+__PMC_EV(P5, EXTERNAL_DATA_CACHE_SNOOP_HITS)				\
+__PMC_EV(P5, MEMORY_ACCESSES_IN_BOTH_PIPES)				\
+__PMC_EV(P5, BANK_CONFLICTS)						\
+__PMC_EV(P5, MISALIGNED_DATA_OR_IO_REFERENCES)				\
+__PMC_EV(P5, CODE_READ)							\
+__PMC_EV(P5, CODE_TLB_MISS)						\
+__PMC_EV(P5, CODE_CACHE_MISS)						\
+__PMC_EV(P5, ANY_SEGMENT_REGISTER_LOADED)				\
+__PMC_EV(P5, BRANCHES)							\
+__PMC_EV(P5, BTB_HITS)							\
+__PMC_EV(P5, TAKEN_BRANCH_OR_BTB_HIT)					\
+__PMC_EV(P5, PIPELINE_FLUSHES)						\
+__PMC_EV(P5, INSTRUCTIONS_EXECUTED)					\
+__PMC_EV(P5, INSTRUCTIONS_EXECUTED_V_PIPE)				\
+__PMC_EV(P5, BUS_CYCLE_DURATION)					\
+__PMC_EV(P5, WRITE_BUFFER_FULL_STALL_DURATION)				\
+__PMC_EV(P5, WAITING_FOR_DATA_MEMORY_READ_STALL_DURATION)		\
+__PMC_EV(P5, STALL_ON_WRITE_TO_AN_E_OR_M_STATE_LINE)			\
+__PMC_EV(P5, LOCKED_BUS_CYCLE)						\
+__PMC_EV(P5, IO_READ_OR_WRITE_CYCLE)					\
+__PMC_EV(P5, NONCACHEABLE_MEMORY_READS)					\
+__PMC_EV(P5, PIPELINE_AGI_STALLS)					\
+__PMC_EV(P5, FLOPS)							\
+__PMC_EV(P5, BREAKPOINT_MATCH_ON_DR0_REGISTER)				\
+__PMC_EV(P5, BREAKPOINT_MATCH_ON_DR1_REGISTER)				\
+__PMC_EV(P5, BREAKPOINT_MATCH_ON_DR2_REGISTER)				\
+__PMC_EV(P5, BREAKPOINT_MATCH_ON_DR3_REGISTER)				\
+__PMC_EV(P5, HARDWARE_INTERRUPTS)					\
+__PMC_EV(P5, DATA_READ_OR_WRITE)					\
+__PMC_EV(P5, DATA_READ_MISS_OR_WRITE_MISS)				\
+__PMC_EV(P5, BUS_OWNERSHIP_LATENCY)					\
+__PMC_EV(P5, BUS_OWNERSHIP_TRANSFERS)					\
+__PMC_EV(P5, MMX_INSTRUCTIONS_EXECUTED_U_PIPE)				\
+__PMC_EV(P5, MMX_INSTRUCTIONS_EXECUTED_V_PIPE)				\
+__PMC_EV(P5, CACHE_M_LINE_SHARING)					\
+__PMC_EV(P5, CACHE_LINE_SHARING)					\
+__PMC_EV(P5, EMMS_INSTRUCTIONS_EXECUTED)				\
+__PMC_EV(P5, TRANSITIONS_BETWEEN_MMX_AND_FP_INSTRUCTIONS)		\
+__PMC_EV(P5, BUS_UTILIZATION_DUE_TO_PROCESSOR_ACTIVITY)			\
+__PMC_EV(P5, WRITES_TO_NONCACHEABLE_MEMORY)				\
+__PMC_EV(P5, SATURATING_MMX_INSTRUCTIONS_EXECUTED)			\
+__PMC_EV(P5, SATURATIONS_PERFORMED)					\
+__PMC_EV(P5, NUMBER_OF_CYCLES_NOT_IN_HALT_STATE)			\
+__PMC_EV(P5, DATA_CACHE_TLB_MISS_STALL_DURATION)			\
+__PMC_EV(P5, MMX_INSTRUCTION_DATA_READS)				\
+__PMC_EV(P5, MMX_INSTRUCTION_DATA_READ_MISSES)				\
+__PMC_EV(P5, FLOATING_POINT_STALLS_DURATION)				\
+__PMC_EV(P5, TAKEN_BRANCHES)						\
+__PMC_EV(P5, D1_STARVATION_AND_FIFO_IS_EMPTY)				\
+__PMC_EV(P5, D1_STARVATION_AND_ONLY_ONE_INSTRUCTION_IN_FIFO)		\
+__PMC_EV(P5, MMX_INSTRUCTION_DATA_WRITES)				\
+__PMC_EV(P5, MMX_INSTRUCTION_DATA_WRITE_MISSES)				\
+__PMC_EV(P5, PIPELINE_FLUSHES_DUE_TO_WRONG_BRANCH_PREDICTIONS)		\
+__PMC_EV(P5,								\
+    PIPELINE_FLUSHES_DUE_TO_WRONG_BRANCH_PREDICTIONS_RESOLVED_IN_WB_STAGE) \
+__PMC_EV(P5, MISALIGNED_DATA_MEMORY_REFERENCE_ON_MMX_INSTRUCTIONS)	\
+__PMC_EV(P5, PIPELINE_STALL_FOR_MMX_INSTRUCTION_DATA_MEMORY_READS)	\
+__PMC_EV(P5, MISPREDICTED_OR_UNPREDICTED_RETURNS)			\
+__PMC_EV(P5, PREDICTED_RETURNS)						\
+__PMC_EV(P5, MMX_MULTIPLY_UNIT_INTERLOCK)				\
+__PMC_EV(P5, MOVD_MOVQ_STORE_STALL_DUE_TO_PREVIOUS_MMX_OPERATION)	\
+__PMC_EV(P5, RETURNS)							\
+__PMC_EV(P5, BTB_FALSE_ENTRIES)						\
+__PMC_EV(P5, BTB_MISS_PREDICTION_ON_NOT_TAKEN_BRANCH)			\
+__PMC_EV(P5,								\
+    FULL_WRITE_BUFFER_STALL_DURATION_WHILE_EXECUTING_MMX_INSTRUCTIONS)	\
+__PMC_EV(P5, STALL_ON_MMX_INSTRUCTION_WRITE_TO_E_OR_M_STATE_LINE)
+
+#define	PMC_EV_P5_FIRST		PMC_EV_P5_DATA_READ
+#define	PMC_EV_P5_LAST	        \
+	PMC_EV_P5_STALL_ON_MMX_INSTRUCTION_WRITE_TO_E_OR_M_STATE_LINE
+
+/*
+ * Events supported by Intel architectural fixed function counters,
+ * from the "Intel 64 and IA-32 Architectures Software Developer's
+ * Manual Volume 3B: System Programming Guide, Part 2", July 2008.
+ */
+#define	__PMC_EV_IAF()							\
+__PMC_EV(IAF, INSTR_RETIRED_ANY)					\
+__PMC_EV(IAF, CPU_CLK_UNHALTED_CORE)					\
+__PMC_EV(IAF, CPU_CLK_UNHALTED_REF)
+
+#define	PMC_EV_IAF_FIRST	PMC_EV_IAF_INSTR_RETIRED_ANY
+#define	PMC_EV_IAF_LAST		PMC_EV_IAF_CPU_CLK_UNHALTED_REF
+
+#define	__PMC_EV_ALIAS_IAF()						\
+__PMC_EV_ALIAS("instruction-retired",	IAF_INSTR_RETIRED_ANY)		\
+__PMC_EV_ALIAS("unhalted-core-cycles",	IAF_CPU_CLK_UNHALTED_CORE)	\
+__PMC_EV_ALIAS("unhalted-reference-cycles", IAF_CPU_CLK_UNHALTED_REF)
+
+/*
+ * Events supported by programmable function counters present in
+ * Intel Atom, Core and Core2 CPUs, from the "Intel 64 and IA-32
+ * Architectures Software Developer's Manual Volume 3B: System Programming
+ * Guide, Part 2", July 2008.
+ *
+ * These PMCs select events with a combination of an event code and
+ * unit mask.  Quirks that need to be taken care of include:
+ * - The set of (event code, umask) combinations supported by a processor
+ *   varies according to the processor model.
+ * - A given (event code, umask) combination need not measure the same
+ *   hardware event in all processor models.
+ * - Event names in vendor documentation for an (event code, umask) pair
+ *   may vary according to the CPU model.
+ * - Identically named events can map to different (event code, umask)
+ *   pairs on different CPUs.
+ * - New (event code, umask) combinations continue to be added as CPUs
+ *   evolve.  The interface between hwpmc(4) and libpmc(3) needs to be
+ *   robust with respect to ABI changes.
+ *
+ * The IAP_EVENT_* symbols below define the ABI between userland and kernel.
+ * New (event code, * umask) combinations used in new CPUs would be added
+ * to the end of the list.  Vendor names for events are mapped to IAP_EVENT_*
+ * symbols using aliases.  The final disambiguation of semantics based on
+ * the CPU model happens inside hwpmc(4).
+ */
+#define	__PMC_EV_IAP()				\
+__PMC_EV(IAP, EVENT_02H_01H)			\
+__PMC_EV(IAP, EVENT_02H_81H)			\
+__PMC_EV(IAP, EVENT_03H_00H)			\
+__PMC_EV(IAP, EVENT_03H_01H)			\
+__PMC_EV(IAP, EVENT_03H_02H)			\
+__PMC_EV(IAP, EVENT_03H_04H)			\
+__PMC_EV(IAP, EVENT_03H_08H)			\
+__PMC_EV(IAP, EVENT_03H_10H)			\
+__PMC_EV(IAP, EVENT_03H_20H)			\
+__PMC_EV(IAP, EVENT_04H_00H)			\
+__PMC_EV(IAP, EVENT_04H_01H)			\
+__PMC_EV(IAP, EVENT_04H_02H)			\
+__PMC_EV(IAP, EVENT_04H_07H)			\
+__PMC_EV(IAP, EVENT_04H_08H)			\
+__PMC_EV(IAP, EVENT_05H_00H)			\
+__PMC_EV(IAP, EVENT_05H_01H)			\
+__PMC_EV(IAP, EVENT_05H_02H)			\
+__PMC_EV(IAP, EVENT_05H_03H)			\
+__PMC_EV(IAP, EVENT_06H_00H)			\
+__PMC_EV(IAP, EVENT_06H_01H)			\
+__PMC_EV(IAP, EVENT_06H_02H)			\
+__PMC_EV(IAP, EVENT_06H_04H)			\
+__PMC_EV(IAP, EVENT_06H_08H)			\
+__PMC_EV(IAP, EVENT_06H_0FH)			\
+__PMC_EV(IAP, EVENT_07H_00H)			\
+__PMC_EV(IAP, EVENT_07H_01H)			\
+__PMC_EV(IAP, EVENT_07H_02H)			\
+__PMC_EV(IAP, EVENT_07H_03H)			\
+__PMC_EV(IAP, EVENT_07H_06H)			\
+__PMC_EV(IAP, EVENT_07H_08H)			\
+__PMC_EV(IAP, EVENT_08H_01H)			\
+__PMC_EV(IAP, EVENT_08H_02H)			\
+__PMC_EV(IAP, EVENT_08H_04H)			\
+__PMC_EV(IAP, EVENT_08H_05H)			\
+__PMC_EV(IAP, EVENT_08H_06H)			\
+__PMC_EV(IAP, EVENT_08H_07H)			\
+__PMC_EV(IAP, EVENT_08H_08H)			\
+__PMC_EV(IAP, EVENT_08H_09H)			\
+__PMC_EV(IAP, EVENT_08H_10H)			\
+__PMC_EV(IAP, EVENT_08H_20H)			\
+__PMC_EV(IAP, EVENT_08H_40H)			\
+__PMC_EV(IAP, EVENT_08H_80H)			\
+__PMC_EV(IAP, EVENT_09H_01H)			\
+__PMC_EV(IAP, EVENT_09H_02H)			\
+__PMC_EV(IAP, EVENT_09H_04H)			\
+__PMC_EV(IAP, EVENT_09H_08H)			\
+__PMC_EV(IAP, EVENT_0BH_01H)			\
+__PMC_EV(IAP, EVENT_0BH_02H)			\
+__PMC_EV(IAP, EVENT_0BH_10H)			\
+__PMC_EV(IAP, EVENT_0CH_01H)			\
+__PMC_EV(IAP, EVENT_0CH_02H)			\
+__PMC_EV(IAP, EVENT_0CH_03H)			\
+__PMC_EV(IAP, EVENT_0EH_01H)			\
+__PMC_EV(IAP, EVENT_0EH_02H)			\
+__PMC_EV(IAP, EVENT_0FH_01H)			\
+__PMC_EV(IAP, EVENT_0FH_02H)			\
+__PMC_EV(IAP, EVENT_0FH_08H)			\
+__PMC_EV(IAP, EVENT_0FH_10H)			\
+__PMC_EV(IAP, EVENT_0FH_20H)			\
+__PMC_EV(IAP, EVENT_0FH_80H)			\
+__PMC_EV(IAP, EVENT_10H_00H)			\
+__PMC_EV(IAP, EVENT_10H_01H)			\
+__PMC_EV(IAP, EVENT_10H_02H)			\
+__PMC_EV(IAP, EVENT_10H_04H)			\
+__PMC_EV(IAP, EVENT_10H_08H)			\
+__PMC_EV(IAP, EVENT_10H_10H)			\
+__PMC_EV(IAP, EVENT_10H_20H)			\
+__PMC_EV(IAP, EVENT_10H_40H)			\
+__PMC_EV(IAP, EVENT_10H_80H)			\
+__PMC_EV(IAP, EVENT_10H_81H)			\
+__PMC_EV(IAP, EVENT_11H_00H)			\
+__PMC_EV(IAP, EVENT_11H_01H)			\
+__PMC_EV(IAP, EVENT_11H_81H)			\
+__PMC_EV(IAP, EVENT_12H_00H)			\
+__PMC_EV(IAP, EVENT_12H_01H)			\
+__PMC_EV(IAP, EVENT_12H_02H)			\
+__PMC_EV(IAP, EVENT_12H_04H)			\
+__PMC_EV(IAP, EVENT_12H_08H)			\
+__PMC_EV(IAP, EVENT_12H_10H)			\
+__PMC_EV(IAP, EVENT_12H_20H)			\
+__PMC_EV(IAP, EVENT_12H_40H)			\
+__PMC_EV(IAP, EVENT_12H_81H)			\
+__PMC_EV(IAP, EVENT_13H_00H)			\
+__PMC_EV(IAP, EVENT_13H_01H)			\
+__PMC_EV(IAP, EVENT_13H_02H)			\
+__PMC_EV(IAP, EVENT_13H_04H)			\
+__PMC_EV(IAP, EVENT_13H_07H)			\
+__PMC_EV(IAP, EVENT_13H_81H)			\
+__PMC_EV(IAP, EVENT_14H_00H)			\
+__PMC_EV(IAP, EVENT_14H_01H)			\
+__PMC_EV(IAP, EVENT_14H_02H)			\
+__PMC_EV(IAP, EVENT_17H_01H)			\
+__PMC_EV(IAP, EVENT_18H_00H)			\
+__PMC_EV(IAP, EVENT_18H_01H)			\
+__PMC_EV(IAP, EVENT_19H_00H)			\
+__PMC_EV(IAP, EVENT_19H_01H)			\
+__PMC_EV(IAP, EVENT_19H_02H)			\
+__PMC_EV(IAP, EVENT_1DH_01H)			\
+__PMC_EV(IAP, EVENT_1DH_02H)			\
+__PMC_EV(IAP, EVENT_1DH_04H)			\
+__PMC_EV(IAP, EVENT_1EH_01H)			\
+__PMC_EV(IAP, EVENT_20H_01H)			\
+__PMC_EV(IAP, EVENT_21H)			\
+__PMC_EV(IAP, EVENT_22H)			\
+__PMC_EV(IAP, EVENT_23H)			\
+__PMC_EV(IAP, EVENT_24H)			\
+__PMC_EV(IAP, EVENT_24H_01H)			\
+__PMC_EV(IAP, EVENT_24H_02H)			\
+__PMC_EV(IAP, EVENT_24H_03H)			\
+__PMC_EV(IAP, EVENT_24H_04H)			\
+__PMC_EV(IAP, EVENT_24H_08H)			\
+__PMC_EV(IAP, EVENT_24H_0CH)			\
+__PMC_EV(IAP, EVENT_24H_10H)			\
+__PMC_EV(IAP, EVENT_24H_20H)			\
+__PMC_EV(IAP, EVENT_24H_30H)			\
+__PMC_EV(IAP, EVENT_24H_40H)			\
+__PMC_EV(IAP, EVENT_24H_80H)			\
+__PMC_EV(IAP, EVENT_24H_AAH)			\
+__PMC_EV(IAP, EVENT_24H_C0H)			\
+__PMC_EV(IAP, EVENT_24H_FFH)			\
+__PMC_EV(IAP, EVENT_25H)			\
+__PMC_EV(IAP, EVENT_26H)			\
+__PMC_EV(IAP, EVENT_26H_01H)			\
+__PMC_EV(IAP, EVENT_26H_02H)			\
+__PMC_EV(IAP, EVENT_26H_04H)			\
+__PMC_EV(IAP, EVENT_26H_08H)			\
+__PMC_EV(IAP, EVENT_26H_0FH)			\
+__PMC_EV(IAP, EVENT_26H_10H)			\
+__PMC_EV(IAP, EVENT_26H_20H)			\
+__PMC_EV(IAP, EVENT_26H_40H)			\
+__PMC_EV(IAP, EVENT_26H_80H)			\
+__PMC_EV(IAP, EVENT_26H_F0H)			\
+__PMC_EV(IAP, EVENT_26H_FFH)			\
+__PMC_EV(IAP, EVENT_27H)			\
+__PMC_EV(IAP, EVENT_27H_01H)			\
+__PMC_EV(IAP, EVENT_27H_02H)			\
+__PMC_EV(IAP, EVENT_27H_04H)			\
+__PMC_EV(IAP, EVENT_27H_08H)			\
+__PMC_EV(IAP, EVENT_27H_0EH)			\
+__PMC_EV(IAP, EVENT_27H_0FH)			\
+__PMC_EV(IAP, EVENT_27H_10H)			\
+__PMC_EV(IAP, EVENT_27H_20H)			\
+__PMC_EV(IAP, EVENT_27H_40H)			\
+__PMC_EV(IAP, EVENT_27H_80H)			\
+__PMC_EV(IAP, EVENT_27H_E0H)			\
+__PMC_EV(IAP, EVENT_27H_F0H)			\
+__PMC_EV(IAP, EVENT_28H)			\
+__PMC_EV(IAP, EVENT_28H_01H)			\
+__PMC_EV(IAP, EVENT_28H_02H)			\
+__PMC_EV(IAP, EVENT_28H_04H)			\
+__PMC_EV(IAP, EVENT_28H_08H)			\
+__PMC_EV(IAP, EVENT_28H_0FH)			\
+__PMC_EV(IAP, EVENT_29H)			\
+__PMC_EV(IAP, EVENT_2AH)			\
+__PMC_EV(IAP, EVENT_2BH)			\
+__PMC_EV(IAP, EVENT_2EH)			\
+__PMC_EV(IAP, EVENT_2EH_01H)			\
+__PMC_EV(IAP, EVENT_2EH_02H)			\
+__PMC_EV(IAP, EVENT_2EH_41H)			\
+__PMC_EV(IAP, EVENT_2EH_4FH)			\
+__PMC_EV(IAP, EVENT_30H)			\
+__PMC_EV(IAP, EVENT_32H)			\
+__PMC_EV(IAP, EVENT_3AH)			\
+__PMC_EV(IAP, EVENT_3AH_00H)			\
+__PMC_EV(IAP, EVENT_3BH_C0H)			\
+__PMC_EV(IAP, EVENT_3CH_00H)			\
+__PMC_EV(IAP, EVENT_3CH_01H)			\
+__PMC_EV(IAP, EVENT_3CH_02H)			\
+__PMC_EV(IAP, EVENT_3DH_01H)			\
+__PMC_EV(IAP, EVENT_40H)			\
+__PMC_EV(IAP, EVENT_40H_01H)			\
+__PMC_EV(IAP, EVENT_40H_02H)			\
+__PMC_EV(IAP, EVENT_40H_04H)			\
+__PMC_EV(IAP, EVENT_40H_08H)			\
+__PMC_EV(IAP, EVENT_40H_0FH)			\
+__PMC_EV(IAP, EVENT_40H_21H)			\
+__PMC_EV(IAP, EVENT_41H)			\
+__PMC_EV(IAP, EVENT_41H_01H)			\
+__PMC_EV(IAP, EVENT_41H_02H)			\
+__PMC_EV(IAP, EVENT_41H_04H)			\
+__PMC_EV(IAP, EVENT_41H_08H)			\
+__PMC_EV(IAP, EVENT_41H_0FH)			\
+__PMC_EV(IAP, EVENT_41H_22H)			\
+__PMC_EV(IAP, EVENT_42H)			\
+__PMC_EV(IAP, EVENT_42H_01H)			\
+__PMC_EV(IAP, EVENT_42H_02H)			\
+__PMC_EV(IAP, EVENT_42H_04H)			\
+__PMC_EV(IAP, EVENT_42H_08H)			\
+__PMC_EV(IAP, EVENT_42H_10H)			\
+__PMC_EV(IAP, EVENT_43H_01H)			\
+__PMC_EV(IAP, EVENT_43H_02H)			\
+__PMC_EV(IAP, EVENT_44H_02H)			\
+__PMC_EV(IAP, EVENT_45H_0FH)			\
+__PMC_EV(IAP, EVENT_46H_00H)			\
+__PMC_EV(IAP, EVENT_47H_00H)			\
+__PMC_EV(IAP, EVENT_48H_00H)			\
+__PMC_EV(IAP, EVENT_48H_02H)			\
+__PMC_EV(IAP, EVENT_49H_00H)			\
+__PMC_EV(IAP, EVENT_49H_01H)			\
+__PMC_EV(IAP, EVENT_49H_02H)			\
+__PMC_EV(IAP, EVENT_49H_04H)			\
+__PMC_EV(IAP, EVENT_49H_10H)			\
+__PMC_EV(IAP, EVENT_49H_20H)			\
+__PMC_EV(IAP, EVENT_49H_40H)			\
+__PMC_EV(IAP, EVENT_49H_80H)			\
+__PMC_EV(IAP, EVENT_4BH_00H)			\
+__PMC_EV(IAP, EVENT_4BH_01H)			\
+__PMC_EV(IAP, EVENT_4BH_02H)			\
+__PMC_EV(IAP, EVENT_4BH_03H)			\
+__PMC_EV(IAP, EVENT_4BH_08H)			\
+__PMC_EV(IAP, EVENT_4CH_00H)			\
+__PMC_EV(IAP, EVENT_4CH_01H)			\
+__PMC_EV(IAP, EVENT_4DH_01H)			\
+__PMC_EV(IAP, EVENT_4EH_01H)			\
+__PMC_EV(IAP, EVENT_4EH_02H)			\
+__PMC_EV(IAP, EVENT_4EH_04H)			\
+__PMC_EV(IAP, EVENT_4EH_10H)			\
+__PMC_EV(IAP, EVENT_4FH_00H)			\
+__PMC_EV(IAP, EVENT_4FH_02H)			\
+__PMC_EV(IAP, EVENT_4FH_04H)			\
+__PMC_EV(IAP, EVENT_4FH_08H)			\
+__PMC_EV(IAP, EVENT_4FH_10H)			\
+__PMC_EV(IAP, EVENT_51H_01H)			\
+__PMC_EV(IAP, EVENT_51H_02H)			\
+__PMC_EV(IAP, EVENT_51H_04H)			\
+__PMC_EV(IAP, EVENT_51H_08H)			\
+__PMC_EV(IAP, EVENT_52H_01H)			\
+__PMC_EV(IAP, EVENT_53H_01H)			\
+__PMC_EV(IAP, EVENT_60H)			\
+__PMC_EV(IAP, EVENT_60H_01H)			\
+__PMC_EV(IAP, EVENT_60H_02H)			\
+__PMC_EV(IAP, EVENT_60H_04H)			\
+__PMC_EV(IAP, EVENT_60H_08H)			\
+__PMC_EV(IAP, EVENT_61H)			\
+__PMC_EV(IAP, EVENT_61H_00H)			\
+__PMC_EV(IAP, EVENT_62H)			\
+__PMC_EV(IAP, EVENT_62H_00H)			\
+__PMC_EV(IAP, EVENT_63H)			\
+__PMC_EV(IAP, EVENT_63H_01H)			\
+__PMC_EV(IAP, EVENT_63H_02H)			\
+__PMC_EV(IAP, EVENT_64H)			\
+__PMC_EV(IAP, EVENT_64H_40H)			\
+__PMC_EV(IAP, EVENT_65H)			\
+__PMC_EV(IAP, EVENT_66H)			\
+__PMC_EV(IAP, EVENT_67H)			\
+__PMC_EV(IAP, EVENT_68H)			\
+__PMC_EV(IAP, EVENT_69H)			\
+__PMC_EV(IAP, EVENT_6AH)			\
+__PMC_EV(IAP, EVENT_6BH)			\
+__PMC_EV(IAP, EVENT_6CH)			\
+__PMC_EV(IAP, EVENT_6CH_01H)			\
+__PMC_EV(IAP, EVENT_6DH)			\
+__PMC_EV(IAP, EVENT_6EH)			\
+__PMC_EV(IAP, EVENT_6FH)			\
+__PMC_EV(IAP, EVENT_70H)			\
+__PMC_EV(IAP, EVENT_77H)			\
+__PMC_EV(IAP, EVENT_78H)			\
+__PMC_EV(IAP, EVENT_7AH)			\
+__PMC_EV(IAP, EVENT_7BH)			\
+__PMC_EV(IAP, EVENT_7DH)			\
+__PMC_EV(IAP, EVENT_7EH)			\
+__PMC_EV(IAP, EVENT_7EH_00H)			\
+__PMC_EV(IAP, EVENT_7FH)			\
+__PMC_EV(IAP, EVENT_80H_00H)			\
+__PMC_EV(IAP, EVENT_80H_01H)			\
+__PMC_EV(IAP, EVENT_80H_02H)			\
+__PMC_EV(IAP, EVENT_80H_03H)			\
+__PMC_EV(IAP, EVENT_80H_04H)			\
+__PMC_EV(IAP, EVENT_80H_10H)			\
+__PMC_EV(IAP, EVENT_81H_00H)			\
+__PMC_EV(IAP, EVENT_81H_01H)			\
+__PMC_EV(IAP, EVENT_81H_02H)			\
+__PMC_EV(IAP, EVENT_82H_01H)			\
+__PMC_EV(IAP, EVENT_82H_02H)			\
+__PMC_EV(IAP, EVENT_82H_04H)			\
+__PMC_EV(IAP, EVENT_82H_10H)			\
+__PMC_EV(IAP, EVENT_82H_12H)			\
+__PMC_EV(IAP, EVENT_82H_40H)			\
+__PMC_EV(IAP, EVENT_83H_01H)			\
+__PMC_EV(IAP, EVENT_83H_02H)			\
+__PMC_EV(IAP, EVENT_85H_00H)			\
+__PMC_EV(IAP, EVENT_85H_01H)			\
+__PMC_EV(IAP, EVENT_85H_02H)			\
+__PMC_EV(IAP, EVENT_85H_04H)			\
+__PMC_EV(IAP, EVENT_85H_10H)			\
+__PMC_EV(IAP, EVENT_85H_20H)			\
+__PMC_EV(IAP, EVENT_85H_40H)			\
+__PMC_EV(IAP, EVENT_85H_80H)			\
+__PMC_EV(IAP, EVENT_86H_00H)			\
+__PMC_EV(IAP, EVENT_87H_00H)			\
+__PMC_EV(IAP, EVENT_87H_01H)			\
+__PMC_EV(IAP, EVENT_87H_02H)			\
+__PMC_EV(IAP, EVENT_87H_04H)			\
+__PMC_EV(IAP, EVENT_87H_08H)			\
+__PMC_EV(IAP, EVENT_87H_0FH)			\
+__PMC_EV(IAP, EVENT_88H_00H)			\
+__PMC_EV(IAP, EVENT_88H_01H)			\
+__PMC_EV(IAP, EVENT_88H_02H)			\
+__PMC_EV(IAP, EVENT_88H_04H)			\
+__PMC_EV(IAP, EVENT_88H_07H)			\
+__PMC_EV(IAP, EVENT_88H_08H)			\
+__PMC_EV(IAP, EVENT_88H_10H)			\
+__PMC_EV(IAP, EVENT_88H_20H)			\
+__PMC_EV(IAP, EVENT_88H_30H)			\
+__PMC_EV(IAP, EVENT_88H_40H)			\
+__PMC_EV(IAP, EVENT_88H_7FH)			\
+__PMC_EV(IAP, EVENT_89H_00H)			\
+__PMC_EV(IAP, EVENT_89H_01H)			\
+__PMC_EV(IAP, EVENT_89H_02H)			\
+__PMC_EV(IAP, EVENT_89H_04H)			\
+__PMC_EV(IAP, EVENT_89H_07H)			\
+__PMC_EV(IAP, EVENT_89H_08H)			\
+__PMC_EV(IAP, EVENT_89H_10H)			\
+__PMC_EV(IAP, EVENT_89H_20H)			\
+__PMC_EV(IAP, EVENT_89H_30H)			\
+__PMC_EV(IAP, EVENT_89H_40H)			\
+__PMC_EV(IAP, EVENT_89H_7FH)			\
+__PMC_EV(IAP, EVENT_8AH_00H)			\
+__PMC_EV(IAP, EVENT_8BH_00H)			\
+__PMC_EV(IAP, EVENT_8CH_00H)			\
+__PMC_EV(IAP, EVENT_8DH_00H)			\
+__PMC_EV(IAP, EVENT_8EH_00H)			\
+__PMC_EV(IAP, EVENT_8FH_00H)			\
+__PMC_EV(IAP, EVENT_90H_00H)			\
+__PMC_EV(IAP, EVENT_91H_00H)			\
+__PMC_EV(IAP, EVENT_92H_00H)			\
+__PMC_EV(IAP, EVENT_93H_00H)			\
+__PMC_EV(IAP, EVENT_94H_00H)			\
+__PMC_EV(IAP, EVENT_97H_00H)			\
+__PMC_EV(IAP, EVENT_98H_00H)			\
+__PMC_EV(IAP, EVENT_A0H_00H)			\
+__PMC_EV(IAP, EVENT_A1H_01H)			\
+__PMC_EV(IAP, EVENT_A1H_02H)			\
+__PMC_EV(IAP, EVENT_A1H_04H)			\
+__PMC_EV(IAP, EVENT_A1H_08H)			\
+__PMC_EV(IAP, EVENT_A1H_10H)			\
+__PMC_EV(IAP, EVENT_A1H_20H)			\
+__PMC_EV(IAP, EVENT_A2H_00H)			\
+__PMC_EV(IAP, EVENT_A2H_01H)			\
+__PMC_EV(IAP, EVENT_A2H_02H)			\
+__PMC_EV(IAP, EVENT_A2H_04H)			\
+__PMC_EV(IAP, EVENT_A2H_08H)			\
+__PMC_EV(IAP, EVENT_A2H_10H)			\
+__PMC_EV(IAP, EVENT_A2H_20H)			\
+__PMC_EV(IAP, EVENT_A2H_40H)			\
+__PMC_EV(IAP, EVENT_A2H_80H)			\
+__PMC_EV(IAP, EVENT_A6H_01H)			\
+__PMC_EV(IAP, EVENT_A7H_01H)			\
+__PMC_EV(IAP, EVENT_A8H_01H)			\
+__PMC_EV(IAP, EVENT_AAH_01H)			\
+__PMC_EV(IAP, EVENT_AAH_02H)			\
+__PMC_EV(IAP, EVENT_AAH_03H)			\
+__PMC_EV(IAP, EVENT_AAH_08H)			\
+__PMC_EV(IAP, EVENT_ABH_01H)			\
+__PMC_EV(IAP, EVENT_ABH_02H)			\
+__PMC_EV(IAP, EVENT_AEH_01H)			\
+__PMC_EV(IAP, EVENT_B0H_00H)			\
+__PMC_EV(IAP, EVENT_B0H_01H)			\
+__PMC_EV(IAP, EVENT_B0H_02H)			\
+__PMC_EV(IAP, EVENT_B0H_04H)			\
+__PMC_EV(IAP, EVENT_B0H_08H)			\
+__PMC_EV(IAP, EVENT_B0H_10H)			\
+__PMC_EV(IAP, EVENT_B0H_20H)			\
+__PMC_EV(IAP, EVENT_B0H_40H)			\
+__PMC_EV(IAP, EVENT_B0H_80H)			\
+__PMC_EV(IAP, EVENT_B1H_00H)			\
+__PMC_EV(IAP, EVENT_B1H_01H)			\
+__PMC_EV(IAP, EVENT_B1H_02H)			\
+__PMC_EV(IAP, EVENT_B1H_04H)			\
+__PMC_EV(IAP, EVENT_B1H_08H)			\
+__PMC_EV(IAP, EVENT_B1H_10H)			\
+__PMC_EV(IAP, EVENT_B1H_1FH)			\
+__PMC_EV(IAP, EVENT_B1H_20H)			\
+__PMC_EV(IAP, EVENT_B1H_3FH)			\
+__PMC_EV(IAP, EVENT_B1H_40H)			\
+__PMC_EV(IAP, EVENT_B1H_80H)			\
+__PMC_EV(IAP, EVENT_B2H_01H)			\
+__PMC_EV(IAP, EVENT_B3H_01H)			\
+__PMC_EV(IAP, EVENT_B3H_02H)			\
+__PMC_EV(IAP, EVENT_B3H_04H)			\
+__PMC_EV(IAP, EVENT_B3H_08H)			\
+__PMC_EV(IAP, EVENT_B3H_10H)			\
+__PMC_EV(IAP, EVENT_B3H_20H)			\
+__PMC_EV(IAP, EVENT_B3H_81H)			\
+__PMC_EV(IAP, EVENT_B3H_82H)			\
+__PMC_EV(IAP, EVENT_B3H_84H)			\
+__PMC_EV(IAP, EVENT_B3H_88H)			\
+__PMC_EV(IAP, EVENT_B3H_90H)			\
+__PMC_EV(IAP, EVENT_B3H_A0H)			\
+__PMC_EV(IAP, EVENT_B4H_01H)			\
+__PMC_EV(IAP, EVENT_B4H_02H)			\
+__PMC_EV(IAP, EVENT_B4H_04H)			\
+__PMC_EV(IAP, EVENT_B7H_01H)			\
+__PMC_EV(IAP, EVENT_B8H_01H)			\
+__PMC_EV(IAP, EVENT_B8H_02H)			\
+__PMC_EV(IAP, EVENT_B8H_04H)			\
+__PMC_EV(IAP, EVENT_BAH_01H)			\
+__PMC_EV(IAP, EVENT_BAH_02H)			\
+__PMC_EV(IAP, EVENT_BBH_01H)			\
+__PMC_EV(IAP, EVENT_C0H_00H)			\
+__PMC_EV(IAP, EVENT_C0H_01H)			\
+__PMC_EV(IAP, EVENT_C0H_02H)			\
+__PMC_EV(IAP, EVENT_C0H_04H)			\
+__PMC_EV(IAP, EVENT_C0H_08H)			\
+__PMC_EV(IAP, EVENT_C1H_00H)			\
+__PMC_EV(IAP, EVENT_C1H_01H)			\
+__PMC_EV(IAP, EVENT_C1H_FEH)			\
+__PMC_EV(IAP, EVENT_C2H_00H)			\
+__PMC_EV(IAP, EVENT_C2H_01H)			\
+__PMC_EV(IAP, EVENT_C2H_02H)			\
+__PMC_EV(IAP, EVENT_C2H_04H)			\
+__PMC_EV(IAP, EVENT_C2H_07H)			\
+__PMC_EV(IAP, EVENT_C2H_08H)			\
+__PMC_EV(IAP, EVENT_C2H_0FH)			\
+__PMC_EV(IAP, EVENT_C2H_10H)			\
+__PMC_EV(IAP, EVENT_C3H_00H)			\
+__PMC_EV(IAP, EVENT_C3H_01H)			\
+__PMC_EV(IAP, EVENT_C3H_02H)			\
+__PMC_EV(IAP, EVENT_C3H_04H)			\
+__PMC_EV(IAP, EVENT_C3H_10H)			\
+__PMC_EV(IAP, EVENT_C4H_00H)			\
+__PMC_EV(IAP, EVENT_C4H_01H)			\
+__PMC_EV(IAP, EVENT_C4H_02H)			\
+__PMC_EV(IAP, EVENT_C4H_04H)			\
+__PMC_EV(IAP, EVENT_C4H_08H)			\
+__PMC_EV(IAP, EVENT_C4H_0CH)			\
+__PMC_EV(IAP, EVENT_C4H_0FH)			\
+__PMC_EV(IAP, EVENT_C5H_00H)			\
+__PMC_EV(IAP, EVENT_C5H_01H)			\
+__PMC_EV(IAP, EVENT_C5H_02H)			\
+__PMC_EV(IAP, EVENT_C5H_04H)			\
+__PMC_EV(IAP, EVENT_C6H_00H)			\
+__PMC_EV(IAP, EVENT_C6H_01H)			\
+__PMC_EV(IAP, EVENT_C6H_02H)			\
+__PMC_EV(IAP, EVENT_C7H_00H)			\
+__PMC_EV(IAP, EVENT_C7H_01H)			\
+__PMC_EV(IAP, EVENT_C7H_02H)			\
+__PMC_EV(IAP, EVENT_C7H_04H)			\
+__PMC_EV(IAP, EVENT_C7H_08H)			\
+__PMC_EV(IAP, EVENT_C7H_10H)			\
+__PMC_EV(IAP, EVENT_C7H_1FH)			\
+__PMC_EV(IAP, EVENT_C8H_00H)			\
+__PMC_EV(IAP, EVENT_C8H_20H)			\
+__PMC_EV(IAP, EVENT_C9H_00H)			\
+__PMC_EV(IAP, EVENT_CAH_00H)			\
+__PMC_EV(IAP, EVENT_CAH_01H)			\
+__PMC_EV(IAP, EVENT_CAH_02H)			\
+__PMC_EV(IAP, EVENT_CAH_04H)			\
+__PMC_EV(IAP, EVENT_CAH_08H)			\
+__PMC_EV(IAP, EVENT_CBH_01H)			\
+__PMC_EV(IAP, EVENT_CBH_02H)			\
+__PMC_EV(IAP, EVENT_CBH_04H)			\
+__PMC_EV(IAP, EVENT_CBH_08H)			\
+__PMC_EV(IAP, EVENT_CBH_10H)			\
+__PMC_EV(IAP, EVENT_CBH_40H)			\
+__PMC_EV(IAP, EVENT_CBH_80H)			\
+__PMC_EV(IAP, EVENT_CCH_00H)			\
+__PMC_EV(IAP, EVENT_CCH_01H)			\
+__PMC_EV(IAP, EVENT_CCH_02H)			\
+__PMC_EV(IAP, EVENT_CCH_03H)			\
+__PMC_EV(IAP, EVENT_CDH_00H)			\
+__PMC_EV(IAP, EVENT_CEH_00H)			\
+__PMC_EV(IAP, EVENT_CFH_00H)			\
+__PMC_EV(IAP, EVENT_D0H_00H)			\
+__PMC_EV(IAP, EVENT_D0H_01H)			\
+__PMC_EV(IAP, EVENT_D1H_01H)			\
+__PMC_EV(IAP, EVENT_D1H_02H)			\
+__PMC_EV(IAP, EVENT_D1H_04H)			\
+__PMC_EV(IAP, EVENT_D1H_08H)			\
+__PMC_EV(IAP, EVENT_D2H_01H)			\
+__PMC_EV(IAP, EVENT_D2H_02H)			\
+__PMC_EV(IAP, EVENT_D2H_04H)			\
+__PMC_EV(IAP, EVENT_D2H_08H)			\
+__PMC_EV(IAP, EVENT_D2H_0FH)			\
+__PMC_EV(IAP, EVENT_D2H_10H)			\
+__PMC_EV(IAP, EVENT_D4H_01H)			\
+__PMC_EV(IAP, EVENT_D4H_02H)			\
+__PMC_EV(IAP, EVENT_D4H_04H)			\
+__PMC_EV(IAP, EVENT_D4H_08H)			\
+__PMC_EV(IAP, EVENT_D4H_0FH)			\
+__PMC_EV(IAP, EVENT_D5H_01H)			\
+__PMC_EV(IAP, EVENT_D5H_02H)			\
+__PMC_EV(IAP, EVENT_D5H_04H)			\
+__PMC_EV(IAP, EVENT_D5H_08H)			\
+__PMC_EV(IAP, EVENT_D5H_0FH)			\
+__PMC_EV(IAP, EVENT_D7H_00H)			\
+__PMC_EV(IAP, EVENT_D8H_00H)			\
+__PMC_EV(IAP, EVENT_D8H_01H)			\
+__PMC_EV(IAP, EVENT_D8H_02H)			\
+__PMC_EV(IAP, EVENT_D8H_03H)			\
+__PMC_EV(IAP, EVENT_D8H_04H)			\
+__PMC_EV(IAP, EVENT_D9H_00H)			\
+__PMC_EV(IAP, EVENT_D9H_01H)			\
+__PMC_EV(IAP, EVENT_D9H_02H)			\
+__PMC_EV(IAP, EVENT_D9H_03H)			\
+__PMC_EV(IAP, EVENT_DAH_00H)			\
+__PMC_EV(IAP, EVENT_DAH_01H)			\
+__PMC_EV(IAP, EVENT_DAH_02H)			\
+__PMC_EV(IAP, EVENT_DBH_00H)			\
+__PMC_EV(IAP, EVENT_DBH_01H)			\
+__PMC_EV(IAP, EVENT_DCH_01H)			\
+__PMC_EV(IAP, EVENT_DCH_02H)			\
+__PMC_EV(IAP, EVENT_DCH_04H)			\
+__PMC_EV(IAP, EVENT_DCH_08H)			\
+__PMC_EV(IAP, EVENT_DCH_10H)			\
+__PMC_EV(IAP, EVENT_DCH_1FH)			\
+__PMC_EV(IAP, EVENT_E0H_00H)			\
+__PMC_EV(IAP, EVENT_E0H_01H)			\
+__PMC_EV(IAP, EVENT_E2H_00H)			\
+__PMC_EV(IAP, EVENT_E4H_00H)			\
+__PMC_EV(IAP, EVENT_E4H_01H)			\
+__PMC_EV(IAP, EVENT_E5H_01H)			\
+__PMC_EV(IAP, EVENT_E6H_00H)			\
+__PMC_EV(IAP, EVENT_E6H_01H)			\
+__PMC_EV(IAP, EVENT_E6H_02H)			\
+__PMC_EV(IAP, EVENT_E8H_01H)			\
+__PMC_EV(IAP, EVENT_E8H_02H)			\
+__PMC_EV(IAP, EVENT_E8H_03H)			\
+__PMC_EV(IAP, EVENT_ECH_01H)			\
+__PMC_EV(IAP, EVENT_F0H_00H)			\
+__PMC_EV(IAP, EVENT_F0H_01H)			\
+__PMC_EV(IAP, EVENT_F0H_02H)			\
+__PMC_EV(IAP, EVENT_F0H_04H)			\
+__PMC_EV(IAP, EVENT_F0H_08H)			\
+__PMC_EV(IAP, EVENT_F0H_10H)			\
+__PMC_EV(IAP, EVENT_F0H_20H)			\
+__PMC_EV(IAP, EVENT_F0H_40H)			\
+__PMC_EV(IAP, EVENT_F0H_80H)			\
+__PMC_EV(IAP, EVENT_F1H_02H)			\
+__PMC_EV(IAP, EVENT_F1H_04H)			\
+__PMC_EV(IAP, EVENT_F1H_07H)			\
+__PMC_EV(IAP, EVENT_F2H_01H)			\
+__PMC_EV(IAP, EVENT_F2H_02H)			\
+__PMC_EV(IAP, EVENT_F2H_04H)			\
+__PMC_EV(IAP, EVENT_F2H_08H)			\
+__PMC_EV(IAP, EVENT_F2H_0FH)			\
+__PMC_EV(IAP, EVENT_F3H_01H)			\
+__PMC_EV(IAP, EVENT_F3H_02H)			\
+__PMC_EV(IAP, EVENT_F3H_04H)			\
+__PMC_EV(IAP, EVENT_F3H_08H)			\
+__PMC_EV(IAP, EVENT_F3H_10H)			\
+__PMC_EV(IAP, EVENT_F3H_20H)			\
+__PMC_EV(IAP, EVENT_F4H_01H)			\
+__PMC_EV(IAP, EVENT_F4H_02H)			\
+__PMC_EV(IAP, EVENT_F4H_04H)			\
+__PMC_EV(IAP, EVENT_F4H_08H)			\
+__PMC_EV(IAP, EVENT_F4H_10H)			\
+__PMC_EV(IAP, EVENT_F6H_01H)			\
+__PMC_EV(IAP, EVENT_F7H_01H)			\
+__PMC_EV(IAP, EVENT_F7H_02H)			\
+__PMC_EV(IAP, EVENT_F7H_04H)			\
+__PMC_EV(IAP, EVENT_F8H_00H)			\
+__PMC_EV(IAP, EVENT_F8H_01H)			\
+__PMC_EV(IAP, EVENT_FDH_01H)			\
+__PMC_EV(IAP, EVENT_FDH_02H)			\
+__PMC_EV(IAP, EVENT_FDH_04H)			\
+__PMC_EV(IAP, EVENT_FDH_08H)			\
+__PMC_EV(IAP, EVENT_FDH_10H)			\
+__PMC_EV(IAP, EVENT_FDH_20H)			\
+__PMC_EV(IAP, EVENT_FDH_40H)
+
+#define	PMC_EV_IAP_FIRST	PMC_EV_IAP_EVENT_02H_01H
+#define	PMC_EV_IAP_LAST		PMC_EV_IAP_EVENT_FDH_40H
+
+/*
+ * Map "architectural" event names to event ids.
+ */
+#define	__PMC_EV_ALIAS_INTEL_ARCHITECTURAL()				\
+__PMC_EV_ALIAS("branch-instruction-retired",	IAP_EVENT_C4H_00H)	\
+__PMC_EV_ALIAS("branch-misses-retired",		IAP_EVENT_C5H_00H)	\
+__PMC_EV_ALIAS("instruction-retired",		IAP_EVENT_C0H_00H)	\
+__PMC_EV_ALIAS("llc-misses",			IAP_EVENT_2EH_41H)	\
+__PMC_EV_ALIAS("llc-reference",			IAP_EVENT_2EH_4FH)	\
+__PMC_EV_ALIAS("unhalted-reference-cycles",	IAP_EVENT_3CH_01H)	\
+__PMC_EV_ALIAS("unhalted-core-cycles",		IAP_EVENT_3CH_00H)
+
+/*
+ * Aliases for Atom PMCs.
+ */
+#define	__PMC_EV_ALIAS_ATOM()						\
+__PMC_EV_ALIAS_INTEL_ARCHITECTURAL()					\
+__PMC_EV_ALIAS("BACLEARS",			IAP_EVENT_E6H_01H)	\
+__PMC_EV_ALIAS("BOGUS_BR",			IAP_EVENT_E4H_00H)	\
+__PMC_EV_ALIAS("BR_BAC_MISSP_EXEC",		IAP_EVENT_8AH_00H)	\
+__PMC_EV_ALIAS("BR_CALL_EXEC",			IAP_EVENT_92H_00H)	\
+__PMC_EV_ALIAS("BR_CALL_MISSP_EXEC",		IAP_EVENT_93H_00H)	\
+__PMC_EV_ALIAS("BR_CND_EXEC",			IAP_EVENT_8BH_00H)	\
+__PMC_EV_ALIAS("BR_CND_MISSP_EXEC",		IAP_EVENT_8CH_00H)	\
+__PMC_EV_ALIAS("BR_IND_CALL_EXEC",		IAP_EVENT_94H_00H)	\
+__PMC_EV_ALIAS("BR_IND_EXEC",			IAP_EVENT_8DH_00H)	\
+__PMC_EV_ALIAS("BR_IND_MISSP_EXEC",		IAP_EVENT_8EH_00H)	\
+__PMC_EV_ALIAS("BR_INST_DECODED",		IAP_EVENT_E0H_01H)	\
+__PMC_EV_ALIAS("BR_INST_EXEC",			IAP_EVENT_88H_00H)	\
+__PMC_EV_ALIAS("BR_INST_RETIRED.ANY",		IAP_EVENT_C4H_00H)	\
+__PMC_EV_ALIAS("BR_INST_RETIRED.ANY1",		IAP_EVENT_C4H_0FH)	\
+__PMC_EV_ALIAS("BR_INST_RETIRED.MISPRED",	IAP_EVENT_C5H_00H)	\
+__PMC_EV_ALIAS("BR_INST_RETIRED.MISPRED_NOT_TAKEN",			\
+    IAP_EVENT_C4H_02H)							\
+__PMC_EV_ALIAS("BR_INST_RETIRED.MISPRED_TAKEN",	IAP_EVENT_C4H_08H)	\
+__PMC_EV_ALIAS("BR_INST_RETIRED.PRED_NOT_TAKEN",IAP_EVENT_C4H_01H)	\
+__PMC_EV_ALIAS("BR_INST_RETIRED.PRED_TAKEN",	IAP_EVENT_C4H_04H)	\
+__PMC_EV_ALIAS("BR_INST_RETIRED.TAKEN",		IAP_EVENT_C4H_0CH)	\
+__PMC_EV_ALIAS("BR_MISSP_EXEC",			IAP_EVENT_89H_00H)	\
+__PMC_EV_ALIAS("BR_RET_BAC_MISSP_EXEC",		IAP_EVENT_91H_00H)	\
+__PMC_EV_ALIAS("BR_RET_EXEC",			IAP_EVENT_8FH_00H)	\
+__PMC_EV_ALIAS("BR_RET_MISSP_EXEC",		IAP_EVENT_90H_00H)	\
+__PMC_EV_ALIAS("BR_TKN_BUBBLE_1",		IAP_EVENT_97H_00H)	\
+__PMC_EV_ALIAS("BR_TKN_BUBBLE_2",		IAP_EVENT_98H_00H)	\
+__PMC_EV_ALIAS("BUSQ_EMPTY",			IAP_EVENT_7DH)		\
+__PMC_EV_ALIAS("BUS_BNR_DRV",			IAP_EVENT_61H)		\
+__PMC_EV_ALIAS("BUS_DATA_RCV",			IAP_EVENT_64H)		\
+__PMC_EV_ALIAS("BUS_DRDY_CLOCKS",		IAP_EVENT_62H)		\
+__PMC_EV_ALIAS("BUS_HITM_DRV",			IAP_EVENT_7BH)		\
+__PMC_EV_ALIAS("BUS_HIT_DRV",			IAP_EVENT_7AH)		\
+__PMC_EV_ALIAS("BUS_IO_WAIT",			IAP_EVENT_7FH)		\
+__PMC_EV_ALIAS("BUS_LOCK_CLOCKS",		IAP_EVENT_63H)		\
+__PMC_EV_ALIAS("BUS_REQUEST_OUTSTANDING",	IAP_EVENT_60H)		\
+__PMC_EV_ALIAS("BUS_TRANS_ANY",			IAP_EVENT_70H)		\
+__PMC_EV_ALIAS("BUS_TRANS_BRD",			IAP_EVENT_65H)		\
+__PMC_EV_ALIAS("BUS_TRANS_BURST",		IAP_EVENT_6EH)		\
+__PMC_EV_ALIAS("BUS_TRANS_DEF",			IAP_EVENT_6DH)		\
+__PMC_EV_ALIAS("BUS_TRANS_IFETCH",		IAP_EVENT_68H)		\
+__PMC_EV_ALIAS("BUS_TRANS_INVAL",		IAP_EVENT_69H)		\
+__PMC_EV_ALIAS("BUS_TRANS_IO",			IAP_EVENT_6CH)		\
+__PMC_EV_ALIAS("BUS_TRANS_MEM",			IAP_EVENT_6FH)		\
+__PMC_EV_ALIAS("BUS_TRANS_P",			IAP_EVENT_6BH)		\
+__PMC_EV_ALIAS("BUS_TRANS_PWR",			IAP_EVENT_6AH)		\
+__PMC_EV_ALIAS("BUS_TRANS_RFO",			IAP_EVENT_66H)		\
+__PMC_EV_ALIAS("BUS_TRANS_WB",			IAP_EVENT_67H)		\
+__PMC_EV_ALIAS("CMP_SNOOP",			IAP_EVENT_78H)		\
+__PMC_EV_ALIAS("CPU_CLK_UNHALTED.BUS",		IAP_EVENT_3CH_01H)	\
+__PMC_EV_ALIAS("CPU_CLK_UNHALTED.CORE_P",	IAP_EVENT_3CH_00H)	\
+__PMC_EV_ALIAS("CPU_CLK_UNHALTED.NO_OTHER",	IAP_EVENT_3CH_02H)	\
+__PMC_EV_ALIAS("CYCLES_DIV_BUSY",		IAP_EVENT_14H_01H)	\
+__PMC_EV_ALIAS("CYCLES_INT_MASKED.CYCLES_INT_MASKED",			\
+    IAP_EVENT_C6H_01H)							\
+__PMC_EV_ALIAS("CYCLES_INT_MASKED.CYCLES_INT_PENDING_AND_MASKED",	\
+    IAP_EVENT_C6H_02H)							\
+__PMC_EV_ALIAS("CYCLES_L1I_MEM_STALLED",	IAP_EVENT_86H_00H)	\
+__PMC_EV_ALIAS("DATA_TLB_MISSES.DTLB_MISS",	IAP_EVENT_08H_07H)	\
+__PMC_EV_ALIAS("DATA_TLB_MISSES.DTLB_MISS_LD",	IAP_EVENT_08H_05H)	\
+__PMC_EV_ALIAS("DATA_TLB_MISSES.DTLB_MISS_ST",	IAP_EVENT_08H_06H)	\
+__PMC_EV_ALIAS("DATA_TLB_MISSES.UTLB_MISS_LD",	IAP_EVENT_08H_09H)	\
+__PMC_EV_ALIAS("DELAYED_BYPASS.FP",		IAP_EVENT_19H_00H)	\
+__PMC_EV_ALIAS("DELAYED_BYPASS.LOAD",		IAP_EVENT_19H_01H)	\
+__PMC_EV_ALIAS("DELAYED_BYPASS.SIMD",		IAP_EVENT_19H_02H)	\
+__PMC_EV_ALIAS("DIV",				IAP_EVENT_13H_00H)	\
+__PMC_EV_ALIAS("DIV.AR",			IAP_EVENT_13H_81H)	\
+__PMC_EV_ALIAS("DIV.S",				IAP_EVENT_13H_01H)	\
+__PMC_EV_ALIAS("DTLB_MISSES.ANY",		IAP_EVENT_08H_01H)	\
+__PMC_EV_ALIAS("DTLB_MISSES.L0_MISS_LD",	IAP_EVENT_08H_04H)	\
+__PMC_EV_ALIAS("DTLB_MISSES.MISS_LD",		IAP_EVENT_08H_02H)	\
+__PMC_EV_ALIAS("DTLB_MISSES.MISS_ST",		IAP_EVENT_08H_08H)	\
+__PMC_EV_ALIAS("EIST_TRANS",			IAP_EVENT_3AH_00H)	\
+__PMC_EV_ALIAS("ESP.ADDITIONS",			IAP_EVENT_ABH_02H)	\
+__PMC_EV_ALIAS("ESP.SYNCH",			IAP_EVENT_ABH_01H)	\
+__PMC_EV_ALIAS("EXT_SNOOP",			IAP_EVENT_77H)		\
+__PMC_EV_ALIAS("FP_ASSIST",			IAP_EVENT_11H_01H)	\
+__PMC_EV_ALIAS("FP_ASSIST.AR",			IAP_EVENT_11H_81H)	\
+__PMC_EV_ALIAS("FP_COMP_OPS_EXE",		IAP_EVENT_10H_00H)	\
+__PMC_EV_ALIAS("FP_MMX_TRANS_TO_FP",		IAP_EVENT_CCH_02H)	\
+__PMC_EV_ALIAS("FP_MMX_TRANS_TO_MMX",		IAP_EVENT_CCH_01H)	\
+__PMC_EV_ALIAS("HW_INT_RCV",			IAP_EVENT_C8H_00H)	\
+__PMC_EV_ALIAS("ICACHE.ACCESSES",		IAP_EVENT_80H_03H)	\
+__PMC_EV_ALIAS("ICACHE.MISSES",			IAP_EVENT_80H_02H)	\
+__PMC_EV_ALIAS("IDLE_DURING_DIV",		IAP_EVENT_18H_00H)	\
+__PMC_EV_ALIAS("ILD_STALL",			IAP_EVENT_87H_00H)	\
+__PMC_EV_ALIAS("INST_QUEUE.FULL",		IAP_EVENT_83H_02H)	\
+__PMC_EV_ALIAS("INST_RETIRED.ANY_P",		IAP_EVENT_C0H_00H)	\
+__PMC_EV_ALIAS("INST_RETIRED.LOADS",		IAP_EVENT_C0H_01H)	\
+__PMC_EV_ALIAS("INST_RETIRED.OTHER",		IAP_EVENT_C0H_04H)	\
+__PMC_EV_ALIAS("INST_RETIRED.STORES",		IAP_EVENT_C0H_02H)	\
+__PMC_EV_ALIAS("ITLB.FLUSH",			IAP_EVENT_82H_04H)	\
+__PMC_EV_ALIAS("ITLB.LARGE_MISS",		IAP_EVENT_82H_10H)	\
+__PMC_EV_ALIAS("ITLB.MISSES",			IAP_EVENT_82H_02H)	\
+__PMC_EV_ALIAS("ITLB.SMALL_MISS",		IAP_EVENT_82H_02H)	\
+__PMC_EV_ALIAS("ITLB_MISS_RETIRED",		IAP_EVENT_C9H_00H)	\
+__PMC_EV_ALIAS("L1D_ALL_CACHE_REF",		IAP_EVENT_43H_02H)	\
+__PMC_EV_ALIAS("L1D_ALL_REF",			IAP_EVENT_43H_01H)	\
+__PMC_EV_ALIAS("L1D_CACHE.LD",			IAP_EVENT_40H_21H)	\
+__PMC_EV_ALIAS("L1D_CACHE.ST",			IAP_EVENT_41H_22H)	\
+__PMC_EV_ALIAS("L1D_CACHE_LOCK",		IAP_EVENT_42H)		\
+__PMC_EV_ALIAS("L1D_CACHE_LOCK_DURATION",	IAP_EVENT_42H_10H)	\
+__PMC_EV_ALIAS("L1D_M_EVICT",			IAP_EVENT_47H_00H)	\
+__PMC_EV_ALIAS("L1D_M_REPL",			IAP_EVENT_46H_00H)	\
+__PMC_EV_ALIAS("L1D_PEND_MISS",			IAP_EVENT_48H_00H)	\
+__PMC_EV_ALIAS("L1D_PREFETCH.REQUESTS",		IAP_EVENT_4EH_10H)	\
+__PMC_EV_ALIAS("L1D_REPL",			IAP_EVENT_45H_0FH)	\
+__PMC_EV_ALIAS("L1D_SPLIT.LOADS",		IAP_EVENT_49H_01H)	\
+__PMC_EV_ALIAS("L1D_SPLIT.STORES",		IAP_EVENT_49H_02H)	\
+__PMC_EV_ALIAS("L1I_MISSES",			IAP_EVENT_81H_00H)	\
+__PMC_EV_ALIAS("L1I_READS",			IAP_EVENT_80H_00H)	\
+__PMC_EV_ALIAS("L2_ADS",			IAP_EVENT_21H)		\
+__PMC_EV_ALIAS("L2_DBUS_BUSY_RD",		IAP_EVENT_23H)		\
+__PMC_EV_ALIAS("L2_IFETCH",			IAP_EVENT_28H)		\
+__PMC_EV_ALIAS("L2_LD",				IAP_EVENT_29H)		\
+__PMC_EV_ALIAS("L2_LINES_IN",			IAP_EVENT_24H)		\
+__PMC_EV_ALIAS("L2_LINES_OUT",			IAP_EVENT_26H)		\
+__PMC_EV_ALIAS("L2_LOCK",			IAP_EVENT_2BH)		\
+__PMC_EV_ALIAS("L2_M_LINES_IN",			IAP_EVENT_25H)		\
+__PMC_EV_ALIAS("L2_M_LINES_OUT",		IAP_EVENT_27H)		\
+__PMC_EV_ALIAS("L2_NO_REQ",			IAP_EVENT_32H)		\
+__PMC_EV_ALIAS("L2_REJECT_BUSQ",		IAP_EVENT_30H)		\
+__PMC_EV_ALIAS("L2_RQSTS",			IAP_EVENT_2EH)		\
+__PMC_EV_ALIAS("L2_RQSTS.SELF.DEMAND.I_STATE",	IAP_EVENT_2EH_41H)	\
+__PMC_EV_ALIAS("L2_RQSTS.SELF.DEMAND.MESI",	IAP_EVENT_2EH_4FH)	\
+__PMC_EV_ALIAS("L2_ST",				IAP_EVENT_2AH)		\
+__PMC_EV_ALIAS("LOAD_BLOCK.L1D",		IAP_EVENT_03H_20H)	\
+__PMC_EV_ALIAS("LOAD_BLOCK.OVERLAP_STORE",	IAP_EVENT_03H_08H)	\
+__PMC_EV_ALIAS("LOAD_BLOCK.STA",		IAP_EVENT_03H_02H)	\
+__PMC_EV_ALIAS("LOAD_BLOCK.STD",		IAP_EVENT_03H_04H)	\
+__PMC_EV_ALIAS("LOAD_BLOCK.UNTIL_RETIRE",	IAP_EVENT_03H_10H)	\
+__PMC_EV_ALIAS("LOAD_HIT_PRE",			IAP_EVENT_4CH_00H)	\
+__PMC_EV_ALIAS("MACHINE_CLEARS.SMC",		IAP_EVENT_C3H_01H)	\
+__PMC_EV_ALIAS("MACHINE_NUKES.MEM_ORDER",	IAP_EVENT_C3H_04H)	\
+__PMC_EV_ALIAS("MACRO_INSTS.ALL_DECODED",	IAP_EVENT_AAH_03H)	\
+__PMC_EV_ALIAS("MACRO_INSTS.CISC_DECODED",	IAP_EVENT_AAH_02H)	\
+__PMC_EV_ALIAS("MEMORY_DISAMBIGUATION.RESET",	IAP_EVENT_09H_01H)	\
+__PMC_EV_ALIAS("MEMORY_DISAMBIGUATION.SUCCESS",	IAP_EVENT_09H_02H)	\
+__PMC_EV_ALIAS("MEM_LOAD_RETIRED.DTLB_MISS",	IAP_EVENT_CBH_04H)	\
+__PMC_EV_ALIAS("MEM_LOAD_RETIRED.L2_HIT",	IAP_EVENT_CBH_01H)	\
+__PMC_EV_ALIAS("MEM_LOAD_RETIRED.L2_LINE_MISS",	IAP_EVENT_CBH_08H)	\
+__PMC_EV_ALIAS("MEM_LOAD_RETIRED.L2_MISS",	IAP_EVENT_CBH_02H)	\
+__PMC_EV_ALIAS("MUL",				IAP_EVENT_12H_00H)	\
+__PMC_EV_ALIAS("MUL.AR",			IAP_EVENT_12H_81H)	\
+__PMC_EV_ALIAS("MUL.S",				IAP_EVENT_12H_01H)	\
+__PMC_EV_ALIAS("PAGE_WALKS.CYCLES",		IAP_EVENT_0CH_03H)	\
+__PMC_EV_ALIAS("PAGE_WALKS.WALKS",		IAP_EVENT_0CH_03H)	\
+__PMC_EV_ALIAS("PREFETCH.PREFETCHNTA",		IAP_EVENT_07H_08H)	\
+__PMC_EV_ALIAS("PREFETCH.PREFETCHT0",		IAP_EVENT_07H_01H)	\
+__PMC_EV_ALIAS("PREFETCH.SW_L2",		IAP_EVENT_07H_06H)	\
+__PMC_EV_ALIAS("PREF_RQSTS_DN",			IAP_EVENT_F8H_00H)	\
+__PMC_EV_ALIAS("PREF_RQSTS_UP",			IAP_EVENT_F0H_00H)	\
+__PMC_EV_ALIAS("RAT_STALLS.ANY",		IAP_EVENT_D2H_0FH)	\
+__PMC_EV_ALIAS("RAT_STALLS.FLAGS",		IAP_EVENT_D2H_04H)	\
+__PMC_EV_ALIAS("RAT_STALLS.FPSW",		IAP_EVENT_D2H_08H)	\
+__PMC_EV_ALIAS("RAT_STALLS.PARTIAL_CYCLES",	IAP_EVENT_D2H_02H)	\
+__PMC_EV_ALIAS("RAT_STALLS.ROB_READ_PORT",	IAP_EVENT_D2H_01H)	\
+__PMC_EV_ALIAS("RESOURCE_STALLS.ANY",		IAP_EVENT_DCH_1FH)	\
+__PMC_EV_ALIAS("RESOURCE_STALLS.BR_MISS_CLEAR",	IAP_EVENT_DCH_10H)	\
+__PMC_EV_ALIAS("RESOURCE_STALLS.FPCW",		IAP_EVENT_DCH_08H)	\
+__PMC_EV_ALIAS("RESOURCE_STALLS.LD_ST",		IAP_EVENT_DCH_04H)	\
+__PMC_EV_ALIAS("RESOURCE_STALLS.ROB_FULL",	IAP_EVENT_DCH_01H)	\
+__PMC_EV_ALIAS("RESOURCE_STALLS.RS_FULL",	IAP_EVENT_DCH_02H)	\
+__PMC_EV_ALIAS("RS_UOPS_DISPATCHED",		IAP_EVENT_A0H_00H)	\
+__PMC_EV_ALIAS("RS_UOPS_DISPATCHED.PORT0",	IAP_EVENT_A1H_01H)	\
+__PMC_EV_ALIAS("RS_UOPS_DISPATCHED.PORT1",	IAP_EVENT_A1H_02H)	\
+__PMC_EV_ALIAS("RS_UOPS_DISPATCHED.PORT2",	IAP_EVENT_A1H_04H)	\
+__PMC_EV_ALIAS("RS_UOPS_DISPATCHED.PORT3",	IAP_EVENT_A1H_08H)	\
+__PMC_EV_ALIAS("RS_UOPS_DISPATCHED.PORT4",	IAP_EVENT_A1H_10H)	\
+__PMC_EV_ALIAS("RS_UOPS_DISPATCHED.PORT5",	IAP_EVENT_A1H_20H)	\
+__PMC_EV_ALIAS("SB_DRAIN_CYCLES",		IAP_EVENT_04H_01H)	\
+__PMC_EV_ALIAS("SEGMENT_REG_LOADS.ANY",		IAP_EVENT_06H_00H)	\
+__PMC_EV_ALIAS("SEG_REG_RENAMES.ANY",		IAP_EVENT_D5H_0FH)	\
+__PMC_EV_ALIAS("SEG_REG_RENAMES.DS",		IAP_EVENT_D5H_02H)	\
+__PMC_EV_ALIAS("SEG_REG_RENAMES.ES",		IAP_EVENT_D5H_01H)	\
+__PMC_EV_ALIAS("SEG_REG_RENAMES.FS",		IAP_EVENT_D5H_04H)	\
+__PMC_EV_ALIAS("SEG_REG_RENAMES.GS",		IAP_EVENT_D5H_08H)	\
+__PMC_EV_ALIAS("SEG_RENAME_STALLS.ANY",		IAP_EVENT_D4H_0FH)	\
+__PMC_EV_ALIAS("SEG_RENAME_STALLS.DS",		IAP_EVENT_D4H_02H)	\
+__PMC_EV_ALIAS("SEG_RENAME_STALLS.ES",		IAP_EVENT_D4H_01H)	\
+__PMC_EV_ALIAS("SEG_RENAME_STALLS.FS",		IAP_EVENT_D4H_04H)	\
+__PMC_EV_ALIAS("SEG_RENAME_STALLS.GS",		IAP_EVENT_D4H_08H)	\
+__PMC_EV_ALIAS("SIMD_ASSIST",			IAP_EVENT_CDH_00H)	\
+__PMC_EV_ALIAS("SIMD_COMP_INST_RETIRED.PACKED_DOUBLE",			\
+    IAP_EVENT_CAH_04H)							\
+__PMC_EV_ALIAS("SIMD_COMP_INST_RETIRED.PACKED_SINGLE",			\
+    IAP_EVENT_CAH_01H)							\
+__PMC_EV_ALIAS("SIMD_COMP_INST_RETIRED.SCALAR_DOUBLE",			\
+    IAP_EVENT_CAH_08H)							\
+__PMC_EV_ALIAS("SIMD_COMP_INST_RETIRED.SCALAR_SINGLE",			\
+    IAP_EVENT_CAH_02H)							\
+__PMC_EV_ALIAS("SIMD_INSTR_RETIRED",		IAP_EVENT_CEH_00H)	\
+__PMC_EV_ALIAS("SIMD_INST_RETIRED.ANY",		IAP_EVENT_C7H_1FH)	\
+__PMC_EV_ALIAS("SIMD_INST_RETIRED.PACKED_DOUBLE", IAP_EVENT_C7H_04H)	\
+__PMC_EV_ALIAS("SIMD_INST_RETIRED.PACKED_SINGLE", IAP_EVENT_C7H_01H)	\
+__PMC_EV_ALIAS("SIMD_INST_RETIRED.SCALAR_DOUBLE", IAP_EVENT_C7H_08H)	\
+__PMC_EV_ALIAS("SIMD_INST_RETIRED.SCALAR_SINGLE", IAP_EVENT_C7H_02H)	\
+__PMC_EV_ALIAS("SIMD_INST_RETIRED.VECTOR",	IAP_EVENT_C7H_10H)	\
+__PMC_EV_ALIAS("SIMD_SAT_INSTR_RETIRED",	IAP_EVENT_CFH_00H)	\
+__PMC_EV_ALIAS("SIMD_SAT_UOP_EXEC.AR",		IAP_EVENT_B1H_80H)	\
+__PMC_EV_ALIAS("SIMD_SAT_UOP_EXEC.S",		IAP_EVENT_B1H_00H)	\
+__PMC_EV_ALIAS("SIMD_UOPS_EXEC.AR",		IAP_EVENT_B0H_80H)	\
+__PMC_EV_ALIAS("SIMD_UOPS_EXEC.S",		IAP_EVENT_B0H_00H)	\
+__PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.ARITHMETIC.AR", IAP_EVENT_B3H_A0H)	\
+__PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.ARITHMETIC.S",  IAP_EVENT_B3H_20H)	\
+__PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.LOGICAL.AR",	IAP_EVENT_B3H_90H)	\
+__PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.LOGICAL.S",	IAP_EVENT_B3H_10H)	\
+__PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.MUL.AR",	IAP_EVENT_B3H_81H)	\
+__PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.MUL.S",	IAP_EVENT_B3H_01H)	\
+__PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.PACK.AR",	IAP_EVENT_B3H_84H)	\
+__PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.PACK.S",	IAP_EVENT_B3H_04H)	\
+__PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.SHIFT.AR",	IAP_EVENT_B3H_82H)	\
+__PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.SHIFT.S",	IAP_EVENT_B3H_02H)	\
+__PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.UNPACK.AR",	IAP_EVENT_B3H_88H)	\
+__PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.UNPACK.S",	IAP_EVENT_B3H_08H)	\
+__PMC_EV_ALIAS("SNOOP_STALL_DRV",		IAP_EVENT_7EH)		\
+__PMC_EV_ALIAS("SSE_PRE_EXEC.L2",		IAP_EVENT_07H_02H)	\
+__PMC_EV_ALIAS("SSE_PRE_EXEC.STORES",		IAP_EVENT_07H_03H)	\
+__PMC_EV_ALIAS("SSE_PRE_MISS.L1",		IAP_EVENT_4BH_01H)	\
+__PMC_EV_ALIAS("SSE_PRE_MISS.L2",		IAP_EVENT_4BH_02H)	\
+__PMC_EV_ALIAS("SSE_PRE_MISS.NTA",		IAP_EVENT_4BH_00H)	\
+__PMC_EV_ALIAS("STORE_BLOCK.ORDER",		IAP_EVENT_04H_02H)	\
+__PMC_EV_ALIAS("STORE_BLOCK.SNOOP",		IAP_EVENT_04H_08H)	\
+__PMC_EV_ALIAS("STORE_FORWARDS.GOOD",		IAP_EVENT_02H_81H)	\
+__PMC_EV_ALIAS("THERMAL_TRIP",			IAP_EVENT_3BH_C0H)	\
+__PMC_EV_ALIAS("UOPS_RETIRED.ANY",		IAP_EVENT_C2H_10H)	\
+__PMC_EV_ALIAS("UOPS_RETIRED.FUSED",		IAP_EVENT_C2H_07H)	\
+__PMC_EV_ALIAS("UOPS_RETIRED.LD_IND_BR",	IAP_EVENT_C2H_01H)	\
+__PMC_EV_ALIAS("UOPS_RETIRED.MACRO_FUSION",	IAP_EVENT_C2H_04H)	\
+__PMC_EV_ALIAS("UOPS_RETIRED.NON_FUSED",	IAP_EVENT_C2H_08H)	\
+__PMC_EV_ALIAS("UOPS_RETIRED.STD_STA",		IAP_EVENT_C2H_02H)	\
+__PMC_EV_ALIAS("X87_COMP_OPS_EXE.ANY.AR",	IAP_EVENT_10H_81H)	\
+__PMC_EV_ALIAS("X87_COMP_OPS_EXE.ANY.S",	IAP_EVENT_10H_01H)	\
+__PMC_EV_ALIAS("X87_OPS_RETIRED.ANY",		IAP_EVENT_C1H_FEH)	\
+__PMC_EV_ALIAS("X87_OPS_RETIRED.FXCH",		IAP_EVENT_C1H_01H)
+
+/*
+ * Aliases for Core PMC events.
+ */
+#define	__PMC_EV_ALIAS_CORE()					\
+__PMC_EV_ALIAS_INTEL_ARCHITECTURAL()				\
+__PMC_EV_ALIAS("BAClears",		IAP_EVENT_E6H_00H)	\
+__PMC_EV_ALIAS("BTB_Misses",		IAP_EVENT_E2H_00H)	\
+__PMC_EV_ALIAS("Br_BAC_Missp_Exec",	IAP_EVENT_8AH_00H)	\
+__PMC_EV_ALIAS("Br_Bogus",		IAP_EVENT_E4H_00H)	\
+__PMC_EV_ALIAS("Br_Call_Exec",		IAP_EVENT_92H_00H)	\
+__PMC_EV_ALIAS("Br_Call_Missp_Exec",	IAP_EVENT_93H_00H)	\
+__PMC_EV_ALIAS("Br_Cnd_Exec",		IAP_EVENT_8BH_00H)	\
+__PMC_EV_ALIAS("Br_Cnd_Missp_Exec",	IAP_EVENT_8CH_00H)	\
+__PMC_EV_ALIAS("Br_Ind_Call_Exec",	IAP_EVENT_94H_00H)	\
+__PMC_EV_ALIAS("Br_Ind_Exec",		IAP_EVENT_8DH_00H)	\
+__PMC_EV_ALIAS("Br_Ind_Missp_Exec",	IAP_EVENT_8EH_00H)	\
+__PMC_EV_ALIAS("Br_Inst_Exec",		IAP_EVENT_88H_00H)	\
+__PMC_EV_ALIAS("Br_Instr_Decoded",	IAP_EVENT_E0H_00H)	\
+__PMC_EV_ALIAS("Br_Instr_Ret",		IAP_EVENT_C4H_00H)	\
+__PMC_EV_ALIAS("Br_MisPred_Ret",	IAP_EVENT_C5H_00H)	\
+__PMC_EV_ALIAS("Br_MisPred_Taken_Ret",	IAP_EVENT_CAH_00H)	\
+__PMC_EV_ALIAS("Br_Missp_Exec",		IAP_EVENT_89H_00H)	\
+__PMC_EV_ALIAS("Br_Ret_BAC_Missp_Exec",	IAP_EVENT_91H_00H)	\
+__PMC_EV_ALIAS("Br_Ret_Exec",		IAP_EVENT_8FH_00H)	\
+__PMC_EV_ALIAS("Br_Ret_Missp_Exec",	IAP_EVENT_90H_00H)	\
+__PMC_EV_ALIAS("Br_Taken_Ret",		IAP_EVENT_C9H_00H)	\
+__PMC_EV_ALIAS("Bus_BNR_Clocks",	IAP_EVENT_61H_00H)	\
+__PMC_EV_ALIAS("Bus_DRDY_Clocks",	IAP_EVENT_62H_00H)	\
+__PMC_EV_ALIAS("Bus_Data_Rcv",		IAP_EVENT_64H_40H)	\
+__PMC_EV_ALIAS("Bus_Locks_Clocks",	IAP_EVENT_63H)		\
+__PMC_EV_ALIAS("Bus_Not_In_Use",	IAP_EVENT_7DH)		\
+__PMC_EV_ALIAS("Bus_Req_Outstanding",	IAP_EVENT_60H)		\
+__PMC_EV_ALIAS("Bus_Snoop_Stall",	IAP_EVENT_7EH_00H)	\
+__PMC_EV_ALIAS("Bus_Snoops",		IAP_EVENT_77H)		\
+__PMC_EV_ALIAS("Bus_Trans_Any",		IAP_EVENT_70H)		\
+__PMC_EV_ALIAS("Bus_Trans_Brd",		IAP_EVENT_65H)		\
+__PMC_EV_ALIAS("Bus_Trans_Burst",	IAP_EVENT_6EH)		\
+__PMC_EV_ALIAS("Bus_Trans_Def",		IAP_EVENT_6DH)		\
+__PMC_EV_ALIAS("Bus_Trans_IO",		IAP_EVENT_6CH)		\
+__PMC_EV_ALIAS("Bus_Trans_Ifetch",	IAP_EVENT_68H)		\
+__PMC_EV_ALIAS("Bus_Trans_Inval",	IAP_EVENT_69H)		\
+__PMC_EV_ALIAS("Bus_Trans_Mem",		IAP_EVENT_6FH)		\
+__PMC_EV_ALIAS("Bus_Trans_P",		IAP_EVENT_6BH)		\
+__PMC_EV_ALIAS("Bus_Trans_Pwr",		IAP_EVENT_6AH)		\
+__PMC_EV_ALIAS("Bus_Trans_RFO",		IAP_EVENT_66H)		\
+__PMC_EV_ALIAS("Bus_Trans_WB",		IAP_EVENT_67H)		\
+__PMC_EV_ALIAS("Cycles_Div_Busy",	IAP_EVENT_14H_00H)	\
+__PMC_EV_ALIAS("Cycles_Int_Masked",	IAP_EVENT_C6H_00H)	\
+__PMC_EV_ALIAS("Cycles_Int_Pending_Masked", IAP_EVENT_C7H_00H)	\
+__PMC_EV_ALIAS("DCU_Snoop_To_Share",	IAP_EVENT_78H)		\
+__PMC_EV_ALIAS("DCache_Cache_LD",	IAP_EVENT_40H)		\
+__PMC_EV_ALIAS("DCache_Cache_Lock",	IAP_EVENT_42H)		\
+__PMC_EV_ALIAS("DCache_Cache_ST",	IAP_EVENT_41H)		\
+__PMC_EV_ALIAS("DCache_M_Evict",	IAP_EVENT_47H_00H)	\
+__PMC_EV_ALIAS("DCache_M_Repl",		IAP_EVENT_46H_00H)	\
+__PMC_EV_ALIAS("DCache_Pend_Miss",	IAP_EVENT_48H_00H)	\
+__PMC_EV_ALIAS("DCache_Repl",		IAP_EVENT_45H_0FH)	\
+__PMC_EV_ALIAS("Data_Mem_Cache_Ref",	IAP_EVENT_44H_02H)	\
+__PMC_EV_ALIAS("Data_Mem_Ref",		IAP_EVENT_43H_01H)	\
+__PMC_EV_ALIAS("Dbus_Busy",		IAP_EVENT_22H)		\
+__PMC_EV_ALIAS("Dbus_Busy_Rd",		IAP_EVENT_23H)		\
+__PMC_EV_ALIAS("Div",			IAP_EVENT_13H_00H)	\
+__PMC_EV_ALIAS("Dtlb_Miss",		IAP_EVENT_49H_00H)	\
+__PMC_EV_ALIAS("ESP_Uops",		IAP_EVENT_D7H_00H)	\
+__PMC_EV_ALIAS("EST_Trans",		IAP_EVENT_3AH)		\
+__PMC_EV_ALIAS("FP_Assist",		IAP_EVENT_11H_00H)	\
+__PMC_EV_ALIAS("FP_Comp_Instr_Ret",	IAP_EVENT_C1H_00H)	\
+__PMC_EV_ALIAS("FP_Comps_Op_Exe",	IAP_EVENT_10H_00H)	\
+__PMC_EV_ALIAS("FP_MMX_Trans",		IAP_EVENT_CCH_01H)	\
+__PMC_EV_ALIAS("Fused_Ld_Uops_Ret",	IAP_EVENT_DAH_01H)	\
+__PMC_EV_ALIAS("Fused_St_Uops_Ret",	IAP_EVENT_DAH_02H)	\
+__PMC_EV_ALIAS("Fused_Uops_Ret",	IAP_EVENT_DAH_00H)	\
+__PMC_EV_ALIAS("HW_Int_Rx",		IAP_EVENT_C8H_00H)	\
+__PMC_EV_ALIAS("ICache_Misses",		IAP_EVENT_81H_00H)	\
+__PMC_EV_ALIAS("ICache_Reads",		IAP_EVENT_80H_00H)	\
+__PMC_EV_ALIAS("IFU_Mem_Stall",		IAP_EVENT_86H_00H)	\
+__PMC_EV_ALIAS("ILD_Stall",		IAP_EVENT_87H_00H)	\
+__PMC_EV_ALIAS("ITLB_Misses",		IAP_EVENT_85H_00H)	\
+__PMC_EV_ALIAS("Instr_Decoded",		IAP_EVENT_D0H_00H)	\
+__PMC_EV_ALIAS("Instr_Ret",		IAP_EVENT_C0H_00H)	\
+__PMC_EV_ALIAS("L1_Pref_Req",		IAP_EVENT_4FH_00H)	\
+__PMC_EV_ALIAS("L2_ADS",		IAP_EVENT_21H)		\
+__PMC_EV_ALIAS("L2_IFetch",		IAP_EVENT_28H)		\
+__PMC_EV_ALIAS("L2_LD",			IAP_EVENT_29H)		\
+__PMC_EV_ALIAS("L2_Lines_In",		IAP_EVENT_24H)		\
+__PMC_EV_ALIAS("L2_Lines_Out",		IAP_EVENT_26H)		\
+__PMC_EV_ALIAS("L2_M_Lines_In",		IAP_EVENT_25H)		\
+__PMC_EV_ALIAS("L2_M_Lines_Out",	IAP_EVENT_27H)		\
+__PMC_EV_ALIAS("L2_No_Request_Cycles",	IAP_EVENT_32H)		\
+__PMC_EV_ALIAS("L2_Reject_Cycles",	IAP_EVENT_30H)		\
+__PMC_EV_ALIAS("L2_Rqsts",		IAP_EVENT_2EH)		\
+__PMC_EV_ALIAS("L2_ST",			IAP_EVENT_2AH)		\
+__PMC_EV_ALIAS("LD_Blocks",		IAP_EVENT_03H_00H)	\
+__PMC_EV_ALIAS("LLC_Misses",		IAP_EVENT_2EH_41H)	\
+__PMC_EV_ALIAS("LLC_Reference",		IAP_EVENT_2EH_4FH)	\
+__PMC_EV_ALIAS("MMX_Assist",		IAP_EVENT_CDH_00H)	\
+__PMC_EV_ALIAS("MMX_FP_Trans",		IAP_EVENT_CCH_00H)	\
+__PMC_EV_ALIAS("MMX_Instr_Exec",	IAP_EVENT_B0H_00H)	\
+__PMC_EV_ALIAS("MMX_Instr_Ret",		IAP_EVENT_CEH_00H)	\
+__PMC_EV_ALIAS("Misalign_Mem_Ref",	IAP_EVENT_05H_00H)	\
+__PMC_EV_ALIAS("Mul",			IAP_EVENT_12H_00H)	\
+__PMC_EV_ALIAS("NonHlt_Ref_Cycles",	IAP_EVENT_3CH_01H)	\
+__PMC_EV_ALIAS("Pref_Rqsts_Dn",		IAP_EVENT_F8H_00H)	\
+__PMC_EV_ALIAS("Pref_Rqsts_Up",		IAP_EVENT_F0H_00H)	\
+__PMC_EV_ALIAS("Resource_Stall",	IAP_EVENT_A2H_00H)	\
+__PMC_EV_ALIAS("SD_Drains",		IAP_EVENT_04H_00H)	\
+__PMC_EV_ALIAS("SIMD_FP_DP_P_Comp_Ret",	IAP_EVENT_D9H_02H)	\
+__PMC_EV_ALIAS("SIMD_FP_DP_P_Ret",	IAP_EVENT_D8H_02H)	\
+__PMC_EV_ALIAS("SIMD_FP_DP_S_Comp_Ret",	IAP_EVENT_D9H_03H)	\
+__PMC_EV_ALIAS("SIMD_FP_DP_S_Ret",	IAP_EVENT_D8H_03H)	\
+__PMC_EV_ALIAS("SIMD_FP_SP_P_Comp_Ret",	IAP_EVENT_D9H_00H)	\
+__PMC_EV_ALIAS("SIMD_FP_SP_Ret",	IAP_EVENT_D8H_00H)	\
+__PMC_EV_ALIAS("SIMD_FP_SP_S_Comp_Ret",	IAP_EVENT_D9H_01H)	\
+__PMC_EV_ALIAS("SIMD_FP_SP_S_Ret",	IAP_EVENT_D8H_01H)	\
+__PMC_EV_ALIAS("SIMD_Int_128_Ret",	IAP_EVENT_D8H_04H)	\
+__PMC_EV_ALIAS("SIMD_Int_Pari_Exec",	IAP_EVENT_B3H_20H)	\
+__PMC_EV_ALIAS("SIMD_Int_Pck_Exec",	IAP_EVENT_B3H_04H)	\
+__PMC_EV_ALIAS("SIMD_Int_Plog_Exec",	IAP_EVENT_B3H_10H)	\
+__PMC_EV_ALIAS("SIMD_Int_Pmul_Exec",	IAP_EVENT_B3H_01H)	\
+__PMC_EV_ALIAS("SIMD_Int_Psft_Exec",	IAP_EVENT_B3H_02H)	\
+__PMC_EV_ALIAS("SIMD_Int_Sat_Exec",	IAP_EVENT_B1H_00H)	\
+__PMC_EV_ALIAS("SIMD_Int_Upck_Exec",	IAP_EVENT_B3H_08H)	\
+__PMC_EV_ALIAS("SMC_Detected",		IAP_EVENT_C3H_00H)	\
+__PMC_EV_ALIAS("SSE_NTStores_Miss",	IAP_EVENT_4BH_03H)	\
+__PMC_EV_ALIAS("SSE_NTStores_Ret",	IAP_EVENT_07H_03H)	\
+__PMC_EV_ALIAS("SSE_PrefNta_Miss",	IAP_EVENT_4BH_00H)	\
+__PMC_EV_ALIAS("SSE_PrefNta_Ret",	IAP_EVENT_07H_00H)	\
+__PMC_EV_ALIAS("SSE_PrefT1_Miss",	IAP_EVENT_4BH_01H)	\
+__PMC_EV_ALIAS("SSE_PrefT1_Ret",	IAP_EVENT_07H_01H)	\
+__PMC_EV_ALIAS("SSE_PrefT2_Miss",	IAP_EVENT_4BH_02H)	\
+__PMC_EV_ALIAS("SSE_PrefT2_Ret",	IAP_EVENT_07H_02H)	\
+__PMC_EV_ALIAS("Seg_Reg_Loads",		IAP_EVENT_06H_00H)	\
+__PMC_EV_ALIAS("Serial_Execution_Cycles", IAP_EVENT_3CH_02H)	\
+__PMC_EV_ALIAS("Thermal_Trip",		IAP_EVENT_3BH_C0H)	\
+__PMC_EV_ALIAS("Unfusion",		IAP_EVENT_DBH_00H)	\
+__PMC_EV_ALIAS("Unhalted_Core_Cycles",	IAP_EVENT_3CH_00H)	\
+__PMC_EV_ALIAS("Uops_Ret",		IAP_EVENT_C2H_00H)
+
+/*
+ * Aliases for Core2 PMC events.
+ */
+#define	__PMC_EV_ALIAS_CORE2()						\
+__PMC_EV_ALIAS_INTEL_ARCHITECTURAL()					\
+__PMC_EV_ALIAS("BACLEARS",		IAP_EVENT_E6H_00H)		\
+__PMC_EV_ALIAS("BOGUS_BR",		IAP_EVENT_E4H_00H)		\
+__PMC_EV_ALIAS("BR_BAC_MISSP_EXEC",	IAP_EVENT_8AH_00H)		\
+__PMC_EV_ALIAS("BR_CALL_EXEC",		IAP_EVENT_92H_00H)		\
+__PMC_EV_ALIAS("BR_CALL_MISSP_EXEC",	IAP_EVENT_93H_00H)		\
+__PMC_EV_ALIAS("BR_CND_EXEC",		IAP_EVENT_8BH_00H)		\
+__PMC_EV_ALIAS("BR_CND_MISSP_EXEC",	IAP_EVENT_8CH_00H)		\
+__PMC_EV_ALIAS("BR_IND_CALL_EXEC",	IAP_EVENT_94H_00H)		\
+__PMC_EV_ALIAS("BR_IND_EXEC",		IAP_EVENT_8DH_00H)		\
+__PMC_EV_ALIAS("BR_IND_MISSP_EXEC",	IAP_EVENT_8EH_00H)		\
+__PMC_EV_ALIAS("BR_INST_DECODED",	IAP_EVENT_E0H_00H)		\
+__PMC_EV_ALIAS("BR_INST_EXEC",		IAP_EVENT_88H_00H)		\
+__PMC_EV_ALIAS("BR_INST_RETIRED.ANY",	IAP_EVENT_C4H_00H)		\
+__PMC_EV_ALIAS("BR_INST_RETIRED.MISPRED", IAP_EVENT_C5H_00H)		\
+__PMC_EV_ALIAS("BR_INST_RETIRED.MISPRED_NOT_TAKEN",			\
+    IAP_EVENT_C4H_02H)							\
+__PMC_EV_ALIAS("BR_INST_RETIRED.MISPRED_TAKEN",				\
+    IAP_EVENT_C4H_08H)							\
+__PMC_EV_ALIAS("BR_INST_RETIRED.PRED_NOT_TAKEN",			\
+    IAP_EVENT_C4H_01H)							\
+__PMC_EV_ALIAS("BR_INST_RETIRED.PRED_TAKEN",				\
+    IAP_EVENT_C4H_04H)							\
+__PMC_EV_ALIAS("BR_INST_RETIRED.TAKEN",	IAP_EVENT_C4H_0CH)		\
+__PMC_EV_ALIAS("BR_MISSP_EXEC",		IAP_EVENT_89H_00H)		\
+__PMC_EV_ALIAS("BR_RET_BAC_MISSP_EXEC",	IAP_EVENT_91H_00H)		\
+__PMC_EV_ALIAS("BR_RET_EXEC",		IAP_EVENT_8FH_00H)		\
+__PMC_EV_ALIAS("BR_RET_MISSP_EXEC",	IAP_EVENT_90H_00H)		\
+__PMC_EV_ALIAS("BR_TKN_BUBBLE_1",	IAP_EVENT_97H_00H)		\
+__PMC_EV_ALIAS("BR_TKN_BUBBLE_2",	IAP_EVENT_98H_00H)		\
+__PMC_EV_ALIAS("BUSQ_EMPTY",		IAP_EVENT_7DH)			\
+__PMC_EV_ALIAS("BUS_BNR_DRV",		IAP_EVENT_61H)			\
+__PMC_EV_ALIAS("BUS_DATA_RCV",		IAP_EVENT_64H)			\
+__PMC_EV_ALIAS("BUS_DRDY_CLOCKS",	IAP_EVENT_62H)			\
+__PMC_EV_ALIAS("BUS_HITM_DRV",		IAP_EVENT_7BH)			\
+__PMC_EV_ALIAS("BUS_HIT_DRV",		IAP_EVENT_7AH)			\
+__PMC_EV_ALIAS("BUS_IO_WAIT",		IAP_EVENT_7FH)			\
+__PMC_EV_ALIAS("BUS_LOCK_CLOCKS",	IAP_EVENT_63H)			\
+__PMC_EV_ALIAS("BUS_REQUEST_OUTSTANDING",				\
+    IAP_EVENT_60H)							\
+__PMC_EV_ALIAS("BUS_TRANS_ANY",		IAP_EVENT_70H)			\
+__PMC_EV_ALIAS("BUS_TRANS_BRD",		IAP_EVENT_65H)			\
+__PMC_EV_ALIAS("BUS_TRANS_BURST",	IAP_EVENT_6EH)			\
+__PMC_EV_ALIAS("BUS_TRANS_DEF",		IAP_EVENT_6DH)			\
+__PMC_EV_ALIAS("BUS_TRANS_IFETCH",	IAP_EVENT_68H)			\
+__PMC_EV_ALIAS("BUS_TRANS_INVAL",	IAP_EVENT_69H)			\
+__PMC_EV_ALIAS("BUS_TRANS_IO",		IAP_EVENT_6CH)			\
+__PMC_EV_ALIAS("BUS_TRANS_MEM",		IAP_EVENT_6FH)			\
+__PMC_EV_ALIAS("BUS_TRANS_P",		IAP_EVENT_6BH)			\
+__PMC_EV_ALIAS("BUS_TRANS_PWR",		IAP_EVENT_6AH)			\
+__PMC_EV_ALIAS("BUS_TRANS_RFO",		IAP_EVENT_66H)			\
+__PMC_EV_ALIAS("BUS_TRANS_WB",		IAP_EVENT_67H)			\
+__PMC_EV_ALIAS("CMP_SNOOP",		IAP_EVENT_78H)			\
+__PMC_EV_ALIAS("CPU_CLK_UNHALTED.BUS",	IAP_EVENT_3CH_01H)		\
+__PMC_EV_ALIAS("CPU_CLK_UNHALTED.CORE_P",				\
+    IAP_EVENT_3CH_00H)							\
+__PMC_EV_ALIAS("CPU_CLK_UNHALTED.NO_OTHER",				\
+    IAP_EVENT_3CH_02H)							\
+__PMC_EV_ALIAS("CYCLES_DIV_BUSY",	IAP_EVENT_14H_00H)		\
+__PMC_EV_ALIAS("CYCLES_INT_MASKED",	IAP_EVENT_C6H_01H)		\
+__PMC_EV_ALIAS("CYCLES_INT_PENDING_AND_MASKED",				\
+    IAP_EVENT_C6H_02H)							\
+__PMC_EV_ALIAS("CYCLES_L1I_MEM_STALLED", IAP_EVENT_86H_00H)		\
+__PMC_EV_ALIAS("DELAYED_BYPASS.FP",	IAP_EVENT_19H_00H)		\
+__PMC_EV_ALIAS("DELAYED_BYPASS.LOAD",	IAP_EVENT_19H_01H)		\
+__PMC_EV_ALIAS("DELAYED_BYPASS.SIMD",	IAP_EVENT_19H_02H)		\
+__PMC_EV_ALIAS("DIV",			IAP_EVENT_13H_00H)		\
+__PMC_EV_ALIAS("DTLB_MISSES.ANY",	IAP_EVENT_08H_01H)		\
+__PMC_EV_ALIAS("DTLB_MISSES.L0_MISS_LD", IAP_EVENT_08H_04H)		\
+__PMC_EV_ALIAS("DTLB_MISSES.MISS_LD",	IAP_EVENT_08H_02H)		\
+__PMC_EV_ALIAS("DTLB_MISSES.MISS_ST",	IAP_EVENT_08H_08H)		\
+__PMC_EV_ALIAS("EIST_TRANS",		IAP_EVENT_3AH_00H)		\
+__PMC_EV_ALIAS("ESP.ADDITIONS",		IAP_EVENT_ABH_02H)		\
+__PMC_EV_ALIAS("ESP.SYNCH",		IAP_EVENT_ABH_01H)		\
+__PMC_EV_ALIAS("EXT_SNOOP",		IAP_EVENT_77H)			\
+__PMC_EV_ALIAS("FP_ASSIST",		IAP_EVENT_11H_00H)		\
+__PMC_EV_ALIAS("FP_COMP_OPS_EXE",	IAP_EVENT_10H_00H)		\
+__PMC_EV_ALIAS("FP_MMX_TRANS_TO_FP",	IAP_EVENT_CCH_02H)		\
+__PMC_EV_ALIAS("FP_MMX_TRANS_TO_MMX",	IAP_EVENT_CCH_01H)		\
+__PMC_EV_ALIAS("HW_INT_RCV",		IAP_EVENT_C8H_00H)		\
+__PMC_EV_ALIAS("IDLE_DURING_DIV",	IAP_EVENT_18H_00H)		\
+__PMC_EV_ALIAS("ILD_STALL",		IAP_EVENT_87H_00H)		\
+__PMC_EV_ALIAS("INST_QUEUE.FULL",	IAP_EVENT_83H_02H)		\
+__PMC_EV_ALIAS("INST_RETIRED.ANY_P",	IAP_EVENT_C0H_00H)		\
+__PMC_EV_ALIAS("INST_RETIRED.LOADS",	IAP_EVENT_C0H_01H)		\
+__PMC_EV_ALIAS("INST_RETIRED.OTHER",	IAP_EVENT_C0H_04H)		\
+__PMC_EV_ALIAS("INST_RETIRED.STORES",	IAP_EVENT_C0H_02H)		\
+__PMC_EV_ALIAS("INST_RETIRED.VM_H",	IAP_EVENT_C0H_08H)		\
+__PMC_EV_ALIAS("ITLB.FLUSH",		IAP_EVENT_82H_40H)		\
+__PMC_EV_ALIAS("ITLB.LARGE_MISS",	IAP_EVENT_82H_10H)		\
+__PMC_EV_ALIAS("ITLB.MISSES",		IAP_EVENT_82H_12H)		\
+__PMC_EV_ALIAS("ITLB.SMALL_MISS",	IAP_EVENT_82H_02H)		\
+__PMC_EV_ALIAS("ITLB_MISS_RETIRED",	IAP_EVENT_C9H_00H)		\
+__PMC_EV_ALIAS("L1D_ALL_CACHE_REF",	IAP_EVENT_43H_02H)		\
+__PMC_EV_ALIAS("L1D_ALL_REF",		IAP_EVENT_43H_01H)		\
+__PMC_EV_ALIAS("L1D_CACHE_LD",		IAP_EVENT_40H)			\
+__PMC_EV_ALIAS("L1D_CACHE_LOCK",	IAP_EVENT_42H)			\
+__PMC_EV_ALIAS("L1D_CACHE_LOCK_DURATION", IAP_EVENT_42H_10H)		\
+__PMC_EV_ALIAS("L1D_CACHE_ST",		IAP_EVENT_41H)			\
+__PMC_EV_ALIAS("L1D_M_EVICT",		IAP_EVENT_47H_00H)		\
+__PMC_EV_ALIAS("L1D_M_REPL",		IAP_EVENT_46H_00H)		\
+__PMC_EV_ALIAS("L1D_PEND_MISS",		IAP_EVENT_48H_00H)		\
+__PMC_EV_ALIAS("L1D_PREFETCH.REQUESTS",	IAP_EVENT_4EH_10H)		\
+__PMC_EV_ALIAS("L1D_REPL",		IAP_EVENT_45H_0FH)		\
+__PMC_EV_ALIAS("L1D_SPLIT.LOADS",	IAP_EVENT_49H_01H)		\
+__PMC_EV_ALIAS("L1D_SPLIT.STORES",	IAP_EVENT_49H_02H)		\
+__PMC_EV_ALIAS("L1I_MISSES",		IAP_EVENT_81H_00H)		\
+__PMC_EV_ALIAS("L1I_READS",		IAP_EVENT_80H_00H)		\
+__PMC_EV_ALIAS("L2_ADS",		IAP_EVENT_21H)			\
+__PMC_EV_ALIAS("L2_DBUS_BUSY_RD",	IAP_EVENT_23H)			\
+__PMC_EV_ALIAS("L2_IFETCH",		IAP_EVENT_28H)			\
+__PMC_EV_ALIAS("L2_LD",			IAP_EVENT_29H)			\
+__PMC_EV_ALIAS("L2_LINES_IN",		IAP_EVENT_24H)			\
+__PMC_EV_ALIAS("L2_LINES_OUT",		IAP_EVENT_26H)			\
+__PMC_EV_ALIAS("L2_LOCK",		IAP_EVENT_2BH)			\
+__PMC_EV_ALIAS("L2_M_LINES_IN",		IAP_EVENT_25H)			\
+__PMC_EV_ALIAS("L2_M_LINES_OUT",	IAP_EVENT_27H)			\
+__PMC_EV_ALIAS("L2_NO_REQ",		IAP_EVENT_32H)			\
+__PMC_EV_ALIAS("L2_REJECT_BUSQ",	IAP_EVENT_30H)			\
+__PMC_EV_ALIAS("L2_RQSTS",		IAP_EVENT_2EH)			\
+__PMC_EV_ALIAS("L2_RQSTS.SELF.DEMAND.I_STATE",				\
+    IAP_EVENT_2EH_41H)							\
+__PMC_EV_ALIAS("L2_RQSTS.SELF.DEMAND.MESI",				\
+    IAP_EVENT_2EH_4FH)							\
+__PMC_EV_ALIAS("L2_ST",			IAP_EVENT_2AH)			\
+__PMC_EV_ALIAS("LOAD_BLOCK.L1D",	IAP_EVENT_03H_20H)		\
+__PMC_EV_ALIAS("LOAD_BLOCK.OVERLAP_STORE",				\
+    IAP_EVENT_03H_08H)							\
+__PMC_EV_ALIAS("LOAD_BLOCK.STA",	IAP_EVENT_03H_02H)		\
+__PMC_EV_ALIAS("LOAD_BLOCK.STD",	IAP_EVENT_03H_04H)		\
+__PMC_EV_ALIAS("LOAD_BLOCK.UNTIL_RETIRE", IAP_EVENT_03H_10H)		\
+__PMC_EV_ALIAS("LOAD_HIT_PRE",		IAP_EVENT_4CH_00H)		\
+__PMC_EV_ALIAS("MACHINE_NUKES.MEM_ORDER", IAP_EVENT_C3H_04H)		\
+__PMC_EV_ALIAS("MACHINE_NUKES.SMC",	IAP_EVENT_C3H_01H)		\
+__PMC_EV_ALIAS("MACRO_INSTS.CISC_DECODED", IAP_EVENT_AAH_08H)		\
+__PMC_EV_ALIAS("MACRO_INSTS.DECODED",	IAP_EVENT_AAH_01H)		\
+__PMC_EV_ALIAS("MEMORY_DISAMBIGUATION.RESET",				\
+    IAP_EVENT_09H_01H)							\
+__PMC_EV_ALIAS("MEMORY_DISAMBIGUATION.SUCCESS",				\
+    IAP_EVENT_09H_02H)							\
+__PMC_EV_ALIAS("MEM_LOAD_RETIRED.DTLB_MISS",				\
+    IAP_EVENT_CBH_10H)							\
+__PMC_EV_ALIAS("MEM_LOAD_RETIRED.L1D_LINE_MISS",			\
+    IAP_EVENT_CBH_02H)							\
+__PMC_EV_ALIAS("MEM_LOAD_RETIRED.L1D_MISS",				\
+    IAP_EVENT_CBH_01H)							\
+__PMC_EV_ALIAS("MEM_LOAD_RETIRED.L2_LINE_MISS",				\
+    IAP_EVENT_CBH_08H)							\
+__PMC_EV_ALIAS("MEM_LOAD_RETIRED.L2_MISS",				\
+    IAP_EVENT_CBH_04H)							\
+__PMC_EV_ALIAS("MUL",			IAP_EVENT_12H_00H)		\
+__PMC_EV_ALIAS("PAGE_WALKS.COUNT",	IAP_EVENT_0CH_01H)		\
+__PMC_EV_ALIAS("PAGE_WALKS.CYCLES",	IAP_EVENT_0CH_02H)		\
+__PMC_EV_ALIAS("PREF_RQSTS_DN",		IAP_EVENT_F8H_00H)		\
+__PMC_EV_ALIAS("PREF_RQSTS_UP",		IAP_EVENT_F0H_00H)		\
+__PMC_EV_ALIAS("RAT_STALLS.ANY",	IAP_EVENT_D2H_0FH)		\
+__PMC_EV_ALIAS("RAT_STALLS.FLAGS",	IAP_EVENT_D2H_04H)		\
+__PMC_EV_ALIAS("RAT_STALLS.FPSW",	IAP_EVENT_D2H_08H)		\
+__PMC_EV_ALIAS("RAT_STALLS.OTHER_SERIALIZATION_STALLS",			\
+    IAP_EVENT_D2H_10H)							\
+__PMC_EV_ALIAS("RAT_STALLS.PARTIAL_CYCLES",				\
+    IAP_EVENT_D2H_02H)							\
+__PMC_EV_ALIAS("RAT_STALLS.ROB_READ_PORT",				\
+    IAP_EVENT_D2H_01H)							\
+__PMC_EV_ALIAS("RESOURCE_STALLS.ANY",	IAP_EVENT_DCH_1FH)		\
+__PMC_EV_ALIAS("RESOURCE_STALLS.BR_MISS_CLEAR",				\
+    IAP_EVENT_DCH_10H)							\
+__PMC_EV_ALIAS("RESOURCE_STALLS.FPCW",	IAP_EVENT_DCH_08H)		\
+__PMC_EV_ALIAS("RESOURCE_STALLS.LD_ST",	IAP_EVENT_DCH_04H)		\
+__PMC_EV_ALIAS("RESOURCE_STALLS.ROB_FULL",				\
+    IAP_EVENT_DCH_01H)							\
+__PMC_EV_ALIAS("RESOURCE_STALLS.RS_FULL", IAP_EVENT_DCH_02H)		\
+__PMC_EV_ALIAS("RS_UOPS_DISPATCHED",	IAP_EVENT_A0H_00H)		\
+__PMC_EV_ALIAS("RS_UOPS_DISPATCHED.PORT0", IAP_EVENT_A1H_01H)		\
+__PMC_EV_ALIAS("RS_UOPS_DISPATCHED.PORT1", IAP_EVENT_A1H_02H)		\
+__PMC_EV_ALIAS("RS_UOPS_DISPATCHED.PORT2", IAP_EVENT_A1H_04H)		\
+__PMC_EV_ALIAS("RS_UOPS_DISPATCHED.PORT3", IAP_EVENT_A1H_08H)		\
+__PMC_EV_ALIAS("RS_UOPS_DISPATCHED.PORT4", IAP_EVENT_A1H_10H)		\
+__PMC_EV_ALIAS("RS_UOPS_DISPATCHED.PORT5", IAP_EVENT_A1H_20H)		\
+__PMC_EV_ALIAS("SB_DRAIN_CYCLES",	IAP_EVENT_04H_01H)		\
+__PMC_EV_ALIAS("SEGMENT_REG_LOADS",	IAP_EVENT_06H_00H)		\
+__PMC_EV_ALIAS("SEG_REG_RENAMES.ANY",	IAP_EVENT_D5H_0FH)		\
+__PMC_EV_ALIAS("SEG_REG_RENAMES.DS",	IAP_EVENT_D5H_02H)		\
+__PMC_EV_ALIAS("SEG_REG_RENAMES.ES",	IAP_EVENT_D5H_01H)		\
+__PMC_EV_ALIAS("SEG_REG_RENAMES.FS",	IAP_EVENT_D5H_04H)		\
+__PMC_EV_ALIAS("SEG_REG_RENAMES.GS",	IAP_EVENT_D5H_08H)		\
+__PMC_EV_ALIAS("SEG_RENAME_STALLS.ANY",	IAP_EVENT_D4H_0FH)		\
+__PMC_EV_ALIAS("SEG_RENAME_STALLS.DS",	IAP_EVENT_D4H_02H)		\
+__PMC_EV_ALIAS("SEG_RENAME_STALLS.ES",	IAP_EVENT_D4H_01H)		\
+__PMC_EV_ALIAS("SEG_RENAME_STALLS.FS",	IAP_EVENT_D4H_04H)		\
+__PMC_EV_ALIAS("SEG_RENAME_STALLS.GS",	IAP_EVENT_D4H_08H)		\
+__PMC_EV_ALIAS("SIMD_ASSIST",		IAP_EVENT_CDH_00H)		\
+__PMC_EV_ALIAS("SIMD_COMP_INST_RETIRED.PACKED_DOUBLE",			\
+    IAP_EVENT_CAH_04H)							\
+__PMC_EV_ALIAS("SIMD_COMP_INST_RETIRED.PACKED_SINGLE",			\
+    IAP_EVENT_CAH_01H)							\
+__PMC_EV_ALIAS("SIMD_COMP_INST_RETIRED.SCALAR_DOUBLE",			\
+    IAP_EVENT_CAH_08H)							\
+__PMC_EV_ALIAS("SIMD_COMP_INST_RETIRED.SCALAR_SINGLE",			\
+    IAP_EVENT_CAH_02H)							\
+__PMC_EV_ALIAS("SIMD_INSTR_RETIRED",	IAP_EVENT_CEH_00H)		\
+__PMC_EV_ALIAS("SIMD_INST_RETIRED.ANY",	IAP_EVENT_C7H_1FH)		\
+__PMC_EV_ALIAS("SIMD_INST_RETIRED.PACKED_DOUBLE",			\
+    IAP_EVENT_C7H_04H)							\
+__PMC_EV_ALIAS("SIMD_INST_RETIRED.PACKED_SINGLE",			\
+    IAP_EVENT_C7H_01H)							\
+__PMC_EV_ALIAS("SIMD_INST_RETIRED.SCALAR_DOUBLE",			\
+    IAP_EVENT_C7H_08H)							\
+__PMC_EV_ALIAS("SIMD_INST_RETIRED.SCALAR_SINGLE",			\
+    IAP_EVENT_C7H_02H)							\
+__PMC_EV_ALIAS("SIMD_INST_RETIRED.VECTOR",	IAP_EVENT_C7H_10H)	\
+__PMC_EV_ALIAS("SIMD_SAT_INSTR_RETIRED",	IAP_EVENT_CFH_00H)	\
+__PMC_EV_ALIAS("SIMD_SAT_UOP_EXEC",		IAP_EVENT_B1H_00H)	\
+__PMC_EV_ALIAS("SIMD_UOPS_EXEC",		IAP_EVENT_B0H_00H)	\
+__PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.ARITHMETIC",	IAP_EVENT_B3H_20H)	\
+__PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.LOGICAL",	IAP_EVENT_B3H_10H)	\
+__PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.MUL",	IAP_EVENT_B3H_01H)	\
+__PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.PACK",	IAP_EVENT_B3H_04H)	\
+__PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.SHIFT",	IAP_EVENT_B3H_02H)	\
+__PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.UNPACK",	IAP_EVENT_B3H_08H)	\
+__PMC_EV_ALIAS("SNOOP_STALL_DRV",		IAP_EVENT_7EH)		\
+__PMC_EV_ALIAS("SSE_PRE_EXEC.L1",		IAP_EVENT_07H_01H)	\
+__PMC_EV_ALIAS("SSE_PRE_EXEC.L2",		IAP_EVENT_07H_02H)	\
+__PMC_EV_ALIAS("SSE_PRE_EXEC.NTA",		IAP_EVENT_07H_00H)	\
+__PMC_EV_ALIAS("SSE_PRE_EXEC.STORES",		IAP_EVENT_07H_03H)	\
+__PMC_EV_ALIAS("SSE_PRE_MISS.L1",		IAP_EVENT_4BH_01H)	\
+__PMC_EV_ALIAS("SSE_PRE_MISS.L2",		IAP_EVENT_4BH_02H)	\
+__PMC_EV_ALIAS("SSE_PRE_MISS.NTA",		IAP_EVENT_4BH_00H)	\
+__PMC_EV_ALIAS("STORE_BLOCK.ORDER",		IAP_EVENT_04H_02H)	\
+__PMC_EV_ALIAS("STORE_BLOCK.SNOOP",		IAP_EVENT_04H_08H)	\
+__PMC_EV_ALIAS("THERMAL_TRIP",			IAP_EVENT_3BH_C0H)	\
+__PMC_EV_ALIAS("UOPS_RETIRED.ANY",		IAP_EVENT_C2H_0FH)	\
+__PMC_EV_ALIAS("UOPS_RETIRED.FUSED",		IAP_EVENT_C2H_07H)	\
+__PMC_EV_ALIAS("UOPS_RETIRED.LD_IND_BR",	IAP_EVENT_C2H_01H)	\
+__PMC_EV_ALIAS("UOPS_RETIRED.MACRO_FUSION",	IAP_EVENT_C2H_04H)	\
+__PMC_EV_ALIAS("UOPS_RETIRED.NON_FUSED",	IAP_EVENT_C2H_08H)	\
+__PMC_EV_ALIAS("UOPS_RETIRED.STD_STA",		IAP_EVENT_C2H_02H)	\
+__PMC_EV_ALIAS("X87_OPS_RETIRED.ANY",		IAP_EVENT_C1H_FEH)	\
+__PMC_EV_ALIAS("X87_OPS_RETIRED.FXCH",		IAP_EVENT_C1H_01H)
+
+/*
+ * Core i7 and Xeon 5500 events removed between 253669-031US June 2009
+ * and 253669-033US December 2009.
+ */
+#define	__PMC_EV_ALIAS_COREI7_OLD()					\
+__PMC_EV_ALIAS("SB_FORWARD.ANY", IAP_EVENT_02H_01H)			\
+__PMC_EV_ALIAS("LOAD_BLOCK.STD", IAP_EVENT_03H_01H)			\
+__PMC_EV_ALIAS("LOAD_BLOCK.ADDRESS_OFFSET", IAP_EVENT_03H_04H)		\
+__PMC_EV_ALIAS("SB_DRAIN.CYCLES", IAP_EVENT_04H_01H)			\
+__PMC_EV_ALIAS("MISALIGN_MEM_REF.LOAD", IAP_EVENT_05H_01H)		\
+__PMC_EV_ALIAS("MISALIGN_MEM_REF.STORE", IAP_EVENT_05H_02H)		\
+__PMC_EV_ALIAS("MISALIGN_MEM_REF.ANY", IAP_EVENT_05H_03H)		\
+__PMC_EV_ALIAS("STORE_BLOCKS.NOT_STA", IAP_EVENT_06H_01H)		\
+__PMC_EV_ALIAS("STORE_BLOCKS.STA", IAP_EVENT_06H_02H)			\
+__PMC_EV_ALIAS("STORE_BLOCKS.ANY", IAP_EVENT_06H_0FH)			\
+__PMC_EV_ALIAS("MEMORY_DISAMBIGURATION.RESET", IAP_EVENT_09H_01H)	\
+__PMC_EV_ALIAS("MEMORY_DISAMBIGURATION.SUCCESS", IAP_EVENT_09H_02H)	\
+__PMC_EV_ALIAS("MEMORY_DISAMBIGURATION.WATCHDOG", IAP_EVENT_09H_04H)	\
+__PMC_EV_ALIAS("MEMORY_DISAMBIGURATION.WATCH_CYCLES", IAP_EVENT_09H_08H)\
+__PMC_EV_ALIAS("HW_INT.RCV", IAP_EVENT_1DH_01H)				\
+__PMC_EV_ALIAS("HW_INT.CYCLES_MASKED", IAP_EVENT_1DH_02H)		\
+__PMC_EV_ALIAS("HW_INT.CYCLES_PENDING_AND_MASKED", IAP_EVENT_1DH_04H)	\
+__PMC_EV_ALIAS("L2_WRITE.RFO.E_STATE", IAP_EVENT_27H_04H)		\
+__PMC_EV_ALIAS("UOPS_DECODED.DEC0", IAP_EVENT_3DH_01H)			\
+__PMC_EV_ALIAS("L1D_CACHE_ST.I_STATE", IAP_EVENT_41H_01H)		\
+__PMC_EV_ALIAS("L1D_CACHE_ST.MESI", IAP_EVENT_41H_0FH)			\
+__PMC_EV_ALIAS("DTLB_MISSES.PDE_MISS", IAP_EVENT_49H_20H)		\
+__PMC_EV_ALIAS("DTLB_MISSES.PDP_MISS", IAP_EVENT_49H_40H)		\
+__PMC_EV_ALIAS("DTLB_MISSES.LARGE_WALK_COMPLETED", IAP_EVENT_49H_80H)	\
+__PMC_EV_ALIAS("SSE_MEM_EXEC.NTA", IAP_EVENT_4BH_01H)			\
+__PMC_EV_ALIAS("SSE_MEM_EXEC.STREAMING_STORES", IAP_EVENT_4BH_08H)	\
+__PMC_EV_ALIAS("SFENCE_CYCLES", IAP_EVENT_4DH_01H)			\
+__PMC_EV_ALIAS("EPT.EPDE_MISS", IAP_EVENT_4FH_02H)			\
+__PMC_EV_ALIAS("EPT.EPDPE_HIT", IAP_EVENT_4FH_04H)			\
+__PMC_EV_ALIAS("EPT.EPDPE_MISS", IAP_EVENT_4FH_08H)			\
+__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA",		\
+    IAP_EVENT_60H_01H)							\
+__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE",		\
+    IAP_EVENT_60H_02H)							\
+__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO",		\
+    IAP_EVENT_60H_04H)							\
+__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.ANY.READ",			\
+    IAP_EVENT_60H_08H)							\
+__PMC_EV_ALIAS("IFU_IVC.FULL", IAP_EVENT_81H_01H)			\
+__PMC_EV_ALIAS("IFU_IVC.L1I_EVICTION", IAP_EVENT_81H_02H)		\
+__PMC_EV_ALIAS("L1I_OPPORTUNISTIC_HITS", IAP_EVENT_83H_01H)		\
+__PMC_EV_ALIAS("ITLB_MISSES.WALK_CYCLES", IAP_EVENT_85H_04H)		\
+__PMC_EV_ALIAS("ITLB_MISSES.PMH_BUSY_CYCLES", IAP_EVENT_85H_04H)	\
+__PMC_EV_ALIAS("ITLB_MISSES.STLB_HIT", IAP_EVENT_85H_10H)		\
+__PMC_EV_ALIAS("ITLB_MISSES.PDE_MISS", IAP_EVENT_85H_20H)		\
+__PMC_EV_ALIAS("ITLB_MISSES.PDP_MISS", IAP_EVENT_85H_40H)		\
+__PMC_EV_ALIAS("ITLB_MISSES.LARGE_WALK_COMPLETED", IAP_EVENT_85H_80H)	\
+__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND.READ_DATA", IAP_EVENT_B0H_01H)	\
+__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND.READ_CODE", IAP_EVENT_B0H_02H)	\
+__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND.RFO", IAP_EVENT_B0H_04H)	\
+__PMC_EV_ALIAS("OFFCORE_REQUESTS.ANY.READ", IAP_EVENT_B0H_08H)		\
+__PMC_EV_ALIAS("OFFCORE_REQUESTS.ANY.RFO", IAP_EVENT_B0H_10H)		\
+__PMC_EV_ALIAS("OFFCORE_REQUESTS.UNCACHED_MEM", IAP_EVENT_B0H_20H)	\
+__PMC_EV_ALIAS("OFFCORE_REQUESTS.ANY", IAP_EVENT_B0H_80H)		\
+__PMC_EV_ALIAS("SNOOPQ_REQUESTS_OUTSTANDING.DATA", IAP_EVENT_B3H_01H)	\
+__PMC_EV_ALIAS("SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE",		\
+    IAP_EVENT_B3H_02H)							\
+__PMC_EV_ALIAS("SNOOPQ_REQUESTS_OUTSTANDING.CODE", IAP_EVENT_B3H_04H)	\
+__PMC_EV_ALIAS("PIC_ACCESSES.TPR_READS", IAP_EVENT_BAH_01H)		\
+__PMC_EV_ALIAS("PIC_ACCESSES.TPR_WRITES", IAP_EVENT_BAH_02H)		\
+__PMC_EV_ALIAS("MACHINE_CLEARS.FUSION_ASSIST", IAP_EVENT_C3H_10H)	\
+__PMC_EV_ALIAS("BOGUS_BR", IAP_EVENT_E4H_01H)				\
+__PMC_EV_ALIAS("L2_HW_PREFETCH.HIT", IAP_EVENT_F3H_01H)			\
+__PMC_EV_ALIAS("L2_HW_PREFETCH.ALLOC", IAP_EVENT_F3H_02H)		\
+__PMC_EV_ALIAS("L2_HW_PREFETCH.DATA_TRIGGER", IAP_EVENT_F3H_04H)	\
+__PMC_EV_ALIAS("L2_HW_PREFETCH.CODE_TRIGGER", IAP_EVENT_F3H_08H)	\
+__PMC_EV_ALIAS("L2_HW_PREFETCH.DCA_TRIGGER", IAP_EVENT_F3H_10H)		\
+__PMC_EV_ALIAS("L2_HW_PREFETCH.KICK_START", IAP_EVENT_F3H_20H)		\
+__PMC_EV_ALIAS("SQ_MISC.PROMOTION", IAP_EVENT_F4H_01H)			\
+__PMC_EV_ALIAS("SQ_MISC.PROMOTION_POST_GO", IAP_EVENT_F4H_02H)		\
+__PMC_EV_ALIAS("SQ_MISC.LRU_HINTS", IAP_EVENT_F4H_04H)			\
+__PMC_EV_ALIAS("SQ_MISC.FILL_DROPPED", IAP_EVENT_F4H_08H)		\
+__PMC_EV_ALIAS("SEGMENT_REG_LOADS", IAP_EVENT_F8H_01H)
+
+/*
+ * Aliases for Core i7 and Xeon 5500 PMC events (253669-033US December 2009)
+ */
+#define	__PMC_EV_ALIAS_COREI7()						\
+__PMC_EV_ALIAS_INTEL_ARCHITECTURAL()					\
+__PMC_EV_ALIAS("SB_DRAIN.ANY", 	IAP_EVENT_04H_07H)			\
+__PMC_EV_ALIAS("STORE_BLOCKS.AT_RET", IAP_EVENT_06H_04H)		\
+__PMC_EV_ALIAS("STORE_BLOCKS.L1D_BLOCK", IAP_EVENT_06H_08H)		\
+__PMC_EV_ALIAS("PARTIAL_ADDRESS_ALIAS", IAP_EVENT_07H_01H)		\
+__PMC_EV_ALIAS("DTLB_LOAD_MISSES.ANY", IAP_EVENT_08H_01H)		\
+__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_COMPLETED", IAP_EVENT_08H_02H)	\
+__PMC_EV_ALIAS("DTLB_LOAD_MISSES.STLB_HIT", IAP_EVENT_08H_10H)		\
+__PMC_EV_ALIAS("DTLB_LOAD_MISSES.PDE_MISS", IAP_EVENT_08H_20H)		\
+__PMC_EV_ALIAS("DTLB_LOAD_MISSES.PDP_MISS", IAP_EVENT_08H_40H)		\
+__PMC_EV_ALIAS("DTLB_LOAD_MISSES.LARGE_WALK_COMPLETED",			\
+    IAP_EVENT_08H_80H) 							\
+__PMC_EV_ALIAS("MEM_INST_RETIRED.LOADS", IAP_EVENT_0BH_01H)		\
+__PMC_EV_ALIAS("MEM_INST_RETIRED.STORES", IAP_EVENT_0BH_02H)		\
+__PMC_EV_ALIAS("MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD",		\
+    IAP_EVENT_0BH_10H) 							\
+__PMC_EV_ALIAS("MEM_STORE_RETIRED.DTLB_MISS", IAP_EVENT_0CH_01H)	\
+__PMC_EV_ALIAS("UOPS_ISSUED.ANY", IAP_EVENT_0EH_01H)			\
+__PMC_EV_ALIAS("UOPS_ISSUED.STALLED_CYCLES", IAP_EVENT_0EH_01H)		\
+__PMC_EV_ALIAS("UOPS_ISSUED.FUSED", IAP_EVENT_0EH_02H)			\
+__PMC_EV_ALIAS("MEM_UNCORE_RETIRED.L3_DATA_MISS_UNKNOWN",		\
+    IAP_EVENT_0FH_01H)							\
+__PMC_EV_ALIAS("MEM_UNCORE_RETIRED.OTHER_CORE_L2_HITM",			\
+    IAP_EVENT_0FH_02H)							\
+__PMC_EV_ALIAS("MEM_UNCORE_RETIRED.REMOTE_CACHE_LOCAL_HOME_HIT",	\
+    IAP_EVENT_0FH_08H)							\
+__PMC_EV_ALIAS("MEM_UNCORE_RETIRED.REMOTE_DRAM",			\
+    IAP_EVENT_0FH_10H)							\
+__PMC_EV_ALIAS("MEM_UNCORE_RETIRED.LOCAL_DRAM", IAP_EVENT_0FH_20H)	\
+__PMC_EV_ALIAS("MEM_UNCORE_RETIRED.UNCACHEABLE", IAP_EVENT_0FH_80H)	\
+__PMC_EV_ALIAS("FP_COMP_OPS_EXE.X87", IAP_EVENT_10H_01H)		\
+__PMC_EV_ALIAS("FP_COMP_OPS_EXE.MMX", IAP_EVENT_10H_02H)		\
+__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_FP", IAP_EVENT_10H_04H)		\
+__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE2_INTEGER", IAP_EVENT_10H_08H)	\
+__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_FP_PACKED", IAP_EVENT_10H_10H)	\
+__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_FP_SCALAR", IAP_EVENT_10H_20H)	\
+__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION",			\
+    IAP_EVENT_10H_40H)							\
+__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION",			\
+    IAP_EVENT_10H_80H)							\
+__PMC_EV_ALIAS("SIMD_INT_128.PACKED_MPY", IAP_EVENT_12H_01H)		\
+__PMC_EV_ALIAS("SIMD_INT_128.PACKED_SHIFT", IAP_EVENT_12H_02H)		\
+__PMC_EV_ALIAS("SIMD_INT_128.PACK", IAP_EVENT_12H_04H)			\
+__PMC_EV_ALIAS("SIMD_INT_128.UNPACK", IAP_EVENT_12H_08H)		\
+__PMC_EV_ALIAS("SIMD_INT_128.PACKED_LOGICAL", IAP_EVENT_12H_10H)	\
+__PMC_EV_ALIAS("SIMD_INT_128.PACKED_ARITH", IAP_EVENT_12H_20H)		\
+__PMC_EV_ALIAS("SIMD_INT_128.SHUFFLE_MOVE", IAP_EVENT_12H_40H)		\
+__PMC_EV_ALIAS("LOAD_DISPATCH.RS", IAP_EVENT_13H_01H)			\
+__PMC_EV_ALIAS("LOAD_DISPATCH.RS_DELAYED", IAP_EVENT_13H_02H)		\
+__PMC_EV_ALIAS("LOAD_DISPATCH.MOB", IAP_EVENT_13H_04H)			\
+__PMC_EV_ALIAS("LOAD_DISPATCH.ANY", IAP_EVENT_13H_07H)			\
+__PMC_EV_ALIAS("ARITH.CYCLES_DIV_BUSY", IAP_EVENT_14H_01H)		\
+__PMC_EV_ALIAS("ARITH.MUL", IAP_EVENT_14H_02H)				\
+__PMC_EV_ALIAS("INST_QUEUE_WRITES", IAP_EVENT_17H_01H)			\
+__PMC_EV_ALIAS("INST_DECODED.DEC0", IAP_EVENT_18H_01H)			\
+__PMC_EV_ALIAS("TWO_UOP_INSTS_DECODED", IAP_EVENT_19H_01H)		\
+__PMC_EV_ALIAS("INST_QUEUE_WRITE_CYCLES", IAP_EVENT_1EH_01H)		\
+__PMC_EV_ALIAS("LSD_OVERFLOW", IAP_EVENT_20H_01H)			\
+__PMC_EV_ALIAS("L2_RQSTS.LD_HIT", IAP_EVENT_24H_01H)			\
+__PMC_EV_ALIAS("L2_RQSTS.LD_MISS", IAP_EVENT_24H_02H)			\
+__PMC_EV_ALIAS("L2_RQSTS.LOADS", IAP_EVENT_24H_03H)			\
+__PMC_EV_ALIAS("L2_RQSTS.RFO_HIT", IAP_EVENT_24H_04H)			\
+__PMC_EV_ALIAS("L2_RQSTS.RFO_MISS", IAP_EVENT_24H_08H)			\
+__PMC_EV_ALIAS("L2_RQSTS.RFOS", IAP_EVENT_24H_0CH)			\
+__PMC_EV_ALIAS("L2_RQSTS.IFETCH_HIT", IAP_EVENT_24H_10H)		\
+__PMC_EV_ALIAS("L2_RQSTS.IFETCH_MISS", IAP_EVENT_24H_20H)		\
+__PMC_EV_ALIAS("L2_RQSTS.IFETCHES", IAP_EVENT_24H_30H)			\
+__PMC_EV_ALIAS("L2_RQSTS.PREFETCH_HIT", IAP_EVENT_24H_40H)		\
+__PMC_EV_ALIAS("L2_RQSTS.PREFETCH_MISS", IAP_EVENT_24H_80H)		\
+__PMC_EV_ALIAS("L2_RQSTS.PREFETCHES", IAP_EVENT_24H_C0H)		\
+__PMC_EV_ALIAS("L2_RQSTS.MISS", IAP_EVENT_24H_AAH)			\
+__PMC_EV_ALIAS("L2_RQSTS.REFERENCES", IAP_EVENT_24H_FFH)		\
+__PMC_EV_ALIAS("L2_DATA_RQSTS.DEMAND.I_STATE", IAP_EVENT_26H_01H)	\
+__PMC_EV_ALIAS("L2_DATA_RQSTS.DEMAND.S_STATE", IAP_EVENT_26H_02H)	\
+__PMC_EV_ALIAS("L2_DATA_RQSTS.DEMAND.E_STATE", IAP_EVENT_26H_04H)	\
+__PMC_EV_ALIAS("L2_DATA_RQSTS.DEMAND.M_STATE", IAP_EVENT_26H_08H)	\
+__PMC_EV_ALIAS("L2_DATA_RQSTS.DEMAND.MESI", IAP_EVENT_26H_0FH)		\
+__PMC_EV_ALIAS("L2_DATA_RQSTS.PREFETCH.I_STATE", IAP_EVENT_26H_10H)	\
+__PMC_EV_ALIAS("L2_DATA_RQSTS.PREFETCH.S_STATE", IAP_EVENT_26H_20H)	\
+__PMC_EV_ALIAS("L2_DATA_RQSTS.PREFETCH.E_STATE", IAP_EVENT_26H_40H)	\
+__PMC_EV_ALIAS("L2_DATA_RQSTS.PREFETCH.M_STATE", IAP_EVENT_26H_80H)	\
+__PMC_EV_ALIAS("L2_DATA_RQSTS.PREFETCH.MESI", IAP_EVENT_26H_F0H)	\
+__PMC_EV_ALIAS("L2_DATA_RQSTS.ANY", IAP_EVENT_26H_FFH)			\
+__PMC_EV_ALIAS("L2_WRITE.RFO.I_STATE", IAP_EVENT_27H_01H)		\
+__PMC_EV_ALIAS("L2_WRITE.RFO.S_STATE", IAP_EVENT_27H_02H)		\
+__PMC_EV_ALIAS("L2_WRITE.RFO.M_STATE", IAP_EVENT_27H_08H)		\
+__PMC_EV_ALIAS("L2_WRITE.RFO.HIT", IAP_EVENT_27H_0EH)			\
+__PMC_EV_ALIAS("L2_WRITE.RFO.MESI", IAP_EVENT_27H_0FH)			\
+__PMC_EV_ALIAS("L2_WRITE.LOCK.I_STATE", IAP_EVENT_27H_10H)		\
+__PMC_EV_ALIAS("L2_WRITE.LOCK.S_STATE", IAP_EVENT_27H_20H)		\
+__PMC_EV_ALIAS("L2_WRITE.LOCK.E_STATE", IAP_EVENT_27H_40H)		\
+__PMC_EV_ALIAS("L2_WRITE.LOCK.M_STATE", IAP_EVENT_27H_80H)		\
+__PMC_EV_ALIAS("L2_WRITE.LOCK.HIT", IAP_EVENT_27H_E0H)			\
+__PMC_EV_ALIAS("L2_WRITE.LOCK.MESI", IAP_EVENT_27H_F0H)			\
+__PMC_EV_ALIAS("L1D_WB_L2.I_STATE", IAP_EVENT_28H_01H)			\
+__PMC_EV_ALIAS("L1D_WB_L2.S_STATE", IAP_EVENT_28H_02H)			\
+__PMC_EV_ALIAS("L1D_WB_L2.E_STATE", IAP_EVENT_28H_04H)			\
+__PMC_EV_ALIAS("L1D_WB_L2.M_STATE", IAP_EVENT_28H_08H)			\
+__PMC_EV_ALIAS("L1D_WB_L2.MESI", IAP_EVENT_28H_0FH)			\
+__PMC_EV_ALIAS("L3_LAT_CACHE.REFERENCE", IAP_EVENT_2EH_4FH)		\
+__PMC_EV_ALIAS("L3_LAT_CACHE.MISS", IAP_EVENT_2EH_41H)			\
+__PMC_EV_ALIAS("CPU_CLK_UNHALTED.THREAD_P", IAP_EVENT_3CH_00H)		\
+__PMC_EV_ALIAS("CPU_CLK_UNHALTED.REF_P", IAP_EVENT_3CH_01H)		\
+__PMC_EV_ALIAS("L1D_CACHE_LD.I_STATE", IAP_EVENT_40H_01H)		\
+__PMC_EV_ALIAS("L1D_CACHE_LD.S_STATE", IAP_EVENT_40H_02H)		\
+__PMC_EV_ALIAS("L1D_CACHE_LD.E_STATE", IAP_EVENT_40H_04H)		\
+__PMC_EV_ALIAS("L1D_CACHE_LD.M_STATE", IAP_EVENT_40H_08H)		\
+__PMC_EV_ALIAS("L1D_CACHE_LD.MESI", IAP_EVENT_40H_0FH)			\
+__PMC_EV_ALIAS("L1D_CACHE_ST.S_STATE", IAP_EVENT_41H_02H)		\
+__PMC_EV_ALIAS("L1D_CACHE_ST.E_STATE", IAP_EVENT_41H_04H)		\
+__PMC_EV_ALIAS("L1D_CACHE_ST.M_STATE", IAP_EVENT_41H_08H)		\
+__PMC_EV_ALIAS("L1D_CACHE_LOCK.HIT", IAP_EVENT_42H_01H)			\
+__PMC_EV_ALIAS("L1D_CACHE_LOCK.S_STATE", IAP_EVENT_42H_02H)		\
+__PMC_EV_ALIAS("L1D_CACHE_LOCK.E_STATE", IAP_EVENT_42H_04H)		\
+__PMC_EV_ALIAS("L1D_CACHE_LOCK.M_STATE", IAP_EVENT_42H_08H)		\
+__PMC_EV_ALIAS("L1D_ALL_REF.ANY", IAP_EVENT_43H_01H)			\
+__PMC_EV_ALIAS("L1D_ALL_REF.CACHEABLE", IAP_EVENT_43H_02H)		\
+__PMC_EV_ALIAS("L1D_PEND_MISS.LOAD_BUFFERS_FULL", IAP_EVENT_48H_02H)	\
+__PMC_EV_ALIAS("DTLB_MISSES.ANY", IAP_EVENT_49H_01H)			\
+__PMC_EV_ALIAS("DTLB_MISSES.WALK_COMPLETED", IAP_EVENT_49H_02H)		\
+__PMC_EV_ALIAS("DTLB_MISSES.STLB_HIT", IAP_EVENT_49H_10H)		\
+__PMC_EV_ALIAS("LOAD_HIT_PRE", IAP_EVENT_4CH_01H)			\
+__PMC_EV_ALIAS("L1D_PREFETCH.REQUESTS", IAP_EVENT_4EH_01H)		\
+__PMC_EV_ALIAS("L1D_PREFETCH.MISS", IAP_EVENT_4EH_02H)			\
+__PMC_EV_ALIAS("L1D_PREFETCH.TRIGGERS", IAP_EVENT_4EH_04H)		\
+__PMC_EV_ALIAS("L1D.REPL", IAP_EVENT_51H_01H)				\
+__PMC_EV_ALIAS("L1D.M_REPL", IAP_EVENT_51H_02H)				\
+__PMC_EV_ALIAS("L1D.M_EVICT", IAP_EVENT_51H_04H)			\
+__PMC_EV_ALIAS("L1D.M_SNOOP_EVICT", IAP_EVENT_51H_08H)			\
+__PMC_EV_ALIAS("L1D_CACHE_PREFETCH_LOCK_FB_HIT", IAP_EVENT_52H_01H)	\
+__PMC_EV_ALIAS("L1D_CACHE_LOCK_FB_HIT", IAP_EVENT_53H_01H)		\
+__PMC_EV_ALIAS("CACHE_LOCK_CYCLES.L1D_L2", IAP_EVENT_63H_01H)		\
+__PMC_EV_ALIAS("CACHE_LOCK_CYCLES.L1D", IAP_EVENT_63H_02H)		\
+__PMC_EV_ALIAS("IO_TRANSACTIONS", IAP_EVENT_6CH_01H)			\
+__PMC_EV_ALIAS("L1I.HITS", IAP_EVENT_80H_01H)				\
+__PMC_EV_ALIAS("L1I.MISSES", IAP_EVENT_80H_02H)				\
+__PMC_EV_ALIAS("L1I.READS", IAP_EVENT_80H_03H)				\
+__PMC_EV_ALIAS("L1I.CYCLES_STALLED", IAP_EVENT_80H_04H)			\
+__PMC_EV_ALIAS("LARGE_ITLB.HIT", IAP_EVENT_82H_01H)			\
+__PMC_EV_ALIAS("ITLB_MISSES.ANY", IAP_EVENT_85H_01H)			\
+__PMC_EV_ALIAS("ITLB_MISSES.WALK_COMPLETED", IAP_EVENT_85H_02H)		\
+__PMC_EV_ALIAS("ILD_STALL.LCP", IAP_EVENT_87H_01H)			\
+__PMC_EV_ALIAS("ILD_STALL.MRU", IAP_EVENT_87H_02H)			\
+__PMC_EV_ALIAS("ILD_STALL.IQ_FULL", IAP_EVENT_87H_04H)			\
+__PMC_EV_ALIAS("ILD_STALL.REGEN", IAP_EVENT_87H_08H)			\
+__PMC_EV_ALIAS("ILD_STALL.ANY", IAP_EVENT_87H_0FH)			\
+__PMC_EV_ALIAS("BR_INST_EXEC.COND", IAP_EVENT_88H_01H)			\
+__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT", IAP_EVENT_88H_02H)		\
+__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NON_CALL", IAP_EVENT_88H_04H)	\
+__PMC_EV_ALIAS("BR_INST_EXEC.NON_CALLS", IAP_EVENT_88H_07H)		\
+__PMC_EV_ALIAS("BR_INST_EXEC.RETURN_NEAR", IAP_EVENT_88H_08H)		\
+__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_88H_10H)	\
+__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_88H_20H)	\
+__PMC_EV_ALIAS("BR_INST_EXEC.NEAR_CALLS", IAP_EVENT_88H_30H)		\
+__PMC_EV_ALIAS("BR_INST_EXEC.TAKEN", IAP_EVENT_88H_40H)			\
+__PMC_EV_ALIAS("BR_INST_EXEC.ANY", IAP_EVENT_88H_7FH)			\
+__PMC_EV_ALIAS("BR_MISP_EXEC.COND", IAP_EVENT_89H_01H)			\
+__PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT", IAP_EVENT_89H_02H)		\
+__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NON_CALL", IAP_EVENT_89H_04H)	\
+__PMC_EV_ALIAS("BR_MISP_EXEC.NON_CALLS", IAP_EVENT_89H_07H)		\
+__PMC_EV_ALIAS("BR_MISP_EXEC.RETURN_NEAR", IAP_EVENT_89H_08H)		\
+__PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_89H_10H)	\
+__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_89H_20H)	\
+__PMC_EV_ALIAS("BR_MISP_EXEC.NEAR_CALLS", IAP_EVENT_89H_30H)		\
+__PMC_EV_ALIAS("BR_MISP_EXEC.TAKEN", IAP_EVENT_89H_40H)			\
+__PMC_EV_ALIAS("BR_MISP_EXEC.ANY", IAP_EVENT_89H_7FH)			\
+__PMC_EV_ALIAS("RESOURCE_STALLS.ANY", IAP_EVENT_A2H_01H)		\
+__PMC_EV_ALIAS("RESOURCE_STALLS.LOAD", IAP_EVENT_A2H_02H)		\
+__PMC_EV_ALIAS("RESOURCE_STALLS.RS_FULL", IAP_EVENT_A2H_04H)		\
+__PMC_EV_ALIAS("RESOURCE_STALLS.STORE", IAP_EVENT_A2H_08H)		\
+__PMC_EV_ALIAS("RESOURCE_STALLS.ROB_FULL", IAP_EVENT_A2H_10H)		\
+__PMC_EV_ALIAS("RESOURCE_STALLS.FPCW", IAP_EVENT_A2H_20H)		\
+__PMC_EV_ALIAS("RESOURCE_STALLS.MXCSR", IAP_EVENT_A2H_40H)		\
+__PMC_EV_ALIAS("RESOURCE_STALLS.OTHER", IAP_EVENT_A2H_80H)		\
+__PMC_EV_ALIAS("MACRO_INSTS.FUSIONS_DECODED", IAP_EVENT_A6H_01H)	\
+__PMC_EV_ALIAS("BACLEAR_FORCE_IQ", IAP_EVENT_A7H_01H)			\
+__PMC_EV_ALIAS("LSD.UOPS", IAP_EVENT_A8H_01H)				\
+__PMC_EV_ALIAS("ITLB_FLUSH", IAP_EVENT_AEH_01H)				\
+__PMC_EV_ALIAS("OFFCORE_REQUESTS.L1D_WRITEBACK", IAP_EVENT_B0H_40H)	\
+__PMC_EV_ALIAS("UOPS_EXECUTED.PORT0", IAP_EVENT_B1H_01H)		\
+__PMC_EV_ALIAS("UOPS_EXECUTED.PORT1", IAP_EVENT_B1H_02H)		\
+__PMC_EV_ALIAS("UOPS_EXECUTED.PORT2_CORE", IAP_EVENT_B1H_04H)		\
+__PMC_EV_ALIAS("UOPS_EXECUTED.PORT3_CORE", IAP_EVENT_B1H_08H)		\
+__PMC_EV_ALIAS("UOPS_EXECUTED.PORT4_CORE", IAP_EVENT_B1H_10H)		\
+__PMC_EV_ALIAS("UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5",		\
+    IAP_EVENT_B1H_1FH)							\
+__PMC_EV_ALIAS("UOPS_EXECUTED.PORT5", IAP_EVENT_B1H_20H)		\
+__PMC_EV_ALIAS("UOPS_EXECUTED.CORE_ACTIVE_CYCLES", IAP_EVENT_B1H_3FH)	\
+__PMC_EV_ALIAS("UOPS_EXECUTED.PORT015", IAP_EVENT_B1H_40H)		\
+__PMC_EV_ALIAS("UOPS_EXECUTED.PORT234", IAP_EVENT_B1H_80H)		\
+__PMC_EV_ALIAS("OFFCORE_REQUESTS_SQ_FULL", IAP_EVENT_B2H_01H)		\
+__PMC_EV_ALIAS("OFF_CORE_RESPONSE_0", IAP_EVENT_B7H_01H)		\
+__PMC_EV_ALIAS("SNOOP_RESPONSE.HIT", IAP_EVENT_B8H_01H)			\
+__PMC_EV_ALIAS("SNOOP_RESPONSE.HITE", IAP_EVENT_B8H_02H)		\
+__PMC_EV_ALIAS("SNOOP_RESPONSE.HITM", IAP_EVENT_B8H_04H)		\
+__PMC_EV_ALIAS("OFF_CORE_RESPONSE_1", IAP_EVENT_BBH_01H)		\
+__PMC_EV_ALIAS("INST_RETIRED.ANY_P", IAP_EVENT_C0H_01H)			\
+__PMC_EV_ALIAS("INST_RETIRED.X87", IAP_EVENT_C0H_02H)			\
+__PMC_EV_ALIAS("INST_RETIRED.MMX", IAP_EVENT_C0H_04H)			\
+__PMC_EV_ALIAS("UOPS_RETIRED.ANY", IAP_EVENT_C2H_01H)			\
+__PMC_EV_ALIAS("UOPS_RETIRED.RETIRE_SLOTS", IAP_EVENT_C2H_02H)		\
+__PMC_EV_ALIAS("UOPS_RETIRED.MACRO_FUSED", IAP_EVENT_C2H_04H)		\
+__PMC_EV_ALIAS("MACHINE_CLEARS.CYCLES", IAP_EVENT_C3H_01H)		\
+__PMC_EV_ALIAS("MACHINE_CLEARS.MEM_ORDER", IAP_EVENT_C3H_02H)		\
+__PMC_EV_ALIAS("MACHINE_CLEARS.SMC", IAP_EVENT_C3H_04H)			\
+__PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_00H)	\
+__PMC_EV_ALIAS("BR_INST_RETIRED.CONDITIONAL", IAP_EVENT_C4H_01H)	\
+__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_CALL", IAP_EVENT_C4H_02H)		\
+__PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_04H)	\
+__PMC_EV_ALIAS("BR_MISP_RETIRED.ALL_BRANCHES", IAP_EVENT_C5H_00H)	\
+__PMC_EV_ALIAS("BR_MISP_RETIRED.NEAR_CALL", IAP_EVENT_C5H_02H)		\
+__PMC_EV_ALIAS("SSEX_UOPS_RETIRED.PACKED_SINGLE", IAP_EVENT_C7H_01H)	\
+__PMC_EV_ALIAS("SSEX_UOPS_RETIRED.SCALAR_SINGLE", IAP_EVENT_C7H_02H)	\
+__PMC_EV_ALIAS("SSEX_UOPS_RETIRED.PACKED_DOUBLE", IAP_EVENT_C7H_04H)	\
+__PMC_EV_ALIAS("SSEX_UOPS_RETIRED.SCALAR_DOUBLE", IAP_EVENT_C7H_08H)	\
+__PMC_EV_ALIAS("SSEX_UOPS_RETIRED.VECTOR_INTEGER", IAP_EVENT_C7H_10H)	\
+__PMC_EV_ALIAS("ITLB_MISS_RETIRED", IAP_EVENT_C8H_20H)			\
+__PMC_EV_ALIAS("MEM_LOAD_RETIRED.L1D_HIT", IAP_EVENT_CBH_01H)		\
+__PMC_EV_ALIAS("MEM_LOAD_RETIRED.L2_HIT", IAP_EVENT_CBH_02H)		\
+__PMC_EV_ALIAS("MEM_LOAD_RETIRED.L3_UNSHARED_HIT", IAP_EVENT_CBH_04H)	\
+__PMC_EV_ALIAS("MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM",		\
+    IAP_EVENT_CBH_08H)							\
+__PMC_EV_ALIAS("MEM_LOAD_RETIRED.L3_MISS", IAP_EVENT_CBH_10H)		\
+__PMC_EV_ALIAS("MEM_LOAD_RETIRED.HIT_LFB", IAP_EVENT_CBH_40H)		\
+__PMC_EV_ALIAS("MEM_LOAD_RETIRED.DTLB_MISS", IAP_EVENT_CBH_80H)		\
+__PMC_EV_ALIAS("FP_MMX_TRANS.TO_FP", IAP_EVENT_CCH_01H)			\
+__PMC_EV_ALIAS("FP_MMX_TRANS.TO_MMX", IAP_EVENT_CCH_02H)		\
+__PMC_EV_ALIAS("FP_MMX_TRANS.ANY", IAP_EVENT_CCH_03H)			\
+__PMC_EV_ALIAS("MACRO_INSTS.DECODED", IAP_EVENT_D0H_01H)		\
+__PMC_EV_ALIAS("UOPS_DECODED.MS", IAP_EVENT_D1H_02H)			\
+__PMC_EV_ALIAS("UOPS_DECODED.ESP_FOLDING", IAP_EVENT_D1H_04H)		\
+__PMC_EV_ALIAS("UOPS_DECODED.ESP_SYNC", IAP_EVENT_D1H_08H)		\
+__PMC_EV_ALIAS("RAT_STALLS.FLAGS", IAP_EVENT_D2H_01H)			\
+__PMC_EV_ALIAS("RAT_STALLS.REGISTERS", IAP_EVENT_D2H_02H)		\
+__PMC_EV_ALIAS("RAT_STALLS.ROB_READ_PORT", IAP_EVENT_D2H_04H)		\
+__PMC_EV_ALIAS("RAT_STALLS.SCOREBOARD", IAP_EVENT_D2H_08H)		\
+__PMC_EV_ALIAS("RAT_STALLS.ANY", IAP_EVENT_D2H_0FH)			\
+__PMC_EV_ALIAS("SEG_RENAME_STALLS", IAP_EVENT_D4H_01H)			\
+__PMC_EV_ALIAS("ES_REG_RENAMES", IAP_EVENT_D5H_01H)			\
+__PMC_EV_ALIAS("UOP_UNFUSION", IAP_EVENT_DBH_01H)			\
+__PMC_EV_ALIAS("BR_INST_DECODED", IAP_EVENT_E0H_01H)			\
+__PMC_EV_ALIAS("BPU_MISSED_CALL_RET", IAP_EVENT_E5H_01H)		\
+__PMC_EV_ALIAS("BACLEAR.CLEAR", IAP_EVENT_E6H_01H)			\
+__PMC_EV_ALIAS("BACLEAR.BAD_TARGET", IAP_EVENT_E6H_02H)			\
+__PMC_EV_ALIAS("BPU_CLEARS.EARLY", IAP_EVENT_E8H_01H)			\
+__PMC_EV_ALIAS("BPU_CLEARS.LATE", IAP_EVENT_E8H_02H)			\
+__PMC_EV_ALIAS("BPU_CLEARS.ANY", IAP_EVENT_E8H_03H)			\
+__PMC_EV_ALIAS("L2_TRANSACTIONS.LOAD", IAP_EVENT_F0H_01H)		\
+__PMC_EV_ALIAS("L2_TRANSACTIONS.RFO", IAP_EVENT_F0H_02H)		\
+__PMC_EV_ALIAS("L2_TRANSACTIONS.IFETCH", IAP_EVENT_F0H_04H)		\
+__PMC_EV_ALIAS("L2_TRANSACTIONS.PREFETCH", IAP_EVENT_F0H_08H)		\
+__PMC_EV_ALIAS("L2_TRANSACTIONS.L1D_WB", IAP_EVENT_F0H_10H)		\
+__PMC_EV_ALIAS("L2_TRANSACTIONS.FILL", IAP_EVENT_F0H_20H)		\
+__PMC_EV_ALIAS("L2_TRANSACTIONS.WB", IAP_EVENT_F0H_40H)			\
+__PMC_EV_ALIAS("L2_TRANSACTIONS.ANY", IAP_EVENT_F0H_80H)		\
+__PMC_EV_ALIAS("L2_LINES_IN.S_STATE", IAP_EVENT_F1H_02H)		\
+__PMC_EV_ALIAS("L2_LINES_IN.E_STATE", IAP_EVENT_F1H_04H)		\
+__PMC_EV_ALIAS("L2_LINES_IN.ANY", IAP_EVENT_F1H_07H)			\
+__PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_CLEAN", IAP_EVENT_F2H_01H)		\
+__PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_DIRTY", IAP_EVENT_F2H_02H)		\
+__PMC_EV_ALIAS("L2_LINES_OUT.PREFETCH_CLEAN", IAP_EVENT_F2H_04H)	\
+__PMC_EV_ALIAS("L2_LINES_OUT.PREFETCH_DIRTY", IAP_EVENT_F2H_08H)	\
+__PMC_EV_ALIAS("L2_LINES_OUT.ANY", IAP_EVENT_F2H_0FH)			\
+__PMC_EV_ALIAS("SQ_MISC.SPLIT_LOCK", IAP_EVENT_F4H_10H)			\
+__PMC_EV_ALIAS("SQ_FULL_STALL_CYCLES", IAP_EVENT_F6H_01H)		\
+__PMC_EV_ALIAS("FP_ASSIST.ALL", IAP_EVENT_F7H_01H)			\
+__PMC_EV_ALIAS("FP_ASSIST.OUTPUT", IAP_EVENT_F7H_02H)			\
+__PMC_EV_ALIAS("FP_ASSIST.INPUT", IAP_EVENT_F7H_04H)			\
+__PMC_EV_ALIAS("SIMD_INT_64.PACKED_MPY", IAP_EVENT_FDH_01H)		\
+__PMC_EV_ALIAS("SIMD_INT_64.PACKED_SHIFT", IAP_EVENT_FDH_02H)		\
+__PMC_EV_ALIAS("SIMD_INT_64.PACK", IAP_EVENT_FDH_04H)			\
+__PMC_EV_ALIAS("SIMD_INT_64.UNPACK", IAP_EVENT_FDH_08H)			\
+__PMC_EV_ALIAS("SIMD_INT_64.PACKED_LOGICAL", IAP_EVENT_FDH_10H)		\
+__PMC_EV_ALIAS("SIMD_INT_64.PACKED_ARITH", IAP_EVENT_FDH_20H)		\
+__PMC_EV_ALIAS("SIMD_INT_64.SHUFFLE_MOVE", IAP_EVENT_FDH_40H)		\
+__PMC_EV_ALIAS_COREI7_OLD()
+
+/*
+ * Aliases for Westmere PMC events (253669-033US December 2009)
+ */
+#define	__PMC_EV_ALIAS_WESTMERE()					\
+__PMC_EV_ALIAS_INTEL_ARCHITECTURAL()					\
+__PMC_EV_ALIAS("LOAD_BLOCK.OVERLAP_STORE", IAP_EVENT_03H_02H)		\
+__PMC_EV_ALIAS("SB_DRAIN.ANY", IAP_EVENT_04H_07H)			\
+__PMC_EV_ALIAS("MISALIGN_MEMORY.STORE", IAP_EVENT_05H_02H)		\
+__PMC_EV_ALIAS("STORE_BLOCKS.AT_RET", IAP_EVENT_06H_04H)		\
+__PMC_EV_ALIAS("STORE_BLOCKS.L1D_BLOCK", IAP_EVENT_06H_08H)		\
+__PMC_EV_ALIAS("PARTIAL_ADDRESS_ALIAS", IAP_EVENT_07H_01H)		\
+__PMC_EV_ALIAS("DTLB_LOAD_MISSES.ANY", IAP_EVENT_08H_01H)		\
+__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_COMPLETED", IAP_EVENT_08H_02H)	\
+__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_CYCLES", IAP_EVENT_08H_04H)	\
+__PMC_EV_ALIAS("DTLB_LOAD_MISSES.STLB_HIT", IAP_EVENT_08H_10H)		\
+__PMC_EV_ALIAS("DTLB_LOAD_MISSES.PDE_MISS", IAP_EVENT_08H_20H)		\
+__PMC_EV_ALIAS("MEM_INST_RETIRED.LOADS", IAP_EVENT_0BH_01H)		\
+__PMC_EV_ALIAS("MEM_INST_RETIRED.STORES", IAP_EVENT_0BH_02H)		\
+__PMC_EV_ALIAS("MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD",		\
+    IAP_EVENT_0BH_10H)							\
+__PMC_EV_ALIAS("MEM_STORE_RETIRED.DTLB_MISS", IAP_EVENT_0CH_01H)	\
+__PMC_EV_ALIAS("UOPS_ISSUED.ANY", IAP_EVENT_0EH_01H)			\
+__PMC_EV_ALIAS("UOPS_ISSUED.STALLED_CYCLES", IAP_EVENT_0EH_01H)		\
+__PMC_EV_ALIAS("UOPS_ISSUED.FUSED", IAP_EVENT_0EH_02H)			\
+__PMC_EV_ALIAS("MEM_UNCORE_RETIRED.LOCAL_HITM", IAP_EVENT_0FH_02H)	\
+__PMC_EV_ALIAS("MEM_UNCORE_RETIRED.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",	\
+    IAP_EVENT_0FH_08H)							\
+__PMC_EV_ALIAS("MEM_UNCORE_RETIRED.LOCAL_DRAM", IAP_EVENT_0FH_10H)	\
+__PMC_EV_ALIAS("MEM_UNCORE_RETIRED.REMOTE_DRAM", IAP_EVENT_0FH_20H)	\
+__PMC_EV_ALIAS("MEM_UNCORE_RETIRED.UNCACHEABLE", IAP_EVENT_0FH_80H)	\
+__PMC_EV_ALIAS("FP_COMP_OPS_EXE.X87", IAP_EVENT_10H_01H)		\
+__PMC_EV_ALIAS("FP_COMP_OPS_EXE.MMX", IAP_EVENT_10H_02H)		\
+__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_FP", IAP_EVENT_10H_04H)		\
+__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE2_INTEGER", IAP_EVENT_10H_08H)	\
+__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_FP_PACKED", IAP_EVENT_10H_10H)	\
+__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_FP_SCALAR", IAP_EVENT_10H_20H)	\
+__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION",			\
+    IAP_EVENT_10H_40H) 							\
+__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION",			\
+    IAP_EVENT_10H_80H)							\
+__PMC_EV_ALIAS("SIMD_INT_128.PACKED_MPY", IAP_EVENT_12H_01H)		\
+__PMC_EV_ALIAS("SIMD_INT_128.PACKED_SHIFT", IAP_EVENT_12H_02H)		\
+__PMC_EV_ALIAS("SIMD_INT_128.PACK", IAP_EVENT_12H_04H)			\
+__PMC_EV_ALIAS("SIMD_INT_128.UNPACK", IAP_EVENT_12H_08H)		\
+__PMC_EV_ALIAS("SIMD_INT_128.PACKED_LOGICAL", IAP_EVENT_12H_10H)	\
+__PMC_EV_ALIAS("SIMD_INT_128.PACKED_ARITH", IAP_EVENT_12H_20H)		\
+__PMC_EV_ALIAS("SIMD_INT_128.SHUFFLE_MOVE", IAP_EVENT_12H_40H)		\
+__PMC_EV_ALIAS("LOAD_DISPATCH.RS", IAP_EVENT_13H_01H)			\
+__PMC_EV_ALIAS("LOAD_DISPATCH.RS_DELAYED", IAP_EVENT_13H_02H)		\
+__PMC_EV_ALIAS("LOAD_DISPATCH.MOB", IAP_EVENT_13H_04H)			\
+__PMC_EV_ALIAS("LOAD_DISPATCH.ANY", IAP_EVENT_13H_07H)			\
+__PMC_EV_ALIAS("ARITH.CYCLES_DIV_BUSY", IAP_EVENT_14H_01H)		\
+__PMC_EV_ALIAS("ARITH.MUL", IAP_EVENT_14H_02H)				\
+__PMC_EV_ALIAS("INST_QUEUE_WRITES", IAP_EVENT_17H_01H)			\
+__PMC_EV_ALIAS("INST_DECODED.DEC0", IAP_EVENT_18H_01H)			\
+__PMC_EV_ALIAS("TWO_UOP_INSTS_DECODED", IAP_EVENT_19H_01H)		\
+__PMC_EV_ALIAS("INST_QUEUE_WRITE_CYCLES", IAP_EVENT_1EH_01H)		\
+__PMC_EV_ALIAS("LSD_OVERFLOW", IAP_EVENT_20H_01H)			\
+__PMC_EV_ALIAS("L2_RQSTS.LD_HIT", IAP_EVENT_24H_01H)			\
+__PMC_EV_ALIAS("L2_RQSTS.LD_MISS", IAP_EVENT_24H_02H)			\
+__PMC_EV_ALIAS("L2_RQSTS.LOADS", IAP_EVENT_24H_03H)			\
+__PMC_EV_ALIAS("L2_RQSTS.RFO_HIT", IAP_EVENT_24H_04H)			\
+__PMC_EV_ALIAS("L2_RQSTS.RFO_MISS", IAP_EVENT_24H_08H)			\
+__PMC_EV_ALIAS("L2_RQSTS.RFOS", IAP_EVENT_24H_0CH)			\
+__PMC_EV_ALIAS("L2_RQSTS.IFETCH_HIT", IAP_EVENT_24H_10H)		\
+__PMC_EV_ALIAS("L2_RQSTS.IFETCH_MISS", IAP_EVENT_24H_20H)		\
+__PMC_EV_ALIAS("L2_RQSTS.IFETCHES", IAP_EVENT_24H_30H)			\
+__PMC_EV_ALIAS("L2_RQSTS.PREFETCH_HIT", IAP_EVENT_24H_40H)		\
+__PMC_EV_ALIAS("L2_RQSTS.PREFETCH_MISS", IAP_EVENT_24H_80H)		\
+__PMC_EV_ALIAS("L2_RQSTS.PREFETCHES", IAP_EVENT_24H_C0H)		\
+__PMC_EV_ALIAS("L2_RQSTS.MISS", IAP_EVENT_24H_AAH)			\
+__PMC_EV_ALIAS("L2_RQSTS.REFERENCES", IAP_EVENT_24H_FFH)		\
+__PMC_EV_ALIAS("L2_DATA_RQSTS.DEMAND.I_STATE", IAP_EVENT_26H_01H)	\
+__PMC_EV_ALIAS("L2_DATA_RQSTS.DEMAND.S_STATE", IAP_EVENT_26H_02H)	\
+__PMC_EV_ALIAS("L2_DATA_RQSTS.DEMAND.E_STATE", IAP_EVENT_26H_04H)	\
+__PMC_EV_ALIAS("L2_DATA_RQSTS.DEMAND.M_STATE", IAP_EVENT_26H_08H)	\
+__PMC_EV_ALIAS("L2_DATA_RQSTS.DEMAND.MESI", IAP_EVENT_26H_0FH)		\
+__PMC_EV_ALIAS("L2_DATA_RQSTS.PREFETCH.I_STATE", IAP_EVENT_26H_10H)	\
+__PMC_EV_ALIAS("L2_DATA_RQSTS.PREFETCH.S_STATE", IAP_EVENT_26H_20H)	\
+__PMC_EV_ALIAS("L2_DATA_RQSTS.PREFETCH.E_STATE", IAP_EVENT_26H_40H)	\
+__PMC_EV_ALIAS("L2_DATA_RQSTS.PREFETCH.M_STATE", IAP_EVENT_26H_80H)	\
+__PMC_EV_ALIAS("L2_DATA_RQSTS.PREFETCH.MESI", IAP_EVENT_26H_F0H)	\
+__PMC_EV_ALIAS("L2_DATA_RQSTS.ANY", IAP_EVENT_26H_FFH)			\
+__PMC_EV_ALIAS("L2_WRITE.RFO.I_STATE", IAP_EVENT_27H_01H)		\
+__PMC_EV_ALIAS("L2_WRITE.RFO.S_STATE", IAP_EVENT_27H_02H)		\
+__PMC_EV_ALIAS("L2_WRITE.RFO.M_STATE", IAP_EVENT_27H_08H)		\
+__PMC_EV_ALIAS("L2_WRITE.RFO.HIT", IAP_EVENT_27H_0EH)			\
+__PMC_EV_ALIAS("L2_WRITE.RFO.MESI", IAP_EVENT_27H_0FH)			\
+__PMC_EV_ALIAS("L2_WRITE.LOCK.I_STATE", IAP_EVENT_27H_10H)		\
+__PMC_EV_ALIAS("L2_WRITE.LOCK.S_STATE", IAP_EVENT_27H_20H)		\
+__PMC_EV_ALIAS("L2_WRITE.LOCK.E_STATE", IAP_EVENT_27H_40H)		\
+__PMC_EV_ALIAS("L2_WRITE.LOCK.M_STATE", IAP_EVENT_27H_80H)		\
+__PMC_EV_ALIAS("L2_WRITE.LOCK.HIT", IAP_EVENT_27H_E0H)			\
+__PMC_EV_ALIAS("L2_WRITE.LOCK.MESI", IAP_EVENT_27H_F0H)			\
+__PMC_EV_ALIAS("L1D_WB_L2.I_STATE", IAP_EVENT_28H_01H)			\
+__PMC_EV_ALIAS("L1D_WB_L2.S_STATE", IAP_EVENT_28H_02H)			\
+__PMC_EV_ALIAS("L1D_WB_L2.E_STATE", IAP_EVENT_28H_04H)			\
+__PMC_EV_ALIAS("L1D_WB_L2.M_STATE", IAP_EVENT_28H_08H)			\
+__PMC_EV_ALIAS("L1D_WB_L2.MESI", IAP_EVENT_28H_0FH)			\
+__PMC_EV_ALIAS("L3_LAT_CACHE.REFERENCE", IAP_EVENT_2EH_02H)		\
+__PMC_EV_ALIAS("L3_LAT_CACHE.MISS", IAP_EVENT_2EH_01H)			\
+__PMC_EV_ALIAS("CPU_CLK_UNHALTED.THREAD_P", IAP_EVENT_3CH_00H)		\
+__PMC_EV_ALIAS("CPU_CLK_UNHALTED.REF_P", IAP_EVENT_3CH_01H)		\
+__PMC_EV_ALIAS("DTLB_MISSES.ANY", IAP_EVENT_49H_01H)			\
+__PMC_EV_ALIAS("DTLB_MISSES.WALK_COMPLETED", IAP_EVENT_49H_02H)		\
+__PMC_EV_ALIAS("DTLB_MISSES.WALK_CYCLES", IAP_EVENT_49H_04H)		\
+__PMC_EV_ALIAS("DTLB_MISSES.STLB_HIT", IAP_EVENT_49H_10H)		\
+__PMC_EV_ALIAS("DTLB_MISSES.LARGE_WALK_COMPLETED", IAP_EVENT_49H_80H)	\
+__PMC_EV_ALIAS("LOAD_HIT_PRE", IAP_EVENT_4CH_01H)			\
+__PMC_EV_ALIAS("L1D_PREFETCH.REQUESTS", IAP_EVENT_4EH_01H)		\
+__PMC_EV_ALIAS("L1D_PREFETCH.MISS", IAP_EVENT_4EH_02H)			\
+__PMC_EV_ALIAS("L1D_PREFETCH.TRIGGERS", IAP_EVENT_4EH_04H)		\
+__PMC_EV_ALIAS("EPT.WALK_CYCLES", IAP_EVENT_4FH_10H)			\
+__PMC_EV_ALIAS("L1D.REPL", IAP_EVENT_51H_01H)				\
+__PMC_EV_ALIAS("L1D.M_REPL", IAP_EVENT_51H_02H)				\
+__PMC_EV_ALIAS("L1D.M_EVICT", IAP_EVENT_51H_04H)			\
+__PMC_EV_ALIAS("L1D.M_SNOOP_EVICT", IAP_EVENT_51H_08H)			\
+__PMC_EV_ALIAS("L1D_CACHE_PREFETCH_LOCK_FB_HIT", IAP_EVENT_52H_01H)	\
+__PMC_EV_ALIAS("L1D_CACHE_LOCK_FB_HIT", IAP_EVENT_53H_01H)		\
+__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA",		\
+    IAP_EVENT_60H_01H)							\
+__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE",		\
+    IAP_EVENT_60H_02H)							\
+__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO",		\
+    IAP_EVENT_60H_04H)							\
+__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.ANY.READ",			\
+    IAP_EVENT_60H_08H)							\
+__PMC_EV_ALIAS("CACHE_LOCK_CYCLES.L1D_L2", IAP_EVENT_63H_01H)		\
+__PMC_EV_ALIAS("CACHE_LOCK_CYCLES.L1D", IAP_EVENT_63H_02H)		\
+__PMC_EV_ALIAS("IO_TRANSACTIONS", IAP_EVENT_6CH_01H)			\
+__PMC_EV_ALIAS("L1I.HITS", IAP_EVENT_80H_01H)				\
+__PMC_EV_ALIAS("L1I.MISSES", IAP_EVENT_80H_02H)				\
+__PMC_EV_ALIAS("L1I.READS", IAP_EVENT_80H_03H)				\
+__PMC_EV_ALIAS("L1I.CYCLES_STALLED", IAP_EVENT_80H_04H)			\
+__PMC_EV_ALIAS("LARGE_ITLB.HIT", IAP_EVENT_82H_01H)			\
+__PMC_EV_ALIAS("ITLB_MISSES.ANY", IAP_EVENT_85H_01H)			\
+__PMC_EV_ALIAS("ITLB_MISSES.WALK_COMPLETED", IAP_EVENT_85H_02H)		\
+__PMC_EV_ALIAS("ITLB_MISSES.WALK_CYCLES", IAP_EVENT_85H_04H)		\
+__PMC_EV_ALIAS("ITLB_MISSES.LARGE_WALK_COMPLETED", IAP_EVENT_85H_80H)	\
+__PMC_EV_ALIAS("ILD_STALL.LCP", IAP_EVENT_87H_01H)			\
+__PMC_EV_ALIAS("ILD_STALL.MRU", IAP_EVENT_87H_02H)			\
+__PMC_EV_ALIAS("ILD_STALL.IQ_FULL", IAP_EVENT_87H_04H)			\
+__PMC_EV_ALIAS("ILD_STALL.REGEN", IAP_EVENT_87H_08H)			\
+__PMC_EV_ALIAS("ILD_STALL.ANY", IAP_EVENT_87H_0FH)			\
+__PMC_EV_ALIAS("BR_INST_EXEC.COND", IAP_EVENT_88H_01H)			\
+__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT", IAP_EVENT_88H_02H)		\
+__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NON_CALL", IAP_EVENT_88H_04H)	\
+__PMC_EV_ALIAS("BR_INST_EXEC.NON_CALLS", IAP_EVENT_88H_07H)		\
+__PMC_EV_ALIAS("BR_INST_EXEC.RETURN_NEAR", IAP_EVENT_88H_08H)		\
+__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_88H_10H)	\
+__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_88H_20H)	\
+__PMC_EV_ALIAS("BR_INST_EXEC.NEAR_CALLS", IAP_EVENT_88H_30H)		\
+__PMC_EV_ALIAS("BR_INST_EXEC.TAKEN", IAP_EVENT_88H_40H)			\
+__PMC_EV_ALIAS("BR_INST_EXEC.ANY", IAP_EVENT_88H_7FH)			\
+__PMC_EV_ALIAS("BR_MISP_EXEC.COND", IAP_EVENT_89H_01H)			\
+__PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT", IAP_EVENT_89H_02H)		\
+__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NON_CALL", IAP_EVENT_89H_04H)	\
+__PMC_EV_ALIAS("BR_MISP_EXEC.NON_CALLS", IAP_EVENT_89H_07H)		\
+__PMC_EV_ALIAS("BR_MISP_EXEC.RETURN_NEAR", IAP_EVENT_89H_08H)		\
+__PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_89H_10H)	\
+__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_89H_20H)	\
+__PMC_EV_ALIAS("BR_MISP_EXEC.NEAR_CALLS", IAP_EVENT_89H_30H)		\
+__PMC_EV_ALIAS("BR_MISP_EXEC.TAKEN", IAP_EVENT_89H_40H)			\
+__PMC_EV_ALIAS("BR_MISP_EXEC.ANY", IAP_EVENT_89H_7FH)			\
+__PMC_EV_ALIAS("RESOURCE_STALLS.ANY", IAP_EVENT_A2H_01H)		\
+__PMC_EV_ALIAS("RESOURCE_STALLS.LOAD", IAP_EVENT_A2H_02H)		\
+__PMC_EV_ALIAS("RESOURCE_STALLS.RS_FULL", IAP_EVENT_A2H_04H)		\
+__PMC_EV_ALIAS("RESOURCE_STALLS.STORE", IAP_EVENT_A2H_08H)		\
+__PMC_EV_ALIAS("RESOURCE_STALLS.ROB_FULL", IAP_EVENT_A2H_10H)		\
+__PMC_EV_ALIAS("RESOURCE_STALLS.FPCW", IAP_EVENT_A2H_20H)		\
+__PMC_EV_ALIAS("RESOURCE_STALLS.MXCSR", IAP_EVENT_A2H_40H)		\
+__PMC_EV_ALIAS("RESOURCE_STALLS.OTHER", IAP_EVENT_A2H_80H)		\
+__PMC_EV_ALIAS("MACRO_INSTS.FUSIONS_DECODED", IAP_EVENT_A6H_01H)	\
+__PMC_EV_ALIAS("BACLEAR_FORCE_IQ", IAP_EVENT_A7H_01H)			\
+__PMC_EV_ALIAS("LSD.UOPS", IAP_EVENT_A8H_01H)				\
+__PMC_EV_ALIAS("ITLB_FLUSH", IAP_EVENT_AEH_01H)				\
+__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND.READ_DATA", IAP_EVENT_B0H_01H)	\
+__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND.READ_CODE", IAP_EVENT_B0H_02H)	\
+__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND.RFO", IAP_EVENT_B0H_04H)	\
+__PMC_EV_ALIAS("OFFCORE_REQUESTS.ANY.READ", IAP_EVENT_B0H_08H)		\
+__PMC_EV_ALIAS("OFFCORE_REQUESTS.ANY.RFO", IAP_EVENT_B0H_10H)		\
+__PMC_EV_ALIAS("OFFCORE_REQUESTS.L1D_WRITEBACK", IAP_EVENT_B0H_40H)	\
+__PMC_EV_ALIAS("OFFCORE_REQUESTS.ANY", IAP_EVENT_B0H_80H)		\
+__PMC_EV_ALIAS("UOPS_EXECUTED.PORT0", IAP_EVENT_B1H_01H)		\
+__PMC_EV_ALIAS("UOPS_EXECUTED.PORT1", IAP_EVENT_B1H_02H)		\
+__PMC_EV_ALIAS("UOPS_EXECUTED.PORT2_CORE", IAP_EVENT_B1H_04H)		\
+__PMC_EV_ALIAS("UOPS_EXECUTED.PORT3_CORE", IAP_EVENT_B1H_08H)		\
+__PMC_EV_ALIAS("UOPS_EXECUTED.PORT4_CORE", IAP_EVENT_B1H_10H)		\
+__PMC_EV_ALIAS("UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5",		\
+    IAP_EVENT_B1H_1FH)							\
+__PMC_EV_ALIAS("UOPS_EXECUTED.PORT5", IAP_EVENT_B1H_20H)		\
+__PMC_EV_ALIAS("UOPS_EXECUTED.CORE_ACTIVE_CYCLES", IAP_EVENT_B1H_3FH)	\
+__PMC_EV_ALIAS("UOPS_EXECUTED.PORT015", IAP_EVENT_B1H_40H)		\
+__PMC_EV_ALIAS("UOPS_EXECUTED.PORT234", IAP_EVENT_B1H_80H)		\
+__PMC_EV_ALIAS("OFFCORE_REQUESTS_SQ_FULL", IAP_EVENT_B2H_01H)		\
+__PMC_EV_ALIAS("SNOOPQ_REQUESTS_OUTSTANDING.DATA", IAP_EVENT_B3H_01H)	\
+__PMC_EV_ALIAS("SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE",		\
+    IAP_EVENT_B3H_02H)							\
+__PMC_EV_ALIAS("SNOOPQ_REQUESTS_OUTSTANDING.CODE", IAP_EVENT_B3H_04H)	\
+__PMC_EV_ALIAS("SNOOPQ_REQUESTS.CODE", IAP_EVENT_B4H_01H)		\
+__PMC_EV_ALIAS("SNOOPQ_REQUESTS.DATA", IAP_EVENT_B4H_02H)		\
+__PMC_EV_ALIAS("SNOOPQ_REQUESTS.INVALIDATE", IAP_EVENT_B4H_04H)		\
+__PMC_EV_ALIAS("OFF_CORE_RESPONSE_0", IAP_EVENT_B7H_01H)		\
+__PMC_EV_ALIAS("SNOOP_RESPONSE.HIT", IAP_EVENT_B8H_01H)			\
+__PMC_EV_ALIAS("SNOOP_RESPONSE.HITE", IAP_EVENT_B8H_02H)		\
+__PMC_EV_ALIAS("SNOOP_RESPONSE.HITM", IAP_EVENT_B8H_04H)		\
+__PMC_EV_ALIAS("OFF_CORE_RESPONSE_1", IAP_EVENT_BBH_01H)		\
+__PMC_EV_ALIAS("INST_RETIRED.ANY_P", IAP_EVENT_C0H_01H)			\
+__PMC_EV_ALIAS("INST_RETIRED.X87", IAP_EVENT_C0H_02H)			\
+__PMC_EV_ALIAS("INST_RETIRED.MMX", IAP_EVENT_C0H_04H)			\
+__PMC_EV_ALIAS("UOPS_RETIRED.ANY", IAP_EVENT_C2H_01H)			\
+__PMC_EV_ALIAS("UOPS_RETIRED.RETIRE_SLOTS", IAP_EVENT_C2H_02H)		\
+__PMC_EV_ALIAS("UOPS_RETIRED.MACRO_FUSED", IAP_EVENT_C2H_04H)		\
+__PMC_EV_ALIAS("MACHINE_CLEARS.CYCLES", IAP_EVENT_C3H_01H)		\
+__PMC_EV_ALIAS("MACHINE_CLEARS.MEM_ORDER", IAP_EVENT_C3H_02H)		\
+__PMC_EV_ALIAS("MACHINE_CLEARS.SMC", IAP_EVENT_C3H_04H)			\
+__PMC_EV_ALIAS("BR_INST_RETIRED.ANY_P", IAP_EVENT_C4H_00H)	\
+__PMC_EV_ALIAS("BR_INST_RETIRED.CONDITIONAL", IAP_EVENT_C4H_01H)	\
+__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_CALL", IAP_EVENT_C4H_02H)		\
+__PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_04H)	\
+__PMC_EV_ALIAS("BR_MISP_RETIRED.ANY_P", IAP_EVENT_C5H_00H)	\
+__PMC_EV_ALIAS("BR_MISP_RETIRED.CONDITIONAL", IAP_EVENT_C5H_01H)	\
+__PMC_EV_ALIAS("BR_MISP_RETIRED.NEAR_CALL", IAP_EVENT_C5H_02H)		\
+__PMC_EV_ALIAS("BR_MISP_RETIRED.ALL_BRANCHES", IAP_EVENT_C5H_04H)	\
+__PMC_EV_ALIAS("SSEX_UOPS_RETIRED.PACKED_SINGLE", IAP_EVENT_C7H_01H)	\
+__PMC_EV_ALIAS("SSEX_UOPS_RETIRED.SCALAR_SINGLE", IAP_EVENT_C7H_02H)	\
+__PMC_EV_ALIAS("SSEX_UOPS_RETIRED.PACKED_DOUBLE", IAP_EVENT_C7H_04H)	\
+__PMC_EV_ALIAS("SSEX_UOPS_RETIRED.SCALAR_DOUBLE", IAP_EVENT_C7H_08H)	\
+__PMC_EV_ALIAS("SSEX_UOPS_RETIRED.VECTOR_INTEGER", IAP_EVENT_C7H_10H)	\
+__PMC_EV_ALIAS("ITLB_MISS_RETIRED", IAP_EVENT_C8H_20H)			\
+__PMC_EV_ALIAS("MEM_LOAD_RETIRED.L1D_HIT", IAP_EVENT_CBH_01H)		\
+__PMC_EV_ALIAS("MEM_LOAD_RETIRED.L2_HIT", IAP_EVENT_CBH_02H)		\
+__PMC_EV_ALIAS("MEM_LOAD_RETIRED.L3_UNSHARED_HIT", IAP_EVENT_CBH_04H)	\
+__PMC_EV_ALIAS("MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM",		\
+    IAP_EVENT_CBH_08H)							\
+__PMC_EV_ALIAS("MEM_LOAD_RETIRED.L3_MISS", IAP_EVENT_CBH_10H)		\
+__PMC_EV_ALIAS("MEM_LOAD_RETIRED.HIT_LFB", IAP_EVENT_CBH_40H)		\
+__PMC_EV_ALIAS("MEM_LOAD_RETIRED.DTLB_MISS", IAP_EVENT_CBH_80H)		\
+__PMC_EV_ALIAS("FP_MMX_TRANS.TO_FP", IAP_EVENT_CCH_01H)			\
+__PMC_EV_ALIAS("FP_MMX_TRANS.TO_MMX", IAP_EVENT_CCH_02H)		\
+__PMC_EV_ALIAS("FP_MMX_TRANS.ANY", IAP_EVENT_CCH_03H)			\
+__PMC_EV_ALIAS("MACRO_INSTS.DECODED", IAP_EVENT_D0H_01H)		\
+__PMC_EV_ALIAS("UOPS_DECODED.STALL_CYCLES", IAP_EVENT_D1H_01H)		\
+__PMC_EV_ALIAS("UOPS_DECODED.MS", IAP_EVENT_D1H_02H)			\
+__PMC_EV_ALIAS("UOPS_DECODED.ESP_FOLDING", IAP_EVENT_D1H_04H)		\
+__PMC_EV_ALIAS("UOPS_DECODED.ESP_SYNC", IAP_EVENT_D1H_08H)		\
+__PMC_EV_ALIAS("RAT_STALLS.FLAGS", IAP_EVENT_D2H_01H)			\
+__PMC_EV_ALIAS("RAT_STALLS.REGISTERS", IAP_EVENT_D2H_02H)		\
+__PMC_EV_ALIAS("RAT_STALLS.ROB_READ_PORT", IAP_EVENT_D2H_04H)		\
+__PMC_EV_ALIAS("RAT_STALLS.SCOREBOARD", IAP_EVENT_D2H_08H)		\
+__PMC_EV_ALIAS("RAT_STALLS.ANY", IAP_EVENT_D2H_0FH)			\
+__PMC_EV_ALIAS("SEG_RENAME_STALLS", IAP_EVENT_D4H_01H)			\
+__PMC_EV_ALIAS("ES_REG_RENAMES", IAP_EVENT_D5H_01H)			\
+__PMC_EV_ALIAS("UOP_UNFUSION", IAP_EVENT_DBH_01H)			\
+__PMC_EV_ALIAS("BR_INST_DECODED", IAP_EVENT_E0H_01H)			\
+__PMC_EV_ALIAS("BPU_MISSED_CALL_RET", IAP_EVENT_E5H_01H)		\
+__PMC_EV_ALIAS("BACLEAR.CLEAR", IAP_EVENT_E6H_01H)			\
+__PMC_EV_ALIAS("BACLEAR.BAD_TARGET", IAP_EVENT_E6H_02H)			\
+__PMC_EV_ALIAS("BPU_CLEARS.EARLY", IAP_EVENT_E8H_01H)			\
+__PMC_EV_ALIAS("BPU_CLEARS.LATE", IAP_EVENT_E8H_02H)			\
+__PMC_EV_ALIAS("THREAD_ACTIVE", IAP_EVENT_ECH_01H)			\
+__PMC_EV_ALIAS("L2_TRANSACTIONS.LOAD", IAP_EVENT_F0H_01H)		\
+__PMC_EV_ALIAS("L2_TRANSACTIONS.RFO", IAP_EVENT_F0H_02H)		\
+__PMC_EV_ALIAS("L2_TRANSACTIONS.IFETCH", IAP_EVENT_F0H_04H)		\
+__PMC_EV_ALIAS("L2_TRANSACTIONS.PREFETCH", IAP_EVENT_F0H_08H)		\
+__PMC_EV_ALIAS("L2_TRANSACTIONS.L1D_WB", IAP_EVENT_F0H_10H)		\
+__PMC_EV_ALIAS("L2_TRANSACTIONS.FILL", IAP_EVENT_F0H_20H)		\
+__PMC_EV_ALIAS("L2_TRANSACTIONS.WB", IAP_EVENT_F0H_40H)			\
+__PMC_EV_ALIAS("L2_TRANSACTIONS.ANY", IAP_EVENT_F0H_80H)		\
+__PMC_EV_ALIAS("L2_LINES_IN.S_STATE", IAP_EVENT_F1H_02H)		\
+__PMC_EV_ALIAS("L2_LINES_IN.E_STATE", IAP_EVENT_F1H_04H)		\
+__PMC_EV_ALIAS("L2_LINES_IN.ANY", IAP_EVENT_F1H_07H)			\
+__PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_CLEAN", IAP_EVENT_F2H_01H)		\
+__PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_DIRTY", IAP_EVENT_F2H_02H)		\
+__PMC_EV_ALIAS("L2_LINES_OUT.PREFETCH_CLEAN", IAP_EVENT_F2H_04H)	\
+__PMC_EV_ALIAS("L2_LINES_OUT.PREFETCH_DIRTY", IAP_EVENT_F2H_08H)	\
+__PMC_EV_ALIAS("L2_LINES_OUT.ANY", IAP_EVENT_F2H_0FH)			\
+__PMC_EV_ALIAS("SQ_MISC.LRU_HINTS", IAP_EVENT_F4H_04H)			\
+__PMC_EV_ALIAS("SQ_MISC.SPLIT_LOCK", IAP_EVENT_F4H_10H)			\
+__PMC_EV_ALIAS("SQ_FULL_STALL_CYCLES", IAP_EVENT_F6H_01H)		\
+__PMC_EV_ALIAS("FP_ASSIST.ALL", IAP_EVENT_F7H_01H)			\
+__PMC_EV_ALIAS("FP_ASSIST.OUTPUT", IAP_EVENT_F7H_02H)			\
+__PMC_EV_ALIAS("FP_ASSIST.INPUT", IAP_EVENT_F7H_04H)			\
+__PMC_EV_ALIAS("SIMD_INT_64.PACKED_MPY", IAP_EVENT_FDH_01H)		\
+__PMC_EV_ALIAS("SIMD_INT_64.PACKED_SHIFT", IAP_EVENT_FDH_02H)		\
+__PMC_EV_ALIAS("SIMD_INT_64.PACK", IAP_EVENT_FDH_04H)			\
+__PMC_EV_ALIAS("SIMD_INT_64.UNPACK", IAP_EVENT_FDH_08H)			\
+__PMC_EV_ALIAS("SIMD_INT_64.PACKED_LOGICAL", IAP_EVENT_FDH_10H)		\
+__PMC_EV_ALIAS("SIMD_INT_64.PACKED_ARITH", IAP_EVENT_FDH_20H)		\
+__PMC_EV_ALIAS("SIMD_INT_64.SHUFFLE_MOVE", IAP_EVENT_FDH_40H)
+
+/* timestamp counters. */
+#define	__PMC_EV_TSC()							\
+	__PMC_EV(TSC, TSC)
+
+#define	PMC_EV_TSC_FIRST	PMC_EV_TSC_TSC
+#define	PMC_EV_TSC_LAST		PMC_EV_TSC_TSC
+
+#define	__PMC_EV_UCF()				\
+__PMC_EV(UCF, UCLOCK)
+
+#define	PMC_EV_UCF_FIRST	PMC_EV_UCF_UCLOCK
+#define	PMC_EV_UCF_LAST		PMC_EV_UCF_UCLOCK
+
+#define	__PMC_EV_UCP()				\
+__PMC_EV(UCP, EVENT_00H_01H)			\
+__PMC_EV(UCP, EVENT_00H_02H)			\
+__PMC_EV(UCP, EVENT_00H_04H)			\
+__PMC_EV(UCP, EVENT_01H_01H)			\
+__PMC_EV(UCP, EVENT_01H_02H)			\
+__PMC_EV(UCP, EVENT_01H_04H)			\
+__PMC_EV(UCP, EVENT_02H_01H)			\
+__PMC_EV(UCP, EVENT_03H_01H)			\
+__PMC_EV(UCP, EVENT_03H_02H)			\
+__PMC_EV(UCP, EVENT_03H_04H)			\
+__PMC_EV(UCP, EVENT_03H_08H)			\
+__PMC_EV(UCP, EVENT_03H_10H)			\
+__PMC_EV(UCP, EVENT_03H_20H)			\
+__PMC_EV(UCP, EVENT_03H_40H)			\
+__PMC_EV(UCP, EVENT_04H_01H)			\
+__PMC_EV(UCP, EVENT_04H_02H)			\
+__PMC_EV(UCP, EVENT_04H_04H)			\
+__PMC_EV(UCP, EVENT_04H_08H)			\
+__PMC_EV(UCP, EVENT_04H_10H)			\
+__PMC_EV(UCP, EVENT_05H_01H)			\
+__PMC_EV(UCP, EVENT_05H_02H)			\
+__PMC_EV(UCP, EVENT_05H_04H)			\
+__PMC_EV(UCP, EVENT_06H_01H)			\
+__PMC_EV(UCP, EVENT_06H_02H)			\
+__PMC_EV(UCP, EVENT_06H_04H)			\
+__PMC_EV(UCP, EVENT_06H_08H)			\
+__PMC_EV(UCP, EVENT_06H_10H)			\
+__PMC_EV(UCP, EVENT_06H_20H)			\
+__PMC_EV(UCP, EVENT_07H_01H)			\
+__PMC_EV(UCP, EVENT_07H_02H)			\
+__PMC_EV(UCP, EVENT_07H_04H)			\
+__PMC_EV(UCP, EVENT_07H_08H)			\
+__PMC_EV(UCP, EVENT_07H_10H)			\
+__PMC_EV(UCP, EVENT_07H_20H)			\
+__PMC_EV(UCP, EVENT_07H_24H)			\
+__PMC_EV(UCP, EVENT_08H_01H)			\
+__PMC_EV(UCP, EVENT_08H_02H)			\
+__PMC_EV(UCP, EVENT_08H_04H)			\
+__PMC_EV(UCP, EVENT_08H_03H)			\
+__PMC_EV(UCP, EVENT_09H_01H)			\
+__PMC_EV(UCP, EVENT_09H_02H)			\
+__PMC_EV(UCP, EVENT_09H_04H)			\
+__PMC_EV(UCP, EVENT_09H_03H)			\
+__PMC_EV(UCP, EVENT_0AH_01H)			\
+__PMC_EV(UCP, EVENT_0AH_02H)			\
+__PMC_EV(UCP, EVENT_0AH_04H)			\
+__PMC_EV(UCP, EVENT_0AH_08H)			\
+__PMC_EV(UCP, EVENT_0AH_0FH)			\
+__PMC_EV(UCP, EVENT_0BH_01H)			\
+__PMC_EV(UCP, EVENT_0BH_02H)			\
+__PMC_EV(UCP, EVENT_0BH_04H)			\
+__PMC_EV(UCP, EVENT_0BH_08H)			\
+__PMC_EV(UCP, EVENT_0BH_10H)			\
+__PMC_EV(UCP, EVENT_0BH_1FH)			\
+__PMC_EV(UCP, EVENT_0CH_01H)			\
+__PMC_EV(UCP, EVENT_0CH_02H)			\
+__PMC_EV(UCP, EVENT_0CH_04H)			\
+__PMC_EV(UCP, EVENT_0CH_08H)			\
+__PMC_EV(UCP, EVENT_20H_01H)			\
+__PMC_EV(UCP, EVENT_20H_02H)			\
+__PMC_EV(UCP, EVENT_20H_04H)			\
+__PMC_EV(UCP, EVENT_20H_08H)			\
+__PMC_EV(UCP, EVENT_20H_10H)			\
+__PMC_EV(UCP, EVENT_20H_20H)			\
+__PMC_EV(UCP, EVENT_21H_01H)			\
+__PMC_EV(UCP, EVENT_21H_02H)			\
+__PMC_EV(UCP, EVENT_21H_04H)			\
+__PMC_EV(UCP, EVENT_22H_01H)			\
+__PMC_EV(UCP, EVENT_22H_02H)			\
+__PMC_EV(UCP, EVENT_22H_04H)			\
+__PMC_EV(UCP, EVENT_23H_01H)			\
+__PMC_EV(UCP, EVENT_23H_02H)			\
+__PMC_EV(UCP, EVENT_23H_04H)			\
+__PMC_EV(UCP, EVENT_24H_02H)			\
+__PMC_EV(UCP, EVENT_24H_04H)			\
+__PMC_EV(UCP, EVENT_25H_01H)			\
+__PMC_EV(UCP, EVENT_25H_02H)			\
+__PMC_EV(UCP, EVENT_25H_04H)			\
+__PMC_EV(UCP, EVENT_26H_01H)			\
+__PMC_EV(UCP, EVENT_27H_01H)			\
+__PMC_EV(UCP, EVENT_27H_02H)			\
+__PMC_EV(UCP, EVENT_27H_04H)			\
+__PMC_EV(UCP, EVENT_27H_08H)			\
+__PMC_EV(UCP, EVENT_27H_10H)			\
+__PMC_EV(UCP, EVENT_27H_20H)			\
+__PMC_EV(UCP, EVENT_28H_01H)			\
+__PMC_EV(UCP, EVENT_28H_02H)			\
+__PMC_EV(UCP, EVENT_28H_04H)			\
+__PMC_EV(UCP, EVENT_28H_08H)			\
+__PMC_EV(UCP, EVENT_28H_10H)			\
+__PMC_EV(UCP, EVENT_28H_20H)			\
+__PMC_EV(UCP, EVENT_29H_01H)			\
+__PMC_EV(UCP, EVENT_29H_02H)			\
+__PMC_EV(UCP, EVENT_29H_04H)			\
+__PMC_EV(UCP, EVENT_29H_08H)			\
+__PMC_EV(UCP, EVENT_29H_10H)			\
+__PMC_EV(UCP, EVENT_29H_20H)			\
+__PMC_EV(UCP, EVENT_2AH_01H)			\
+__PMC_EV(UCP, EVENT_2AH_02H)			\
+__PMC_EV(UCP, EVENT_2AH_04H)			\
+__PMC_EV(UCP, EVENT_2AH_07H)			\
+__PMC_EV(UCP, EVENT_2BH_01H)			\
+__PMC_EV(UCP, EVENT_2BH_02H)			\
+__PMC_EV(UCP, EVENT_2BH_04H)			\
+__PMC_EV(UCP, EVENT_2BH_07H)			\
+__PMC_EV(UCP, EVENT_2CH_01H)			\
+__PMC_EV(UCP, EVENT_2CH_02H)			\
+__PMC_EV(UCP, EVENT_2CH_04H)			\
+__PMC_EV(UCP, EVENT_2CH_07H)			\
+__PMC_EV(UCP, EVENT_2DH_01H)			\
+__PMC_EV(UCP, EVENT_2DH_02H)			\
+__PMC_EV(UCP, EVENT_2DH_04H)			\
+__PMC_EV(UCP, EVENT_2DH_07H)			\
+__PMC_EV(UCP, EVENT_2EH_01H)			\
+__PMC_EV(UCP, EVENT_2EH_02H)			\
+__PMC_EV(UCP, EVENT_2EH_04H)			\
+__PMC_EV(UCP, EVENT_2EH_07H)			\
+__PMC_EV(UCP, EVENT_2FH_01H)			\
+__PMC_EV(UCP, EVENT_2FH_02H)			\
+__PMC_EV(UCP, EVENT_2FH_04H)			\
+__PMC_EV(UCP, EVENT_2FH_07H)			\
+__PMC_EV(UCP, EVENT_2FH_08H)			\
+__PMC_EV(UCP, EVENT_2FH_10H)			\
+__PMC_EV(UCP, EVENT_2FH_20H)			\
+__PMC_EV(UCP, EVENT_2FH_38H)			\
+__PMC_EV(UCP, EVENT_30H_01H)			\
+__PMC_EV(UCP, EVENT_30H_02H)			\
+__PMC_EV(UCP, EVENT_30H_04H)			\
+__PMC_EV(UCP, EVENT_30H_07H)			\
+__PMC_EV(UCP, EVENT_31H_01H)			\
+__PMC_EV(UCP, EVENT_31H_02H)			\
+__PMC_EV(UCP, EVENT_31H_04H)			\
+__PMC_EV(UCP, EVENT_31H_07H)			\
+__PMC_EV(UCP, EVENT_32H_01H)			\
+__PMC_EV(UCP, EVENT_32H_02H)			\
+__PMC_EV(UCP, EVENT_32H_04H)			\
+__PMC_EV(UCP, EVENT_32H_07H)			\
+__PMC_EV(UCP, EVENT_33H_01H)			\
+__PMC_EV(UCP, EVENT_33H_02H)			\
+__PMC_EV(UCP, EVENT_33H_04H)			\
+__PMC_EV(UCP, EVENT_33H_07H)			\
+__PMC_EV(UCP, EVENT_34H_01H)			\
+__PMC_EV(UCP, EVENT_34H_02H)			\
+__PMC_EV(UCP, EVENT_34H_04H)			\
+__PMC_EV(UCP, EVENT_34H_08H)			\
+__PMC_EV(UCP, EVENT_34H_10H)			\
+__PMC_EV(UCP, EVENT_34H_20H)			\
+__PMC_EV(UCP, EVENT_35H_01H)			\
+__PMC_EV(UCP, EVENT_35H_02H)			\
+__PMC_EV(UCP, EVENT_35H_04H)			\
+__PMC_EV(UCP, EVENT_40H_01H)			\
+__PMC_EV(UCP, EVENT_40H_02H)			\
+__PMC_EV(UCP, EVENT_40H_04H)			\
+__PMC_EV(UCP, EVENT_40H_08H)			\
+__PMC_EV(UCP, EVENT_40H_10H)			\
+__PMC_EV(UCP, EVENT_40H_20H)			\
+__PMC_EV(UCP, EVENT_40H_07H)			\
+__PMC_EV(UCP, EVENT_40H_38H)			\
+__PMC_EV(UCP, EVENT_41H_01H)			\
+__PMC_EV(UCP, EVENT_41H_02H)			\
+__PMC_EV(UCP, EVENT_41H_04H)			\
+__PMC_EV(UCP, EVENT_41H_08H)			\
+__PMC_EV(UCP, EVENT_41H_10H)			\
+__PMC_EV(UCP, EVENT_41H_20H)			\
+__PMC_EV(UCP, EVENT_41H_07H)			\
+__PMC_EV(UCP, EVENT_41H_38H)			\
+__PMC_EV(UCP, EVENT_42H_01H)			\
+__PMC_EV(UCP, EVENT_42H_02H)			\
+__PMC_EV(UCP, EVENT_42H_04H)			\
+__PMC_EV(UCP, EVENT_42H_08H)			\
+__PMC_EV(UCP, EVENT_43H_01H)			\
+__PMC_EV(UCP, EVENT_43H_02H)			\
+__PMC_EV(UCP, EVENT_60H_01H)			\
+__PMC_EV(UCP, EVENT_60H_02H)			\
+__PMC_EV(UCP, EVENT_60H_04H)			\
+__PMC_EV(UCP, EVENT_61H_01H)			\
+__PMC_EV(UCP, EVENT_61H_02H)			\
+__PMC_EV(UCP, EVENT_61H_04H)			\
+__PMC_EV(UCP, EVENT_62H_01H)			\
+__PMC_EV(UCP, EVENT_62H_02H)			\
+__PMC_EV(UCP, EVENT_62H_04H)			\
+__PMC_EV(UCP, EVENT_63H_01H)			\
+__PMC_EV(UCP, EVENT_63H_02H)			\
+__PMC_EV(UCP, EVENT_63H_04H)			\
+__PMC_EV(UCP, EVENT_63H_08H)			\
+__PMC_EV(UCP, EVENT_63H_10H)			\
+__PMC_EV(UCP, EVENT_63H_20H)			\
+__PMC_EV(UCP, EVENT_64H_01H)			\
+__PMC_EV(UCP, EVENT_64H_02H)			\
+__PMC_EV(UCP, EVENT_64H_04H)			\
+__PMC_EV(UCP, EVENT_64H_08H)			\
+__PMC_EV(UCP, EVENT_64H_10H)			\
+__PMC_EV(UCP, EVENT_64H_20H)			\
+__PMC_EV(UCP, EVENT_65H_01H)			\
+__PMC_EV(UCP, EVENT_65H_02H)			\
+__PMC_EV(UCP, EVENT_65H_04H)			\
+__PMC_EV(UCP, EVENT_66H_01H)			\
+__PMC_EV(UCP, EVENT_66H_02H)			\
+__PMC_EV(UCP, EVENT_66H_04H)			\
+__PMC_EV(UCP, EVENT_67H_01H)			\
+__PMC_EV(UCP, EVENT_80H_01H)			\
+__PMC_EV(UCP, EVENT_80H_02H)			\
+__PMC_EV(UCP, EVENT_80H_04H)			\
+__PMC_EV(UCP, EVENT_80H_08H)			\
+__PMC_EV(UCP, EVENT_81H_01H)			\
+__PMC_EV(UCP, EVENT_81H_02H)			\
+__PMC_EV(UCP, EVENT_81H_04H)			\
+__PMC_EV(UCP, EVENT_81H_08H)			\
+__PMC_EV(UCP, EVENT_82H_01H)			\
+__PMC_EV(UCP, EVENT_83H_01H)			\
+__PMC_EV(UCP, EVENT_83H_02H)			\
+__PMC_EV(UCP, EVENT_83H_04H)			\
+__PMC_EV(UCP, EVENT_83H_08H)			\
+__PMC_EV(UCP, EVENT_84H_01H)			\
+__PMC_EV(UCP, EVENT_84H_02H)			\
+__PMC_EV(UCP, EVENT_84H_04H)			\
+__PMC_EV(UCP, EVENT_84H_08H)			\
+__PMC_EV(UCP, EVENT_85H_02H)			\
+__PMC_EV(UCP, EVENT_86H_01H)
+
+#define	PMC_EV_UCP_FIRST	PMC_EV_UCP_EVENT_00H_01H
+#define	PMC_EV_UCP_LAST		PMC_EV_UCP_EVENT_86H_01H
+
+#define	__PMC_EV_ALIAS_COREI7UC()					\
+__PMC_EV_ALIAS("GQ_CYCLES_FULL.READ_TRACKER", UCP_EVENT_00H_01H)	\
+__PMC_EV_ALIAS("GQ_CYCLES_FULL.WRITE_TRACKER", UCP_EVENT_00H_02H)	\
+__PMC_EV_ALIAS("GQ_CYCLES_FULL.PEER_PROBE_TRACKER", UCP_EVENT_00H_04H)	\
+__PMC_EV_ALIAS("GQ_CYCLES_NOT_EMPTY.READ_TRACKER", UCP_EVENT_01H_01H)	\
+__PMC_EV_ALIAS("GQ_CYCLES_NOT_EMPTY.WRITE_TRACKER", UCP_EVENT_01H_02H)	\
+__PMC_EV_ALIAS("GQ_CYCLES_NOT_EMPTY.PEER_PROBE_TRACKER", UCP_EVENT_01H_04H)	\
+__PMC_EV_ALIAS("GQ_ALLOC.READ_TRACKER", UCP_EVENT_03H_01H)	\
+__PMC_EV_ALIAS("GQ_ALLOC.RT_L3_MISS", UCP_EVENT_03H_02H)	\
+__PMC_EV_ALIAS("GQ_ALLOC.RT_TO_L3_RESP", UCP_EVENT_03H_04H)	\
+__PMC_EV_ALIAS("GQ_ALLOC.RT_TO_RTID_ACQUIRED", UCP_EVENT_03H_08H)	\
+__PMC_EV_ALIAS("GQ_ALLOC.WT_TO_RTID_ACQUIRED", UCP_EVENT_03H_10H)	\
+__PMC_EV_ALIAS("GQ_ALLOC.WRITE_TRACKER", UCP_EVENT_03H_20H)	\
+__PMC_EV_ALIAS("GQ_ALLOC.PEER_PROBE_TRACKER", UCP_EVENT_03H_40H)	\
+__PMC_EV_ALIAS("GQ_DATA.FROM_QPI", UCP_EVENT_04H_01H)	\
+__PMC_EV_ALIAS("GQ_DATA.FROM_QMC", UCP_EVENT_04H_02H)	\
+__PMC_EV_ALIAS("GQ_DATA.FROM_L3", UCP_EVENT_04H_04H)	\
+__PMC_EV_ALIAS("GQ_DATA.FROM_CORES_02", UCP_EVENT_04H_08H)	\
+__PMC_EV_ALIAS("GQ_DATA.FROM_CORES_13", UCP_EVENT_04H_10H)	\
+__PMC_EV_ALIAS("GQ_DATA.TO_QPI_QMC", UCP_EVENT_05H_01H)	\
+__PMC_EV_ALIAS("GQ_DATA.TO_L3", UCP_EVENT_05H_02H)	\
+__PMC_EV_ALIAS("GQ_DATA.TO_CORES", UCP_EVENT_05H_04H)	\
+__PMC_EV_ALIAS("SNP_RESP_TO_LOCAL_HOME.I_STATE", UCP_EVENT_06H_01H)	\
+__PMC_EV_ALIAS("SNP_RESP_TO_LOCAL_HOME.S_STATE", UCP_EVENT_06H_02H)	\
+__PMC_EV_ALIAS("SNP_RESP_TO_LOCAL_HOME.FWD_S_STATE", UCP_EVENT_06H_04H)	\
+__PMC_EV_ALIAS("SNP_RESP_TO_LOCAL_HOME.FWD_I_STATE", UCP_EVENT_06H_08H)	\
+__PMC_EV_ALIAS("SNP_RESP_TO_LOCAL_HOME.CONFLICT", UCP_EVENT_06H_10H)	\
+__PMC_EV_ALIAS("SNP_RESP_TO_LOCAL_HOME.WB", UCP_EVENT_06H_20H)	\
+__PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.I_STATE", UCP_EVENT_07H_01H)	\
+__PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.S_STATE", UCP_EVENT_07H_02H)	\
+__PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.FWD_S_STATE", UCP_EVENT_07H_04H)	\
+__PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.FWD_I_STATE", UCP_EVENT_07H_08H)	\
+__PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.CONFLICT", UCP_EVENT_07H_10H)	\
+__PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.WB", UCP_EVENT_07H_20H)	\
+__PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.HITM", UCP_EVENT_07H_24H)	\
+__PMC_EV_ALIAS("L3_HITS.READ", UCP_EVENT_08H_01H)	\
+__PMC_EV_ALIAS("L3_HITS.WRITE", UCP_EVENT_08H_02H)	\
+__PMC_EV_ALIAS("L3_HITS.PROBE", UCP_EVENT_08H_04H)	\
+__PMC_EV_ALIAS("L3_HITS.ANY", UCP_EVENT_08H_03H)	\
+__PMC_EV_ALIAS("L3_MISS.READ", UCP_EVENT_09H_01H)	\
+__PMC_EV_ALIAS("L3_MISS.WRITE", UCP_EVENT_09H_02H)	\
+__PMC_EV_ALIAS("L3_MISS.PROBE", UCP_EVENT_09H_04H)	\
+__PMC_EV_ALIAS("L3_MISS.ANY", UCP_EVENT_09H_03H)	\
+__PMC_EV_ALIAS("L3_LINES_IN.M_STATE", UCP_EVENT_0AH_01H)	\
+__PMC_EV_ALIAS("L3_LINES_IN.E_STATE", UCP_EVENT_0AH_02H)	\
+__PMC_EV_ALIAS("L3_LINES_IN.S_STATE", UCP_EVENT_0AH_04H)	\
+__PMC_EV_ALIAS("L3_LINES_IN.F_STATE", UCP_EVENT_0AH_08H)	\
+__PMC_EV_ALIAS("L3_LINES_IN.ANY", UCP_EVENT_0AH_0FH)	\
+__PMC_EV_ALIAS("L3_LINES_OUT.M_STATE", UCP_EVENT_0BH_01H)	\
+__PMC_EV_ALIAS("L3_LINES_OUT.E_STATE", UCP_EVENT_0BH_02H)	\
+__PMC_EV_ALIAS("L3_LINES_OUT.S_STATE", UCP_EVENT_0BH_04H)	\
+__PMC_EV_ALIAS("L3_LINES_OUT.I_STATE", UCP_EVENT_0BH_08H)	\
+__PMC_EV_ALIAS("L3_LINES_OUT.F_STATE", UCP_EVENT_0BH_10H)	\
+__PMC_EV_ALIAS("L3_LINES_OUT.ANY", UCP_EVENT_0BH_1FH)	\
+__PMC_EV_ALIAS("QHL_REQUESTS.IOH_READS", UCP_EVENT_20H_01H)	\
+__PMC_EV_ALIAS("QHL_REQUESTS.IOH_WRITES", UCP_EVENT_20H_02H)	\
+__PMC_EV_ALIAS("QHL_REQUESTS.REMOTE_READS", UCP_EVENT_20H_04H)	\
+__PMC_EV_ALIAS("QHL_REQUESTS.REMOTE_WRITES", UCP_EVENT_20H_08H)	\
+__PMC_EV_ALIAS("QHL_REQUESTS.LOCAL_READS", UCP_EVENT_20H_10H)	\
+__PMC_EV_ALIAS("QHL_REQUESTS.LOCAL_WRITES", UCP_EVENT_20H_20H)	\
+__PMC_EV_ALIAS("QHL_CYCLES_FULL.IOH", UCP_EVENT_21H_01H)	\
+__PMC_EV_ALIAS("QHL_CYCLES_FULL.REMOTE", UCP_EVENT_21H_02H)	\
+__PMC_EV_ALIAS("QHL_CYCLES_FULL.LOCAL", UCP_EVENT_21H_04H)	\
+__PMC_EV_ALIAS("QHL_CYCLES_NOT_EMPTY.IOH", UCP_EVENT_22H_01H)	\
+__PMC_EV_ALIAS("QHL_CYCLES_NOT_EMPTY.REMOTE", UCP_EVENT_22H_02H)	\
+__PMC_EV_ALIAS("QHL_CYCLES_NOT_EMPTY.LOCAL", UCP_EVENT_22H_04H)	\
+__PMC_EV_ALIAS("QHL_OCCUPANCY.IOH", UCP_EVENT_23H_01H)	\
+__PMC_EV_ALIAS("QHL_OCCUPANCY.REMOTE", UCP_EVENT_23H_02H)	\
+__PMC_EV_ALIAS("QHL_OCCUPANCY.LOCAL", UCP_EVENT_23H_04H)	\
+__PMC_EV_ALIAS("QHL_ADDRESS_CONFLICTS.2WAY", UCP_EVENT_24H_02H)	\
+__PMC_EV_ALIAS("QHL_ADDRESS_CONFLICTS.3WAY", UCP_EVENT_24H_04H)	\
+__PMC_EV_ALIAS("QHL_CONFLICT_CYCLES.IOH", UCP_EVENT_25H_01H)	\
+__PMC_EV_ALIAS("QHL_CONFLICT_CYCLES.REMOTE", UCP_EVENT_25H_02H)	\
+__PMC_EV_ALIAS("QHL_CONFLICT_CYCLES.LOCAL", UCP_EVENT_25H_04H)	\
+__PMC_EV_ALIAS("QHL_TO_QMC_BYPASS", UCP_EVENT_26H_01H)	\
+__PMC_EV_ALIAS("QMC_NORMAL_FULL.READ.CH0", UCP_EVENT_27H_01H)	\
+__PMC_EV_ALIAS("QMC_NORMAL_FULL.READ.CH1", UCP_EVENT_27H_02H)	\
+__PMC_EV_ALIAS("QMC_NORMAL_FULL.READ.CH2", UCP_EVENT_27H_04H)	\
+__PMC_EV_ALIAS("QMC_NORMAL_FULL.WRITE.CH0", UCP_EVENT_27H_08H)	\
+__PMC_EV_ALIAS("QMC_NORMAL_FULL.WRITE.CH1", UCP_EVENT_27H_10H)	\
+__PMC_EV_ALIAS("QMC_NORMAL_FULL.WRITE.CH2", UCP_EVENT_27H_20H)	\
+__PMC_EV_ALIAS("QMC_ISOC_FULL.READ.CH0", UCP_EVENT_28H_01H)	\
+__PMC_EV_ALIAS("QMC_ISOC_FULL.READ.CH1", UCP_EVENT_28H_02H)	\
+__PMC_EV_ALIAS("QMC_ISOC_FULL.READ.CH2", UCP_EVENT_28H_04H)	\
+__PMC_EV_ALIAS("QMC_ISOC_FULL.WRITE.CH0", UCP_EVENT_28H_08H)	\
+__PMC_EV_ALIAS("QMC_ISOC_FULL.WRITE.CH1", UCP_EVENT_28H_10H)	\
+__PMC_EV_ALIAS("QMC_ISOC_FULL.WRITE.CH2", UCP_EVENT_28H_20H)	\
+__PMC_EV_ALIAS("QMC_BUSY.READ.CH0", UCP_EVENT_29H_01H)	\
+__PMC_EV_ALIAS("QMC_BUSY.READ.CH1", UCP_EVENT_29H_02H)	\
+__PMC_EV_ALIAS("QMC_BUSY.READ.CH2", UCP_EVENT_29H_04H)	\
+__PMC_EV_ALIAS("QMC_BUSY.WRITE.CH0", UCP_EVENT_29H_08H)	\
+__PMC_EV_ALIAS("QMC_BUSY.WRITE.CH1", UCP_EVENT_29H_10H)	\
+__PMC_EV_ALIAS("QMC_BUSY.WRITE.CH2", UCP_EVENT_29H_20H)	\
+__PMC_EV_ALIAS("QMC_OCCUPANCY.CH0", UCP_EVENT_2AH_01H)	\
+__PMC_EV_ALIAS("QMC_OCCUPANCY.CH1", UCP_EVENT_2AH_02H)	\
+__PMC_EV_ALIAS("QMC_OCCUPANCY.CH2", UCP_EVENT_2AH_04H)	\
+__PMC_EV_ALIAS("QMC_ISSOC_OCCUPANCY.CH0", UCP_EVENT_2BH_01H)	\
+__PMC_EV_ALIAS("QMC_ISSOC_OCCUPANCY.CH1", UCP_EVENT_2BH_02H)	\
+__PMC_EV_ALIAS("QMC_ISSOC_OCCUPANCY.CH2", UCP_EVENT_2BH_04H)	\
+__PMC_EV_ALIAS("QMC_ISSOC_READS.ANY", UCP_EVENT_2BH_07H)	\
+__PMC_EV_ALIAS("QMC_NORMAL_READS.CH0", UCP_EVENT_2CH_01H)	\
+__PMC_EV_ALIAS("QMC_NORMAL_READS.CH1", UCP_EVENT_2CH_02H)	\
+__PMC_EV_ALIAS("QMC_NORMAL_READS.CH2", UCP_EVENT_2CH_04H)	\
+__PMC_EV_ALIAS("QMC_NORMAL_READS.ANY", UCP_EVENT_2CH_07H)	\
+__PMC_EV_ALIAS("QMC_HIGH_PRIORITY_READS.CH0", UCP_EVENT_2DH_01H)	\
+__PMC_EV_ALIAS("QMC_HIGH_PRIORITY_READS.CH1", UCP_EVENT_2DH_02H)	\
+__PMC_EV_ALIAS("QMC_HIGH_PRIORITY_READS.CH2", UCP_EVENT_2DH_04H)	\
+__PMC_EV_ALIAS("QMC_HIGH_PRIORITY_READS.ANY", UCP_EVENT_2DH_07H)	\
+__PMC_EV_ALIAS("QMC_CRITICAL_PRIORITY_READS.CH0", UCP_EVENT_2EH_01H)	\
+__PMC_EV_ALIAS("QMC_CRITICAL_PRIORITY_READS.CH1", UCP_EVENT_2EH_02H)	\
+__PMC_EV_ALIAS("QMC_CRITICAL_PRIORITY_READS.CH2", UCP_EVENT_2EH_04H)	\
+__PMC_EV_ALIAS("QMC_CRITICAL_PRIORITY_READS.ANY", UCP_EVENT_2EH_07H)	\
+__PMC_EV_ALIAS("QMC_WRITES.FULL.CH0", UCP_EVENT_2FH_01H)	\
+__PMC_EV_ALIAS("QMC_WRITES.FULL.CH1", UCP_EVENT_2FH_02H)	\
+__PMC_EV_ALIAS("QMC_WRITES.FULL.CH2", UCP_EVENT_2FH_04H)	\
+__PMC_EV_ALIAS("QMC_WRITES.FULL.ANY", UCP_EVENT_2FH_07H)	\
+__PMC_EV_ALIAS("QMC_WRITES.PARTIAL.CH0", UCP_EVENT_2FH_08H)	\
+__PMC_EV_ALIAS("QMC_WRITES.PARTIAL.CH1", UCP_EVENT_2FH_10H)	\
+__PMC_EV_ALIAS("QMC_WRITES.PARTIAL.CH2", UCP_EVENT_2FH_20H)	\
+__PMC_EV_ALIAS("QMC_WRITES.PARTIAL.ANY", UCP_EVENT_2FH_38H)	\
+__PMC_EV_ALIAS("QMC_CANCEL.CH0", UCP_EVENT_30H_01H)	\
+__PMC_EV_ALIAS("QMC_CANCEL.CH1", UCP_EVENT_30H_02H)	\
+__PMC_EV_ALIAS("QMC_CANCEL.CH2", UCP_EVENT_30H_04H)	\
+__PMC_EV_ALIAS("QMC_CANCEL.ANY", UCP_EVENT_30H_07H)	\
+__PMC_EV_ALIAS("QMC_PRIORITY_UPDATES.CH0", UCP_EVENT_31H_01H)	\
+__PMC_EV_ALIAS("QMC_PRIORITY_UPDATES.CH1", UCP_EVENT_31H_02H)	\
+__PMC_EV_ALIAS("QMC_PRIORITY_UPDATES.CH2", UCP_EVENT_31H_04H)	\
+__PMC_EV_ALIAS("QMC_PRIORITY_UPDATES.ANY", UCP_EVENT_31H_07H)	\
+__PMC_EV_ALIAS("QHL_FRC_ACK_CNFLTS.LOCAL", UCP_EVENT_33H_04H)	\
+__PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.HOME.LINK_0", UCP_EVENT_40H_01H)	\
+__PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.SNOOP.LINK_0", UCP_EVENT_40H_02H)	\
+__PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.NDR.LINK_0", UCP_EVENT_40H_04H)	\
+__PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.HOME.LINK_1", UCP_EVENT_40H_08H)	\
+__PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.SNOOP.LINK_1", UCP_EVENT_40H_10H)	\
+__PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.NDR.LINK_1", UCP_EVENT_40H_20H)	\
+__PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.LINK_0", UCP_EVENT_40H_07H)	\
+__PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.LINK_1", UCP_EVENT_40H_38H)	\
+__PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.DRS.LINK_0", UCP_EVENT_41H_01H)	\
+__PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.NCB.LINK_0", UCP_EVENT_41H_02H)	\
+__PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.NCS.LINK_0", UCP_EVENT_41H_04H)	\
+__PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.DRS.LINK_1", UCP_EVENT_41H_08H)	\
+__PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.NCB.LINK_1", UCP_EVENT_41H_10H)	\
+__PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.NCS.LINK_1", UCP_EVENT_41H_20H)	\
+__PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.LINK_0", UCP_EVENT_41H_07H)	\
+__PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.LINK_1", UCP_EVENT_41H_38H)	\
+__PMC_EV_ALIAS("QPI_TX_HEADER.BUSY.LINK_0", UCP_EVENT_42H_02H)	\
+__PMC_EV_ALIAS("QPI_TX_HEADER.BUSY.LINK_1", UCP_EVENT_42H_08H)	\
+__PMC_EV_ALIAS("QPI_RX_NO_PPT_CREDIT.STALLS.LINK_0", UCP_EVENT_43H_01H)	\
+__PMC_EV_ALIAS("QPI_RX_NO_PPT_CREDIT.STALLS.LINK_1", UCP_EVENT_43H_02H)	\
+__PMC_EV_ALIAS("DRAM_OPEN.CH0", UCP_EVENT_60H_01H)	\
+__PMC_EV_ALIAS("DRAM_OPEN.CH1", UCP_EVENT_60H_02H)	\
+__PMC_EV_ALIAS("DRAM_OPEN.CH2", UCP_EVENT_60H_04H)	\
+__PMC_EV_ALIAS("DRAM_PAGE_CLOSE.CH0", UCP_EVENT_61H_01H)	\
+__PMC_EV_ALIAS("DRAM_PAGE_CLOSE.CH1", UCP_EVENT_61H_02H)	\
+__PMC_EV_ALIAS("DRAM_PAGE_CLOSE.CH2", UCP_EVENT_61H_04H)	\
+__PMC_EV_ALIAS("DRAM_PAGE_MISS.CH0", UCP_EVENT_62H_01H)	\
+__PMC_EV_ALIAS("DRAM_PAGE_MISS.CH1", UCP_EVENT_62H_02H)	\
+__PMC_EV_ALIAS("DRAM_PAGE_MISS.CH2", UCP_EVENT_62H_04H)	\
+__PMC_EV_ALIAS("DRAM_READ_CAS.CH0", UCP_EVENT_63H_01H)	\
+__PMC_EV_ALIAS("DRAM_READ_CAS.AUTOPRE_CH0", UCP_EVENT_63H_02H)	\
+__PMC_EV_ALIAS("DRAM_READ_CAS.CH1", UCP_EVENT_63H_04H)	\
+__PMC_EV_ALIAS("DRAM_READ_CAS.AUTOPRE_CH1", UCP_EVENT_63H_08H)	\
+__PMC_EV_ALIAS("DRAM_READ_CAS.CH2", UCP_EVENT_63H_10H)	\
+__PMC_EV_ALIAS("DRAM_READ_CAS.AUTOPRE_CH2", UCP_EVENT_63H_20H)	\
+__PMC_EV_ALIAS("DRAM_WRITE_CAS.CH0", UCP_EVENT_64H_01H)	\
+__PMC_EV_ALIAS("DRAM_WRITE_CAS.AUTOPRE_CH0", UCP_EVENT_64H_02H)	\
+__PMC_EV_ALIAS("DRAM_WRITE_CAS.CH1", UCP_EVENT_64H_04H)	\
+__PMC_EV_ALIAS("DRAM_WRITE_CAS.AUTOPRE_CH1", UCP_EVENT_64H_08H)	\
+__PMC_EV_ALIAS("DRAM_WRITE_CAS.CH2", UCP_EVENT_64H_10H)	\
+__PMC_EV_ALIAS("DRAM_WRITE_CAS.AUTOPRE_CH2", UCP_EVENT_64H_20H)	\
+__PMC_EV_ALIAS("DRAM_REFRESH.CH0", UCP_EVENT_65H_01H)	\
+__PMC_EV_ALIAS("DRAM_REFRESH.CH1", UCP_EVENT_65H_02H)	\
+__PMC_EV_ALIAS("DRAM_REFRESH.CH2", UCP_EVENT_65H_04H)	\
+__PMC_EV_ALIAS("DRAM_PRE_ALL.CH0", UCP_EVENT_66H_01H)	\
+__PMC_EV_ALIAS("DRAM_PRE_ALL.CH1", UCP_EVENT_66H_02H)	\
+__PMC_EV_ALIAS("DRAM_PRE_ALL.CH2", UCP_EVENT_66H_04H)
+
+#define	__PMC_EV_ALIAS_WESTMEREUC()					\
+__PMC_EV_ALIAS("GQ_CYCLES_FULL.READ_TRACKER", UCP_EVENT_00H_01H)	\
+__PMC_EV_ALIAS("GQ_CYCLES_FULL.WRITE_TRACKER", UCP_EVENT_00H_02H)	\
+__PMC_EV_ALIAS("GQ_CYCLES_FULL.PEER_PROBE_TRACKER", UCP_EVENT_00H_04H)	\
+__PMC_EV_ALIAS("GQ_CYCLES_NOT_EMPTY.READ_TRACKER", UCP_EVENT_01H_01H)	\
+__PMC_EV_ALIAS("GQ_CYCLES_NOT_EMPTY.WRITE_TRACKER", UCP_EVENT_01H_02H)	\
+__PMC_EV_ALIAS("GQ_CYCLES_NOT_EMPTY.PEER_PROBE_TRACKER", UCP_EVENT_01H_04H)	\
+__PMC_EV_ALIAS("GQ_OCCUPANCY.READ_TRACKER", UCP_EVENT_02H_01H)	\
+__PMC_EV_ALIAS("GQ_ALLOC.READ_TRACKER", UCP_EVENT_03H_01H)	\
+__PMC_EV_ALIAS("GQ_ALLOC.RT_L3_MISS", UCP_EVENT_03H_02H)	\
+__PMC_EV_ALIAS("GQ_ALLOC.RT_TO_L3_RESP", UCP_EVENT_03H_04H)	\
+__PMC_EV_ALIAS("GQ_ALLOC.RT_TO_RTID_ACQUIRED", UCP_EVENT_03H_08H)	\
+__PMC_EV_ALIAS("GQ_ALLOC.WT_TO_RTID_ACQUIRED", UCP_EVENT_03H_10H)	\
+__PMC_EV_ALIAS("GQ_ALLOC.WRITE_TRACKER", UCP_EVENT_03H_20H)	\
+__PMC_EV_ALIAS("GQ_ALLOC.PEER_PROBE_TRACKER", UCP_EVENT_03H_40H)	\
+__PMC_EV_ALIAS("GQ_DATA.FROM_QPI", UCP_EVENT_04H_01H)	\
+__PMC_EV_ALIAS("GQ_DATA.FROM_QMC", UCP_EVENT_04H_02H)	\
+__PMC_EV_ALIAS("GQ_DATA.FROM_L3", UCP_EVENT_04H_04H)	\
+__PMC_EV_ALIAS("GQ_DATA.FROM_CORES_02", UCP_EVENT_04H_08H)	\
+__PMC_EV_ALIAS("GQ_DATA.FROM_CORES_13", UCP_EVENT_04H_10H)	\
+__PMC_EV_ALIAS("GQ_DATA.TO_QPI_QMC", UCP_EVENT_05H_01H)	\
+__PMC_EV_ALIAS("GQ_DATA.TO_L3", UCP_EVENT_05H_02H)	\
+__PMC_EV_ALIAS("GQ_DATA.TO_CORES", UCP_EVENT_05H_04H)	\
+__PMC_EV_ALIAS("SNP_RESP_TO_LOCAL_HOME.I_STATE", UCP_EVENT_06H_01H)	\
+__PMC_EV_ALIAS("SNP_RESP_TO_LOCAL_HOME.S_STATE", UCP_EVENT_06H_02H)	\
+__PMC_EV_ALIAS("SNP_RESP_TO_LOCAL_HOME.FWD_S_STATE", UCP_EVENT_06H_04H)	\
+__PMC_EV_ALIAS("SNP_RESP_TO_LOCAL_HOME.FWD_I_STATE", UCP_EVENT_06H_08H)	\
+__PMC_EV_ALIAS("SNP_RESP_TO_LOCAL_HOME.CONFLICT", UCP_EVENT_06H_10H)	\
+__PMC_EV_ALIAS("SNP_RESP_TO_LOCAL_HOME.WB", UCP_EVENT_06H_20H)	\
+__PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.I_STATE", UCP_EVENT_07H_01H)	\
+__PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.S_STATE", UCP_EVENT_07H_02H)	\
+__PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.FWD_S_STATE", UCP_EVENT_07H_04H)	\
+__PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.FWD_I_STATE", UCP_EVENT_07H_08H)	\
+__PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.CONFLICT", UCP_EVENT_07H_10H)	\
+__PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.WB", UCP_EVENT_07H_20H)	\
+__PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.HITM", UCP_EVENT_07H_24H)	\
+__PMC_EV_ALIAS("L3_HITS.READ", UCP_EVENT_08H_01H)	\
+__PMC_EV_ALIAS("L3_HITS.WRITE", UCP_EVENT_08H_02H)	\
+__PMC_EV_ALIAS("L3_HITS.PROBE", UCP_EVENT_08H_04H)	\
+__PMC_EV_ALIAS("L3_HITS.ANY", UCP_EVENT_08H_03H)	\
+__PMC_EV_ALIAS("L3_MISS.READ", UCP_EVENT_09H_01H)	\
+__PMC_EV_ALIAS("L3_MISS.WRITE", UCP_EVENT_09H_02H)	\
+__PMC_EV_ALIAS("L3_MISS.PROBE", UCP_EVENT_09H_04H)	\
+__PMC_EV_ALIAS("L3_MISS.ANY", UCP_EVENT_09H_03H)	\
+__PMC_EV_ALIAS("L3_LINES_IN.M_STATE", UCP_EVENT_0AH_01H)	\
+__PMC_EV_ALIAS("L3_LINES_IN.E_STATE", UCP_EVENT_0AH_02H)	\
+__PMC_EV_ALIAS("L3_LINES_IN.S_STATE", UCP_EVENT_0AH_04H)	\
+__PMC_EV_ALIAS("L3_LINES_IN.F_STATE", UCP_EVENT_0AH_08H)	\
+__PMC_EV_ALIAS("L3_LINES_IN.ANY", UCP_EVENT_0AH_0FH)	\
+__PMC_EV_ALIAS("L3_LINES_OUT.M_STATE", UCP_EVENT_0BH_01H)	\
+__PMC_EV_ALIAS("L3_LINES_OUT.E_STATE", UCP_EVENT_0BH_02H)	\
+__PMC_EV_ALIAS("L3_LINES_OUT.S_STATE", UCP_EVENT_0BH_04H)	\
+__PMC_EV_ALIAS("L3_LINES_OUT.I_STATE", UCP_EVENT_0BH_08H)	\
+__PMC_EV_ALIAS("L3_LINES_OUT.F_STATE", UCP_EVENT_0BH_10H)	\
+__PMC_EV_ALIAS("L3_LINES_OUT.ANY", UCP_EVENT_0BH_1FH)	\
+__PMC_EV_ALIAS("GQ_SNOOP.GOTO_S", UCP_EVENT_0CH_01H)	\
+__PMC_EV_ALIAS("GQ_SNOOP.GOTO_I", UCP_EVENT_0CH_02H)	\
+__PMC_EV_ALIAS("GQ_SNOOP.GOTO_S_HIT", UCP_EVENT_0CH_04H)	\
+__PMC_EV_ALIAS("GQ_SNOOP.GOTO_I_HIT", UCP_EVENT_0CH_08H)	\
+__PMC_EV_ALIAS("QHL_REQUESTS.IOH_READS", UCP_EVENT_20H_01H)	\
+__PMC_EV_ALIAS("QHL_REQUESTS.IOH_WRITES", UCP_EVENT_20H_02H)	\
+__PMC_EV_ALIAS("QHL_REQUESTS.REMOTE_READS", UCP_EVENT_20H_04H)	\
+__PMC_EV_ALIAS("QHL_REQUESTS.REMOTE_WRITES", UCP_EVENT_20H_08H)	\
+__PMC_EV_ALIAS("QHL_REQUESTS.LOCAL_READS", UCP_EVENT_20H_10H)	\
+__PMC_EV_ALIAS("QHL_REQUESTS.LOCAL_WRITES", UCP_EVENT_20H_20H)	\
+__PMC_EV_ALIAS("QHL_CYCLES_FULL.IOH", UCP_EVENT_21H_01H)	\
+__PMC_EV_ALIAS("QHL_CYCLES_FULL.REMOTE", UCP_EVENT_21H_02H)	\
+__PMC_EV_ALIAS("QHL_CYCLES_FULL.LOCAL", UCP_EVENT_21H_04H)	\
+__PMC_EV_ALIAS("QHL_CYCLES_NOT_EMPTY.IOH", UCP_EVENT_22H_01H)	\
+__PMC_EV_ALIAS("QHL_CYCLES_NOT_EMPTY.REMOTE", UCP_EVENT_22H_02H)	\
+__PMC_EV_ALIAS("QHL_CYCLES_NOT_EMPTY.LOCAL", UCP_EVENT_22H_04H)	\
+__PMC_EV_ALIAS("QHL_OCCUPANCY.IOH", UCP_EVENT_23H_01H)	\
+__PMC_EV_ALIAS("QHL_OCCUPANCY.REMOTE", UCP_EVENT_23H_02H)	\
+__PMC_EV_ALIAS("QHL_OCCUPANCY.LOCAL", UCP_EVENT_23H_04H)	\
+__PMC_EV_ALIAS("QHL_ADDRESS_CONFLICTS.2WAY", UCP_EVENT_24H_02H)	\
+__PMC_EV_ALIAS("QHL_ADDRESS_CONFLICTS.3WAY", UCP_EVENT_24H_04H)	\
+__PMC_EV_ALIAS("QHL_CONFLICT_CYCLES.IOH", UCP_EVENT_25H_01H)	\
+__PMC_EV_ALIAS("QHL_CONFLICT_CYCLES.REMOTE", UCP_EVENT_25H_02H)	\
+__PMC_EV_ALIAS("QHL_CONFLICT_CYCLES.LOCAL", UCP_EVENT_25H_04H)	\
+__PMC_EV_ALIAS("QHL_TO_QMC_BYPASS", UCP_EVENT_26H_01H)	\
+__PMC_EV_ALIAS("QMC_ISOC_FULL.READ.CH0", UCP_EVENT_28H_01H)	\
+__PMC_EV_ALIAS("QMC_ISOC_FULL.READ.CH1", UCP_EVENT_28H_02H)	\
+__PMC_EV_ALIAS("QMC_ISOC_FULL.READ.CH2", UCP_EVENT_28H_04H)	\
+__PMC_EV_ALIAS("QMC_ISOC_FULL.WRITE.CH0", UCP_EVENT_28H_08H)	\
+__PMC_EV_ALIAS("QMC_ISOC_FULL.WRITE.CH1", UCP_EVENT_28H_10H)	\
+__PMC_EV_ALIAS("QMC_ISOC_FULL.WRITE.CH2", UCP_EVENT_28H_20H)	\
+__PMC_EV_ALIAS("QMC_BUSY.READ.CH0", UCP_EVENT_29H_01H)	\
+__PMC_EV_ALIAS("QMC_BUSY.READ.CH1", UCP_EVENT_29H_02H)	\
+__PMC_EV_ALIAS("QMC_BUSY.READ.CH2", UCP_EVENT_29H_04H)	\
+__PMC_EV_ALIAS("QMC_BUSY.WRITE.CH0", UCP_EVENT_29H_08H)	\
+__PMC_EV_ALIAS("QMC_BUSY.WRITE.CH1", UCP_EVENT_29H_10H)	\
+__PMC_EV_ALIAS("QMC_BUSY.WRITE.CH2", UCP_EVENT_29H_20H)	\
+__PMC_EV_ALIAS("QMC_OCCUPANCY.CH0", UCP_EVENT_2AH_01H)	\
+__PMC_EV_ALIAS("QMC_OCCUPANCY.CH1", UCP_EVENT_2AH_02H)	\
+__PMC_EV_ALIAS("QMC_OCCUPANCY.CH2", UCP_EVENT_2AH_04H)	\
+__PMC_EV_ALIAS("QMC_OCCUPANCY.ANY", UCP_EVENT_2AH_07H)	\
+__PMC_EV_ALIAS("QMC_ISSOC_OCCUPANCY.CH0", UCP_EVENT_2BH_01H)	\
+__PMC_EV_ALIAS("QMC_ISSOC_OCCUPANCY.CH1", UCP_EVENT_2BH_02H)	\
+__PMC_EV_ALIAS("QMC_ISSOC_OCCUPANCY.CH2", UCP_EVENT_2BH_04H)	\
+__PMC_EV_ALIAS("QMC_ISSOC_READS.ANY", UCP_EVENT_2BH_07H)	\
+__PMC_EV_ALIAS("QMC_NORMAL_READS.CH0", UCP_EVENT_2CH_01H)	\
+__PMC_EV_ALIAS("QMC_NORMAL_READS.CH1", UCP_EVENT_2CH_02H)	\
+__PMC_EV_ALIAS("QMC_NORMAL_READS.CH2", UCP_EVENT_2CH_04H)	\
+__PMC_EV_ALIAS("QMC_NORMAL_READS.ANY", UCP_EVENT_2CH_07H)	\
+__PMC_EV_ALIAS("QMC_HIGH_PRIORITY_READS.CH0", UCP_EVENT_2DH_01H)	\
+__PMC_EV_ALIAS("QMC_HIGH_PRIORITY_READS.CH1", UCP_EVENT_2DH_02H)	\
+__PMC_EV_ALIAS("QMC_HIGH_PRIORITY_READS.CH2", UCP_EVENT_2DH_04H)	\
+__PMC_EV_ALIAS("QMC_HIGH_PRIORITY_READS.ANY", UCP_EVENT_2DH_07H)	\
+__PMC_EV_ALIAS("QMC_CRITICAL_PRIORITY_READS.CH0", UCP_EVENT_2EH_01H)	\
+__PMC_EV_ALIAS("QMC_CRITICAL_PRIORITY_READS.CH1", UCP_EVENT_2EH_02H)	\
+__PMC_EV_ALIAS("QMC_CRITICAL_PRIORITY_READS.CH2", UCP_EVENT_2EH_04H)	\
+__PMC_EV_ALIAS("QMC_CRITICAL_PRIORITY_READS.ANY", UCP_EVENT_2EH_07H)	\
+__PMC_EV_ALIAS("QMC_WRITES.FULL.CH0", UCP_EVENT_2FH_01H)	\
+__PMC_EV_ALIAS("QMC_WRITES.FULL.CH1", UCP_EVENT_2FH_02H)	\
+__PMC_EV_ALIAS("QMC_WRITES.FULL.CH2", UCP_EVENT_2FH_04H)	\
+__PMC_EV_ALIAS("QMC_WRITES.FULL.ANY", UCP_EVENT_2FH_07H)	\
+__PMC_EV_ALIAS("QMC_WRITES.PARTIAL.CH0", UCP_EVENT_2FH_08H)	\
+__PMC_EV_ALIAS("QMC_WRITES.PARTIAL.CH1", UCP_EVENT_2FH_10H)	\
+__PMC_EV_ALIAS("QMC_WRITES.PARTIAL.CH2", UCP_EVENT_2FH_20H)	\
+__PMC_EV_ALIAS("QMC_WRITES.PARTIAL.ANY", UCP_EVENT_2FH_38H)	\
+__PMC_EV_ALIAS("QMC_CANCEL.CH0", UCP_EVENT_30H_01H)	\
+__PMC_EV_ALIAS("QMC_CANCEL.CH1", UCP_EVENT_30H_02H)	\
+__PMC_EV_ALIAS("QMC_CANCEL.CH2", UCP_EVENT_30H_04H)	\
+__PMC_EV_ALIAS("QMC_CANCEL.ANY", UCP_EVENT_30H_07H)	\
+__PMC_EV_ALIAS("QMC_PRIORITY_UPDATES.CH0", UCP_EVENT_31H_01H)	\
+__PMC_EV_ALIAS("QMC_PRIORITY_UPDATES.CH1", UCP_EVENT_31H_02H)	\
+__PMC_EV_ALIAS("QMC_PRIORITY_UPDATES.CH2", UCP_EVENT_31H_04H)	\
+__PMC_EV_ALIAS("QMC_PRIORITY_UPDATES.ANY", UCP_EVENT_31H_07H)	\
+__PMC_EV_ALIAS("IMC_RETRY.CH0", UCP_EVENT_32H_01H)	\
+__PMC_EV_ALIAS("IMC_RETRY.CH1", UCP_EVENT_32H_02H)	\
+__PMC_EV_ALIAS("IMC_RETRY.CH2", UCP_EVENT_32H_04H)	\
+__PMC_EV_ALIAS("IMC_RETRY.ANY", UCP_EVENT_32H_07H)	\
+__PMC_EV_ALIAS("QHL_FRC_ACK_CNFLTS.IOH", UCP_EVENT_33H_01H)	\
+__PMC_EV_ALIAS("QHL_FRC_ACK_CNFLTS.REMOTE", UCP_EVENT_33H_02H)	\
+__PMC_EV_ALIAS("QHL_FRC_ACK_CNFLTS.LOCAL", UCP_EVENT_33H_04H)	\
+__PMC_EV_ALIAS("QHL_FRC_ACK_CNFLTS.ANY", UCP_EVENT_33H_07H)	\
+__PMC_EV_ALIAS("QHL_SLEEPS.IOH_ORDER", UCP_EVENT_34H_01H)	\
+__PMC_EV_ALIAS("QHL_SLEEPS.REMOTE_ORDER", UCP_EVENT_34H_02H)	\
+__PMC_EV_ALIAS("QHL_SLEEPS.LOCAL_ORDER", UCP_EVENT_34H_04H)	\
+__PMC_EV_ALIAS("QHL_SLEEPS.IOH_CONFLICT", UCP_EVENT_34H_08H)	\
+__PMC_EV_ALIAS("QHL_SLEEPS.REMOTE_CONFLICT", UCP_EVENT_34H_10H)	\
+__PMC_EV_ALIAS("QHL_SLEEPS.LOCAL_CONFLICT", UCP_EVENT_34H_20H)	\
+__PMC_EV_ALIAS("ADDR_OPCODE_MATCH.IOH", UCP_EVENT_35H_01H)	\
+__PMC_EV_ALIAS("ADDR_OPCODE_MATCH.REMOTE", UCP_EVENT_35H_02H)	\
+__PMC_EV_ALIAS("ADDR_OPCODE_MATCH.LOCAL", UCP_EVENT_35H_04H)	\
+__PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.HOME.LINK_0", UCP_EVENT_40H_01H)	\
+__PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.SNOOP.LINK_0", UCP_EVENT_40H_02H)	\
+__PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.NDR.LINK_0", UCP_EVENT_40H_04H)	\
+__PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.HOME.LINK_1", UCP_EVENT_40H_08H)	\
+__PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.SNOOP.LINK_1", UCP_EVENT_40H_10H)	\
+__PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.NDR.LINK_1", UCP_EVENT_40H_20H)	\
+__PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.LINK_0", UCP_EVENT_40H_07H)	\
+__PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.LINK_1", UCP_EVENT_40H_38H)	\
+__PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.DRS.LINK_0", UCP_EVENT_41H_01H)	\
+__PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.NCB.LINK_0", UCP_EVENT_41H_02H)	\
+__PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.NCS.LINK_0", UCP_EVENT_41H_04H)	\
+__PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.DRS.LINK_1", UCP_EVENT_41H_08H)	\
+__PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.NCB.LINK_1", UCP_EVENT_41H_10H)	\
+__PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.NCS.LINK_1", UCP_EVENT_41H_20H)	\
+__PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.LINK_0", UCP_EVENT_41H_07H)	\
+__PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.LINK_1", UCP_EVENT_41H_38H)	\
+__PMC_EV_ALIAS("QPI_TX_HEADER.FULL.LINK_0", UCP_EVENT_42H_01H)	\
+__PMC_EV_ALIAS("QPI_TX_HEADER.BUSY.LINK_0", UCP_EVENT_42H_02H)	\
+__PMC_EV_ALIAS("QPI_TX_HEADER.FULL.LINK_1", UCP_EVENT_42H_04H)	\
+__PMC_EV_ALIAS("QPI_TX_HEADER.BUSY.LINK_1", UCP_EVENT_42H_08H)	\
+__PMC_EV_ALIAS("QPI_RX_NO_PPT_CREDIT.STALLS.LINK_0", UCP_EVENT_43H_01H)	\
+__PMC_EV_ALIAS("QPI_RX_NO_PPT_CREDIT.STALLS.LINK_1", UCP_EVENT_43H_02H)	\
+__PMC_EV_ALIAS("DRAM_OPEN.CH0", UCP_EVENT_60H_01H)	\
+__PMC_EV_ALIAS("DRAM_OPEN.CH1", UCP_EVENT_60H_02H)	\
+__PMC_EV_ALIAS("DRAM_OPEN.CH2", UCP_EVENT_60H_04H)	\
+__PMC_EV_ALIAS("DRAM_PAGE_CLOSE.CH0", UCP_EVENT_61H_01H)	\
+__PMC_EV_ALIAS("DRAM_PAGE_CLOSE.CH1", UCP_EVENT_61H_02H)	\
+__PMC_EV_ALIAS("DRAM_PAGE_CLOSE.CH2", UCP_EVENT_61H_04H)	\
+__PMC_EV_ALIAS("DRAM_PAGE_MISS.CH0", UCP_EVENT_62H_01H)	\
+__PMC_EV_ALIAS("DRAM_PAGE_MISS.CH1", UCP_EVENT_62H_02H)	\
+__PMC_EV_ALIAS("DRAM_PAGE_MISS.CH2", UCP_EVENT_62H_04H)	\
+__PMC_EV_ALIAS("DRAM_READ_CAS.CH0", UCP_EVENT_63H_01H)	\
+__PMC_EV_ALIAS("DRAM_READ_CAS.AUTOPRE_CH0", UCP_EVENT_63H_02H)	\
+__PMC_EV_ALIAS("DRAM_READ_CAS.CH1", UCP_EVENT_63H_04H)	\
+__PMC_EV_ALIAS("DRAM_READ_CAS.AUTOPRE_CH1", UCP_EVENT_63H_08H)	\
+__PMC_EV_ALIAS("DRAM_READ_CAS.CH2", UCP_EVENT_63H_10H)	\
+__PMC_EV_ALIAS("DRAM_READ_CAS.AUTOPRE_CH2", UCP_EVENT_63H_20H)	\
+__PMC_EV_ALIAS("DRAM_WRITE_CAS.CH0", UCP_EVENT_64H_01H)	\
+__PMC_EV_ALIAS("DRAM_WRITE_CAS.AUTOPRE_CH0", UCP_EVENT_64H_02H)	\
+__PMC_EV_ALIAS("DRAM_WRITE_CAS.CH1", UCP_EVENT_64H_04H)	\
+__PMC_EV_ALIAS("DRAM_WRITE_CAS.AUTOPRE_CH1", UCP_EVENT_64H_08H)	\
+__PMC_EV_ALIAS("DRAM_WRITE_CAS.CH2", UCP_EVENT_64H_10H)	\
+__PMC_EV_ALIAS("DRAM_WRITE_CAS.AUTOPRE_CH2", UCP_EVENT_64H_20H)	\
+__PMC_EV_ALIAS("DRAM_REFRESH.CH0", UCP_EVENT_65H_01H)	\
+__PMC_EV_ALIAS("DRAM_REFRESH.CH1", UCP_EVENT_65H_02H)	\
+__PMC_EV_ALIAS("DRAM_REFRESH.CH2", UCP_EVENT_65H_04H)	\
+__PMC_EV_ALIAS("DRAM_PRE_ALL.CH0", UCP_EVENT_66H_01H)	\
+__PMC_EV_ALIAS("DRAM_PRE_ALL.CH1", UCP_EVENT_66H_02H)	\
+__PMC_EV_ALIAS("DRAM_PRE_ALL.CH2", UCP_EVENT_66H_04H)	\
+__PMC_EV_ALIAS("DRAM_THERMAL_THROTTLED", UCP_EVENT_67H_01H)	\
+__PMC_EV_ALIAS("THERMAL_THROTTLING_TEMP.CORE_0", UCP_EVENT_80H_01H)	\
+__PMC_EV_ALIAS("THERMAL_THROTTLING_TEMP.CORE_1", UCP_EVENT_80H_02H)	\
+__PMC_EV_ALIAS("THERMAL_THROTTLING_TEMP.CORE_2", UCP_EVENT_80H_04H)	\
+__PMC_EV_ALIAS("THERMAL_THROTTLING_TEMP.CORE_3", UCP_EVENT_80H_08H)	\
+__PMC_EV_ALIAS("THERMAL_THROTTLED_TEMP.CORE_0", UCP_EVENT_81H_01H)	\
+__PMC_EV_ALIAS("THERMAL_THROTTLED_TEMP.CORE_1", UCP_EVENT_81H_02H)	\
+__PMC_EV_ALIAS("THERMAL_THROTTLED_TEMP.CORE_2", UCP_EVENT_81H_04H)	\
+__PMC_EV_ALIAS("THERMAL_THROTTLED_TEMP.CORE_3", UCP_EVENT_81H_08H)	\
+__PMC_EV_ALIAS("PROCHOT_ASSERTION", UCP_EVENT_82H_01H)	\
+__PMC_EV_ALIAS("THERMAL_THROTTLING_PROCHOT.CORE_0", UCP_EVENT_83H_01H)	\
+__PMC_EV_ALIAS("THERMAL_THROTTLING_PROCHOT.CORE_1", UCP_EVENT_83H_02H)	\
+__PMC_EV_ALIAS("THERMAL_THROTTLING_PROCHOT.CORE_2", UCP_EVENT_83H_04H)	\
+__PMC_EV_ALIAS("THERMAL_THROTTLING_PROCHOT.CORE_3", UCP_EVENT_83H_08H)	\
+__PMC_EV_ALIAS("TURBO_MODE.CORE_0", UCP_EVENT_84H_01H)	\
+__PMC_EV_ALIAS("TURBO_MODE.CORE_1", UCP_EVENT_84H_02H)	\
+__PMC_EV_ALIAS("TURBO_MODE.CORE_2", UCP_EVENT_84H_04H)	\
+__PMC_EV_ALIAS("TURBO_MODE.CORE_3", UCP_EVENT_84H_08H)	\
+__PMC_EV_ALIAS("CYCLES_UNHALTED_L3_FLL_ENABLE", UCP_EVENT_85H_02H)	\
+__PMC_EV_ALIAS("CYCLES_UNHALTED_L3_FLL_DISABLE", UCP_EVENT_86H_01H)
+
+/*
+ * Intel XScale events from:
+ *
+ * Intel XScale Core Developer's Manual
+ * January, 2004, #27347302
+ *
+ * 3rd Generation Intel XScale Microarchitecture
+ * Developer's Manual
+ * May 2007, #31628302
+ *
+ * First 14 events are for 1st and 2nd Generation Intel XScale cores. The
+ * remaining are available only on 3rd Generation Intel XScale cores.
+ */
+#define	__PMC_EV_XSCALE()				\
+	__PMC_EV(XSCALE, IC_FETCH)			\
+	__PMC_EV(XSCALE, IC_MISS)			\
+	__PMC_EV(XSCALE, DATA_DEPENDENCY_STALLED)	\
+	__PMC_EV(XSCALE, ITLB_MISS)			\
+	__PMC_EV(XSCALE, DTLB_MISS)			\
+	__PMC_EV(XSCALE, BRANCH_RETIRED)		\
+	__PMC_EV(XSCALE, BRANCH_MISPRED)		\
+	__PMC_EV(XSCALE, INSTR_RETIRED)			\
+	__PMC_EV(XSCALE, DC_FULL_CYCLE)			\
+	__PMC_EV(XSCALE, DC_FULL_CONTIG)		\
+	__PMC_EV(XSCALE, DC_ACCESS)			\
+	__PMC_EV(XSCALE, DC_MISS)			\
+	__PMC_EV(XSCALE, DC_WRITEBACK)			\
+	__PMC_EV(XSCALE, PC_CHANGE)			\
+	__PMC_EV(XSCALE, BRANCH_RETIRED_ALL)		\
+	__PMC_EV(XSCALE, INSTR_CYCLE)			\
+	__PMC_EV(XSCALE, CP_STALL)			\
+	__PMC_EV(XSCALE, PC_CHANGE_ALL)			\
+	__PMC_EV(XSCALE, PIPELINE_FLUSH)		\
+	__PMC_EV(XSCALE, BACKEND_STALL)			\
+	__PMC_EV(XSCALE, MULTIPLIER_USE)		\
+	__PMC_EV(XSCALE, MULTIPLIER_STALLED)		\
+	__PMC_EV(XSCALE, DATA_CACHE_STALLED)		\
+	__PMC_EV(XSCALE, L2_CACHE_REQ)			\
+	__PMC_EV(XSCALE, L2_CACHE_MISS)			\
+	__PMC_EV(XSCALE, ADDRESS_BUS_TRANS)		\
+	__PMC_EV(XSCALE, SELF_ADDRESS_BUS_TRANS)	\
+	__PMC_EV(XSCALE, DATA_BUS_TRANS)
+
+#define	PMC_EV_XSCALE_FIRST	PMC_EV_XSCALE_IC_FETCH
+#define	PMC_EV_XSCALE_LAST	PMC_EV_XSCALE_DATA_BUS_TRANS
+
+/*
+ * MIPS Events from "Programming the MIPS32 24K Core Family",
+ * Document Number: MD00355 Revision 04.63 December 19, 2008
+ * These events are kept in the order found in Table 7.4.
+ * For counters which are different between the left hand
+ * column (0/2) and the right hand column (1/3) the left
+ * hand is given first, e.g. BRANCH_COMPLETED and BRANCH_MISPRED
+ * in the definition below.
+ */
+
+#define __PMC_EV_MIPS24K()                         \
+	__PMC_EV(MIPS24K, CYCLE)                   \
+	__PMC_EV(MIPS24K, INSTR_EXECUTED)          \
+	__PMC_EV(MIPS24K, BRANCH_COMPLETED)        \
+	__PMC_EV(MIPS24K, BRANCH_MISPRED)          \
+	__PMC_EV(MIPS24K, RETURN)                  \
+	__PMC_EV(MIPS24K, RETURN_MISPRED)          \
+	__PMC_EV(MIPS24K, RETURN_NOT_31)           \
+	__PMC_EV(MIPS24K, RETURN_NOTPRED)          \
+	__PMC_EV(MIPS24K, ITLB_ACCESS)             \
+	__PMC_EV(MIPS24K, ITLB_MISS)               \
+	__PMC_EV(MIPS24K, DTLB_ACCESS)             \
+	__PMC_EV(MIPS24K, DTLB_MISS)               \
+	__PMC_EV(MIPS24K, JTLB_IACCESS)            \
+	__PMC_EV(MIPS24K, JTLB_IMISS)              \
+	__PMC_EV(MIPS24K, JTLB_DACCESS)            \
+	__PMC_EV(MIPS24K, JTLB_DMISS)              \
+	__PMC_EV(MIPS24K, IC_FETCH)                \
+	__PMC_EV(MIPS24K, IC_MISS)                 \
+	__PMC_EV(MIPS24K, DC_LOADSTORE)            \
+	__PMC_EV(MIPS24K, DC_WRITEBACK)            \
+	__PMC_EV(MIPS24K, DC_MISS)                 \
+	__PMC_EV(MIPS24K, STORE_MISS)              \
+	__PMC_EV(MIPS24K, LOAD_MISS)               \
+	__PMC_EV(MIPS24K, INTEGER_COMPLETED)       \
+	__PMC_EV(MIPS24K, FP_COMPLETED)            \
+	__PMC_EV(MIPS24K, LOAD_COMPLETED)          \
+	__PMC_EV(MIPS24K, STORE_COMPLETED)         \
+	__PMC_EV(MIPS24K, BARRIER_COMPLETED)       \
+	__PMC_EV(MIPS24K, MIPS16_COMPLETED)        \
+	__PMC_EV(MIPS24K, NOP_COMPLETED)           \
+	__PMC_EV(MIPS24K, INTEGER_MULDIV_COMPLETED)\
+	__PMC_EV(MIPS24K, RF_STALL)                \
+	__PMC_EV(MIPS24K, INSTR_REFETCH)           \
+	__PMC_EV(MIPS24K, STORE_COND_COMPLETED)    \
+	__PMC_EV(MIPS24K, STORE_COND_FAILED)       \
+	__PMC_EV(MIPS24K, ICACHE_REQUESTS)         \
+	__PMC_EV(MIPS24K, ICACHE_HIT)              \
+	__PMC_EV(MIPS24K, L2_WRITEBACK)            \
+	__PMC_EV(MIPS24K, L2_ACCESS)               \
+	__PMC_EV(MIPS24K, L2_MISS)                 \
+	__PMC_EV(MIPS24K, L2_ERR_CORRECTED)        \
+	__PMC_EV(MIPS24K, EXCEPTIONS)              \
+	__PMC_EV(MIPS24K, RF_CYCLES_STALLED)       \
+	__PMC_EV(MIPS24K, IFU_CYCLES_STALLED)      \
+	__PMC_EV(MIPS24K, ALU_CYCLES_STALLED)      \
+	__PMC_EV(MIPS24K, UNCACHED_LOAD)           \
+	__PMC_EV(MIPS24K, UNCACHED_STORE)          \
+	__PMC_EV(MIPS24K, CP2_REG_TO_REG_COMPLETED)\
+	__PMC_EV(MIPS24K, MFTC_COMPLETED)          \
+	__PMC_EV(MIPS24K, IC_BLOCKED_CYCLES)       \
+	__PMC_EV(MIPS24K, DC_BLOCKED_CYCLES)       \
+	__PMC_EV(MIPS24K, L2_IMISS_STALL_CYCLES)   \
+	__PMC_EV(MIPS24K, L2_DMISS_STALL_CYCLES)   \
+	__PMC_EV(MIPS24K, DMISS_CYCLES)            \
+	__PMC_EV(MIPS24K, L2_MISS_CYCLES)          \
+	__PMC_EV(MIPS24K, UNCACHED_BLOCK_CYCLES)   \
+	__PMC_EV(MIPS24K, MDU_STALL_CYCLES)        \
+	__PMC_EV(MIPS24K, FPU_STALL_CYCLES)        \
+	__PMC_EV(MIPS24K, CP2_STALL_CYCLES)        \
+	__PMC_EV(MIPS24K, COREXTEND_STALL_CYCLES)  \
+	__PMC_EV(MIPS24K, ISPRAM_STALL_CYCLES)     \
+	__PMC_EV(MIPS24K, DSPRAM_STALL_CYCLES)     \
+	__PMC_EV(MIPS24K, CACHE_STALL_CYCLES)      \
+	__PMC_EV(MIPS24K, LOAD_TO_USE_STALLS)      \
+	__PMC_EV(MIPS24K, BASE_MISPRED_STALLS)     \
+	__PMC_EV(MIPS24K, CPO_READ_STALLS)         \
+	__PMC_EV(MIPS24K, BRANCH_MISPRED_CYCLES)   \
+	__PMC_EV(MIPS24K, IFETCH_BUFFER_FULL)      \
+	__PMC_EV(MIPS24K, FETCH_BUFFER_ALLOCATED)  \
+	__PMC_EV(MIPS24K, EJTAG_ITRIGGER)          \
+	__PMC_EV(MIPS24K, EJTAG_DTRIGGER)          \
+	__PMC_EV(MIPS24K, FSB_LT_QUARTER)          \
+	__PMC_EV(MIPS24K, FSB_QUARTER_TO_HALF)     \
+	__PMC_EV(MIPS24K, FSB_GT_HALF)             \
+	__PMC_EV(MIPS24K, FSB_FULL_PIPELINE_STALLS)\
+	__PMC_EV(MIPS24K, LDQ_LT_QUARTER)          \
+	__PMC_EV(MIPS24K, LDQ_QUARTER_TO_HALF)     \
+	__PMC_EV(MIPS24K, LDQ_GT_HALF)             \
+	__PMC_EV(MIPS24K, LDQ_FULL_PIPELINE_STALLS)\
+	__PMC_EV(MIPS24K, WBB_LT_QUARTER)          \
+	__PMC_EV(MIPS24K, WBB_QUARTER_TO_HALF)     \
+	__PMC_EV(MIPS24K, WBB_GT_HALF)             \
+	__PMC_EV(MIPS24K, WBB_FULL_PIPELINE_STALLS) \
+	__PMC_EV(MIPS24K, REQUEST_LATENCY)         \
+	__PMC_EV(MIPS24K, REQUEST_COUNT)
+
+#define	PMC_EV_MIPS24K_FIRST	PMC_EV_MIPS24K_CYCLE
+#define	PMC_EV_MIPS24K_LAST	PMC_EV_MIPS24K_WBB_FULL_PIPELINE_STALLS
+
+/*
+ * All known PMC events.
+ *
+ * PMC event numbers are allocated sparsely to allow new PMC events to
+ * be added to a PMC class without breaking ABI compatibility.  The
+ * current allocation scheme is:
+ *
+ * START	#EVENTS		DESCRIPTION
+ * 0		0x1000		Reserved
+ * 0x1000	0x0001		TSC
+ * 0x2000	0x0080		AMD K7 events
+ * 0x2080	0x0100		AMD K8 events
+ * 0x10000	0x0080		INTEL architectural fixed-function events
+ * 0x10080	0x0F80		INTEL architectural programmable events
+ * 0x11000	0x0080		INTEL Pentium 4 events
+ * 0x11080	0x0080		INTEL Pentium MMX events
+ * 0x11100	0x0100		INTEL Pentium Pro/P-II/P-III/Pentium-M events
+ * 0x11200	0x00FF		INTEL XScale events
+ * 0x11300      0x00FF          MIPS 24K events
+ */
+#define	__PMC_EVENTS()				\
+	__PMC_EV_BLOCK(TSC,	0x01000)	\
+	__PMC_EV_TSC()				\
+	__PMC_EV_BLOCK(K7,	0x2000)		\
+	__PMC_EV_K7()				\
+	__PMC_EV_BLOCK(K8,	0x2080)		\
+	__PMC_EV_K8()				\
+	__PMC_EV_BLOCK(IAF,	0x10000)	\
+	__PMC_EV_IAF()				\
+	__PMC_EV_BLOCK(IAP,	0x10080)	\
+	__PMC_EV_IAP()				\
+	__PMC_EV_BLOCK(P4,	0x11000)	\
+	__PMC_EV_P4()				\
+	__PMC_EV_BLOCK(P5,	0x11080)	\
+	__PMC_EV_P5()				\
+	__PMC_EV_BLOCK(P6,	0x11100)	\
+	__PMC_EV_P6()				\
+	__PMC_EV_BLOCK(XSCALE,	0x11200)	\
+	__PMC_EV_XSCALE()                       \
+	__PMC_EV_BLOCK(MIPS24K,	0x11300)	\
+	__PMC_EV_MIPS24K()			\
+	__PMC_EV_BLOCK(UCF,	0x12000)	\
+	__PMC_EV_UCF()				\
+	__PMC_EV_BLOCK(UCP,	0x12080)	\
+	__PMC_EV_UCP()				\
+
+#define	PMC_EVENT_FIRST	PMC_EV_TSC_TSC
+#define	PMC_EVENT_LAST	PMC_EV_UCP_LAST
+
+#endif /* _DEV_HWPMC_PMC_EVENTS_H_ */
diff --git a/sys/kern/kern_pmc.c b/sys/kern/kern_pmc.c
new file mode 100644
index 0000000..c3516a9
--- /dev/null
+++ b/sys/kern/kern_pmc.c
@@ -0,0 +1,184 @@
+/*-
+ * Copyright (c) 2003-2008 Joseph Koshy
+ * Copyright (c) 2007 The FreeBSD Foundation
+ * All rights reserved.
+ *
+ * Portions of this software were developed by A. Joseph Koshy under
+ * sponsorship from the FreeBSD Foundation and Google, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: src/sys/kern/kern_pmc.c,v 1.9 2011/02/25 10:11:01 netchild Exp $");
+
+#include "opt_hwpmc_hooks.h"
+
+#include <sys/types.h>
+#include <sys/pmc.h>
+#include <sys/pmckern.h>
+#include <sys/smp.h>
+#include <sys/sysctl.h>
+
+#ifdef	HWPMC_HOOKS
+FEATURE(hwpmc_hooks, "Kernel support for HW PMC");
+#define	PMC_KERNEL_VERSION	PMC_VERSION
+#else
+#define	PMC_KERNEL_VERSION	0
+#endif
+
+const int pmc_kernel_version = PMC_KERNEL_VERSION;
+
+/* Hook variable. */
+int (*pmc_hook)(struct thread *td, int function, void *arg) = NULL;
+
+/* Interrupt handler */
+int (*pmc_intr)(int cpu, struct trapframe *tf) = NULL;
+
+/* Bitmask of CPUs requiring servicing at hardclock time */
+volatile cpumask_t pmc_cpumask;
+
+/*
+ * A global count of SS mode PMCs.  When non-zero, this means that
+ * we have processes that are sampling the system as a whole.
+ */
+volatile int pmc_ss_count;
+
+/*
+ * Since PMC(4) may not be loaded in the current kernel, the
+ * convention followed is that a non-NULL value of 'pmc_hook' implies
+ * the presence of this kernel module.
+ *
+ * This requires us to protect 'pmc_hook' with a
+ * shared (sx) lock -- thus making the process of calling into PMC(4)
+ * somewhat more expensive than a simple 'if' check and indirect call.
+ */
+struct sx pmc_sx;
+
+static void
+pmc_init_sx(void)
+{
+	sx_init_flags(&pmc_sx, "pmc-sx", SX_NOWITNESS);
+}
+
+SYSINIT(pmcsx, SI_SUB_LOCK, SI_ORDER_MIDDLE, pmc_init_sx, NULL);
+
+/*
+ * Helper functions.
+ */
+
+/*
+ * A note on the CPU numbering scheme used by the hwpmc(4) driver.
+ *
+ * CPUs are denoted using numbers in the range 0..[pmc_cpu_max()-1].
+ * CPUs could be numbered "sparsely" in this range; the predicate
+ * `pmc_cpu_is_present()' is used to test whether a given CPU is
+ * physically present.
+ *
+ * Further, a CPU that is physically present may be administratively
+ * disabled or otherwise unavailable for use by hwpmc(4).  The
+ * `pmc_cpu_is_active()' predicate tests for CPU usability.  An
+ * "active" CPU participates in thread scheduling and can field
+ * interrupts raised by PMC hardware.
+ *
+ * On systems with hyperthreaded CPUs, multiple logical CPUs may share
+ * PMC hardware resources.  For such processors one logical CPU is
+ * denoted as the primary owner of the in-CPU PMC resources. The
+ * pmc_cpu_is_primary() predicate is used to distinguish this primary
+ * CPU from the others.
+ */
+
+int
+pmc_cpu_is_active(int cpu)
+{
+#ifdef	SMP
+	return (pmc_cpu_is_present(cpu) &&
+	    (hlt_cpus_mask & (1 << cpu)) == 0);
+#else
+	return (1);
+#endif
+}
+
+/* Deprecated. */
+int
+pmc_cpu_is_disabled(int cpu)
+{
+	return (!pmc_cpu_is_active(cpu));
+}
+
+int
+pmc_cpu_is_present(int cpu)
+{
+#ifdef	SMP
+	return (!CPU_ABSENT(cpu));
+#else
+	return (1);
+#endif
+}
+
+int
+pmc_cpu_is_primary(int cpu)
+{
+#ifdef	SMP
+	return ((logical_cpus_mask & (1 << cpu)) == 0);
+#else
+	return (1);
+#endif
+}
+
+
+/*
+ * Return the maximum CPU number supported by the system.  The return
+ * value is used for scaling internal data structures and for runtime
+ * checks.
+ */
+unsigned int
+pmc_cpu_max(void)
+{
+#ifdef	SMP
+	return (mp_maxid+1);
+#else
+	return (1);
+#endif
+}
+
+#ifdef	INVARIANTS
+
+/*
+ * Return the count of CPUs in the `active' state in the system.
+ */
+int
+pmc_cpu_max_active(void)
+{
+#ifdef	SMP
+	/*
+	 * When support for CPU hot-plugging is added to the kernel,
+	 * this function would change to return the current number
+	 * of "active" CPUs.
+	 */
+	return (mp_ncpus);
+#else
+	return (1);
+#endif
+}
+
+#endif
diff --git a/sys/sys/pmc.h b/sys/sys/pmc.h
new file mode 100644
index 0000000..00e4814
--- /dev/null
+++ b/sys/sys/pmc.h
@@ -0,0 +1,1064 @@
+/*-
+ * Copyright (c) 2003-2008, Joseph Koshy
+ * Copyright (c) 2007 The FreeBSD Foundation
+ * All rights reserved.
+ *
+ * Portions of this software were developed by A. Joseph Koshy under
+ * sponsorship from the FreeBSD Foundation and Google, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: src/sys/sys/pmc.h,v 1.30 2010/06/15 09:12:31 fabient Exp $
+ */
+
+#ifndef _SYS_PMC_H_
+#define	_SYS_PMC_H_
+
+#include <dev/hwpmc/pmc_events.h>
+
+#include <machine/pmc_mdep.h>
+#include <machine/profile.h>
+
+#define	PMC_MODULE_NAME		"hwpmc"
+#define	PMC_NAME_MAX		16 /* HW counter name size */
+#define	PMC_CLASS_MAX		6  /* max #classes of PMCs per-system */
+
+/*
+ * Kernel<->userland API version number [MMmmpppp]
+ *
+ * Major numbers are to be incremented when an incompatible change to
+ * the ABI occurs that older clients will not be able to handle.
+ *
+ * Minor numbers are incremented when a backwards compatible change
+ * occurs that allows older correct programs to run unchanged.  For
+ * example, when support for a new PMC type is added.
+ *
+ * The patch version is incremented for every bug fix.
+ */
+#define	PMC_VERSION_MAJOR	0x03
+#define	PMC_VERSION_MINOR	0x01
+#define	PMC_VERSION_PATCH	0x0000
+
+#define	PMC_VERSION		(PMC_VERSION_MAJOR << 24 |		\
+	PMC_VERSION_MINOR << 16 | PMC_VERSION_PATCH)
+
+/*
+ * Kinds of CPUs known.
+ *
+ * We keep track of CPU variants that need to be distinguished in
+ * some way for PMC operations.  CPU names are grouped by manufacturer
+ * and numbered sparsely in order to minimize changes to the ABI involved
+ * when new CPUs are added.
+ */
+
+#define	__PMC_CPUS()						\
+	__PMC_CPU(AMD_K7,	0x00,	"AMD K7")		\
+	__PMC_CPU(AMD_K8,	0x01,	"AMD K8")		\
+	__PMC_CPU(INTEL_P5,	0x80,	"Intel Pentium")	\
+	__PMC_CPU(INTEL_P6,	0x81,	"Intel Pentium Pro")	\
+	__PMC_CPU(INTEL_CL,	0x82,	"Intel Celeron")	\
+	__PMC_CPU(INTEL_PII,	0x83,	"Intel Pentium II")	\
+	__PMC_CPU(INTEL_PIII,	0x84,	"Intel Pentium III")	\
+	__PMC_CPU(INTEL_PM,	0x85,	"Intel Pentium M")	\
+	__PMC_CPU(INTEL_PIV,	0x86,	"Intel Pentium IV")	\
+	__PMC_CPU(INTEL_CORE,	0x87,	"Intel Core Solo/Duo")	\
+	__PMC_CPU(INTEL_CORE2,	0x88,	"Intel Core2")		\
+	__PMC_CPU(INTEL_CORE2EXTREME,	0x89,	"Intel Core2 Extreme")	\
+	__PMC_CPU(INTEL_ATOM,	0x8A,	"Intel Atom") \
+	__PMC_CPU(INTEL_COREI7, 0x8B,   "Intel Core i7") \
+	__PMC_CPU(INTEL_WESTMERE, 0x8C,   "Intel Westmere") \
+	__PMC_CPU(INTEL_XSCALE,	0x100,	"Intel XScale") \
+	__PMC_CPU(MIPS_24K,     0x200,  "MIPS 24K")
+
+enum pmc_cputype {
+#undef	__PMC_CPU
+#define	__PMC_CPU(S,V,D)	PMC_CPU_##S = V,
+	__PMC_CPUS()
+};
+
+#define	PMC_CPU_FIRST	PMC_CPU_AMD_K7
+#define	PMC_CPU_LAST	PMC_CPU_MIPS_24K
+
+/*
+ * Classes of PMCs
+ */
+
+#define	__PMC_CLASSES()							\
+	__PMC_CLASS(TSC)	/* CPU Timestamp counter */		\
+	__PMC_CLASS(K7)		/* AMD K7 performance counters */	\
+	__PMC_CLASS(K8)		/* AMD K8 performance counters */	\
+	__PMC_CLASS(P5)		/* Intel Pentium counters */		\
+	__PMC_CLASS(P6)		/* Intel Pentium Pro counters */	\
+	__PMC_CLASS(P4)		/* Intel Pentium-IV counters */		\
+	__PMC_CLASS(IAF)	/* Intel Core2/Atom, fixed function */	\
+	__PMC_CLASS(IAP)	/* Intel Core...Atom, programmable */	\
+	__PMC_CLASS(UCF)	/* Intel Uncore fixed function */	\
+	__PMC_CLASS(UCP)	/* Intel Uncore programmable */		\
+	__PMC_CLASS(XSCALE)	/* Intel XScale counters */		\
+	__PMC_CLASS(MIPS24K)    /* MIPS 24K */
+
+enum pmc_class {
+#undef  __PMC_CLASS
+#define	__PMC_CLASS(N)	PMC_CLASS_##N ,
+	__PMC_CLASSES()
+};
+
+#define	PMC_CLASS_FIRST	PMC_CLASS_TSC
+#define	PMC_CLASS_LAST	PMC_CLASS_MIPS24K
+
+/*
+ * A PMC can be in the following states:
+ *
+ * Hardware states:
+ *   DISABLED   -- administratively prohibited from being used.
+ *   FREE       -- HW available for use
+ * Software states:
+ *   ALLOCATED  -- allocated
+ *   STOPPED    -- allocated, but not counting events
+ *   RUNNING    -- allocated, and in operation; 'pm_runcount'
+ *                 holds the number of CPUs using this PMC at
+ *                 a given instant
+ *   DELETED    -- being destroyed
+ */
+
+#define	__PMC_HWSTATES()			\
+	__PMC_STATE(DISABLED)			\
+	__PMC_STATE(FREE)
+
+#define	__PMC_SWSTATES()			\
+	__PMC_STATE(ALLOCATED)			\
+	__PMC_STATE(STOPPED)			\
+	__PMC_STATE(RUNNING)			\
+	__PMC_STATE(DELETED)
+
+#define	__PMC_STATES()				\
+	__PMC_HWSTATES()			\
+	__PMC_SWSTATES()
+
+enum pmc_state {
+#undef	__PMC_STATE
+#define	__PMC_STATE(S)	PMC_STATE_##S,
+	__PMC_STATES()
+	__PMC_STATE(MAX)
+};
+
+#define	PMC_STATE_FIRST	PMC_STATE_DISABLED
+#define	PMC_STATE_LAST	PMC_STATE_DELETED
+
+/*
+ * An allocated PMC may used as a 'global' counter or as a
+ * 'thread-private' one.  Each such mode of use can be in either
+ * statistical sampling mode or in counting mode.  Thus a PMC in use
+ *
+ * SS i.e., SYSTEM STATISTICAL  -- system-wide statistical profiling
+ * SC i.e., SYSTEM COUNTER      -- system-wide counting mode
+ * TS i.e., THREAD STATISTICAL  -- thread virtual, statistical profiling
+ * TC i.e., THREAD COUNTER      -- thread virtual, counting mode
+ *
+ * Statistical profiling modes rely on the PMC periodically delivering
+ * a interrupt to the CPU (when the configured number of events have
+ * been measured), so the PMC must have the ability to generate
+ * interrupts.
+ *
+ * In counting modes, the PMC counts its configured events, with the
+ * value of the PMC being read whenever needed by its owner process.
+ *
+ * The thread specific modes "virtualize" the PMCs -- the PMCs appear
+ * to be thread private and count events only when the profiled thread
+ * actually executes on the CPU.
+ *
+ * The system-wide "global" modes keep the PMCs running all the time
+ * and are used to measure the behaviour of the whole system.
+ */
+
+#define	__PMC_MODES()				\
+	__PMC_MODE(SS,	0)			\
+	__PMC_MODE(SC,	1)			\
+	__PMC_MODE(TS,	2)			\
+	__PMC_MODE(TC,	3)
+
+enum pmc_mode {
+#undef	__PMC_MODE
+#define	__PMC_MODE(M,N)	PMC_MODE_##M = N,
+	__PMC_MODES()
+};
+
+#define	PMC_MODE_FIRST	PMC_MODE_SS
+#define	PMC_MODE_LAST	PMC_MODE_TC
+
+#define	PMC_IS_COUNTING_MODE(mode)				\
+	((mode) == PMC_MODE_SC || (mode) == PMC_MODE_TC)
+#define	PMC_IS_SYSTEM_MODE(mode)				\
+	((mode) == PMC_MODE_SS || (mode) == PMC_MODE_SC)
+#define	PMC_IS_SAMPLING_MODE(mode)				\
+	((mode) == PMC_MODE_SS || (mode) == PMC_MODE_TS)
+#define	PMC_IS_VIRTUAL_MODE(mode)				\
+	((mode) == PMC_MODE_TS || (mode) == PMC_MODE_TC)
+
+/*
+ * PMC row disposition
+ */
+
+#define	__PMC_DISPOSITIONS(N)					\
+	__PMC_DISP(STANDALONE)	/* global/disabled counters */	\
+	__PMC_DISP(FREE)	/* free/available */		\
+	__PMC_DISP(THREAD)	/* thread-virtual PMCs */	\
+	__PMC_DISP(UNKNOWN)	/* sentinel */
+
+enum pmc_disp {
+#undef	__PMC_DISP
+#define	__PMC_DISP(D)	PMC_DISP_##D ,
+	__PMC_DISPOSITIONS()
+};
+
+#define	PMC_DISP_FIRST	PMC_DISP_STANDALONE
+#define	PMC_DISP_LAST	PMC_DISP_THREAD
+
+/*
+ * Counter capabilities
+ *
+ * __PMC_CAPS(NAME, VALUE, DESCRIPTION)
+ */
+
+#define	__PMC_CAPS()							\
+	__PMC_CAP(INTERRUPT,	0, "generate interrupts")		\
+	__PMC_CAP(USER,		1, "count user-mode events")		\
+	__PMC_CAP(SYSTEM,	2, "count system-mode events")		\
+	__PMC_CAP(EDGE,		3, "do edge detection of events")	\
+	__PMC_CAP(THRESHOLD,	4, "ignore events below a threshold")	\
+	__PMC_CAP(READ,		5, "read PMC counter")			\
+	__PMC_CAP(WRITE,	6, "reprogram PMC counter")		\
+	__PMC_CAP(INVERT,	7, "invert comparision sense")		\
+	__PMC_CAP(QUALIFIER,	8, "further qualify monitored events")	\
+	__PMC_CAP(PRECISE,	9, "perform precise sampling")		\
+	__PMC_CAP(TAGGING,	10, "tag upstream events")		\
+	__PMC_CAP(CASCADE,	11, "cascade counters")
+
+enum pmc_caps
+{
+#undef	__PMC_CAP
+#define	__PMC_CAP(NAME, VALUE, DESCR)	PMC_CAP_##NAME = (1 << VALUE) ,
+	__PMC_CAPS()
+};
+
+#define	PMC_CAP_FIRST		PMC_CAP_INTERRUPT
+#define	PMC_CAP_LAST		PMC_CAP_CASCADE
+
+/*
+ * PMC Event Numbers
+ *
+ * These are generated from the definitions in "dev/hwpmc/pmc_events.h".
+ */
+
+enum pmc_event {
+#undef	__PMC_EV
+#undef	__PMC_EV_BLOCK
+#define	__PMC_EV_BLOCK(C,V)	PMC_EV_ ## C ## __BLOCK_START = (V) - 1 ,
+#define	__PMC_EV(C,N)		PMC_EV_ ## C ## _ ## N ,
+	__PMC_EVENTS()
+};
+
+/*
+ * PMC SYSCALL INTERFACE
+ */
+
+/*
+ * "PMC_OPS" -- these are the commands recognized by the kernel
+ * module, and are used when performing a system call from userland.
+ */
+#define	__PMC_OPS()							\
+	__PMC_OP(CONFIGURELOG, "Set log file")				\
+	__PMC_OP(FLUSHLOG, "Flush log file")				\
+	__PMC_OP(GETCPUINFO, "Get system CPU information")		\
+	__PMC_OP(GETDRIVERSTATS, "Get driver statistics")		\
+	__PMC_OP(GETMODULEVERSION, "Get module version")		\
+	__PMC_OP(GETPMCINFO, "Get per-cpu PMC information")		\
+	__PMC_OP(PMCADMIN, "Set PMC state")				\
+	__PMC_OP(PMCALLOCATE, "Allocate and configure a PMC")		\
+	__PMC_OP(PMCATTACH, "Attach a PMC to a process")		\
+	__PMC_OP(PMCDETACH, "Detach a PMC from a process")		\
+	__PMC_OP(PMCGETMSR, "Get a PMC's hardware address")		\
+	__PMC_OP(PMCRELEASE, "Release a PMC")				\
+	__PMC_OP(PMCRW, "Read/Set a PMC")				\
+	__PMC_OP(PMCSETCOUNT, "Set initial count/sampling rate")	\
+	__PMC_OP(PMCSTART, "Start a PMC")				\
+	__PMC_OP(PMCSTOP, "Stop a PMC")					\
+	__PMC_OP(WRITELOG, "Write a cookie to the log file")
+
+
+enum pmc_ops {
+#undef	__PMC_OP
+#define	__PMC_OP(N, D)	PMC_OP_##N,
+	__PMC_OPS()
+};
+
+
+/*
+ * Flags used in operations on PMCs.
+ */
+
+#define	PMC_F_FORCE		0x00000001 /*OP ADMIN force operation */
+#define	PMC_F_DESCENDANTS	0x00000002 /*OP ALLOCATE track descendants */
+#define	PMC_F_LOG_PROCCSW	0x00000004 /*OP ALLOCATE track ctx switches */
+#define	PMC_F_LOG_PROCEXIT	0x00000008 /*OP ALLOCATE log proc exits */
+#define	PMC_F_NEWVALUE		0x00000010 /*OP RW write new value */
+#define	PMC_F_OLDVALUE		0x00000020 /*OP RW get old value */
+#define	PMC_F_KGMON		0x00000040 /*OP ALLOCATE kgmon(8) profiling */
+/* V2 API */
+#define	PMC_F_CALLCHAIN		0x00000080 /*OP ALLOCATE capture callchains */
+
+/* internal flags */
+#define	PMC_F_ATTACHED_TO_OWNER	0x00010000 /*attached to owner*/
+#define	PMC_F_NEEDS_LOGFILE	0x00020000 /*needs log file */
+#define	PMC_F_ATTACH_DONE	0x00040000 /*attached at least once */
+
+#define	PMC_CALLCHAIN_DEPTH_MAX	32
+#define	PMC_CC_F_USERSPACE	0x01	   /*userspace callchain*/
+
+/*
+ * Cookies used to denote allocated PMCs, and the values of PMCs.
+ */
+
+typedef uint32_t	pmc_id_t;
+typedef uint64_t	pmc_value_t;
+
+#define	PMC_ID_INVALID		(~ (pmc_id_t) 0)
+
+/*
+ * PMC IDs have the following format:
+ *
+ * +--------+----------+-----------+-----------+
+ * |   CPU  | PMC MODE | PMC CLASS | ROW INDEX |
+ * +--------+----------+-----------+-----------+
+ *
+ * where each field is 8 bits wide.  Field 'CPU' is set to the
+ * requested CPU for system-wide PMCs or PMC_CPU_ANY for process-mode
+ * PMCs.  Field 'PMC MODE' is the allocated PMC mode.  Field 'PMC
+ * CLASS' is the class of the PMC.  Field 'ROW INDEX' is the row index
+ * for the PMC.
+ *
+ * The 'ROW INDEX' ranges over 0..NWPMCS where NHWPMCS is the total
+ * number of hardware PMCs on this cpu.
+ */
+
+
+#define	PMC_ID_TO_ROWINDEX(ID)	((ID) & 0xFF)
+#define	PMC_ID_TO_CLASS(ID)	(((ID) & 0xFF00) >> 8)
+#define	PMC_ID_TO_MODE(ID)	(((ID) & 0xFF0000) >> 16)
+#define	PMC_ID_TO_CPU(ID)	(((ID) & 0xFF000000) >> 24)
+#define	PMC_ID_MAKE_ID(CPU,MODE,CLASS,ROWINDEX)			\
+	((((CPU) & 0xFF) << 24) | (((MODE) & 0xFF) << 16) |	\
+	(((CLASS) & 0xFF) << 8) | ((ROWINDEX) & 0xFF))
+
+/*
+ * Data structures for system calls supported by the pmc driver.
+ */
+
+/*
+ * OP PMCALLOCATE
+ *
+ * Allocate a PMC on the named CPU.
+ */
+
+#define	PMC_CPU_ANY	~0
+
+struct pmc_op_pmcallocate {
+	uint32_t	pm_caps;	/* PMC_CAP_* */
+	uint32_t	pm_cpu;		/* CPU number or PMC_CPU_ANY */
+	enum pmc_class	pm_class;	/* class of PMC desired */
+	enum pmc_event	pm_ev;		/* [enum pmc_event] desired */
+	uint32_t	pm_flags;	/* additional modifiers PMC_F_* */
+	enum pmc_mode	pm_mode;	/* desired mode */
+	pmc_id_t	pm_pmcid;	/* [return] process pmc id */
+
+	union pmc_md_op_pmcallocate pm_md; /* MD layer extensions */
+};
+
+/*
+ * OP PMCADMIN
+ *
+ * Set the administrative state (i.e., whether enabled or disabled) of
+ * a PMC 'pm_pmc' on CPU 'pm_cpu'.  Note that 'pm_pmc' specifies an
+ * absolute PMC number and need not have been first allocated by the
+ * calling process.
+ */
+
+struct pmc_op_pmcadmin {
+	int		pm_cpu;		/* CPU# */
+	uint32_t	pm_flags;	/* flags */
+	int		pm_pmc;         /* PMC# */
+	enum pmc_state  pm_state;	/* desired state */
+};
+
+/*
+ * OP PMCATTACH / OP PMCDETACH
+ *
+ * Attach/detach a PMC and a process.
+ */
+
+struct pmc_op_pmcattach {
+	pmc_id_t	pm_pmc;		/* PMC to attach to */
+	pid_t		pm_pid;		/* target process */
+};
+
+/*
+ * OP PMCSETCOUNT
+ *
+ * Set the sampling rate (i.e., the reload count) for statistical counters.
+ * 'pm_pmcid' need to have been previously allocated using PMCALLOCATE.
+ */
+
+struct pmc_op_pmcsetcount {
+	pmc_value_t	pm_count;	/* initial/sample count */
+	pmc_id_t	pm_pmcid;	/* PMC id to set */
+};
+
+
+/*
+ * OP PMCRW
+ *
+ * Read the value of a PMC named by 'pm_pmcid'.  'pm_pmcid' needs
+ * to have been previously allocated using PMCALLOCATE.
+ */
+
+
+struct pmc_op_pmcrw {
+	uint32_t	pm_flags;	/* PMC_F_{OLD,NEW}VALUE*/
+	pmc_id_t	pm_pmcid;	/* pmc id */
+	pmc_value_t	pm_value;	/* new&returned value */
+};
+
+
+/*
+ * OP GETPMCINFO
+ *
+ * retrieve PMC state for a named CPU.  The caller is expected to
+ * allocate 'npmc' * 'struct pmc_info' bytes of space for the return
+ * values.
+ */
+
+struct pmc_info {
+	char		pm_name[PMC_NAME_MAX]; /* pmc name */
+	enum pmc_class	pm_class;	/* enum pmc_class */
+	int		pm_enabled;	/* whether enabled */
+	enum pmc_disp	pm_rowdisp;	/* FREE, THREAD or STANDLONE */
+	pid_t		pm_ownerpid;	/* owner, or -1 */
+	enum pmc_mode	pm_mode;	/* current mode [enum pmc_mode] */
+	enum pmc_event	pm_event;	/* current event */
+	uint32_t	pm_flags;	/* current flags */
+	pmc_value_t	pm_reloadcount;	/* sampling counters only */
+};
+
+struct pmc_op_getpmcinfo {
+	int32_t		pm_cpu;		/* 0 <= cpu < mp_maxid */
+	struct pmc_info	pm_pmcs[];	/* space for 'npmc' structures */
+};
+
+
+/*
+ * OP GETCPUINFO
+ *
+ * Retrieve system CPU information.
+ */
+
+struct pmc_classinfo {
+	enum pmc_class	pm_class;	/* class id */
+	uint32_t	pm_caps;	/* counter capabilities */
+	uint32_t	pm_width;	/* width of the PMC */
+	uint32_t	pm_num;		/* number of PMCs in class */
+};
+
+struct pmc_op_getcpuinfo {
+	enum pmc_cputype pm_cputype; /* what kind of CPU */
+	uint32_t	pm_ncpu;    /* max CPU number */
+	uint32_t	pm_npmc;    /* #PMCs per CPU */
+	uint32_t	pm_nclass;  /* #classes of PMCs */
+	struct pmc_classinfo  pm_classes[PMC_CLASS_MAX];
+};
+
+/*
+ * OP CONFIGURELOG
+ *
+ * Configure a log file for writing system-wide statistics to.
+ */
+
+struct pmc_op_configurelog {
+	int		pm_flags;
+	int		pm_logfd;   /* logfile fd (or -1) */
+};
+
+/*
+ * OP GETDRIVERSTATS
+ *
+ * Retrieve pmc(4) driver-wide statistics.
+ */
+
+struct pmc_op_getdriverstats {
+	int	pm_intr_ignored;	/* #interrupts ignored */
+	int	pm_intr_processed;	/* #interrupts processed */
+	int	pm_intr_bufferfull;	/* #interrupts with ENOSPC */
+	int	pm_syscalls;		/* #syscalls */
+	int	pm_syscall_errors;	/* #syscalls with errors */
+	int	pm_buffer_requests;	/* #buffer requests */
+	int	pm_buffer_requests_failed; /* #failed buffer requests */
+	int	pm_log_sweeps;		/* #sample buffer processing passes */
+};
+
+/*
+ * OP RELEASE / OP START / OP STOP
+ *
+ * Simple operations on a PMC id.
+ */
+
+struct pmc_op_simple {
+	pmc_id_t	pm_pmcid;
+};
+
+/*
+ * OP WRITELOG
+ *
+ * Flush the current log buffer and write 4 bytes of user data to it.
+ */
+
+struct pmc_op_writelog {
+	uint32_t	pm_userdata;
+};
+
+/*
+ * OP GETMSR
+ *
+ * Retrieve the machine specific address assoicated with the allocated
+ * PMC.  This number can be used subsequently with a read-performance-counter
+ * instruction.
+ */
+
+struct pmc_op_getmsr {
+	uint32_t	pm_msr;		/* machine specific address */
+	pmc_id_t	pm_pmcid;	/* allocated pmc id */
+};
+
+#ifdef _KERNEL
+
+#include <sys/malloc.h>
+#include <sys/sysctl.h>
+
+#include <machine/frame.h>
+
+#define	PMC_HASH_SIZE				16
+#define	PMC_MTXPOOL_SIZE			32
+#define	PMC_LOG_BUFFER_SIZE			4
+#define	PMC_NLOGBUFFERS				16
+#define	PMC_NSAMPLES				32
+#define	PMC_CALLCHAIN_DEPTH			8
+
+#define PMC_SYSCTL_NAME_PREFIX "kern." PMC_MODULE_NAME "."
+
+/*
+ * Locking keys
+ *
+ * (b) - pmc_bufferlist_mtx (spin lock)
+ * (k) - pmc_kthread_mtx (sleep lock)
+ * (o) - po->po_mtx (spin lock)
+ */
+
+/*
+ * PMC commands
+ */
+
+struct pmc_syscall_args {
+	uint32_t	pmop_code;	/* one of PMC_OP_* */
+	void		*pmop_data;	/* syscall parameter */
+};
+
+/*
+ * Interface to processor specific s1tuff
+ */
+
+/*
+ * struct pmc_descr
+ *
+ * Machine independent (i.e., the common parts) of a human readable
+ * PMC description.
+ */
+
+struct pmc_descr {
+	char		pd_name[PMC_NAME_MAX]; /* name */
+	uint32_t	pd_caps;	/* capabilities */
+	enum pmc_class	pd_class;	/* class of the PMC */
+	uint32_t	pd_width;	/* width in bits */
+};
+
+/*
+ * struct pmc_target
+ *
+ * This structure records all the target processes associated with a
+ * PMC.
+ */
+
+struct pmc_target {
+	LIST_ENTRY(pmc_target)	pt_next;
+	struct pmc_process	*pt_process; /* target descriptor */
+};
+
+/*
+ * struct pmc
+ *
+ * Describes each allocated PMC.
+ *
+ * Each PMC has precisely one owner, namely the process that allocated
+ * the PMC.
+ *
+ * A PMC may be attached to multiple target processes.  The
+ * 'pm_targets' field links all the target processes being monitored
+ * by this PMC.
+ *
+ * The 'pm_savedvalue' field is protected by a mutex.
+ *
+ * On a multi-cpu machine, multiple target threads associated with a
+ * process-virtual PMC could be concurrently executing on different
+ * CPUs.  The 'pm_runcount' field is atomically incremented every time
+ * the PMC gets scheduled on a CPU and atomically decremented when it
+ * get descheduled.  Deletion of a PMC is only permitted when this
+ * field is '0'.
+ *
+ */
+
+struct pmc {
+	LIST_HEAD(,pmc_target)	pm_targets;	/* list of target processes */
+	LIST_ENTRY(pmc)		pm_next;	/* owner's list */
+
+	/*
+	 * System-wide PMCs are allocated on a CPU and are not moved
+	 * around.  For system-wide PMCs we record the CPU the PMC was
+	 * allocated on in the 'CPU' field of the pmc ID.
+	 *
+	 * Virtual PMCs run on whichever CPU is currently executing
+	 * their targets' threads.  For these PMCs we need to save
+	 * their current PMC counter values when they are taken off
+	 * CPU.
+	 */
+
+	union {
+		pmc_value_t	pm_savedvalue;	/* Virtual PMCS */
+	} pm_gv;
+
+	/*
+	 * For sampling mode PMCs, we keep track of the PMC's "reload
+	 * count", which is the counter value to be loaded in when
+	 * arming the PMC for the next counting session.  For counting
+	 * modes on PMCs that are read-only (e.g., the x86 TSC), we
+	 * keep track of the initial value at the start of
+	 * counting-mode operation.
+	 */
+
+	union {
+		pmc_value_t	pm_reloadcount;	/* sampling PMC modes */
+		pmc_value_t	pm_initial;	/* counting PMC modes */
+	} pm_sc;
+
+	uint32_t	pm_stalled;	/* marks stalled sampling PMCs */
+	uint32_t	pm_caps;	/* PMC capabilities */
+	enum pmc_event	pm_event;	/* event being measured */
+	uint32_t	pm_flags;	/* additional flags PMC_F_... */
+	struct pmc_owner *pm_owner;	/* owner thread state */
+	int		pm_runcount;	/* #cpus currently on */
+	enum pmc_state	pm_state;	/* current PMC state */
+
+	/*
+	 * The PMC ID field encodes the row-index for the PMC, its
+	 * mode, class and the CPU# associated with the PMC.
+	 */
+
+	pmc_id_t	pm_id;		/* allocated PMC id */
+
+	/* md extensions */
+	union pmc_md_pmc	pm_md;
+};
+
+/*
+ * Accessor macros for 'struct pmc'
+ */
+
+#define	PMC_TO_MODE(P)		PMC_ID_TO_MODE((P)->pm_id)
+#define	PMC_TO_CLASS(P)		PMC_ID_TO_CLASS((P)->pm_id)
+#define	PMC_TO_ROWINDEX(P)	PMC_ID_TO_ROWINDEX((P)->pm_id)
+#define	PMC_TO_CPU(P)		PMC_ID_TO_CPU((P)->pm_id)
+
+
+/*
+ * struct pmc_process
+ *
+ * Record a 'target' process being profiled.
+ *
+ * The target process being profiled could be different from the owner
+ * process which allocated the PMCs.  Each target process descriptor
+ * is associated with NHWPMC 'struct pmc *' pointers.  Each PMC at a
+ * given hardware row-index 'n' will use slot 'n' of the 'pp_pmcs[]'
+ * array.  The size of this structure is thus PMC architecture
+ * dependent.
+ *
+ */
+
+struct pmc_targetstate {
+	struct pmc	*pp_pmc;   /* target PMC */
+	pmc_value_t	pp_pmcval; /* per-process value */
+};
+
+struct pmc_process {
+	LIST_ENTRY(pmc_process) pp_next;	/* hash chain */
+	int		pp_refcnt;		/* reference count */
+	uint32_t	pp_flags;		/* flags PMC_PP_* */
+	struct proc	*pp_proc;		/* target thread */
+	struct pmc_targetstate pp_pmcs[];       /* NHWPMCs */
+};
+
+#define	PMC_PP_ENABLE_MSR_ACCESS	0x00000001
+
+/*
+ * struct pmc_owner
+ *
+ * We associate a PMC with an 'owner' process.
+ *
+ * A process can be associated with 0..NCPUS*NHWPMC PMCs during its
+ * lifetime, where NCPUS is the numbers of CPUS in the system and
+ * NHWPMC is the number of hardware PMCs per CPU.  These are
+ * maintained in the list headed by the 'po_pmcs' to save on space.
+ *
+ */
+
+struct pmc_owner  {
+	LIST_ENTRY(pmc_owner)	po_next;	/* hash chain */
+	LIST_ENTRY(pmc_owner)	po_ssnext;	/* list of SS PMC owners */
+	LIST_HEAD(, pmc)	po_pmcs;	/* owned PMC list */
+	TAILQ_HEAD(, pmclog_buffer) po_logbuffers; /* (o) logbuffer list */
+	struct mtx		po_mtx;		/* spin lock for (o) */
+	struct proc		*po_owner;	/* owner proc */
+	uint32_t		po_flags;	/* (k) flags PMC_PO_* */
+	struct proc		*po_kthread;	/* (k) helper kthread */
+	struct pmclog_buffer	*po_curbuf;	/* current log buffer */
+	struct file		*po_file;	/* file reference */
+	int			po_error;	/* recorded error */
+	short			po_sscount;	/* # SS PMCs owned */
+	short			po_logprocmaps;	/* global mappings done */
+};
+
+#define	PMC_PO_OWNS_LOGFILE		0x00000001 /* has a log file */
+#define	PMC_PO_SHUTDOWN			0x00000010 /* in the process of shutdown */
+#define	PMC_PO_INITIAL_MAPPINGS_DONE	0x00000020
+
+/*
+ * struct pmc_hw -- describe the state of the PMC hardware
+ *
+ * When in use, a HW PMC is associated with one allocated 'struct pmc'
+ * pointed to by field 'phw_pmc'.  When inactive, this field is NULL.
+ *
+ * On an SMP box, one or more HW PMC's in process virtual mode with
+ * the same 'phw_pmc' could be executing on different CPUs.  In order
+ * to handle this case correctly, we need to ensure that only
+ * incremental counts get added to the saved value in the associated
+ * 'struct pmc'.  The 'phw_save' field is used to keep the saved PMC
+ * value at the time the hardware is started during this context
+ * switch (i.e., the difference between the new (hardware) count and
+ * the saved count is atomically added to the count field in 'struct
+ * pmc' at context switch time).
+ *
+ */
+
+struct pmc_hw {
+	uint32_t	phw_state;	/* see PHW_* macros below */
+	struct pmc	*phw_pmc;	/* current thread PMC */
+};
+
+#define	PMC_PHW_RI_MASK		0x000000FF
+#define	PMC_PHW_CPU_SHIFT	8
+#define	PMC_PHW_CPU_MASK	0x0000FF00
+#define	PMC_PHW_FLAGS_SHIFT	16
+#define	PMC_PHW_FLAGS_MASK	0xFFFF0000
+
+#define	PMC_PHW_INDEX_TO_STATE(ri)	((ri) & PMC_PHW_RI_MASK)
+#define	PMC_PHW_STATE_TO_INDEX(state)	((state) & PMC_PHW_RI_MASK)
+#define	PMC_PHW_CPU_TO_STATE(cpu)	(((cpu) << PMC_PHW_CPU_SHIFT) & \
+	PMC_PHW_CPU_MASK)
+#define	PMC_PHW_STATE_TO_CPU(state)	(((state) & PMC_PHW_CPU_MASK) >> \
+	PMC_PHW_CPU_SHIFT)
+#define	PMC_PHW_FLAGS_TO_STATE(flags)	(((flags) << PMC_PHW_FLAGS_SHIFT) & \
+	PMC_PHW_FLAGS_MASK)
+#define	PMC_PHW_STATE_TO_FLAGS(state)	(((state) & PMC_PHW_FLAGS_MASK) >> \
+	PMC_PHW_FLAGS_SHIFT)
+#define	PMC_PHW_FLAG_IS_ENABLED		(PMC_PHW_FLAGS_TO_STATE(0x01))
+#define	PMC_PHW_FLAG_IS_SHAREABLE	(PMC_PHW_FLAGS_TO_STATE(0x02))
+
+/*
+ * struct pmc_sample
+ *
+ * Space for N (tunable) PC samples and associated control data.
+ */
+
+struct pmc_sample {
+	uint16_t		ps_nsamples;	/* callchain depth */
+	uint8_t			ps_cpu;		/* cpu number */
+	uint8_t			ps_flags;	/* other flags */
+	pid_t			ps_pid;		/* process PID or -1 */
+	struct thread		*ps_td;		/* which thread */
+	struct pmc		*ps_pmc;	/* interrupting PMC */
+	uintptr_t		*ps_pc;		/* (const) callchain start */
+};
+
+#define	PMC_SAMPLE_FREE		((uint16_t) 0)
+#define	PMC_SAMPLE_INUSE	((uint16_t) 0xFFFF)
+
+struct pmc_samplebuffer {
+	struct pmc_sample * volatile ps_read;	/* read pointer */
+	struct pmc_sample * volatile ps_write;	/* write pointer */
+	uintptr_t		*ps_callchains;	/* all saved call chains */
+	struct pmc_sample	*ps_fence;	/* one beyond ps_samples[] */
+	struct pmc_sample	ps_samples[];	/* array of sample entries */
+};
+
+
+/*
+ * struct pmc_cpustate
+ *
+ * A CPU is modelled as a collection of HW PMCs with space for additional
+ * flags.
+ */
+
+struct pmc_cpu {
+	uint32_t	pc_state;	/* physical cpu number + flags */
+	struct pmc_samplebuffer *pc_sb; /* space for samples */
+	struct pmc_hw	*pc_hwpmcs[];	/* 'npmc' pointers */
+};
+
+#define	PMC_PCPU_CPU_MASK		0x000000FF
+#define	PMC_PCPU_FLAGS_MASK		0xFFFFFF00
+#define	PMC_PCPU_FLAGS_SHIFT		8
+#define	PMC_PCPU_STATE_TO_CPU(S)	((S) & PMC_PCPU_CPU_MASK)
+#define	PMC_PCPU_STATE_TO_FLAGS(S)	(((S) & PMC_PCPU_FLAGS_MASK) >> PMC_PCPU_FLAGS_SHIFT)
+#define	PMC_PCPU_FLAGS_TO_STATE(F)	(((F) << PMC_PCPU_FLAGS_SHIFT) & PMC_PCPU_FLAGS_MASK)
+#define	PMC_PCPU_CPU_TO_STATE(C)	((C) & PMC_PCPU_CPU_MASK)
+#define	PMC_PCPU_FLAG_HTT		(PMC_PCPU_FLAGS_TO_STATE(0x1))
+
+/*
+ * struct pmc_binding
+ *
+ * CPU binding information.
+ */
+
+struct pmc_binding {
+	int	pb_bound;	/* is bound? */
+	int	pb_cpu;		/* if so, to which CPU */
+};
+
+
+struct pmc_mdep;
+
+/*
+ * struct pmc_classdep
+ *
+ * PMC class-dependent operations.
+ */
+struct pmc_classdep {
+	uint32_t	pcd_caps;	/* class capabilities */
+	enum pmc_class	pcd_class;	/* class id */
+	int		pcd_num;	/* number of PMCs */
+	int		pcd_ri;		/* row index of the first PMC in class */
+	int		pcd_width;	/* width of the PMC */
+
+	/* configuring/reading/writing the hardware PMCs */
+	int (*pcd_config_pmc)(int _cpu, int _ri, struct pmc *_pm);
+	int (*pcd_get_config)(int _cpu, int _ri, struct pmc **_ppm);
+	int (*pcd_read_pmc)(int _cpu, int _ri, pmc_value_t *_value);
+	int (*pcd_write_pmc)(int _cpu, int _ri, pmc_value_t _value);
+
+	/* pmc allocation/release */
+	int (*pcd_allocate_pmc)(int _cpu, int _ri, struct pmc *_t,
+		const struct pmc_op_pmcallocate *_a);
+	int (*pcd_release_pmc)(int _cpu, int _ri, struct pmc *_pm);
+
+	/* starting and stopping PMCs */
+	int (*pcd_start_pmc)(int _cpu, int _ri);
+	int (*pcd_stop_pmc)(int _cpu, int _ri);
+
+	/* description */
+	int (*pcd_describe)(int _cpu, int _ri, struct pmc_info *_pi,
+		struct pmc **_ppmc);
+
+	/* class-dependent initialization & finalization */
+	int (*pcd_pcpu_init)(struct pmc_mdep *_md, int _cpu);
+	int (*pcd_pcpu_fini)(struct pmc_mdep *_md, int _cpu);
+
+	/* machine-specific interface */
+	int (*pcd_get_msr)(int _ri, uint32_t *_msr);
+};
+
+/*
+ * struct pmc_mdep
+ *
+ * Machine dependent bits needed per CPU type.
+ */
+
+struct pmc_mdep  {
+	uint32_t	pmd_cputype;    /* from enum pmc_cputype */
+	uint32_t	pmd_npmc;	/* number of PMCs per CPU */
+	uint32_t	pmd_nclass;	/* number of PMC classes present */
+
+	/*
+	 * Machine dependent methods.
+	 */
+
+	/* per-cpu initialization and finalization */
+	int (*pmd_pcpu_init)(struct pmc_mdep *_md, int _cpu);
+	int (*pmd_pcpu_fini)(struct pmc_mdep *_md, int _cpu);
+
+	/* thread context switch in/out */
+	int (*pmd_switch_in)(struct pmc_cpu *_p, struct pmc_process *_pp);
+	int (*pmd_switch_out)(struct pmc_cpu *_p, struct pmc_process *_pp);
+
+	/* handle a PMC interrupt */
+	int (*pmd_intr)(int _cpu, struct trapframe *_tf);
+
+	/*
+	 * PMC class dependent information.
+	 */
+	struct pmc_classdep pmd_classdep[];
+};
+
+/*
+ * Per-CPU state.  This is an array of 'mp_ncpu' pointers
+ * to struct pmc_cpu descriptors.
+ */
+
+extern struct pmc_cpu **pmc_pcpu;
+
+/* driver statistics */
+extern struct pmc_op_getdriverstats pmc_stats;
+
+#if	defined(DEBUG) && DEBUG
+
+/* debug flags, major flag groups */
+struct pmc_debugflags {
+	int	pdb_CPU;
+	int	pdb_CSW;
+	int	pdb_LOG;
+	int	pdb_MDP;
+	int	pdb_MOD;
+	int	pdb_OWN;
+	int	pdb_PMC;
+	int	pdb_PRC;
+	int	pdb_SAM;
+};
+
+extern struct pmc_debugflags pmc_debugflags;
+
+#define	PMC_DEBUG_STRSIZE		128
+#define	PMC_DEBUG_DEFAULT_FLAGS		{ 0, 0, 0, 0, 0, 0, 0, 0 }
+
+#define	PMCDBG(M,N,L,F,...) do {					\
+	if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N))	\
+		printf(#M ":" #N ":" #L  ": " F "\n", __VA_ARGS__);	\
+} while (0)
+
+/* Major numbers */
+#define	PMC_DEBUG_MAJ_CPU		0 /* cpu switches */
+#define	PMC_DEBUG_MAJ_CSW		1 /* context switches */
+#define	PMC_DEBUG_MAJ_LOG		2 /* logging */
+#define	PMC_DEBUG_MAJ_MDP		3 /* machine dependent */
+#define	PMC_DEBUG_MAJ_MOD		4 /* misc module infrastructure */
+#define	PMC_DEBUG_MAJ_OWN		5 /* owner */
+#define	PMC_DEBUG_MAJ_PMC		6 /* pmc management */
+#define	PMC_DEBUG_MAJ_PRC		7 /* processes */
+#define	PMC_DEBUG_MAJ_SAM		8 /* sampling */
+
+/* Minor numbers */
+
+/* Common (8 bits) */
+#define	PMC_DEBUG_MIN_ALL		0 /* allocation */
+#define	PMC_DEBUG_MIN_REL		1 /* release */
+#define	PMC_DEBUG_MIN_OPS		2 /* ops: start, stop, ... */
+#define	PMC_DEBUG_MIN_INI		3 /* init */
+#define	PMC_DEBUG_MIN_FND		4 /* find */
+
+/* MODULE */
+#define	PMC_DEBUG_MIN_PMH	       14 /* pmc_hook */
+#define	PMC_DEBUG_MIN_PMS	       15 /* pmc_syscall */
+
+/* OWN */
+#define	PMC_DEBUG_MIN_ORM		8 /* owner remove */
+#define	PMC_DEBUG_MIN_OMR		9 /* owner maybe remove */
+
+/* PROCESSES */
+#define	PMC_DEBUG_MIN_TLK		8 /* link target */
+#define	PMC_DEBUG_MIN_TUL		9 /* unlink target */
+#define	PMC_DEBUG_MIN_EXT	       10 /* process exit */
+#define	PMC_DEBUG_MIN_EXC	       11 /* process exec */
+#define	PMC_DEBUG_MIN_FRK	       12 /* process fork */
+#define	PMC_DEBUG_MIN_ATT	       13 /* attach/detach */
+#define	PMC_DEBUG_MIN_SIG	       14 /* signalling */
+
+/* CONTEXT SWITCHES */
+#define	PMC_DEBUG_MIN_SWI		8 /* switch in */
+#define	PMC_DEBUG_MIN_SWO		9 /* switch out */
+
+/* PMC */
+#define	PMC_DEBUG_MIN_REG		8 /* pmc register */
+#define	PMC_DEBUG_MIN_ALR		9 /* allocate row */
+
+/* MACHINE DEPENDENT LAYER */
+#define	PMC_DEBUG_MIN_REA		8 /* read */
+#define	PMC_DEBUG_MIN_WRI		9 /* write */
+#define	PMC_DEBUG_MIN_CFG	       10 /* config */
+#define	PMC_DEBUG_MIN_STA	       11 /* start */
+#define	PMC_DEBUG_MIN_STO	       12 /* stop */
+#define	PMC_DEBUG_MIN_INT	       13 /* interrupts */
+
+/* CPU */
+#define	PMC_DEBUG_MIN_BND		8 /* bind */
+#define	PMC_DEBUG_MIN_SEL		9 /* select */
+
+/* LOG */
+#define	PMC_DEBUG_MIN_GTB		8 /* get buf */
+#define	PMC_DEBUG_MIN_SIO		9 /* schedule i/o */
+#define	PMC_DEBUG_MIN_FLS	       10 /* flush */
+#define	PMC_DEBUG_MIN_SAM	       11 /* sample */
+
+#else
+#define	PMCDBG(M,N,L,F,...)		/* nothing */
+#endif
+
+/* declare a dedicated memory pool */
+MALLOC_DECLARE(M_PMC);
+
+/*
+ * Functions
+ */
+
+struct pmc_mdep *pmc_md_initialize(void);	/* MD init function */
+void	pmc_md_finalize(struct pmc_mdep *_md);	/* MD fini function */
+int	pmc_getrowdisp(int _ri);
+int	pmc_process_interrupt(int _cpu, struct pmc *_pm,
+    struct trapframe *_tf, int _inuserspace);
+int	pmc_save_kernel_callchain(uintptr_t *_cc, int _maxsamples,
+    struct trapframe *_tf);
+int	pmc_save_user_callchain(uintptr_t *_cc, int _maxsamples,
+    struct trapframe *_tf);
+#endif /* _KERNEL */
+#endif /* _SYS_PMC_H_ */
diff --git a/sys/sys/pmckern.h b/sys/sys/pmckern.h
new file mode 100644
index 0000000..7676748
--- /dev/null
+++ b/sys/sys/pmckern.h
@@ -0,0 +1,140 @@
+/*-
+ * Copyright (c) 2003-2007, Joseph Koshy
+ * Copyright (c) 2007 The FreeBSD Foundation
+ * All rights reserved.
+ *
+ * Portions of this software were developed by A. Joseph Koshy under
+ * sponsorship from the FreeBSD Foundation and Google, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: src/sys/sys/pmckern.h,v 1.8 2008/09/22 10:37:02 jkoshy Exp $
+ */
+
+/*
+ * PMC interface used by the base kernel.
+ */
+
+#ifndef _SYS_PMCKERN_H_
+#define _SYS_PMCKERN_H_
+
+#include <sys/param.h>
+#include <sys/kernel.h>
+#include <sys/lock.h>
+#include <sys/proc.h>
+#include <sys/sx.h>
+
+#define	PMC_FN_PROCESS_EXEC		1
+#define	PMC_FN_CSW_IN			2
+#define	PMC_FN_CSW_OUT			3
+#define	PMC_FN_DO_SAMPLES		4
+#define	PMC_FN_KLD_LOAD			5
+#define	PMC_FN_KLD_UNLOAD		6
+#define	PMC_FN_MMAP			7
+#define	PMC_FN_MUNMAP			8
+#define	PMC_FN_USER_CALLCHAIN		9
+
+struct pmckern_procexec {
+	int		pm_credentialschanged;
+	uintfptr_t	pm_entryaddr;
+};
+
+struct pmckern_map_in {
+	void		*pm_file;	/* filename or vnode pointer */
+	uintfptr_t	pm_address;	/* address object is loaded at */
+};
+
+struct pmckern_map_out {
+	uintfptr_t	pm_address;	/* start address of region */
+	size_t		pm_size;	/* size of unmapped region */
+};
+
+/* hook */
+extern int (*pmc_hook)(struct thread *_td, int _function, void *_arg);
+extern int (*pmc_intr)(int _cpu, struct trapframe *_frame);
+
+/* SX lock protecting the hook */
+extern struct sx pmc_sx;
+
+/* Per-cpu flags indicating availability of sampling data */
+extern volatile cpumask_t pmc_cpumask;
+
+/* Count of system-wide sampling PMCs in existence */
+extern volatile int pmc_ss_count;
+
+/* kernel version number */
+extern const int pmc_kernel_version;
+
+/* Hook invocation; for use within the kernel */
+#define	PMC_CALL_HOOK(t, cmd, arg)		\
+do {						\
+	sx_slock(&pmc_sx);			\
+	if (pmc_hook != NULL)			\
+		(pmc_hook)((t), (cmd), (arg));	\
+	sx_sunlock(&pmc_sx);			\
+} while (0)
+
+/* Hook invocation that needs an exclusive lock */
+#define	PMC_CALL_HOOK_X(t, cmd, arg)		\
+do {						\
+	sx_xlock(&pmc_sx);			\
+	if (pmc_hook != NULL)			\
+		(pmc_hook)((t), (cmd), (arg));	\
+	sx_xunlock(&pmc_sx);			\
+} while (0)
+
+/*
+ * Some hook invocations (e.g., from context switch and clock handling
+ * code) need to be lock-free.
+ */
+#define	PMC_CALL_HOOK_UNLOCKED(t, cmd, arg)	\
+do {						\
+	if (pmc_hook != NULL)			\
+		(pmc_hook)((t), (cmd), (arg));	\
+} while (0)
+
+#define	PMC_SWITCH_CONTEXT(t,cmd)	PMC_CALL_HOOK_UNLOCKED(t,cmd,NULL)
+
+/* Check if a process is using HWPMCs.*/
+#define PMC_PROC_IS_USING_PMCS(p)				\
+	(__predict_false(atomic_load_acq_int(&(p)->p_flag) &	\
+	    P_HWPMC))
+
+#define	PMC_SYSTEM_SAMPLING_ACTIVE()		(pmc_ss_count > 0)
+
+/* Check if a CPU has recorded samples. */
+#define	PMC_CPU_HAS_SAMPLES(C)	(__predict_false(pmc_cpumask & (1 << (C))))
+
+/*
+ * Helper functions.
+ */
+int		pmc_cpu_is_disabled(int _cpu);  /* deprecated */
+int		pmc_cpu_is_active(int _cpu);
+int		pmc_cpu_is_present(int _cpu);
+int		pmc_cpu_is_primary(int _cpu);
+unsigned int	pmc_cpu_max(void);
+
+#ifdef	INVARIANTS
+int		pmc_cpu_max_active(void);
+#endif
+
+#endif /* _SYS_PMCKERN_H_ */
diff --git a/sys/sys/pmclog.h b/sys/sys/pmclog.h
new file mode 100644
index 0000000..781baeb
--- /dev/null
+++ b/sys/sys/pmclog.h
@@ -0,0 +1,269 @@
+/*-
+ * Copyright (c) 2005-2007, Joseph Koshy
+ * Copyright (c) 2007 The FreeBSD Foundation
+ * All rights reserved.
+ *
+ * Portions of this software were developed by A. Joseph Koshy under
+ * sponsorship from the FreeBSD Foundation and Google, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: src/sys/sys/pmclog.h,v 1.7 2008/11/27 09:00:47 jkoshy Exp $
+ */
+
+#ifndef	_SYS_PMCLOG_H_
+#define	_SYS_PMCLOG_H_
+
+#include <sys/pmc.h>
+
+enum pmclog_type {
+	/* V1 ABI */
+	PMCLOG_TYPE_CLOSELOG,
+	PMCLOG_TYPE_DROPNOTIFY,
+	PMCLOG_TYPE_INITIALIZE,
+	PMCLOG_TYPE_MAPPINGCHANGE, /* unused in v1 */
+	PMCLOG_TYPE_PCSAMPLE,
+	PMCLOG_TYPE_PMCALLOCATE,
+	PMCLOG_TYPE_PMCATTACH,
+	PMCLOG_TYPE_PMCDETACH,
+	PMCLOG_TYPE_PROCCSW,
+	PMCLOG_TYPE_PROCEXEC,
+	PMCLOG_TYPE_PROCEXIT,
+	PMCLOG_TYPE_PROCFORK,
+	PMCLOG_TYPE_SYSEXIT,
+	PMCLOG_TYPE_USERDATA,
+	/*
+	 * V2 ABI
+	 *
+	 * The MAP_{IN,OUT} event types obsolete the MAPPING_CHANGE
+	 * event type.  The CALLCHAIN event type obsoletes the
+	 * PCSAMPLE event type.
+	 */
+	PMCLOG_TYPE_MAP_IN,
+	PMCLOG_TYPE_MAP_OUT,
+	PMCLOG_TYPE_CALLCHAIN
+};
+
+/*
+ * A log entry descriptor comprises of a 32 bit header and a 64 bit
+ * time stamp followed by as many 32 bit words are required to record
+ * the event.
+ *
+ * Header field format:
+ *
+ *  31           24           16                                   0
+ *   +------------+------------+-----------------------------------+
+ *   |    MAGIC   |    TYPE    |               LENGTH              |
+ *   +------------+------------+-----------------------------------+
+ *
+ * MAGIC 	is the constant PMCLOG_HEADER_MAGIC.
+ * TYPE  	contains a value of type enum pmclog_type.
+ * LENGTH	contains the length of the event record, in bytes.
+ */
+
+#define	PMCLOG_ENTRY_HEADER				\
+	uint32_t		pl_header;		\
+	uint32_t		pl_ts_sec;		\
+	uint32_t		pl_ts_nsec;
+
+
+/*
+ * The following structures are used to describe the size of each kind
+ * of log entry to sizeof().  To keep the compiler from adding
+ * padding, the fields of each structure are aligned to their natural
+ * boundaries, and the structures are marked as 'packed'.
+ *
+ * The actual reading and writing of the log file is always in terms
+ * of 4 byte quantities.
+ */
+
+struct pmclog_callchain {
+	PMCLOG_ENTRY_HEADER
+	uint32_t		pl_pid;
+	uint32_t		pl_pmcid;
+	uint32_t		pl_cpuflags;
+	/* 8 byte aligned */
+	uintptr_t		pl_pc[PMC_CALLCHAIN_DEPTH_MAX];
+} __packed;
+
+#define	PMC_CALLCHAIN_CPUFLAGS_TO_CPU(CF)	(((CF) >> 16) & 0xFFFF)
+#define	PMC_CALLCHAIN_CPUFLAGS_TO_USERMODE(CF)	((CF) & PMC_CC_F_USERSPACE)
+#define	PMC_CALLCHAIN_TO_CPUFLAGS(CPU,FLAGS)	\
+	(((CPU) << 16) | ((FLAGS) & 0xFFFF))
+
+struct pmclog_closelog {
+	PMCLOG_ENTRY_HEADER
+};
+
+struct pmclog_dropnotify {
+	PMCLOG_ENTRY_HEADER
+};
+
+struct pmclog_initialize {
+	PMCLOG_ENTRY_HEADER
+	uint32_t		pl_version;	/* driver version */
+	uint32_t		pl_cpu;		/* enum pmc_cputype */
+} __packed;
+
+struct pmclog_map_in {
+	PMCLOG_ENTRY_HEADER
+	uint32_t		pl_pid;
+	uintfptr_t		pl_start;	/* 8 byte aligned */
+	char			pl_pathname[PATH_MAX];
+} __packed;
+
+struct pmclog_map_out {
+	PMCLOG_ENTRY_HEADER
+	uint32_t		pl_pid;
+	uintfptr_t		pl_start;	/* 8 byte aligned */
+	uintfptr_t		pl_end;
+} __packed;
+
+struct pmclog_pcsample {
+	PMCLOG_ENTRY_HEADER
+	uint32_t		pl_pid;
+	uintfptr_t		pl_pc;		/* 8 byte aligned */
+	uint32_t		pl_pmcid;
+	uint32_t		pl_usermode;
+} __packed;
+
+struct pmclog_pmcallocate {
+	PMCLOG_ENTRY_HEADER
+	uint32_t		pl_pmcid;
+	uint32_t		pl_event;
+	uint32_t		pl_flags;
+} __packed;
+
+struct pmclog_pmcattach {
+	PMCLOG_ENTRY_HEADER
+	uint32_t		pl_pmcid;
+	uint32_t		pl_pid;
+	char			pl_pathname[PATH_MAX];
+} __packed;
+
+struct pmclog_pmcdetach {
+	PMCLOG_ENTRY_HEADER
+	uint32_t		pl_pmcid;
+	uint32_t		pl_pid;
+} __packed;
+
+struct pmclog_proccsw {
+	PMCLOG_ENTRY_HEADER
+	uint32_t		pl_pmcid;
+	uint64_t		pl_value;	/* keep 8 byte aligned */
+	uint32_t		pl_pid;
+} __packed;
+
+struct pmclog_procexec {
+	PMCLOG_ENTRY_HEADER
+	uint32_t		pl_pid;
+	uintfptr_t		pl_start;	/* keep 8 byte aligned */
+	uint32_t		pl_pmcid;
+	char			pl_pathname[PATH_MAX];
+} __packed;
+
+struct pmclog_procexit {
+	PMCLOG_ENTRY_HEADER
+	uint32_t		pl_pmcid;
+	uint64_t		pl_value;	/* keep 8 byte aligned */
+	uint32_t		pl_pid;
+} __packed;
+
+struct pmclog_procfork {
+	PMCLOG_ENTRY_HEADER
+	uint32_t		pl_oldpid;
+	uint32_t		pl_newpid;
+} __packed;
+
+struct pmclog_sysexit {
+	PMCLOG_ENTRY_HEADER
+	uint32_t		pl_pid;
+} __packed;
+
+struct pmclog_userdata {
+	PMCLOG_ENTRY_HEADER
+	uint32_t		pl_userdata;
+} __packed;
+
+union pmclog_entry {		/* only used to size scratch areas */
+	struct pmclog_callchain		pl_cc;
+	struct pmclog_closelog		pl_cl;
+	struct pmclog_dropnotify	pl_dn;
+	struct pmclog_initialize	pl_i;
+	struct pmclog_map_in		pl_mi;
+	struct pmclog_map_out		pl_mo;
+	struct pmclog_pcsample		pl_s;
+	struct pmclog_pmcallocate	pl_a;
+	struct pmclog_pmcattach		pl_t;
+	struct pmclog_pmcdetach		pl_d;
+	struct pmclog_proccsw		pl_c;
+	struct pmclog_procexec		pl_x;
+	struct pmclog_procexit		pl_e;
+	struct pmclog_procfork		pl_f;
+	struct pmclog_sysexit		pl_se;
+	struct pmclog_userdata		pl_u;
+};
+
+#define	PMCLOG_HEADER_MAGIC					0xEEU
+
+#define	PMCLOG_HEADER_TO_LENGTH(H)				\
+	((H) & 0x0000FFFF)
+#define	PMCLOG_HEADER_TO_TYPE(H)				\
+	(((H) & 0x00FF0000) >> 16)
+#define	PMCLOG_HEADER_TO_MAGIC(H)				\
+	(((H) & 0xFF000000) >> 24)
+#define	PMCLOG_HEADER_CHECK_MAGIC(H)				\
+	(PMCLOG_HEADER_TO_MAGIC(H) == PMCLOG_HEADER_MAGIC)
+
+#ifdef	_KERNEL
+
+/*
+ * Prototypes
+ */
+int	pmclog_configure_log(struct pmc_mdep *_md, struct pmc_owner *_po,
+    int _logfd);
+int	pmclog_deconfigure_log(struct pmc_owner *_po);
+int	pmclog_flush(struct pmc_owner *_po);
+void	pmclog_initialize(void);
+void	pmclog_process_callchain(struct pmc *_pm, struct pmc_sample *_ps);
+void	pmclog_process_closelog(struct pmc_owner *po);
+void	pmclog_process_dropnotify(struct pmc_owner *po);
+void	pmclog_process_map_in(struct pmc_owner *po, pid_t pid,
+    uintfptr_t start, const char *path);
+void	pmclog_process_map_out(struct pmc_owner *po, pid_t pid,
+    uintfptr_t start, uintfptr_t end);
+void	pmclog_process_pmcallocate(struct pmc *_pm);
+void	pmclog_process_pmcattach(struct pmc *_pm, pid_t _pid, char *_path);
+void	pmclog_process_pmcdetach(struct pmc *_pm, pid_t _pid);
+void	pmclog_process_proccsw(struct pmc *_pm, struct pmc_process *_pp,
+    pmc_value_t _v);
+void	pmclog_process_procexec(struct pmc_owner *_po, pmc_id_t _pmid, pid_t _pid,
+    uintfptr_t _startaddr, char *_path);
+void	pmclog_process_procexit(struct pmc *_pm, struct pmc_process *_pp);
+void	pmclog_process_procfork(struct pmc_owner *_po, pid_t _oldpid, pid_t _newpid);
+void	pmclog_process_sysexit(struct pmc_owner *_po, pid_t _pid);
+int	pmclog_process_userlog(struct pmc_owner *_po,
+    struct pmc_op_writelog *_wl);
+void	pmclog_shutdown(void);
+#endif	/* _KERNEL */
+
+#endif	/* _SYS_PMCLOG_H_ */
diff --git a/usr.sbin/pmcannotate/Makefile b/usr.sbin/pmcannotate/Makefile
new file mode 100644
index 0000000..529f46f
--- /dev/null
+++ b/usr.sbin/pmcannotate/Makefile
@@ -0,0 +1,10 @@
+#
+# $FreeBSD: src/usr.sbin/pmcannotate/Makefile,v 1.2 2010/01/02 11:07:44 ed Exp $
+#
+
+PROG=	pmcannotate
+MAN=	pmcannotate.8
+
+SRCS=	pmcannotate.c
+
+.include <bsd.prog.mk>
diff --git a/usr.sbin/pmcannotate/pmcannotate.8 b/usr.sbin/pmcannotate/pmcannotate.8
new file mode 100644
index 0000000..3f7faa4
--- /dev/null
+++ b/usr.sbin/pmcannotate/pmcannotate.8
@@ -0,0 +1,109 @@
+.\" Copyright (c) 2008 Nokia Corporation
+.\" All rights reserved.
+.\"
+.\" This software was developed by Attilio Rao for the IPSO project under
+.\" contract to Nokia Corporation.
+.\"
+.\" Redistribution and use in source and binary forms, with or without
+.\" modification, are permitted provided that the following conditions
+.\" are met:
+.\" 1. Redistributions of source code must retain the above copyright
+.\"    notice, this list of conditions and the following disclaimer.
+.\" 2. Redistributions in binary form must reproduce the above copyright
+.\"    notice, this list of conditions and the following disclaimer in the
+.\"    documentation and/or other materials provided with the distribution.
+.\"
+.\" This software is provided by the authors ``as is'' and
+.\" any express or implied warranties, including, but not limited to, the
+.\" implied warranties of merchantability and fitness for a particular purpose
+.\" are disclaimed.  in no event shall the authors be liable
+.\" for any direct, indirect, incidental, special, exemplary, or consequential
+.\" damages (including, but not limited to, procurement of substitute goods
+.\" or services; loss of use, data, or profits; or business interruption)
+.\" however caused and on any theory of liability, whether in contract, strict
+.\" liability, or tort (including negligence or otherwise) arising in any way
+.\" out of the use of this software, even if advised of the possibility of
+.\" such damage.
+.\"
+.\" $FreeBSD: src/usr.sbin/pmcannotate/pmcannotate.8,v 1.3 2010/04/14 19:08:06 uqs Exp $
+.\"
+.Dd November 20, 2008
+.Dt PMCANNOTATE 8
+.Os
+.Sh NAME
+.Nm pmcannotate
+.Nd "sources printout with inlined profiling"
+.Sh SYNOPSIS
+.Nm
+.Op Fl a
+.Op Fl h
+.Op Fl k Ar pathname
+.Op Fl l Ar level
+.Ar pmcout.out binaryobj
+.Sh DESCRIPTION
+The
+.Nm
+utility can produce both C sources or assembly sources of a program with
+a line-by-line based profiling.
+The profiling informations are retrieved through a
+.Xr pmcstat 8
+raw output while the program operations are retrieved through the
+.Xr objdump 1
+tool.
+.Pp
+When calling
+.Nm
+the raw output is passed through the
+.Ar pmcout.out
+argument, while the program is passed through the
+.Ar binaryobj
+argument.
+.Pp
+As long as
+.Nm
+relies on
+.Xr objdump 1
+and
+.Xr pmcstat 8
+to work, it will fail if one of them is not available.
+.Sh OPTIONS
+The following options are available:
+.Bl -tag -width indent
+.It Fl a
+Shows the program profiling inlined in the assembly code only.
+No C informations involving C sources are provided.
+.It Fl h
+Prints out informations about the usage of the tool.
+.It Fl l Ar level
+Changes the lower bound (expressed in percentage) for traced functions
+that will be printed out in the report.
+The default value is 0.5%.
+.It Fl k Ar kerneldir
+Set the pathname of the kernel directory to argument
+.Ar kerneldir .
+This directory specifies where
+.Nm
+should look for the kernel and its modules.
+The default is
+.Pa /boot/kernel .
+.El
+.Sh LIMITATIONS
+As long as
+.Nm
+relies on the
+.Xr objdump 1
+utility to retrieve the C code, the program needs to be compiled with
+debugging options.
+Sometimes, in particular with heavy optimization levels, the
+.Xr objdump 1
+utility embeds the code of inlining functions directly in the callers,
+making an output difficult to read.
+The x86 version reports the sampling from pmcstat collecting the following
+instruction in regard of the interrupted one.
+This means that the samples may be attributed to the line below the one
+of interest.
+.Sh SEE ALSO
+.Xr objdump 1 ,
+.Xr pmcstat 8
+.Sh AUTHORS
+.An Attilio Rao Aq attilio@FreeBSD.org
diff --git a/usr.sbin/pmcannotate/pmcannotate.c b/usr.sbin/pmcannotate/pmcannotate.c
new file mode 100644
index 0000000..3ce8e5b
--- /dev/null
+++ b/usr.sbin/pmcannotate/pmcannotate.c
@@ -0,0 +1,804 @@
+/*-
+ * Copyright (c) 2008 Nokia Corporation
+ * All rights reserved.
+ *
+ * This software was developed by Attilio Rao for the IPSO project under
+ * contract to Nokia Corporation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice unmodified, this list of conditions, and the following
+ *    disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: src/usr.sbin/pmcannotate/pmcannotate.c,v 1.4 2010/10/16 17:30:27 bcr Exp $");
+
+#include <sys/param.h>
+#include <sys/queue.h>
+
+#include <ctype.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include <unistd.h>
+
+#define	FNBUFF	161
+#define	LNBUFF	161
+
+#define	TMPPATH	"/tmp/pmcannotate.XXXXXX"
+
+#define	FATAL(ptr, x ...) do {						\
+	fqueue_deleteall();						\
+	general_deleteall();						\
+	if ((ptr) != NULL)						\
+		perror(ptr);						\
+	fprintf(stderr, ##x);						\
+	remove(tbfl);							\
+	remove(tofl);							\
+	exit(EXIT_FAILURE);						\
+} while (0)
+
+#define	PERCSAMP(x)	((x) * 100 / totalsamples)
+
+struct entry {
+        TAILQ_ENTRY(entry)	en_iter;
+        char		*en_name;
+	uintptr_t	en_pc;
+	uintptr_t	en_ostart;
+	uintptr_t	en_oend;
+	u_int		en_nsamples;
+};
+
+struct aggent {
+	TAILQ_ENTRY(aggent)	ag_fiter;
+	long		ag_offset;
+	uintptr_t	ag_ostart;
+	uintptr_t	ag_oend;
+	char		*ag_name;
+	u_int		ag_nsamples;
+};
+
+static struct aggent	*agg_create(const char *name, u_int nsamples,
+			    uintptr_t start, uintptr_t end);
+static void		 agg_destroy(struct aggent *agg) __unused;
+static void		 asmparse(FILE *fp);
+static int		 cparse(FILE *fp);
+static void		 entry_acqref(struct entry *entry);
+static struct entry	*entry_create(const char *name, uintptr_t pc,
+			    uintptr_t start, uintptr_t end);
+static void		 entry_destroy(struct entry *entry) __unused;
+static void		 fqueue_compact(float th);
+static void		 fqueue_deleteall(void);
+static struct aggent	*fqueue_findent_by_name(const char *name);
+static int		 fqueue_getall(const char *bin, char *temp, int asmf);
+static int		 fqueue_insertent(struct entry *entry);
+static int		 fqueue_insertgen(void);
+static void		 general_deleteall(void);
+static struct entry	*general_findent(uintptr_t pc);
+static void		 general_insertent(struct entry *entry);
+static void		 general_printasm(FILE *fp, struct aggent *agg);
+static int		 general_printc(FILE *fp, struct aggent *agg);
+static int		 printblock(FILE *fp, struct aggent *agg);
+static void		 usage(const char *progname) __dead2;
+
+static TAILQ_HEAD(, entry) mainlst = TAILQ_HEAD_INITIALIZER(mainlst);
+static TAILQ_HEAD(, aggent) fqueue = TAILQ_HEAD_INITIALIZER(fqueue);
+
+/*
+ * Use a float value in order to automatically promote operations
+ * to return a float value rather than use casts.
+ */
+static float totalsamples;
+
+/*
+ * Identifies a string cointaining objdump's assembly printout.
+ */
+static inline int
+isasminline(const char *str)
+{
+	void *ptr;
+	int nbytes;
+
+	if (isxdigit(str[1]) == 0)
+		return (0);
+	if (sscanf(str, " %p%n", &ptr, &nbytes) != 1)
+		return (0);
+	if (str[nbytes] != ':' || isspace(str[nbytes + 1]) == 0)
+		return (0);
+	return (1);
+}
+
+/*
+ * Identifies a string containing objdump's assembly printout
+ * for a new function.
+ */
+static inline int
+newfunction(const char *str)
+{
+	char fname[FNBUFF];
+	void *ptr;
+	int nbytes;
+
+	if (isspace(str[0]))
+		return (0);
+	if (sscanf(str, "%p <%[^>:]>:%n", &ptr, fname, &nbytes) != 2)
+		return (0);
+	return (nbytes);
+}
+
+/*
+ * Create a new first-level aggregation object for a specified
+ * function.
+ */
+static struct aggent *
+agg_create(const char *name, u_int nsamples, uintptr_t start, uintptr_t end)
+{
+	struct aggent *agg;
+
+	agg = calloc(1, sizeof(struct aggent));
+	if (agg == NULL)
+		return (NULL);
+	agg->ag_name = strdup(name);
+	if (agg->ag_name == NULL) {
+		free(agg);
+		return (NULL);
+	}
+	agg->ag_nsamples = nsamples;
+	agg->ag_ostart = start;
+	agg->ag_oend = end;
+	return (agg);
+}
+
+/*
+ * Destroy a first-level aggregation object for a specified
+ * function.
+ */
+static void
+agg_destroy(struct aggent *agg)
+{
+
+	free(agg->ag_name);
+	free(agg);
+}
+
+/*
+ * Analyze the "objdump -d" output, locate functions and start
+ * printing out the assembly functions content.
+ * We do not use newfunction() because we actually need the
+ * function name in available form, but the heurstic used is
+ * the same.
+ */
+static void
+asmparse(FILE *fp)
+{
+	char buffer[LNBUFF], fname[FNBUFF];
+	struct aggent *agg;
+	void *ptr;
+
+	while (fgets(buffer, LNBUFF, fp) != NULL) {
+		if (isspace(buffer[0]))
+			continue;
+		if (sscanf(buffer, "%p <%[^>:]>:", &ptr, fname) != 2)
+			continue;
+		agg = fqueue_findent_by_name(fname);
+		if (agg == NULL)
+			continue;
+		agg->ag_offset = ftell(fp);
+	}
+
+	TAILQ_FOREACH(agg, &fqueue, ag_fiter) {
+		if (fseek(fp, agg->ag_offset, SEEK_SET) == -1)
+			return;
+		printf("Profile trace for function: %s() [%.2f%%]\n",
+		    agg->ag_name, PERCSAMP(agg->ag_nsamples));
+		general_printasm(fp, agg);
+		printf("\n");
+	}
+}
+
+/*
+ * Analyze the "objdump -S" output, locate functions and start
+ * printing out the C functions content.
+ * We do not use newfunction() because we actually need the
+ * function name in available form, but the heurstic used is
+ * the same.
+ * In order to maintain the printout sorted, on the first pass it
+ * simply stores the file offsets in order to fastly moved later
+ * (when the file is hot-cached also) when the real printout will
+ * happen.
+ */
+static int
+cparse(FILE *fp)
+{
+	char buffer[LNBUFF], fname[FNBUFF];
+	struct aggent *agg;
+	void *ptr;
+
+	while (fgets(buffer, LNBUFF, fp) != NULL) {
+		if (isspace(buffer[0]))
+			continue;
+		if (sscanf(buffer, "%p <%[^>:]>:", &ptr, fname) != 2)
+			continue;
+		agg = fqueue_findent_by_name(fname);
+		if (agg == NULL)
+			continue;
+		agg->ag_offset = ftell(fp);
+	}
+
+	TAILQ_FOREACH(agg, &fqueue, ag_fiter) {
+		if (fseek(fp, agg->ag_offset, SEEK_SET) == -1)
+			return (-1);
+		printf("Profile trace for function: %s() [%.2f%%]\n",
+		    agg->ag_name, PERCSAMP(agg->ag_nsamples));
+		if (general_printc(fp, agg) == -1)
+			return (-1);
+		printf("\n");
+	}
+	return (0);
+}
+
+/*
+ * Bump the number of samples for any raw entry.
+ */
+static void
+entry_acqref(struct entry *entry)
+{
+
+	entry->en_nsamples++;
+}
+
+/*
+ * Create a new raw entry object for a specified function.
+ */
+static struct entry *
+entry_create(const char *name, uintptr_t pc, uintptr_t start, uintptr_t end)
+{
+	struct entry *obj;
+
+	obj = calloc(1, sizeof(struct entry));
+	if (obj == NULL)
+		return (NULL);
+	obj->en_name = strdup(name);
+	if (obj->en_name == NULL) {
+		free(obj);
+		return (NULL);
+	}
+	obj->en_pc = pc;
+	obj->en_ostart = start;
+	obj->en_oend = end;
+	obj->en_nsamples = 1;
+	return (obj);
+}
+
+/*
+ * Destroy a raw entry object for a specified function.
+ */
+static void
+entry_destroy(struct entry *entry)
+{
+
+	free(entry->en_name);
+	free(entry);
+}
+
+/*
+ * Specify a lower bound in percentage and drop from the
+ * first-level aggregation queue all the objects with a
+ * smaller impact.
+ */
+static void
+fqueue_compact(float th)
+{
+	u_int thi;
+	struct aggent *agg, *tmpagg;
+
+	if (totalsamples == 0)
+		return;
+
+	/* Revert the percentage calculation. */
+	thi = th * totalsamples / 100;
+	TAILQ_FOREACH_SAFE(agg, &fqueue, ag_fiter, tmpagg)
+		if (agg->ag_nsamples < thi)
+			TAILQ_REMOVE(&fqueue, agg, ag_fiter);
+}
+
+/*
+ * Flush the first-level aggregates queue.
+ */
+static void
+fqueue_deleteall(void)
+{
+	struct aggent *agg;
+
+	while (TAILQ_EMPTY(&fqueue) == 0) {
+		agg = TAILQ_FIRST(&fqueue);
+		TAILQ_REMOVE(&fqueue, agg, ag_fiter);
+	}
+}
+
+/*
+ * Insert a raw entry into the aggregations queue.
+ * If the respective first-level aggregation object
+ * does not exist create it and maintain it sorted
+ * in respect of the number of samples.
+ */
+static int
+fqueue_insertent(struct entry *entry)
+{
+	struct aggent *obj, *tmp;
+	int found;
+
+	found = 0;
+	TAILQ_FOREACH(obj, &fqueue, ag_fiter)
+		if (!strcmp(obj->ag_name, entry->en_name)) {
+			found = 1;
+			obj->ag_nsamples += entry->en_nsamples;
+			break;
+		}
+
+	/*
+	 * If the first-level aggregation object already exists,
+	 * just aggregate the samples and, if needed, resort
+	 * it.
+	 */
+	if (found) {
+		TAILQ_REMOVE(&fqueue, obj, ag_fiter);
+		found = 0;
+		TAILQ_FOREACH(tmp, &fqueue, ag_fiter)
+			if (obj->ag_nsamples > tmp->ag_nsamples) {
+				found = 1;
+				break;
+			}
+		if (found)
+			TAILQ_INSERT_BEFORE(tmp, obj, ag_fiter);
+		else
+			TAILQ_INSERT_TAIL(&fqueue, obj, ag_fiter);
+		return (0);
+	}
+
+	/*
+	 * If the first-level aggregation object does not
+	 * exist, create it and put in the sorted queue.
+	 * If this is the first object, we need to set the
+	 * head of the queue.
+	 */
+	obj = agg_create(entry->en_name, entry->en_nsamples, entry->en_ostart,
+	    entry->en_oend);
+	if (obj == NULL)
+		return (-1);
+	if (TAILQ_EMPTY(&fqueue) != 0) {
+		TAILQ_INSERT_HEAD(&fqueue, obj, ag_fiter);
+		return (0);
+	}
+	TAILQ_FOREACH(tmp, &fqueue, ag_fiter)
+		if (obj->ag_nsamples > tmp->ag_nsamples) {
+			found = 1;
+			break;
+		}
+	if (found)
+		TAILQ_INSERT_BEFORE(tmp, obj, ag_fiter);
+	else
+		TAILQ_INSERT_TAIL(&fqueue, obj, ag_fiter);
+	return (0);
+}
+
+/*
+ * Lookup a first-level aggregation object by name.
+ */
+static struct aggent *
+fqueue_findent_by_name(const char *name)
+{
+	struct aggent *obj;
+
+	TAILQ_FOREACH(obj, &fqueue, ag_fiter)
+		if (!strcmp(obj->ag_name, name))
+			return (obj);
+	return (NULL);
+}
+
+/*
+ * Return the number of object in the first-level aggregations queue.
+ */
+static int
+fqueue_getall(const char *bin, char *temp, int asmf)
+{
+	char tmpf[MAXPATHLEN * 2 + 50];
+	struct aggent *agg;
+	uintptr_t start, end;
+
+	if (mkstemp(temp) == -1)
+		return (-1);
+	TAILQ_FOREACH(agg, &fqueue, ag_fiter) {
+		bzero(tmpf, sizeof(tmpf));
+		start = agg->ag_ostart;
+		end = agg->ag_oend;
+
+		/*
+		 * Fix-up the end address in order to show it in the objdump's
+		 * trace.
+		 */
+		end++;
+		if (asmf)
+			snprintf(tmpf, sizeof(tmpf),
+			    "objdump --start-address=%p "
+			    "--stop-address=%p -d %s >> %s", (void *)start,
+			    (void *)end, bin, temp);
+		else
+			snprintf(tmpf, sizeof(tmpf),
+			    "objdump --start-address=%p "
+			    "--stop-address=%p -S %s >> %s", (void *)start,
+			    (void *)end, bin, temp);
+		if (system(tmpf) != 0)
+			return (-1);
+	}
+	return (0);
+}
+
+/*
+ * Insert all the raw entries present in the general queue
+ * into the first-level aggregations queue.
+ */
+static int
+fqueue_insertgen(void)
+{
+	struct entry *obj;
+
+	TAILQ_FOREACH(obj, &mainlst, en_iter)
+		if (fqueue_insertent(obj) == -1)
+			return (-1);
+	return (0);
+}
+
+/*
+ * Flush the raw entries general queue.
+ */
+static void
+general_deleteall(void)
+{
+	struct entry *obj;
+
+	while (TAILQ_EMPTY(&mainlst) == 0) {
+		obj = TAILQ_FIRST(&mainlst);
+		TAILQ_REMOVE(&mainlst, obj, en_iter);
+	}
+}
+
+/*
+ * Lookup a raw entry by the PC.
+ */
+static struct entry *
+general_findent(uintptr_t pc)
+{
+	struct entry *obj;
+
+	TAILQ_FOREACH(obj, &mainlst, en_iter)
+		if (obj->en_pc == pc)
+			return (obj);
+	return (NULL);
+}
+
+/*
+ * Insert a new raw entry in the general queue.
+ */
+static void
+general_insertent(struct entry *entry)
+{
+
+	TAILQ_INSERT_TAIL(&mainlst, entry, en_iter);
+}
+
+/*
+ * Printout the body of an "objdump -d" assembly function.
+ * It does simply stops when a new function is encountered,
+ * bringing back the file position in order to not mess up
+ * subsequent analysis.
+ * C lines and others not recognized are simply skipped.
+ */
+static void
+general_printasm(FILE *fp, struct aggent *agg)
+{
+	char buffer[LNBUFF];
+	struct entry *obj;
+	int nbytes;
+	void *ptr;
+
+	while (fgets(buffer, LNBUFF, fp) != NULL) {
+		if ((nbytes = newfunction(buffer)) != 0) {
+			fseek(fp, nbytes * -1, SEEK_CUR);
+			break;
+		}
+		if (!isasminline(buffer))
+			continue;
+		if (sscanf(buffer, " %p:", &ptr) != 1)
+			continue;
+		obj = general_findent((uintptr_t)ptr);
+		if (obj == NULL)
+			printf("\t| %s", buffer);
+		else
+			printf("%.2f%%\t| %s",
+			    (float)obj->en_nsamples * 100 / agg->ag_nsamples,
+			    buffer);
+	}
+}
+
+/*
+ * Printout the body of an "objdump -S" function.
+ * It does simply stops when a new function is encountered,
+ * bringing back the file position in order to not mess up
+ * subsequent analysis.
+ * It expect from the starting to the end to find, always, valid blocks
+ * (see below for an explanation of the "block" concept).
+ */
+static int
+general_printc(FILE *fp, struct aggent *agg)
+{
+	char buffer[LNBUFF];
+
+	while (fgets(buffer, LNBUFF, fp) != NULL) {
+		fseek(fp, strlen(buffer) * -1, SEEK_CUR);
+		if (newfunction(buffer) != 0)
+			break;
+		if (printblock(fp, agg) == -1)
+			return (-1);
+	}
+	return (0);
+}
+
+/*
+ * Printout a single block inside an "objdump -S" function.
+ * The block is composed of a first part in C and subsequent translation
+ * in assembly.
+ * This code also operates a second-level aggregation packing together
+ * samples relative to PCs into a (lower bottom) block with their
+ * C (higher half) counterpart.
+ */
+static int
+printblock(FILE *fp, struct aggent *agg)
+{
+	char buffer[LNBUFF];
+	long lstart;
+	struct entry *obj;
+	u_int tnsamples;
+	int done, nbytes, sentinel;
+	void *ptr;
+
+	/*
+	 * We expect the first thing of the block is C code, so simply give
+	 * up if asm line is found.
+	 */
+	lstart = ftell(fp);
+	sentinel = 0;
+	for (;;) {
+		if (fgets(buffer, LNBUFF, fp) == NULL)
+			return (0);
+		if (isasminline(buffer) != 0)
+			break;
+		sentinel = 1;
+		nbytes = newfunction(buffer);
+		if (nbytes != 0) {
+			if (fseek(fp, nbytes * -1, SEEK_CUR) == -1)
+				return (-1);
+			return (0);
+		}
+	}
+
+	/*
+	 * If the sentinel is not set, it means it did not match any
+	 * "high half" for this code so simply give up.
+	 * Operates the second-level aggregation.
+	 */
+	tnsamples = 0;
+	do {
+		if (sentinel == 0)
+			return (-1);
+		if (sscanf(buffer, " %p:", &ptr) != 1)
+			return (-1);
+		obj = general_findent((uintptr_t)ptr);
+		if (obj != NULL)
+			tnsamples += obj->en_nsamples;
+	} while (fgets(buffer, LNBUFF, fp) != NULL && isasminline(buffer) != 0);
+
+	/* Rewind to the start of the block in order to start the printout. */
+	if (fseek(fp, lstart, SEEK_SET) == -1)
+		return (-1);
+
+	/* Again the high half of the block rappresenting the C part. */
+	done = 0;
+	while (fgets(buffer, LNBUFF, fp) != NULL && isasminline(buffer) == 0) {
+		if (tnsamples == 0 || done != 0)
+			printf("\t| %s", buffer);
+		else {
+			done = 1;
+			printf("%.2f%%\t| %s",
+			    (float)tnsamples * 100 / agg->ag_nsamples, buffer);
+		}
+	}
+
+	/*
+	 * Again the low half of the block rappresenting the asm
+	 * translation part.
+	 */
+	for (;;) {
+		if (fgets(buffer, LNBUFF, fp) == NULL)
+			return (0);
+		if (isasminline(buffer) == 0)
+			break;
+		nbytes = newfunction(buffer);
+		if (nbytes != 0) {
+			if (fseek(fp, nbytes * -1, SEEK_CUR) == -1)
+				return (-1);
+			return (0);
+		}
+	}
+	if (fseek(fp, strlen(buffer) * -1, SEEK_CUR) == -1)
+		return (-1);
+	return (0);
+}
+
+/*
+ * Helper printout functions.
+ */
+static void
+usage(const char *progname)
+{
+
+	fprintf(stderr,
+	    "usage: %s [-a] [-h] [-k kfile] [-l lb] pmcraw.out binary\n",
+	    progname);
+	exit(EXIT_SUCCESS);
+}
+
+int
+main(int argc, char *argv[])
+{
+	char buffer[LNBUFF], fname[FNBUFF], tbfl[] = TMPPATH, tofl[] = TMPPATH;
+	char tmpf[MAXPATHLEN * 2 + 50];
+	float limit;
+	char *bin, *exec, *kfile, *ofile;
+	struct entry *obj;
+	FILE *gfp, *bfp;
+	void *ptr, *hstart, *hend;
+	uintptr_t tmppc, ostart, oend;
+	int cget, asmsrc;
+
+	exec = argv[0];
+	ofile = NULL;
+	bin = NULL;
+	kfile = NULL;
+	asmsrc = 0;
+	limit = 0.5;
+	while ((cget = getopt(argc, argv, "ahl:k:")) != -1)
+		switch(cget) {
+		case 'a':
+			asmsrc = 1;
+			break;
+		case 'k':
+			kfile = optarg;
+			break;
+		case 'l':
+			limit = (float)atof(optarg);
+			break;
+		case 'h':
+		case '?':
+		default:
+			usage(exec);
+		}
+	argc -= optind;
+	argv += optind;
+	if (argc != 2)
+		usage(exec);
+	ofile = argv[0];
+	bin = argv[1];
+
+	if (access(bin, R_OK | F_OK) == -1)
+		FATAL(exec, "%s: Impossible to locate the binary file\n",
+		    exec);
+	if (access(ofile, R_OK | F_OK) == -1)
+		FATAL(exec, "%s: Impossible to locate the pmcstat file\n",
+		    exec);
+	if (kfile != NULL && access(kfile, R_OK | F_OK) == -1)
+		FATAL(exec, "%s: Impossible to locate the kernel file\n",
+		    exec);
+
+	bzero(tmpf, sizeof(tmpf));
+	if (mkstemp(tofl) == -1)
+		FATAL(exec, "%s: Impossible to create the tmp file\n",
+		    exec);
+	if (kfile != NULL)
+		snprintf(tmpf, sizeof(tmpf), "pmcstat -k %s -R %s -m %s",
+		    kfile, ofile, tofl);
+	else
+		snprintf(tmpf, sizeof(tmpf), "pmcstat -R %s -m %s", ofile,
+		    tofl);
+	if (system(tmpf) != 0)
+		FATAL(exec, "%s: Impossible to create the tmp file\n",
+		    exec);
+
+	gfp = fopen(tofl, "r");
+	if (gfp == NULL)
+		FATAL(exec, "%s: Impossible to open the map file\n",
+		    exec);
+
+	/*
+	 * Make the collection of raw entries from a pmcstat mapped file.
+	 * The heuristic here wants strings in the form:
+	 * "addr funcname startfaddr endfaddr".
+	 */
+	while (fgets(buffer, LNBUFF, gfp) != NULL) {
+		if (isspace(buffer[0]))
+			continue;
+		if (sscanf(buffer, "%p %s %p %p\n", &ptr, fname,
+		    &hstart, &hend) != 4)
+			FATAL(NULL,
+			    "%s: Invalid scan of function in the map file\n",
+			    exec);
+		ostart = (uintptr_t)hstart;
+		oend = (uintptr_t)hend;
+		tmppc = (uintptr_t)ptr;
+		totalsamples++;
+		obj = general_findent(tmppc);
+		if (obj != NULL) {
+			entry_acqref(obj);
+			continue;
+		}
+		obj = entry_create(fname, tmppc, ostart, oend);
+		if (obj == NULL)
+			FATAL(exec,
+			    "%s: Impossible to create a new object\n", exec);
+		general_insertent(obj);
+	}
+	if (fclose(gfp) == EOF)
+		FATAL(exec, "%s: Impossible to close the filedesc\n",
+		    exec);
+	if (remove(tofl) == -1)
+                FATAL(exec, "%s: Impossible to remove the tmpfile\n",
+                    exec);
+
+	/*
+	 * Remove the loose end objects and feed the first-level aggregation
+	 * queue.
+	 */
+	if (fqueue_insertgen() == -1)
+		FATAL(exec, "%s: Impossible to generate an analysis\n",
+		    exec);
+	fqueue_compact(limit);
+	if (fqueue_getall(bin, tbfl, asmsrc) == -1)
+		FATAL(exec, "%s: Impossible to create the tmp file\n",
+		    exec);
+
+	bfp = fopen(tbfl, "r");
+	if (bfp == NULL)
+		FATAL(exec, "%s: Impossible to open the binary file\n",
+		    exec);
+
+	if (asmsrc != 0)
+		asmparse(bfp);
+	else if (cparse(bfp) == -1)
+		FATAL(NULL, "%s: Invalid format for the C file\n", exec);
+	if (fclose(bfp) == EOF)
+                FATAL(exec, "%s: Impossible to close the filedesc\n",
+                    exec);
+	if (remove(tbfl) == -1)
+                FATAL(exec, "%s: Impossible to remove the tmpfile\n",
+                    exec);
+	return (0);
+}
diff --git a/usr.sbin/pmccontrol/Makefile b/usr.sbin/pmccontrol/Makefile
new file mode 100644
index 0000000..f5469b0
--- /dev/null
+++ b/usr.sbin/pmccontrol/Makefile
@@ -0,0 +1,13 @@
+#
+# $FreeBSD: src/usr.sbin/pmccontrol/Makefile,v 1.3 2010/01/02 11:07:44 ed Exp $
+#
+
+PROG=	pmccontrol
+MAN=	pmccontrol.8
+
+DPADD=	${LIBPMC}
+LDADD=	-lpmc
+
+SRCS=	pmccontrol.c
+
+.include <bsd.prog.mk>
diff --git a/usr.sbin/pmccontrol/pmccontrol.8 b/usr.sbin/pmccontrol/pmccontrol.8
new file mode 100644
index 0000000..c163205
--- /dev/null
+++ b/usr.sbin/pmccontrol/pmccontrol.8
@@ -0,0 +1,127 @@
+.\" Copyright (c) 2003,2008 Joseph Koshy.  All rights reserved.
+.\"
+.\" Redistribution and use in source and binary forms, with or without
+.\" modification, are permitted provided that the following conditions
+.\" are met:
+.\" 1. Redistributions of source code must retain the above copyright
+.\"    notice, this list of conditions and the following disclaimer.
+.\" 2. Redistributions in binary form must reproduce the above copyright
+.\"    notice, this list of conditions and the following disclaimer in the
+.\"    documentation and/or other materials provided with the distribution.
+.\"
+.\" This software is provided by Joseph Koshy ``as is'' and
+.\" any express or implied warranties, including, but not limited to, the
+.\" implied warranties of merchantability and fitness for a particular purpose
+.\" are disclaimed.  in no event shall Joseph Koshy be liable
+.\" for any direct, indirect, incidental, special, exemplary, or consequential
+.\" damages (including, but not limited to, procurement of substitute goods
+.\" or services; loss of use, data, or profits; or business interruption)
+.\" however caused and on any theory of liability, whether in contract, strict
+.\" liability, or tort (including negligence or otherwise) arising in any way
+.\" out of the use of this software, even if advised of the possibility of
+.\" such damage.
+.\"
+.\" $FreeBSD: src/usr.sbin/pmccontrol/pmccontrol.8,v 1.4 2010/04/14 19:08:06 uqs Exp $
+.\"
+.Dd November 9, 2008
+.Dt PMCCONTROL 8
+.Os
+.Sh NAME
+.Nm pmccontrol
+.Nd "control hardware performance monitoring counters"
+.Sh SYNOPSIS
+.Nm
+.Oo Fl c Ar cpu | Fl d Ar pmc | Fl e Ar pmc Oc ...
+.Nm
+.Fl l
+.Nm
+.Fl L
+.Nm
+.Fl s
+.Sh DESCRIPTION
+The
+.Nm
+utility controls the operation of the system's hardware performance
+monitoring counters.
+.Sh OPTIONS
+The
+.Nm
+utility processes options in command line order, so later options modify
+the effect of earlier ones.
+The following options are available:
+.Bl -tag -width indent
+.It Fl c Ar cpu
+Subsequent enable and disable options affect the CPU
+denoted by argument
+.Ar cpu .
+The argument
+.Ar cpu
+is a number denoting a CPU in the system, or
+.Dq Li * ,
+denoting all unhalted CPUs in the system.
+.It Fl d Ar pmc
+Disable PMC number
+.Ar pmc
+on the CPU specified by
+.Fl c ,
+preventing it from being used till subsequently re-enabled.
+The argument
+.Ar pmc
+is a number denoting a specific PMC, or
+.Dq Li *
+denoting all the PMCs on the specified CPU.
+.Pp
+Only idle PMCs may be disabled.
+.\" XXX this probably needs to be fixed.
+.It Fl e Ar pmc
+Enable PMC number
+.Ar pmc ,
+on the CPU specified by
+.Fl c ,
+allowing it to be used in the future.
+The argument
+.Ar pmc
+is a number denoting a specific PMC, or
+.Dq Li *
+denoting all the PMCs on the specified CPU.
+If PMC
+.Ar pmc
+is already enabled, this option has no effect.
+.It Fl l
+List available hardware performance counters and their current
+disposition.
+.It Fl L
+List available hardware performance counter classes and their
+supported event names.
+.It Fl s
+Print driver statistics maintained by
+.Xr hwpmc 4 .
+.El
+.Sh EXAMPLES
+To disable all PMCs on all CPUs, use the command:
+.Dl "pmccontrol -d*"
+.Pp
+To enable all PMCs on all CPUs, use:
+.Dl "pmccontrol -e*"
+.Pp
+To disable PMCs 0 and 1 on CPU 2, use:
+.Dl "pmccontrol -c2 -d0 -d1"
+.Pp
+To disable PMC 0 of CPU 0 only, and enable all other PMCS on all other
+CPUs, use:
+.Dl "pmccontrol -c* -e* -c0 -d0"
+.Sh DIAGNOSTICS
+.Ex -std
+.Sh SEE ALSO
+.Xr pmc 3 ,
+.Xr pmclog 3 ,
+.Xr hwpmc 4 ,
+.Xr pmcstat 8 ,
+.Xr sysctl 8
+.Sh HISTORY
+The
+.Nm
+utility first appeared in
+.Fx 6.0 .
+.Sh AUTHORS
+.An Joseph Koshy Aq jkoshy@FreeBSD.org
diff --git a/usr.sbin/pmccontrol/pmccontrol.c b/usr.sbin/pmccontrol/pmccontrol.c
new file mode 100644
index 0000000..03a3b1d
--- /dev/null
+++ b/usr.sbin/pmccontrol/pmccontrol.c
@@ -0,0 +1,501 @@
+/*-
+ * Copyright (c) 2003,2004 Joseph Koshy
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: src/usr.sbin/pmccontrol/pmccontrol.c,v 1.9 2010/10/11 14:31:24 gnn Exp $");
+
+#include <sys/types.h>
+#include <sys/queue.h>
+#include <sys/sysctl.h>
+
+#include <assert.h>
+#include <err.h>
+#include <errno.h>
+#include <fcntl.h>
+#include <limits.h>
+#include <pmc.h>
+#include <stdarg.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sysexits.h>
+#include <unistd.h>
+
+/* Compile time defaults */
+
+#define	PMCC_PRINT_USAGE	0
+#define	PMCC_PRINT_EVENTS	1
+#define	PMCC_LIST_STATE 	2
+#define	PMCC_ENABLE_DISABLE	3
+#define	PMCC_SHOW_STATISTICS	4
+
+#define	PMCC_CPU_ALL		-1
+#define	PMCC_CPU_WILDCARD	'*'
+
+#define	PMCC_PMC_ALL		-1
+#define	PMCC_PMC_WILDCARD	'*'
+
+#define	PMCC_OP_IGNORE		0
+#define	PMCC_OP_DISABLE		1
+#define	PMCC_OP_ENABLE		2
+
+#define	PMCC_PROGRAM_NAME	"pmccontrol"
+
+STAILQ_HEAD(pmcc_op_list, pmcc_op) head = STAILQ_HEAD_INITIALIZER(head);
+
+struct pmcc_op {
+	char	op_cpu;
+	char	op_pmc;
+	char	op_op;
+	STAILQ_ENTRY(pmcc_op) op_next;
+};
+
+/* Function Prototypes */
+#if	DEBUG
+static void	pmcc_init_debug(void);
+#endif
+
+static int	pmcc_do_list_state(void);
+static int	pmcc_do_enable_disable(struct pmcc_op_list *);
+static int	pmcc_do_list_events(void);
+
+/* Globals */
+
+static char usage_message[] =
+	"Usage:\n"
+	"       " PMCC_PROGRAM_NAME " -L\n"
+	"       " PMCC_PROGRAM_NAME " -l\n"
+	"       " PMCC_PROGRAM_NAME " -s\n"
+	"       " PMCC_PROGRAM_NAME " [-e pmc | -d pmc | -c cpu] ...";
+
+#if DEBUG
+FILE *debug_stream = NULL;
+#endif
+
+#if DEBUG
+#define DEBUG_MSG(...)					                \
+	(void) fprintf(debug_stream, "[pmccontrol] " __VA_ARGS__);
+#else
+#define DEBUG_MSG(m)		/*  */
+#endif /* !DEBUG */
+
+int pmc_syscall = -1;
+
+#define PMC_CALL(cmd, params)						\
+if ((error = syscall(pmc_syscall, PMC_OP_##cmd, (params))) != 0)	\
+{									\
+	DEBUG_MSG("ERROR: syscall [" #cmd "]");				\
+	exit(EX_OSERR);							\
+}
+
+#if DEBUG
+/* log debug messages to a separate file */
+static void
+pmcc_init_debug(void)
+{
+	char *fn;
+
+	fn = getenv("PMCCONTROL_DEBUG");
+	if (fn != NULL)
+	{
+		debug_stream = fopen(fn, "w");
+		if (debug_stream == NULL)
+			debug_stream = stderr;
+	} else
+		debug_stream = stderr;
+}
+#endif
+
+static int
+pmcc_do_enable_disable(struct pmcc_op_list *op_list)
+{
+	int c, error, i, j, ncpu, npmc, t;
+	cpumask_t haltedcpus, cpumask;
+	struct pmcc_op *np;
+	unsigned char *map;
+	unsigned char op;
+	int cpu, pmc;
+	size_t dummy;
+
+	if ((ncpu = pmc_ncpu()) < 0)
+		err(EX_OSERR, "Unable to determine the number of cpus");
+
+	/* Determine the set of active CPUs. */
+	cpumask = (1 << ncpu) - 1;
+	dummy = sizeof(int);
+	haltedcpus = (cpumask_t) 0;
+	if (ncpu > 1 && sysctlbyname("machdep.hlt_cpus", &haltedcpus,
+	    &dummy, NULL, 0) < 0)
+		err(EX_OSERR, "ERROR: Cannot determine which CPUs are "
+		    "halted");
+	cpumask &= ~haltedcpus;
+
+	/* Determine the maximum number of PMCs in any CPU. */
+	npmc = 0;
+	for (c = 0; c < ncpu; c++) {
+		if ((t = pmc_npmc(c)) < 0)
+			err(EX_OSERR, "Unable to determine the number of "
+			    "PMCs in CPU %d", c);
+		npmc = t > npmc ? t : npmc;
+	}
+
+	if (npmc == 0)
+		errx(EX_CONFIG, "No PMCs found");
+
+	if ((map = malloc(npmc * ncpu)) == NULL)
+		err(EX_SOFTWARE, "Out of memory");
+
+	(void) memset(map, PMCC_OP_IGNORE, npmc*ncpu);
+
+	error = 0;
+	STAILQ_FOREACH(np, op_list, op_next) {
+
+		cpu = np->op_cpu;
+		pmc = np->op_pmc;
+		op  = np->op_op;
+
+		if (cpu >= ncpu)
+			errx(EX_DATAERR, "CPU id too large: \"%d\"", cpu);
+
+		if (pmc >= npmc)
+			errx(EX_DATAERR, "PMC id too large: \"%d\"", pmc);
+
+#define MARKMAP(M,C,P,V)	do {				\
+		*((M) + (C)*npmc + (P)) = (V);			\
+} while (0)
+
+#define	SET_PMCS(C,P,V)		do {				\
+		if ((P) == PMCC_PMC_ALL) {			\
+			for (j = 0; j < npmc; j++)		\
+				MARKMAP(map, (C), j, (V));	\
+		} else						\
+			MARKMAP(map, (C), (P), (V));		\
+} while (0)
+
+#define MAP(M,C,P)	(*((M) + (C)*npmc + (P)))
+
+		if (cpu == PMCC_CPU_ALL)
+			for (i = 0; i < ncpu; i++) {
+				if ((1 << i) & cpumask)
+					SET_PMCS(i, pmc, op);
+			}
+		else
+			SET_PMCS(cpu, pmc, op);
+	}
+
+	/* Configure PMCS */
+	for (i = 0; i < ncpu; i++)
+		for (j = 0; j < npmc; j++) {
+			unsigned char b;
+
+			b = MAP(map, i, j);
+
+			error = 0;
+
+			if (b == PMCC_OP_ENABLE)
+				error = pmc_enable(i, j);
+			else if (b == PMCC_OP_DISABLE)
+				error = pmc_disable(i, j);
+
+			if (error < 0)
+				err(EX_OSERR, "%s of PMC %d on CPU %d failed",
+				    b == PMCC_OP_ENABLE ? "Enable" :
+				    "Disable", j, i);
+		}
+
+	return error;
+}
+
+static int
+pmcc_do_list_state(void)
+{
+	size_t dummy;
+	int c, cpu, n, npmc, ncpu;
+	unsigned int logical_cpus_mask;
+	struct pmc_info *pd;
+	struct pmc_pmcinfo *pi;
+	const struct pmc_cpuinfo *pc;
+
+	if (pmc_cpuinfo(&pc) != 0)
+		err(EX_OSERR, "Unable to determine CPU information");
+
+	printf("%d %s CPUs present, with %d PMCs per CPU\n", pc->pm_ncpu,
+	       pmc_name_of_cputype(pc->pm_cputype),
+		pc->pm_npmc);
+
+	dummy = sizeof(logical_cpus_mask);
+	if (sysctlbyname("machdep.logical_cpus_mask", &logical_cpus_mask,
+		&dummy, NULL, 0) < 0)
+		logical_cpus_mask = 0;
+
+	ncpu = pc->pm_ncpu;
+
+	for (c = cpu = 0; cpu < ncpu; cpu++) {
+#if	defined(__i386__) || defined(__amd64__)
+		if (pc->pm_cputype == PMC_CPU_INTEL_PIV &&
+		    (logical_cpus_mask & (1 << cpu)))
+			continue; /* skip P4-style 'logical' cpus */
+#endif
+		if (pmc_pmcinfo(cpu, &pi) < 0) {
+			if (errno == ENXIO)
+				continue;
+			err(EX_OSERR, "Unable to get PMC status for CPU %d",
+			    cpu);
+		}
+
+		printf("#CPU %d:\n", c++);
+		npmc = pmc_npmc(cpu);
+		printf("#N  NAME             CLASS  STATE    ROW-DISP\n");
+
+		for (n = 0; n < npmc; n++) {
+			pd = &pi->pm_pmcs[n];
+
+			printf(" %-2d %-16s %-6s %-8s %-10s",
+			    n,
+			    pd->pm_name,
+			    pmc_name_of_class(pd->pm_class),
+			    pd->pm_enabled ? "ENABLED" : "DISABLED",
+			    pmc_name_of_disposition(pd->pm_rowdisp));
+
+			if (pd->pm_ownerpid != -1) {
+			        printf(" (pid %d)", pd->pm_ownerpid);
+				printf(" %-32s",
+				    pmc_name_of_event(pd->pm_event));
+				if (PMC_IS_SAMPLING_MODE(pd->pm_mode))
+					printf(" (reload count %jd)",
+					    pd->pm_reloadcount);
+			}
+			printf("\n");
+		}
+		free(pi);
+	}
+	return 0;
+}
+
+static int
+pmcc_do_list_events(void)
+{
+	enum pmc_class c;
+	unsigned int i, j, nevents;
+	const char **eventnamelist;
+	const struct pmc_cpuinfo *ci;
+
+	if (pmc_cpuinfo(&ci) != 0)
+		err(EX_OSERR, "Unable to determine CPU information");
+
+	eventnamelist = NULL;
+
+	for (i = 0; i < ci->pm_nclass; i++) {
+		c = ci->pm_classes[i].pm_class;
+
+		printf("%s\n", pmc_name_of_class(c));
+		if (pmc_event_names_of_class(c, &eventnamelist, &nevents) < 0)
+			err(EX_OSERR, "ERROR: Cannot find information for "
+			    "event class \"%s\"", pmc_name_of_class(c));
+
+		for (j = 0; j < nevents; j++)
+			printf("\t%s\n", eventnamelist[j]);
+
+		free(eventnamelist);
+	}
+	return 0;
+}
+
+static int
+pmcc_show_statistics(void)
+{
+
+	struct pmc_driverstats gms;
+
+	if (pmc_get_driver_stats(&gms) < 0)
+		err(EX_OSERR, "ERROR: cannot retrieve driver statistics");
+
+	/*
+	 * Print statistics.
+	 */
+
+#define	PRINT(N,V)	(void) printf("%-40s %d\n", (N), gms.pm_##V)
+	PRINT("interrupts processed:", intr_processed);
+	PRINT("non-PMC interrupts:", intr_ignored);
+	PRINT("sampling stalls due to space shortages:", intr_bufferfull);
+	PRINT("system calls:", syscalls);
+	PRINT("system calls with errors:", syscall_errors);
+	PRINT("buffer requests:", buffer_requests);
+	PRINT("buffer requests failed:", buffer_requests_failed);
+	PRINT("sampling log sweeps:", log_sweeps);
+
+	return 0;
+}
+
+/*
+ * Main
+ */
+
+int
+main(int argc, char **argv)
+{
+	int error, command, currentcpu, option, pmc;
+	char *dummy;
+	struct pmcc_op *p;
+
+#if DEBUG
+	pmcc_init_debug();
+#endif
+
+	/* parse args */
+
+	currentcpu = PMCC_CPU_ALL;
+	command    = PMCC_PRINT_USAGE;
+	error      = 0;
+
+	STAILQ_INIT(&head);
+
+	while ((option = getopt(argc, argv, ":c:d:e:lLs")) != -1)
+		switch (option) {
+		case 'L':
+			if (command != PMCC_PRINT_USAGE) {
+				error = 1;
+				break;
+			}
+			command = PMCC_PRINT_EVENTS;
+			break;
+
+		case 'c':
+			if (command != PMCC_PRINT_USAGE &&
+			    command != PMCC_ENABLE_DISABLE) {
+				error = 1;
+				break;
+			}
+			command = PMCC_ENABLE_DISABLE;
+
+			if (*optarg == PMCC_CPU_WILDCARD)
+				currentcpu = PMCC_CPU_ALL;
+			else {
+				currentcpu = strtoul(optarg, &dummy, 0);
+				if (*dummy != '\0' || currentcpu < 0)
+					errx(EX_DATAERR,
+					    "\"%s\" is not a valid CPU id",
+					    optarg);
+			}
+			break;
+
+		case 'd':
+		case 'e':
+			if (command != PMCC_PRINT_USAGE &&
+			    command != PMCC_ENABLE_DISABLE) {
+				error = 1;
+				break;
+			}
+			command = PMCC_ENABLE_DISABLE;
+
+			if (*optarg == PMCC_PMC_WILDCARD)
+				pmc = PMCC_PMC_ALL;
+			else {
+				pmc = strtoul(optarg, &dummy, 0);
+				if (*dummy != '\0' || pmc < 0)
+					errx(EX_DATAERR,
+					    "\"%s\" is not a valid PMC id",
+					    optarg);
+			}
+
+			if ((p = malloc(sizeof(*p))) == NULL)
+				err(EX_SOFTWARE, "Out of memory");
+
+			p->op_cpu = currentcpu;
+			p->op_pmc = pmc;
+			p->op_op  = option == 'd' ? PMCC_OP_DISABLE :
+			    PMCC_OP_ENABLE;
+
+			STAILQ_INSERT_TAIL(&head, p, op_next);
+			break;
+
+		case 'l':
+			if (command != PMCC_PRINT_USAGE) {
+				error = 1;
+				break;
+			}
+			command = PMCC_LIST_STATE;
+			break;
+
+		case 's':
+			if (command != PMCC_PRINT_USAGE) {
+				error = 1;
+				break;
+			}
+			command = PMCC_SHOW_STATISTICS;
+			break;
+
+		case ':':
+			errx(EX_USAGE,
+			    "Missing argument to option '-%c'", optopt);
+			break;
+
+		case '?':
+			warnx("Unrecognized option \"-%c\"", optopt);
+			errx(EX_USAGE, usage_message);
+			break;
+
+		default:
+			error = 1;
+			break;
+
+		}
+
+	if (command == PMCC_PRINT_USAGE)
+		(void) errx(EX_USAGE, usage_message);
+
+	if (error)
+		exit(EX_USAGE);
+
+	if (pmc_init() < 0)
+		err(EX_UNAVAILABLE,
+		    "Initialization of the pmc(3) library failed");
+
+	switch (command) {
+	case PMCC_LIST_STATE:
+		error = pmcc_do_list_state();
+		break;
+	case PMCC_PRINT_EVENTS:
+		error = pmcc_do_list_events();
+		break;
+	case PMCC_SHOW_STATISTICS:
+		error = pmcc_show_statistics();
+		break;
+	case PMCC_ENABLE_DISABLE:
+		if (STAILQ_EMPTY(&head))
+			errx(EX_USAGE, "No PMCs specified to enable or disable");
+		error = pmcc_do_enable_disable(&head);
+		break;
+	default:
+		assert(0);
+
+	}
+
+	if (error != 0)
+		err(EX_OSERR, "Command failed");
+	exit(0);
+}
diff --git a/usr.sbin/pmcstat/Makefile b/usr.sbin/pmcstat/Makefile
new file mode 100644
index 0000000..ec41400
--- /dev/null
+++ b/usr.sbin/pmcstat/Makefile
@@ -0,0 +1,14 @@
+#
+# $FreeBSD: src/usr.sbin/pmcstat/Makefile,v 1.10 2010/02/25 20:24:19 ru Exp $
+#
+
+PROG=	pmcstat
+MAN=	pmcstat.8
+
+DPADD=	${LIBELF} ${LIBKVM} ${LIBPMC} ${LIBM} ${LIBNCURSES}
+LDADD=	-lelf -lkvm -lpmc -lm -lncurses
+
+SRCS=	pmcstat.c pmcstat.h pmcstat_log.c \
+pmcpl_callgraph.c pmcpl_gprof.c pmcpl_annotate.c pmcpl_calltree.c
+
+.include <bsd.prog.mk>
diff --git a/usr.sbin/pmcstat/pmcpl_annotate.c b/usr.sbin/pmcstat/pmcpl_annotate.c
new file mode 100644
index 0000000..99c26be
--- /dev/null
+++ b/usr.sbin/pmcstat/pmcpl_annotate.c
@@ -0,0 +1,111 @@
+/*-
+ * Copyright (c) 2005-2007, Joseph Koshy
+ * Copyright (c) 2007 The FreeBSD Foundation
+ * All rights reserved.
+ *
+ * Portions of this software were developed by A. Joseph Koshy under
+ * sponsorship from the FreeBSD Foundation and Google, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * Transform a hwpmc(4) log into human readable form, and into
+ * gprof(1) compatible profiles.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: src/usr.sbin/pmcstat/pmcpl_annotate.c,v 1.1 2010/02/11 22:51:44 fabient Exp $");
+
+#include <sys/param.h>
+#include <sys/endian.h>
+#include <sys/gmon.h>
+#include <sys/imgact_aout.h>
+#include <sys/imgact_elf.h>
+#include <sys/mman.h>
+#include <sys/pmc.h>
+#include <sys/queue.h>
+#include <sys/socket.h>
+#include <sys/stat.h>
+#include <sys/wait.h>
+
+#include <netinet/in.h>
+
+#include <assert.h>
+#include <err.h>
+#include <errno.h>
+#include <fcntl.h>
+#include <gelf.h>
+#include <libgen.h>
+#include <limits.h>
+#include <netdb.h>
+#include <pmc.h>
+#include <pmclog.h>
+#include <sysexits.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+
+#include "pmcstat.h"
+#include "pmcstat_log.h"
+#include "pmcpl_annotate.h"
+
+/*
+ * Record a callchain.
+ */
+
+void
+pmcpl_annotate_process(struct pmcstat_process *pp, struct pmcstat_pmcrecord *pmcr,
+    uint32_t nsamples, uintfptr_t *cc, int usermode, uint32_t cpu)
+{
+	struct pmcstat_pcmap *map;
+	struct pmcstat_symbol *sym;
+	uintfptr_t newpc;
+	struct pmcstat_image *image;
+
+	(void) pmcr; (void) nsamples; (void) usermode; (void) cpu;
+
+	map = pmcstat_process_find_map(usermode ? pp : pmcstat_kernproc, cc[0]);
+	if (map == NULL) {
+		/* Unknown offset. */
+		pmcstat_stats.ps_samples_unknown_offset++;
+		return;
+	}
+
+	assert(cc[0] >= map->ppm_lowpc && cc[0] < map->ppm_highpc);
+
+	image = map->ppm_image;
+	newpc = cc[0] - (map->ppm_lowpc +
+		(image->pi_vaddr - image->pi_start));
+	sym = pmcstat_symbol_search(image, newpc);
+	if (sym == NULL)
+		return;
+
+	fprintf(args.pa_graphfile, "%p %s 0x%jx 0x%jx\n",
+		(void *)cc[0],
+		pmcstat_string_unintern(sym->ps_name),
+		(uintmax_t)(sym->ps_start +
+		image->pi_vaddr), (uintmax_t)(sym->ps_end +
+		image->pi_vaddr));
+}
diff --git a/usr.sbin/pmcstat/pmcpl_annotate.h b/usr.sbin/pmcstat/pmcpl_annotate.h
new file mode 100644
index 0000000..56aa85f
--- /dev/null
+++ b/usr.sbin/pmcstat/pmcpl_annotate.h
@@ -0,0 +1,41 @@
+/*-
+ * Copyright (c) 2005-2007, Joseph Koshy
+ * Copyright (c) 2007 The FreeBSD Foundation
+ * All rights reserved.
+ *
+ * Portions of this software were developed by A. Joseph Koshy under
+ * sponsorship from the FreeBSD Foundation and Google, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: src/usr.sbin/pmcstat/pmcpl_annotate.h,v 1.1 2010/02/11 22:51:44 fabient Exp $
+ */
+
+#ifndef	_PMCSTAT_PL_ANNOTATE_H_
+#define	_PMCSTAT_PL_ANNOTATE_H_
+
+/* Function prototypes */
+void pmcpl_annotate_process(
+    struct pmcstat_process *pp, struct pmcstat_pmcrecord *pmcr,
+    uint32_t nsamples, uintfptr_t *cc, int usermode, uint32_t cpu);
+
+#endif	/* _PMCSTAT_PL_ANNOTATE_H_ */
diff --git a/usr.sbin/pmcstat/pmcpl_callgraph.c b/usr.sbin/pmcstat/pmcpl_callgraph.c
new file mode 100644
index 0000000..47a6838
--- /dev/null
+++ b/usr.sbin/pmcstat/pmcpl_callgraph.c
@@ -0,0 +1,686 @@
+/*-
+ * Copyright (c) 2005-2007, Joseph Koshy
+ * Copyright (c) 2007 The FreeBSD Foundation
+ * All rights reserved.
+ *
+ * Portions of this software were developed by A. Joseph Koshy under
+ * sponsorship from the FreeBSD Foundation and Google, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * Transform a hwpmc(4) log into human readable form, and into
+ * gprof(1) compatible profiles.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: src/usr.sbin/pmcstat/pmcpl_callgraph.c,v 1.5 2010/09/03 13:54:02 fabient Exp $");
+
+#include <sys/param.h>
+#include <sys/endian.h>
+#include <sys/gmon.h>
+#include <sys/imgact_aout.h>
+#include <sys/imgact_elf.h>
+#include <sys/mman.h>
+#include <sys/pmc.h>
+#include <sys/queue.h>
+#include <sys/socket.h>
+#include <sys/stat.h>
+#include <sys/wait.h>
+
+#include <netinet/in.h>
+
+#include <assert.h>
+#include <curses.h>
+#include <err.h>
+#include <errno.h>
+#include <fcntl.h>
+#include <gelf.h>
+#include <libgen.h>
+#include <limits.h>
+#include <netdb.h>
+#include <pmc.h>
+#include <pmclog.h>
+#include <sysexits.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+
+#include "pmcstat.h"
+#include "pmcstat_log.h"
+#include "pmcstat_top.h"
+#include "pmcpl_callgraph.h"
+
+/* Get the sample value in percent related to nsamples. */
+#define PMCPL_CG_COUNTP(a) \
+	((a)->pcg_count * 100.0 / nsamples)
+
+/*
+ * The toplevel CG nodes (i.e., with rank == 0) are placed in a hash table.
+ */
+
+struct pmcstat_cgnode_hash_list pmcstat_cgnode_hash[PMCSTAT_NHASH];
+int pmcstat_cgnode_hash_count;
+
+static pmcstat_interned_string pmcstat_previous_filename_printed;
+
+static struct pmcstat_cgnode *
+pmcstat_cgnode_allocate(struct pmcstat_image *image, uintfptr_t pc)
+{
+	struct pmcstat_cgnode *cg;
+
+	if ((cg = malloc(sizeof(*cg))) == NULL)
+		err(EX_OSERR, "ERROR: Cannot allocate callgraph node");
+
+	cg->pcg_image = image;
+	cg->pcg_func = pc;
+
+	cg->pcg_count = 0;
+	cg->pcg_nchildren = 0;
+	LIST_INIT(&cg->pcg_children);
+
+	return (cg);
+}
+
+/*
+ * Free a node and its children.
+ */
+static void
+pmcstat_cgnode_free(struct pmcstat_cgnode *cg)
+{
+	struct pmcstat_cgnode *cgc, *cgtmp;
+
+	LIST_FOREACH_SAFE(cgc, &cg->pcg_children, pcg_sibling, cgtmp)
+		pmcstat_cgnode_free(cgc);
+	free(cg);
+}
+
+/*
+ * Look for a callgraph node associated with pmc `pmcid' in the global
+ * hash table that corresponds to the given `pc' value in the process
+ * `pp'.
+ */
+static struct pmcstat_cgnode *
+pmcstat_cgnode_hash_lookup_pc(struct pmcstat_process *pp, pmc_id_t pmcid,
+    uintfptr_t pc, int usermode)
+{
+	struct pmcstat_pcmap *ppm;
+	struct pmcstat_symbol *sym;
+	struct pmcstat_image *image;
+	struct pmcstat_cgnode *cg;
+	struct pmcstat_cgnode_hash *h;
+	uintfptr_t loadaddress;
+	unsigned int i, hash;
+
+	ppm = pmcstat_process_find_map(usermode ? pp : pmcstat_kernproc, pc);
+	if (ppm == NULL)
+		return (NULL);
+
+	image = ppm->ppm_image;
+
+	loadaddress = ppm->ppm_lowpc + image->pi_vaddr - image->pi_start;
+	pc -= loadaddress;	/* Convert to an offset in the image. */
+
+	/*
+	 * Try determine the function at this offset.  If we can't
+	 * find a function round leave the `pc' value alone.
+	 */
+	if ((sym = pmcstat_symbol_search(image, pc)) != NULL)
+		pc = sym->ps_start;
+	else
+		pmcstat_stats.ps_samples_unknown_function++;
+
+	for (hash = i = 0; i < sizeof(uintfptr_t); i++)
+		hash += (pc >> i) & 0xFF;
+
+	hash &= PMCSTAT_HASH_MASK;
+
+	cg = NULL;
+	LIST_FOREACH(h, &pmcstat_cgnode_hash[hash], pch_next)
+	{
+		if (h->pch_pmcid != pmcid)
+			continue;
+
+		cg = h->pch_cgnode;
+
+		assert(cg != NULL);
+
+		if (cg->pcg_image == image && cg->pcg_func == pc)
+			return (cg);
+	}
+
+	/*
+	 * We haven't seen this (pmcid, pc) tuple yet, so allocate a
+	 * new callgraph node and a new hash table entry for it.
+	 */
+	cg = pmcstat_cgnode_allocate(image, pc);
+	if ((h = malloc(sizeof(*h))) == NULL)
+		err(EX_OSERR, "ERROR: Could not allocate callgraph node");
+
+	h->pch_pmcid = pmcid;
+	h->pch_cgnode = cg;
+	LIST_INSERT_HEAD(&pmcstat_cgnode_hash[hash], h, pch_next);
+
+	pmcstat_cgnode_hash_count++;
+
+	return (cg);
+}
+
+/*
+ * Compare two callgraph nodes for sorting.
+ */
+static int
+pmcstat_cgnode_compare(const void *a, const void *b)
+{
+	const struct pmcstat_cgnode *const *pcg1, *const *pcg2, *cg1, *cg2;
+
+	pcg1 = (const struct pmcstat_cgnode *const *) a;
+	cg1 = *pcg1;
+	pcg2 = (const struct pmcstat_cgnode *const *) b;
+	cg2 = *pcg2;
+
+	/* Sort in reverse order */
+	if (cg1->pcg_count < cg2->pcg_count)
+		return (1);
+	if (cg1->pcg_count > cg2->pcg_count)
+		return (-1);
+	return (0);
+}
+
+/*
+ * Find (allocating if a needed) a callgraph node in the given
+ * parent with the same (image, pcoffset) pair.
+ */
+
+static struct pmcstat_cgnode *
+pmcstat_cgnode_find(struct pmcstat_cgnode *parent, struct pmcstat_image *image,
+    uintfptr_t pcoffset)
+{
+	struct pmcstat_cgnode *child;
+
+	LIST_FOREACH(child, &parent->pcg_children, pcg_sibling) {
+		if (child->pcg_image == image &&
+		    child->pcg_func == pcoffset)
+			return (child);
+	}
+
+	/*
+	 * Allocate a new structure.
+	 */
+
+	child = pmcstat_cgnode_allocate(image, pcoffset);
+
+	/*
+	 * Link it into the parent.
+	 */
+	LIST_INSERT_HEAD(&parent->pcg_children, child, pcg_sibling);
+	parent->pcg_nchildren++;
+
+	return (child);
+}
+
+/*
+ * Print one callgraph node.  The output format is:
+ *
+ * indentation %(parent's samples) #nsamples function@object
+ */
+static void
+pmcstat_cgnode_print(struct pmcstat_cgnode *cg, int depth, uint32_t total)
+{
+	uint32_t n;
+	const char *space;
+	struct pmcstat_symbol *sym;
+	struct pmcstat_cgnode **sortbuffer, **cgn, *pcg;
+
+	space = " ";
+
+	if (depth > 0)
+		(void) fprintf(args.pa_graphfile, "%*s", depth, space);
+
+	if (cg->pcg_count == total)
+		(void) fprintf(args.pa_graphfile, "100.0%% ");
+	else
+		(void) fprintf(args.pa_graphfile, "%05.2f%% ",
+		    100.0 * cg->pcg_count / total);
+
+	n = fprintf(args.pa_graphfile, " [%u] ", cg->pcg_count);
+
+	/* #samples is a 12 character wide field. */
+	if (n < 12)
+		(void) fprintf(args.pa_graphfile, "%*s", 12 - n, space);
+
+	if (depth > 0)
+		(void) fprintf(args.pa_graphfile, "%*s", depth, space);
+
+	sym = pmcstat_symbol_search(cg->pcg_image, cg->pcg_func);
+	if (sym)
+		(void) fprintf(args.pa_graphfile, "%s",
+		    pmcstat_string_unintern(sym->ps_name));
+	else
+		(void) fprintf(args.pa_graphfile, "%p",
+		    (void *) (cg->pcg_image->pi_vaddr + cg->pcg_func));
+
+	if (pmcstat_previous_filename_printed !=
+	    cg->pcg_image->pi_fullpath) {
+		pmcstat_previous_filename_printed = cg->pcg_image->pi_fullpath;
+		(void) fprintf(args.pa_graphfile, " @ %s\n",
+		    pmcstat_string_unintern(
+		    pmcstat_previous_filename_printed));
+	} else
+		(void) fprintf(args.pa_graphfile, "\n");
+
+	if (cg->pcg_nchildren == 0)
+		return;
+
+	if ((sortbuffer = (struct pmcstat_cgnode **)
+		malloc(sizeof(struct pmcstat_cgnode *) *
+		    cg->pcg_nchildren)) == NULL)
+		err(EX_OSERR, "ERROR: Cannot print callgraph");
+	cgn = sortbuffer;
+
+	LIST_FOREACH(pcg, &cg->pcg_children, pcg_sibling)
+	    *cgn++ = pcg;
+
+	assert(cgn - sortbuffer == (int) cg->pcg_nchildren);
+
+	qsort(sortbuffer, cg->pcg_nchildren, sizeof(struct pmcstat_cgnode *),
+	    pmcstat_cgnode_compare);
+
+	for (cgn = sortbuffer, n = 0; n < cg->pcg_nchildren; n++, cgn++)
+		pmcstat_cgnode_print(*cgn, depth+1, cg->pcg_count);
+
+	free(sortbuffer);
+}
+
+/*
+ * Record a callchain.
+ */
+
+void
+pmcpl_cg_process(struct pmcstat_process *pp, struct pmcstat_pmcrecord *pmcr,
+    uint32_t nsamples, uintfptr_t *cc, int usermode, uint32_t cpu)
+{
+	uintfptr_t pc, loadaddress;
+	uint32_t n;
+	struct pmcstat_image *image;
+	struct pmcstat_pcmap *ppm;
+	struct pmcstat_symbol *sym;
+	struct pmcstat_cgnode *parent, *child;
+	struct pmcstat_process *km;
+	pmc_id_t pmcid;
+
+	(void) cpu;
+
+	/*
+	 * Find the callgraph node recorded in the global hash table
+	 * for this (pmcid, pc).
+	 */
+
+	pc = cc[0];
+	pmcid = pmcr->pr_pmcid;
+	parent = pmcstat_cgnode_hash_lookup_pc(pp, pmcid, pc, usermode);
+	if (parent == NULL) {
+		pmcstat_stats.ps_callchain_dubious_frames++;
+		pmcr->pr_dubious_frames++;
+		return;
+	}
+
+	parent->pcg_count++;
+
+	/*
+	 * For each return address in the call chain record, subject
+	 * to the maximum depth desired.
+	 * - Find the image associated with the sample.  Stop if there
+	 *   there is no valid image at that address.
+	 * - Find the function that overlaps the return address.
+	 * - If found: use the start address of the function.
+	 *   If not found (say an object's symbol table is not present or
+	 *   is incomplete), round down to th gprof bucket granularity.
+	 * - Convert return virtual address to an offset in the image.
+	 * - Look for a child with the same {offset,image} tuple,
+	 *   inserting one if needed.
+	 * - Increment the count of occurrences of the child.
+	 */
+	km = pmcstat_kernproc;
+
+	for (n = 1; n < (uint32_t) args.pa_graphdepth && n < nsamples; n++,
+	    parent = child) {
+		pc = cc[n];
+
+		ppm = pmcstat_process_find_map(usermode ? pp : km, pc);
+		if (ppm == NULL) {
+			/* Detect full frame capture (kernel + user). */
+			if (!usermode) {
+				ppm = pmcstat_process_find_map(pp, pc);
+				if (ppm != NULL)
+					km = pp;
+			}
+		}
+		if (ppm == NULL)
+			return;
+
+		image = ppm->ppm_image;
+		loadaddress = ppm->ppm_lowpc + image->pi_vaddr -
+		    image->pi_start;
+		pc -= loadaddress;
+
+		if ((sym = pmcstat_symbol_search(image, pc)) != NULL)
+			pc = sym->ps_start;
+
+		child = pmcstat_cgnode_find(parent, image, pc);
+		child->pcg_count++;
+	}
+}
+
+/*
+ * Printing a callgraph for a PMC.
+ */
+static void
+pmcstat_callgraph_print_for_pmcid(struct pmcstat_pmcrecord *pmcr)
+{
+	int n, nentries;
+	uint32_t nsamples;
+	pmc_id_t pmcid;
+	struct pmcstat_cgnode **sortbuffer, **cgn;
+	struct pmcstat_cgnode_hash *pch;
+
+	/*
+	 * We pull out all callgraph nodes in the top-level hash table
+	 * with a matching PMC id.  We then sort these based on the
+	 * frequency of occurrence.  Each callgraph node is then
+	 * printed.
+	 */
+
+	nsamples = 0;
+	pmcid = pmcr->pr_pmcid;
+	if ((sortbuffer = (struct pmcstat_cgnode **)
+	    malloc(sizeof(struct pmcstat_cgnode *) *
+	    pmcstat_cgnode_hash_count)) == NULL)
+		err(EX_OSERR, "ERROR: Cannot sort callgraph");
+	cgn = sortbuffer;
+
+	for (n = 0; n < PMCSTAT_NHASH; n++)
+		LIST_FOREACH(pch, &pmcstat_cgnode_hash[n], pch_next)
+		    if (pch->pch_pmcid == pmcid) {
+			    nsamples += pch->pch_cgnode->pcg_count;
+			    *cgn++ = pch->pch_cgnode;
+		    }
+
+	nentries = cgn - sortbuffer;
+	assert(nentries <= pmcstat_cgnode_hash_count);
+
+	if (nentries == 0) {
+		free(sortbuffer);
+		return;
+	}
+
+	qsort(sortbuffer, nentries, sizeof(struct pmcstat_cgnode *),
+	    pmcstat_cgnode_compare);
+
+	(void) fprintf(args.pa_graphfile,
+	    "@ %s [%u samples]\n\n",
+	    pmcstat_string_unintern(pmcr->pr_pmcname),
+	    nsamples);
+
+	for (cgn = sortbuffer, n = 0; n < nentries; n++, cgn++) {
+		pmcstat_previous_filename_printed = NULL;
+		pmcstat_cgnode_print(*cgn, 0, nsamples);
+		(void) fprintf(args.pa_graphfile, "\n");
+	}
+
+	free(sortbuffer);
+}
+
+/*
+ * Print out callgraphs.
+ */
+
+static void
+pmcstat_callgraph_print(void)
+{
+	struct pmcstat_pmcrecord *pmcr;
+
+	LIST_FOREACH(pmcr, &pmcstat_pmcs, pr_next)
+	    pmcstat_callgraph_print_for_pmcid(pmcr);
+}
+
+static void
+pmcstat_cgnode_topprint(struct pmcstat_cgnode *cg,
+    int depth, uint32_t nsamples)
+{
+	int v_attrs, vs_len, ns_len, width, len, n, nchildren;
+	float v;
+	char ns[30], vs[10];
+	struct pmcstat_symbol *sym;
+	struct pmcstat_cgnode **sortbuffer, **cgn, *pcg;
+
+	(void) depth;
+
+	/* Format value. */
+	v = PMCPL_CG_COUNTP(cg);
+	snprintf(vs, sizeof(vs), "%.1f", v);
+	v_attrs = PMCSTAT_ATTRPERCENT(v);
+
+	/* Format name. */
+	sym = pmcstat_symbol_search(cg->pcg_image, cg->pcg_func);
+	if (sym != NULL) {
+		snprintf(ns, sizeof(ns), "%s",
+		    pmcstat_string_unintern(sym->ps_name));
+	} else
+		snprintf(ns, sizeof(ns), "%p",
+		    (void *)cg->pcg_func);
+
+	PMCSTAT_ATTRON(v_attrs);
+	PMCSTAT_PRINTW("%5.5s", vs);
+	PMCSTAT_ATTROFF(v_attrs);
+	PMCSTAT_PRINTW(" %-10.10s %-20.20s",
+	    pmcstat_string_unintern(cg->pcg_image->pi_name),
+	    ns);
+
+	nchildren = cg->pcg_nchildren;
+	if (nchildren == 0) {
+		PMCSTAT_PRINTW("\n");
+		return;
+	}
+
+	width = pmcstat_displaywidth - 40;
+
+	if ((sortbuffer = (struct pmcstat_cgnode **)
+		malloc(sizeof(struct pmcstat_cgnode *) *
+		    nchildren)) == NULL)
+		err(EX_OSERR, "ERROR: Cannot print callgraph");
+	cgn = sortbuffer;
+
+	LIST_FOREACH(pcg, &cg->pcg_children, pcg_sibling)
+	    *cgn++ = pcg;
+
+	assert(cgn - sortbuffer == (int)nchildren);
+
+	qsort(sortbuffer, nchildren, sizeof(struct pmcstat_cgnode *),
+	    pmcstat_cgnode_compare);
+
+	/* Count how many callers. */
+	for (cgn = sortbuffer, n = 0; n < nchildren; n++, cgn++) {
+		pcg = *cgn;
+
+		v = PMCPL_CG_COUNTP(pcg);
+		if (v < pmcstat_threshold)
+			break;
+	}
+	nchildren = n;
+
+	for (cgn = sortbuffer, n = 0; n < nchildren; n++, cgn++) {
+		pcg = *cgn;
+
+		/* Format value. */
+		if (nchildren > 1) {
+			v = PMCPL_CG_COUNTP(pcg);
+			vs_len = snprintf(vs, sizeof(vs), ":%.1f", v);
+			v_attrs = PMCSTAT_ATTRPERCENT(v);
+		} else
+			vs_len = 0;
+
+		/* Format name. */
+		sym = pmcstat_symbol_search(pcg->pcg_image, pcg->pcg_func);
+		if (sym != NULL) {
+			ns_len = snprintf(ns, sizeof(ns), "%s",
+			    pmcstat_string_unintern(sym->ps_name));
+		} else
+			ns_len = snprintf(ns, sizeof(ns), "%p",
+			    (void *)pcg->pcg_func);
+
+		len = ns_len + vs_len + 1;
+		if (width - len < 0) {
+			PMCSTAT_PRINTW(" ...");
+			break;
+		}
+		width -= len;
+
+		PMCSTAT_PRINTW(" %s", ns);
+		if (nchildren > 1) {
+			PMCSTAT_ATTRON(v_attrs);
+			PMCSTAT_PRINTW("%s", vs);
+			PMCSTAT_ATTROFF(v_attrs);
+		}
+	}
+	PMCSTAT_PRINTW("\n");
+	free(sortbuffer);
+}
+
+/*
+ * Top mode display.
+ */
+
+void
+pmcpl_cg_topdisplay(void)
+{
+	int n, nentries;
+	uint32_t nsamples;
+	struct pmcstat_cgnode **sortbuffer, **cgn;
+	struct pmcstat_cgnode_hash *pch;
+	struct pmcstat_pmcrecord *pmcr;
+
+	pmcr = pmcstat_pmcindex_to_pmcr(pmcstat_pmcinfilter);
+	if (!pmcr)
+		err(EX_SOFTWARE, "ERROR: invalid pmcindex");
+
+	/*
+	 * We pull out all callgraph nodes in the top-level hash table
+	 * with a matching PMC index.  We then sort these based on the
+	 * frequency of occurrence.  Each callgraph node is then
+	 * printed.
+	 */
+
+	nsamples = 0;
+
+	if ((sortbuffer = (struct pmcstat_cgnode **)
+	    malloc(sizeof(struct pmcstat_cgnode *) *
+	    pmcstat_cgnode_hash_count)) == NULL)
+		err(EX_OSERR, "ERROR: Cannot sort callgraph");
+	cgn = sortbuffer;
+
+	for (n = 0; n < PMCSTAT_NHASH; n++)
+		LIST_FOREACH(pch, &pmcstat_cgnode_hash[n], pch_next)
+		    if (pmcr == NULL || pch->pch_pmcid == pmcr->pr_pmcid) {
+			    nsamples += pch->pch_cgnode->pcg_count;
+			    *cgn++ = pch->pch_cgnode;
+		    }
+
+	nentries = cgn - sortbuffer;
+	assert(nentries <= pmcstat_cgnode_hash_count);
+
+	if (nentries == 0) {
+		free(sortbuffer);
+		return;
+	}
+
+	qsort(sortbuffer, nentries, sizeof(struct pmcstat_cgnode *),
+	    pmcstat_cgnode_compare);
+
+	PMCSTAT_PRINTW("%5.5s %-10.10s %-20.20s %s\n",
+	    "%SAMP", "IMAGE", "FUNCTION", "CALLERS");
+
+	nentries = min(pmcstat_displayheight - 2, nentries);
+
+	for (cgn = sortbuffer, n = 0; n < nentries; n++, cgn++) {
+		if (PMCPL_CG_COUNTP(*cgn) < pmcstat_threshold)
+			break;
+		pmcstat_cgnode_topprint(*cgn, 0, nsamples);
+	}
+
+	free(sortbuffer);
+}
+
+/*
+ * Handle top mode keypress.
+ */
+
+int
+pmcpl_cg_topkeypress(int c, WINDOW *w)
+{
+
+	(void) c; (void) w;
+
+	return 0;
+}
+
+int
+pmcpl_cg_init(void)
+{
+	int i;
+
+	pmcstat_cgnode_hash_count = 0;
+	pmcstat_previous_filename_printed = NULL;
+
+	for (i = 0; i < PMCSTAT_NHASH; i++) {
+		LIST_INIT(&pmcstat_cgnode_hash[i]);
+	}
+
+	return (0);
+}
+
+void
+pmcpl_cg_shutdown(FILE *mf)
+{
+	int i;
+	struct pmcstat_cgnode_hash *pch, *pchtmp;
+
+	(void) mf;
+
+	if (args.pa_flags & FLAG_DO_CALLGRAPHS)
+		pmcstat_callgraph_print();
+
+	/*
+	 * Free memory.
+	 */
+	for (i = 0; i < PMCSTAT_NHASH; i++) {
+		LIST_FOREACH_SAFE(pch, &pmcstat_cgnode_hash[i], pch_next,
+		    pchtmp) {
+			pmcstat_cgnode_free(pch->pch_cgnode);
+			LIST_REMOVE(pch, pch_next);
+			free(pch);
+		}
+	}
+}
diff --git a/usr.sbin/pmcstat/pmcpl_callgraph.h b/usr.sbin/pmcstat/pmcpl_callgraph.h
new file mode 100644
index 0000000..09a7579
--- /dev/null
+++ b/usr.sbin/pmcstat/pmcpl_callgraph.h
@@ -0,0 +1,67 @@
+/*-
+ * Copyright (c) 2005-2007, Joseph Koshy
+ * Copyright (c) 2007 The FreeBSD Foundation
+ * All rights reserved.
+ *
+ * Portions of this software were developed by A. Joseph Koshy under
+ * sponsorship from the FreeBSD Foundation and Google, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: src/usr.sbin/pmcstat/pmcpl_callgraph.h,v 1.1 2010/02/11 22:51:44 fabient Exp $
+ */
+
+#ifndef	_PMCSTAT_PL_CALLGRAPH_H_
+#define	_PMCSTAT_PL_CALLGRAPH_H_
+
+/*
+ * Each call graph node is tracked by a pmcstat_cgnode struct.
+ */
+
+struct pmcstat_cgnode {
+	struct pmcstat_image	*pcg_image;
+	uintfptr_t		pcg_func;
+	uint32_t		pcg_count;
+	uint32_t		pcg_nchildren;
+	LIST_ENTRY(pmcstat_cgnode) pcg_sibling;
+	LIST_HEAD(,pmcstat_cgnode) pcg_children;
+};
+
+struct pmcstat_cgnode_hash {
+	struct pmcstat_cgnode  *pch_cgnode;
+	pmc_id_t		pch_pmcid;
+	LIST_ENTRY(pmcstat_cgnode_hash) pch_next;
+};
+extern LIST_HEAD(pmcstat_cgnode_hash_list, pmcstat_cgnode_hash) pmcstat_cgnode_hash[PMCSTAT_NHASH];
+extern int pmcstat_cgnode_hash_count;
+
+/* Function prototypes */
+int pmcpl_cg_init(void);
+void pmcpl_cg_shutdown(FILE *mf);
+void pmcpl_cg_process(
+    struct pmcstat_process *pp, struct pmcstat_pmcrecord *pmcr,
+    uint32_t nsamples, uintfptr_t *cc, int usermode, uint32_t cpu);
+int pmcpl_cg_topkeypress(int c, WINDOW *w);
+void pmcpl_cg_topdisplay(void);
+void pmcpl_cg_configure(char *opt);
+
+#endif	/* _PMCSTAT_PL_CALLGRAPH_H_ */
diff --git a/usr.sbin/pmcstat/pmcpl_calltree.c b/usr.sbin/pmcstat/pmcpl_calltree.c
new file mode 100644
index 0000000..efb92f8
--- /dev/null
+++ b/usr.sbin/pmcstat/pmcpl_calltree.c
@@ -0,0 +1,1044 @@
+/*-
+ * Copyright (c) 2009, Fabien Thomas
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * Process hwpmc(4) samples as calltree.
+ *
+ * Output file format compatible with Kcachegrind (kdesdk).
+ * Handle top mode with a sorted tree display.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: src/usr.sbin/pmcstat/pmcpl_calltree.c,v 1.9 2010/09/03 13:54:02 fabient Exp $");
+
+#include <sys/param.h>
+#include <sys/endian.h>
+#include <sys/queue.h>
+
+#include <assert.h>
+#include <curses.h>
+#include <ctype.h>
+#include <err.h>
+#include <errno.h>
+#include <fcntl.h>
+#include <pmc.h>
+#include <pmclog.h>
+#include <sysexits.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+#include <sysexits.h>
+
+#include "pmcstat.h"
+#include "pmcstat_log.h"
+#include "pmcstat_top.h"
+#include "pmcpl_calltree.h"
+
+#define PMCPL_CT_GROWSIZE	4
+
+static pmcstat_interned_string pmcpl_ct_prevfn;
+
+static int pmcstat_skiplink = 0;
+
+struct pmcpl_ct_node;
+
+/* Get the sample value for PMC a. */
+#define PMCPL_CT_SAMPLE(a, b) \
+	((a) < (b)->npmcs ? (b)->sb[a] : 0)
+
+/* Get the sample value in percent related to rsamples. */
+#define PMCPL_CT_SAMPLEP(a, b) \
+	(PMCPL_CT_SAMPLE(a, b) * 100.0 / rsamples->sb[a])
+
+struct pmcpl_ct_sample {
+	int		npmcs;		/* Max pmc index available. */
+	unsigned	*sb;		/* Sample buffer for 0..npmcs. */
+};
+
+struct pmcpl_ct_arc {
+	struct pmcpl_ct_sample	pcta_samples;
+	struct pmcpl_ct_sample	pcta_callid;
+	unsigned		pcta_call;
+	struct pmcpl_ct_node	*pcta_child;
+};
+
+struct pmcpl_ct_instr {
+	uintfptr_t		pctf_func;
+	struct pmcpl_ct_sample	pctf_samples;
+};
+
+/*
+ * Each calltree node is tracked by a pmcpl_ct_node struct.
+ */
+struct pmcpl_ct_node {
+#define PMCPL_PCT_TAG	0x00000001	/* Loop detection. */
+	uint32_t		pct_flags;
+	struct pmcstat_image	*pct_image;
+	uintfptr_t		pct_func;
+	struct pmcpl_ct_sample	pct_samples;
+
+	int			pct_narc;
+	int			pct_arc_c;
+	struct pmcpl_ct_arc 	*pct_arc;
+
+	/* TODO: optimize for large number of items. */
+	int			pct_ninstr;
+	int			pct_instr_c;
+	struct pmcpl_ct_instr	*pct_instr;
+};
+
+struct pmcpl_ct_node_hash {
+	struct pmcpl_ct_node  *pch_ctnode;
+	LIST_ENTRY(pmcpl_ct_node_hash) pch_next;
+};
+
+struct pmcpl_ct_sample pmcpl_ct_callid;
+
+#define PMCPL_CT_MAXCOL		PMC_CALLCHAIN_DEPTH_MAX
+#define PMCPL_CT_MAXLINE	1024	/* TODO: dynamic. */
+
+struct pmcpl_ct_line {
+	unsigned	ln_sum;
+	unsigned	ln_index;
+};
+
+struct pmcpl_ct_line	pmcpl_ct_topmax[PMCPL_CT_MAXLINE+1];
+struct pmcpl_ct_node	*pmcpl_ct_topscreen[PMCPL_CT_MAXCOL+1][PMCPL_CT_MAXLINE+1];
+
+/*
+ * All nodes indexed by function/image name are placed in a hash table.
+ */
+static LIST_HEAD(,pmcpl_ct_node_hash) pmcpl_ct_node_hash[PMCSTAT_NHASH];
+
+/*
+ * Root node for the graph.
+ */
+static struct pmcpl_ct_node *pmcpl_ct_root;
+
+/*
+ * Prototypes
+ */
+
+/*
+ * Initialize a samples.
+ */
+
+static void
+pmcpl_ct_samples_init(struct pmcpl_ct_sample *samples)
+{
+
+	samples->npmcs = 0;
+	samples->sb = NULL;
+}
+
+/*
+ * Free a samples.
+ */
+
+static void
+pmcpl_ct_samples_free(struct pmcpl_ct_sample *samples)
+{
+
+	samples->npmcs = 0;
+	free(samples->sb);
+	samples->sb = NULL;
+}
+
+/*
+ * Grow a sample block to store pmcstat_npmcs PMCs.
+ */
+
+static void
+pmcpl_ct_samples_grow(struct pmcpl_ct_sample *samples)
+{
+	int npmcs;
+
+	/* Enough storage. */
+	if (pmcstat_npmcs <= samples->npmcs)
+                return;
+
+	npmcs = samples->npmcs +
+	    max(pmcstat_npmcs - samples->npmcs, PMCPL_CT_GROWSIZE);
+	samples->sb = realloc(samples->sb, npmcs * sizeof(unsigned));
+	if (samples->sb == NULL)
+		errx(EX_SOFTWARE, "ERROR: out of memory");
+	bzero((char *)samples->sb + samples->npmcs * sizeof(unsigned),
+	    (npmcs - samples->npmcs) * sizeof(unsigned));
+	samples->npmcs = npmcs;
+}
+
+/*
+ * Compute the sum of all root arcs.
+ */
+
+static void
+pmcpl_ct_samples_root(struct pmcpl_ct_sample *samples)
+{
+	int i, pmcin;
+
+	pmcpl_ct_samples_init(samples);
+	pmcpl_ct_samples_grow(samples);
+
+	for (i = 0; i < pmcpl_ct_root->pct_narc; i++)
+		for (pmcin = 0; pmcin < pmcstat_npmcs; pmcin++)
+			samples->sb[pmcin] += PMCPL_CT_SAMPLE(pmcin,
+			    &pmcpl_ct_root->pct_arc[i].pcta_samples);
+}
+
+/*
+ * Grow the arc table.
+ */
+
+static void
+pmcpl_ct_arc_grow(int cursize, int *maxsize, struct pmcpl_ct_arc **items)
+{
+	int nmaxsize;
+
+	if (cursize < *maxsize)
+		return;
+
+	nmaxsize = *maxsize + max(cursize + 1 - *maxsize, PMCPL_CT_GROWSIZE);
+	*items = realloc(*items, nmaxsize * sizeof(struct pmcpl_ct_arc));
+	if (*items == NULL)
+		errx(EX_SOFTWARE, "ERROR: out of memory");
+	bzero((char *)*items + *maxsize * sizeof(struct pmcpl_ct_arc),
+	    (nmaxsize - *maxsize) * sizeof(struct pmcpl_ct_arc));
+	*maxsize = nmaxsize;
+}
+
+/*
+ * Grow the instr table.
+ */
+
+static void
+pmcpl_ct_instr_grow(int cursize, int *maxsize, struct pmcpl_ct_instr **items)
+{
+	int nmaxsize;
+
+	if (cursize < *maxsize)
+		return;
+
+	nmaxsize = *maxsize + max(cursize + 1 - *maxsize, PMCPL_CT_GROWSIZE);
+	*items = realloc(*items, nmaxsize * sizeof(struct pmcpl_ct_instr));
+	if (*items == NULL)
+		errx(EX_SOFTWARE, "ERROR: out of memory");
+	bzero((char *)*items + *maxsize * sizeof(struct pmcpl_ct_instr),
+	    (nmaxsize - *maxsize) * sizeof(struct pmcpl_ct_instr));
+	*maxsize = nmaxsize;
+}
+
+/*
+ * Add a new instruction sample to given node.
+ */
+
+static void
+pmcpl_ct_instr_add(struct pmcpl_ct_node *ct, int pmcin, uintfptr_t pc)
+{
+	int i;
+	struct pmcpl_ct_instr *in;
+
+	for (i = 0; i<ct->pct_ninstr; i++) {
+		if (ct->pct_instr[i].pctf_func == pc) {
+			in = &ct->pct_instr[i];
+			pmcpl_ct_samples_grow(&in->pctf_samples);
+			in->pctf_samples.sb[pmcin]++;
+			return;
+		}
+	}
+
+	pmcpl_ct_instr_grow(ct->pct_ninstr, &ct->pct_instr_c, &ct->pct_instr);
+	in = &ct->pct_instr[ct->pct_ninstr];
+	in->pctf_func = pc;
+	pmcpl_ct_samples_init(&in->pctf_samples);
+	pmcpl_ct_samples_grow(&in->pctf_samples);
+	in->pctf_samples.sb[pmcin] = 1;
+	ct->pct_ninstr++;
+}
+
+/*
+ * Allocate a new node.
+ */
+
+static struct pmcpl_ct_node *
+pmcpl_ct_node_allocate(struct pmcstat_image *image, uintfptr_t pc)
+{
+	struct pmcpl_ct_node *ct;
+
+	if ((ct = malloc(sizeof(*ct))) == NULL)
+		err(EX_OSERR, "ERROR: Cannot allocate callgraph node");
+
+	ct->pct_flags	= 0;
+	ct->pct_image 	= image;
+	ct->pct_func	= pc;
+
+	pmcpl_ct_samples_init(&ct->pct_samples);
+
+	ct->pct_narc	= 0;
+	ct->pct_arc_c	= 0;
+	ct->pct_arc	= NULL;
+
+	ct->pct_ninstr	= 0;
+	ct->pct_instr_c	= 0;
+	ct->pct_instr	= NULL;
+
+	return (ct);
+}
+
+/*
+ * Free a node.
+ */
+
+static void
+pmcpl_ct_node_free(struct pmcpl_ct_node *ct)
+{
+	int i;
+
+	for (i = 0; i < ct->pct_narc; i++) {
+		pmcpl_ct_samples_free(&ct->pct_arc[i].pcta_samples);
+		pmcpl_ct_samples_free(&ct->pct_arc[i].pcta_callid);
+	}
+
+	pmcpl_ct_samples_free(&ct->pct_samples);
+	free(ct->pct_arc);
+	free(ct->pct_instr);
+	free(ct);
+}
+
+/*
+ * Clear the graph tag on each node.
+ */
+static void
+pmcpl_ct_node_cleartag(void)
+{
+	int i;
+	struct pmcpl_ct_node_hash *pch;
+
+	for (i = 0; i < PMCSTAT_NHASH; i++)
+		LIST_FOREACH(pch, &pmcpl_ct_node_hash[i], pch_next)
+			pch->pch_ctnode->pct_flags &= ~PMCPL_PCT_TAG;
+
+	pmcpl_ct_root->pct_flags &= ~PMCPL_PCT_TAG;
+}
+
+/*
+ * Print the callchain line by line with maximum cost at top.
+ */
+
+static int
+pmcpl_ct_node_dumptop(int pmcin, struct pmcpl_ct_node *ct,
+    struct pmcpl_ct_sample *rsamples, int x, int *y)
+{
+	int i, terminal;
+	struct pmcpl_ct_arc *arc;
+
+	if (ct->pct_flags & PMCPL_PCT_TAG)
+		return 0;
+
+	ct->pct_flags |= PMCPL_PCT_TAG;
+
+	if (x >= PMCPL_CT_MAXCOL) {
+		pmcpl_ct_topscreen[x][*y] = NULL;
+		return 1;
+	}
+	pmcpl_ct_topscreen[x][*y] = ct;
+
+	/*
+	 * Check if this is a terminal node.
+	 * We need to check that some samples exist
+	 * for at least one arc for that PMC.
+	 */
+	terminal = 1;
+	for (i = 0; i < ct->pct_narc; i++) {
+		arc = &ct->pct_arc[i];
+		if (PMCPL_CT_SAMPLE(pmcin,
+		    &arc->pcta_samples) != 0 &&
+		    PMCPL_CT_SAMPLEP(pmcin,
+		    &arc->pcta_samples) > pmcstat_threshold &&
+		    (arc->pcta_child->pct_flags & PMCPL_PCT_TAG) == 0) {
+			terminal = 0;
+			break;
+		}
+	}
+
+	if (ct->pct_narc == 0 || terminal) {
+		pmcpl_ct_topscreen[x+1][*y] = NULL;
+		if (*y >= PMCPL_CT_MAXLINE)
+			return 1;
+		*y = *y + 1;
+		for (i=0; i < x; i++)
+			pmcpl_ct_topscreen[i][*y] =
+			    pmcpl_ct_topscreen[i][*y - 1];
+		return 0;
+	}
+
+	for (i = 0; i < ct->pct_narc; i++) {
+		if (PMCPL_CT_SAMPLE(pmcin,
+		    &ct->pct_arc[i].pcta_samples) == 0)
+			continue;
+		if (PMCPL_CT_SAMPLEP(pmcin,
+		    &ct->pct_arc[i].pcta_samples) > pmcstat_threshold) {
+			if (pmcpl_ct_node_dumptop(pmcin,
+			        ct->pct_arc[i].pcta_child,
+			        rsamples, x+1, y))
+				return 1;
+		}
+	}
+
+	return 0;
+}
+
+/*
+ * Compare two top line by sum.
+ */
+static int
+pmcpl_ct_line_compare(const void *a, const void *b)
+{
+	const struct pmcpl_ct_line *ct1, *ct2;
+
+	ct1 = (const struct pmcpl_ct_line *) a;
+	ct2 = (const struct pmcpl_ct_line *) b;
+
+	/* Sort in reverse order */
+	if (ct1->ln_sum < ct2->ln_sum)
+		return (1);
+	if (ct1->ln_sum > ct2->ln_sum)
+		return (-1);
+	return (0);
+}
+
+/*
+ * Format and display given PMC index.
+ */
+
+static void
+pmcpl_ct_node_printtop(struct pmcpl_ct_sample *rsamples, int pmcin, int maxy)
+{
+#undef	TS
+#undef	TSI
+#define	TS(x, y)	(pmcpl_ct_topscreen[x][y])
+#define	TSI(x, y)	(pmcpl_ct_topscreen[x][pmcpl_ct_topmax[y].ln_index])
+
+	int v_attrs, ns_len, vs_len, is_len, width, indentwidth, x, y;
+	float v;
+	char ns[30], vs[10], is[20];
+	struct pmcpl_ct_node *ct;
+	struct pmcstat_symbol *sym;
+	const char *space = " ";
+
+	/*
+	 * Sort by line cost.
+	 */
+	for (y = 0; ; y++) {
+		ct = TS(1, y);
+		if (ct == NULL)
+			break;
+
+		pmcpl_ct_topmax[y].ln_sum = 0;
+		pmcpl_ct_topmax[y].ln_index = y;
+		for (x = 1; TS(x, y) != NULL; x++) {
+			pmcpl_ct_topmax[y].ln_sum +=
+			    PMCPL_CT_SAMPLE(pmcin, &TS(x, y)->pct_samples);
+		}
+	}
+	qsort(pmcpl_ct_topmax, y, sizeof(pmcpl_ct_topmax[0]),
+	    pmcpl_ct_line_compare);
+	pmcpl_ct_topmax[y].ln_index = y;
+
+	for (y = 0; y < maxy; y++) {
+		ct = TSI(1, y);
+		if (ct == NULL)
+			break;
+
+		if (y > 0)
+			PMCSTAT_PRINTW("\n");
+
+		/* Output sum. */
+		v = pmcpl_ct_topmax[y].ln_sum * 100.0 /
+		    rsamples->sb[pmcin];
+		snprintf(vs, sizeof(vs), "%.1f", v);
+		v_attrs = PMCSTAT_ATTRPERCENT(v);
+		PMCSTAT_ATTRON(v_attrs);
+		PMCSTAT_PRINTW("%5.5s ", vs);
+		PMCSTAT_ATTROFF(v_attrs);
+
+		width = indentwidth = 5 + 1;
+
+		for (x = 1; (ct = TSI(x, y)) != NULL; x++) {
+
+			vs[0] = '\0'; vs_len = 0;
+			is[0] = '\0'; is_len = 0;
+
+			/* Format value. */
+			v = PMCPL_CT_SAMPLEP(pmcin, &ct->pct_samples);
+			if (v > pmcstat_threshold)
+				vs_len  = snprintf(vs, sizeof(vs),
+				    "(%.1f%%)", v);
+			v_attrs = PMCSTAT_ATTRPERCENT(v);
+
+			if (pmcstat_skiplink && v <= pmcstat_threshold) {
+				strlcpy(ns, ".", sizeof(ns));
+				ns_len = 1;
+			} else {
+			sym = pmcstat_symbol_search(ct->pct_image, ct->pct_func);
+			if (sym != NULL) {
+				ns_len = snprintf(ns, sizeof(ns), "%s",
+				    pmcstat_string_unintern(sym->ps_name));
+			} else
+				ns_len = snprintf(ns, sizeof(ns), "%p",
+				    (void *)ct->pct_func);
+
+			/* Format image. */
+			if (x == 1 ||
+			    TSI(x-1, y)->pct_image != ct->pct_image)
+				is_len = snprintf(is, sizeof(is), "@%s",
+				    pmcstat_string_unintern(ct->pct_image->pi_name));
+
+			/* Check for line wrap. */
+			width += ns_len + is_len + vs_len + 1;
+			}
+			if (width >= pmcstat_displaywidth) {
+				maxy--;
+				if (y >= maxy)
+					break;
+				PMCSTAT_PRINTW("\n%*s", indentwidth, space);
+				width = indentwidth + ns_len + is_len + vs_len;
+			}
+
+			PMCSTAT_ATTRON(v_attrs);
+			PMCSTAT_PRINTW("%s%s%s ", ns, is, vs);
+			PMCSTAT_ATTROFF(v_attrs);
+		}
+	}
+}
+
+/*
+ * Output top mode snapshot.
+ */
+
+void
+pmcpl_ct_topdisplay(void)
+{
+	int y;
+	struct pmcpl_ct_sample r, *rsamples;
+
+	rsamples = &r;
+	pmcpl_ct_samples_root(rsamples);
+
+	pmcpl_ct_node_cleartag();
+
+	PMCSTAT_PRINTW("%5.5s %s\n", "%SAMP", "CALLTREE");
+
+	y = 0;
+	if (pmcpl_ct_node_dumptop(pmcstat_pmcinfilter,
+	    pmcpl_ct_root, rsamples, 0, &y))
+		PMCSTAT_PRINTW("...\n");
+	pmcpl_ct_topscreen[1][y] = NULL;
+
+	pmcpl_ct_node_printtop(rsamples,
+	    pmcstat_pmcinfilter, pmcstat_displayheight - 2);
+
+	pmcpl_ct_samples_free(rsamples);
+}
+
+/*
+ * Handle top mode keypress.
+ */
+
+int
+pmcpl_ct_topkeypress(int c, WINDOW *w)
+{
+
+	switch (c) {
+	case 'f':
+		pmcstat_skiplink = !pmcstat_skiplink;
+		wprintw(w, "skip empty link %s", pmcstat_skiplink ? "on" : "off");
+		break;
+	}
+
+	return 0;
+}
+
+/*
+ * Look for a callgraph node associated with pmc `pmcid' in the global
+ * hash table that corresponds to the given `pc' value in the process map
+ * `ppm'.
+ */
+
+static struct pmcpl_ct_node *
+pmcpl_ct_node_hash_lookup_pc(struct pmcpl_ct_node *parent,
+    struct pmcstat_pcmap *ppm, uintfptr_t pc, int pmcin)
+{
+	struct pmcstat_symbol *sym;
+	struct pmcstat_image *image;
+	struct pmcpl_ct_node *ct;
+	struct pmcpl_ct_node_hash *h;
+	struct pmcpl_ct_arc *arc;
+	uintfptr_t loadaddress;
+	int i;
+	unsigned int hash;
+
+	assert(parent != NULL);
+
+	image = ppm->ppm_image;
+
+	loadaddress = ppm->ppm_lowpc + image->pi_vaddr - image->pi_start;
+	pc -= loadaddress;	/* Convert to an offset in the image. */
+
+	/*
+	 * Try determine the function at this offset.  If we can't
+	 * find a function round leave the `pc' value alone.
+	 */
+	if ((sym = pmcstat_symbol_search(image, pc)) != NULL)
+		pc = sym->ps_start;
+	else
+		pmcstat_stats.ps_samples_unknown_function++;
+
+	for (hash = i = 0; i < (int)sizeof(uintfptr_t); i++)
+		hash += (pc >> i) & 0xFF;
+
+	hash &= PMCSTAT_HASH_MASK;
+
+	ct = NULL;
+	LIST_FOREACH(h, &pmcpl_ct_node_hash[hash], pch_next) {
+		ct = h->pch_ctnode;
+
+		assert(ct != NULL);
+
+		if (ct->pct_image == image && ct->pct_func == pc) {
+			/*
+			 * Find related arc in parent node and
+			 * increment the sample count.
+			 */
+			for (i = 0; i < parent->pct_narc; i++) {
+				if (parent->pct_arc[i].pcta_child == ct) {
+					arc = &parent->pct_arc[i];
+					pmcpl_ct_samples_grow(&arc->pcta_samples);
+					arc->pcta_samples.sb[pmcin]++;
+					/* Estimate call count. */
+					pmcpl_ct_samples_grow(&arc->pcta_callid);
+					if (pmcpl_ct_callid.sb[pmcin] -
+					    arc->pcta_callid.sb[pmcin] > 1)
+						arc->pcta_call++;
+					arc->pcta_callid.sb[pmcin] =
+					    pmcpl_ct_callid.sb[pmcin];
+					return (ct);
+				}
+			}
+
+			/*
+			 * No arc found for us, add ourself to the parent.
+			 */
+			pmcpl_ct_arc_grow(parent->pct_narc,
+			    &parent->pct_arc_c, &parent->pct_arc);
+			arc = &parent->pct_arc[parent->pct_narc];
+			pmcpl_ct_samples_grow(&arc->pcta_samples);
+			arc->pcta_samples.sb[pmcin] = 1;
+			arc->pcta_call = 1;
+			pmcpl_ct_samples_grow(&arc->pcta_callid);
+			arc->pcta_callid.sb[pmcin] = pmcpl_ct_callid.sb[pmcin];
+			arc->pcta_child = ct;
+			parent->pct_narc++;
+			return (ct);
+		}
+	}
+
+	/*
+	 * We haven't seen this (pmcid, pc) tuple yet, so allocate a
+	 * new callgraph node and a new hash table entry for it.
+	 */
+	ct = pmcpl_ct_node_allocate(image, pc);
+	if ((h = malloc(sizeof(*h))) == NULL)
+		err(EX_OSERR, "ERROR: Could not allocate callgraph node");
+
+	h->pch_ctnode = ct;
+	LIST_INSERT_HEAD(&pmcpl_ct_node_hash[hash], h, pch_next);
+
+	pmcpl_ct_arc_grow(parent->pct_narc,
+	    &parent->pct_arc_c, &parent->pct_arc);
+	arc = &parent->pct_arc[parent->pct_narc];
+	pmcpl_ct_samples_grow(&arc->pcta_samples);
+	arc->pcta_samples.sb[pmcin] = 1;
+	arc->pcta_call = 1;
+	pmcpl_ct_samples_grow(&arc->pcta_callid);
+	arc->pcta_callid.sb[pmcin] = pmcpl_ct_callid.sb[pmcin];
+	arc->pcta_child = ct;
+	parent->pct_narc++;
+	return (ct);
+}
+
+/*
+ * Record a callchain.
+ */
+
+void
+pmcpl_ct_process(struct pmcstat_process *pp, struct pmcstat_pmcrecord *pmcr,
+    uint32_t nsamples, uintfptr_t *cc, int usermode, uint32_t cpu)
+{
+	int n, pmcin;
+	struct pmcstat_pcmap *ppm[PMC_CALLCHAIN_DEPTH_MAX];
+	struct pmcstat_process *km;
+	struct pmcpl_ct_node *parent, *child;
+
+	(void) cpu;
+
+	assert(nsamples>0 && nsamples<=PMC_CALLCHAIN_DEPTH_MAX);
+
+	/* Get the PMC index. */
+	pmcin = pmcr->pr_pmcin;
+
+	/*
+	 * Validate mapping for the callchain.
+	 * Go from bottom to first invalid entry.
+	 */
+	km = pmcstat_kernproc;
+	for (n = 0; n < (int)nsamples; n++) {
+		ppm[n] = pmcstat_process_find_map(usermode ?
+		    pp : km, cc[n]);
+		if (ppm[n] == NULL) {
+			/* Detect full frame capture (kernel + user). */
+			if (!usermode) {
+				ppm[n] = pmcstat_process_find_map(pp, cc[n]);
+				if (ppm[n] != NULL)
+					km = pp;
+			}
+		}
+		if (ppm[n] == NULL)
+			break;
+	}
+	if (n-- == 0) {
+		pmcstat_stats.ps_callchain_dubious_frames++;
+		pmcr->pr_dubious_frames++;
+		return;
+	}
+
+	/* Increase the call generation counter. */
+	pmcpl_ct_samples_grow(&pmcpl_ct_callid);
+	pmcpl_ct_callid.sb[pmcin]++;
+
+	/*
+	 * Iterate remaining addresses.
+	 */
+	for (parent = pmcpl_ct_root, child = NULL; n >= 0; n--) {
+		child = pmcpl_ct_node_hash_lookup_pc(parent, ppm[n], cc[n],
+		    pmcin);
+		if (child == NULL) {
+			pmcstat_stats.ps_callchain_dubious_frames++;
+			continue;
+		}
+		parent = child;
+	}
+
+	/*
+	 * Increment the sample count for this PMC.
+	 */
+	if (child != NULL) {
+		pmcpl_ct_samples_grow(&child->pct_samples);
+		child->pct_samples.sb[pmcin]++;
+
+		/* Update per instruction sample if required. */
+		if (args.pa_ctdumpinstr)
+			pmcpl_ct_instr_add(child, pmcin, cc[0] -
+			    (ppm[0]->ppm_lowpc + ppm[0]->ppm_image->pi_vaddr -
+			     ppm[0]->ppm_image->pi_start));
+	}
+}
+
+/*
+ * Print node self cost.
+ */
+
+static void
+pmcpl_ct_node_printself(struct pmcpl_ct_node *ct)
+{
+	int i, j, line;
+	uintptr_t addr;
+	struct pmcstat_symbol *sym;
+	char sourcefile[PATH_MAX];
+	char funcname[PATH_MAX];
+
+	/*
+	 * Object binary.
+	 */
+#ifdef PMCPL_CT_OPTIMIZEFN
+	if (pmcpl_ct_prevfn != ct->pct_image->pi_fullpath) {
+#endif
+		pmcpl_ct_prevfn = ct->pct_image->pi_fullpath;
+		fprintf(args.pa_graphfile, "ob=%s\n",
+		    pmcstat_string_unintern(pmcpl_ct_prevfn));
+#ifdef PMCPL_CT_OPTIMIZEFN
+	}
+#endif
+
+	/*
+	 * Function name.
+	 */
+	if (pmcstat_image_addr2line(ct->pct_image, ct->pct_func,
+	    sourcefile, sizeof(sourcefile), &line,
+	    funcname, sizeof(funcname))) {
+		fprintf(args.pa_graphfile, "fn=%s\n",
+		    funcname);
+	} else {
+		sym = pmcstat_symbol_search(ct->pct_image, ct->pct_func);
+		if (sym != NULL)
+			fprintf(args.pa_graphfile, "fn=%s\n",
+			    pmcstat_string_unintern(sym->ps_name));
+		else
+			fprintf(args.pa_graphfile, "fn=%p\n",
+			    (void *)(ct->pct_image->pi_vaddr + ct->pct_func));
+	}
+
+	/*
+	 * Self cost.
+	 */
+	if (ct->pct_ninstr > 0) {
+		for (i = 0; i < ct->pct_ninstr; i++) {
+			addr = ct->pct_image->pi_vaddr +
+			    ct->pct_instr[i].pctf_func;
+			line = 0;
+			if (pmcstat_image_addr2line(ct->pct_image, addr,
+			    sourcefile, sizeof(sourcefile), &line,
+			    funcname, sizeof(funcname)))
+				fprintf(args.pa_graphfile, "fl=%s\n", sourcefile);
+			fprintf(args.pa_graphfile, "%p %u", (void *)addr, line);
+			for (j = 0; j<pmcstat_npmcs; j++)
+				fprintf(args.pa_graphfile, " %u",
+				    PMCPL_CT_SAMPLE(j,
+				    &ct->pct_instr[i].pctf_samples));
+			fprintf(args.pa_graphfile, "\n");
+		}
+	} else {
+		addr = ct->pct_image->pi_vaddr + ct->pct_func;
+		line = 0;
+		if (pmcstat_image_addr2line(ct->pct_image, addr,
+		    sourcefile, sizeof(sourcefile), &line,
+		    funcname, sizeof(funcname)))
+			fprintf(args.pa_graphfile, "fl=%s\n", sourcefile);
+		fprintf(args.pa_graphfile, "* *");
+		for (i = 0; i<pmcstat_npmcs ; i++)
+			fprintf(args.pa_graphfile, " %u",
+			    PMCPL_CT_SAMPLE(i, &ct->pct_samples));
+		fprintf(args.pa_graphfile, "\n");
+	}
+}
+
+/*
+ * Print node child cost.
+ */
+
+static void
+pmcpl_ct_node_printchild(struct pmcpl_ct_node *ct)
+{
+	int i, j, line;
+	uintptr_t addr;
+	struct pmcstat_symbol *sym;
+	struct pmcpl_ct_node *child;
+	char sourcefile[PATH_MAX];
+	char funcname[PATH_MAX];
+
+	/*
+	 * Child cost.
+	 * TODO: attach child cost to the real position in the funtion.
+	 * TODO: cfn=<fn> / call <ncall> addr(<fn>) / addr(call <fn>) <arccost>
+	 */
+	for (i=0 ; i<ct->pct_narc; i++) {
+		child = ct->pct_arc[i].pcta_child;
+
+		/* Object binary. */
+#ifdef PMCPL_CT_OPTIMIZEFN
+		if (pmcpl_ct_prevfn != child->pct_image->pi_fullpath) {
+#endif
+			pmcpl_ct_prevfn = child->pct_image->pi_fullpath;
+			fprintf(args.pa_graphfile, "cob=%s\n",
+			    pmcstat_string_unintern(pmcpl_ct_prevfn));
+#if PMCPL_CT_OPTIMIZEFN
+		}
+#endif
+		/* Child function name. */
+		addr = child->pct_image->pi_vaddr + child->pct_func;
+		/* Child function source file. */
+		if (pmcstat_image_addr2line(child->pct_image, addr,
+		    sourcefile, sizeof(sourcefile), &line,
+		    funcname, sizeof(funcname))) {
+			fprintf(args.pa_graphfile, "cfn=%s\n", funcname);
+			fprintf(args.pa_graphfile, "cfl=%s\n", sourcefile);
+		} else {
+			sym = pmcstat_symbol_search(child->pct_image,
+			    child->pct_func);
+			if (sym != NULL)
+				fprintf(args.pa_graphfile, "cfn=%s\n",
+				    pmcstat_string_unintern(sym->ps_name));
+			else
+				fprintf(args.pa_graphfile, "cfn=%p\n", (void *)addr);
+		}
+
+		/* Child function address, line and call count. */
+		fprintf(args.pa_graphfile, "calls=%u %p %u\n",
+		    ct->pct_arc[i].pcta_call, (void *)addr, line);
+
+		if (ct->pct_image != NULL) {
+			/* Call address, line, sample. */
+			addr = ct->pct_image->pi_vaddr + ct->pct_func;
+			line = 0;
+			if (pmcstat_image_addr2line(ct->pct_image, addr, sourcefile,
+			    sizeof(sourcefile), &line,
+			    funcname, sizeof(funcname)))
+				fprintf(args.pa_graphfile, "%p %u", (void *)addr, line);
+			else
+				fprintf(args.pa_graphfile, "* *");
+		}
+		else
+			fprintf(args.pa_graphfile, "* *");
+		for (j = 0; j<pmcstat_npmcs; j++)
+			fprintf(args.pa_graphfile, " %u",
+			    PMCPL_CT_SAMPLE(j, &ct->pct_arc[i].pcta_samples));
+		fprintf(args.pa_graphfile, "\n");
+	}
+}
+
+/*
+ * Clean the PMC name for Kcachegrind formula
+ */
+
+static void
+pmcpl_ct_fixup_pmcname(char *s)
+{
+	char *p;
+
+	for (p = s; *p; p++)
+		if (!isalnum(*p))
+			*p = '_';
+}
+
+/*
+ * Print a calltree (KCachegrind) for all PMCs.
+ */
+
+static void
+pmcpl_ct_print(void)
+{
+	int n, i;
+	struct pmcpl_ct_node_hash *pch;
+	struct pmcpl_ct_sample rsamples;
+	char name[40];
+
+	pmcpl_ct_samples_root(&rsamples);
+	pmcpl_ct_prevfn = NULL;
+
+	fprintf(args.pa_graphfile,
+		"version: 1\n"
+		"creator: pmcstat\n"
+		"positions: instr line\n"
+		"events:");
+	for (i=0; i<pmcstat_npmcs; i++) {
+		snprintf(name, sizeof(name), "%s_%d",
+		    pmcstat_pmcindex_to_name(i), i);
+		pmcpl_ct_fixup_pmcname(name);
+		fprintf(args.pa_graphfile, " %s", name);
+	}
+	fprintf(args.pa_graphfile, "\nsummary:");
+	for (i=0; i<pmcstat_npmcs ; i++)
+		fprintf(args.pa_graphfile, " %u",
+		    PMCPL_CT_SAMPLE(i, &rsamples));
+	fprintf(args.pa_graphfile, "\n\n");
+
+	/*
+	 * Fake root node
+	 */
+	fprintf(args.pa_graphfile, "ob=FreeBSD\n");
+	fprintf(args.pa_graphfile, "fn=ROOT\n");
+	fprintf(args.pa_graphfile, "* *");
+	for (i = 0; i<pmcstat_npmcs ; i++)
+		fprintf(args.pa_graphfile, " 0");
+	fprintf(args.pa_graphfile, "\n");
+	pmcpl_ct_node_printchild(pmcpl_ct_root);
+
+	for (n = 0; n < PMCSTAT_NHASH; n++)
+		LIST_FOREACH(pch, &pmcpl_ct_node_hash[n], pch_next) {
+			pmcpl_ct_node_printself(pch->pch_ctnode);
+			pmcpl_ct_node_printchild(pch->pch_ctnode);
+	}
+
+	pmcpl_ct_samples_free(&rsamples);
+}
+
+int
+pmcpl_ct_configure(char *opt)
+{
+
+	if (strncmp(opt, "skiplink=", 9) == 0) {
+		pmcstat_skiplink = atoi(opt+9);
+	} else
+		return (0);
+
+	return (1);
+}
+
+int
+pmcpl_ct_init(void)
+{
+	int i;
+
+	pmcpl_ct_prevfn = NULL;
+	pmcpl_ct_root = pmcpl_ct_node_allocate(NULL, 0);
+
+	for (i = 0; i < PMCSTAT_NHASH; i++)
+		LIST_INIT(&pmcpl_ct_node_hash[i]);
+
+	pmcpl_ct_samples_init(&pmcpl_ct_callid);
+
+	return (0);
+}
+
+void
+pmcpl_ct_shutdown(FILE *mf)
+{
+	int i;
+	struct pmcpl_ct_node_hash *pch, *pchtmp;
+
+	(void) mf;
+
+	if (args.pa_flags & FLAG_DO_CALLGRAPHS)
+		pmcpl_ct_print();
+
+	/*
+	 * Free memory.
+	 */
+
+	for (i = 0; i < PMCSTAT_NHASH; i++) {
+		LIST_FOREACH_SAFE(pch, &pmcpl_ct_node_hash[i], pch_next,
+		    pchtmp) {
+			pmcpl_ct_node_free(pch->pch_ctnode);
+			free(pch);
+		}
+	}
+
+	pmcpl_ct_node_free(pmcpl_ct_root);
+	pmcpl_ct_root = NULL;
+
+	pmcpl_ct_samples_free(&pmcpl_ct_callid);
+}
diff --git a/usr.sbin/pmcstat/pmcpl_calltree.h b/usr.sbin/pmcstat/pmcpl_calltree.h
new file mode 100644
index 0000000..58149fa
--- /dev/null
+++ b/usr.sbin/pmcstat/pmcpl_calltree.h
@@ -0,0 +1,42 @@
+/*-
+ * Copyright (c) 2009, Fabien Thomas
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: src/usr.sbin/pmcstat/pmcpl_calltree.h,v 1.1 2010/02/11 22:51:44 fabient Exp $
+ */
+
+#ifndef	_PMCSTAT_PL_CALLTREE_H_
+#define	_PMCSTAT_PL_CALLTREE_H_
+
+/* Function prototypes */
+int pmcpl_ct_init(void);
+void pmcpl_ct_shutdown(FILE *mf);
+void pmcpl_ct_process(
+    struct pmcstat_process *pp, struct pmcstat_pmcrecord *pmcr,
+    uint32_t nsamples, uintfptr_t *cc, int usermode, uint32_t cpu);
+int pmcpl_ct_topkeypress(int c, WINDOW *w);
+void pmcpl_ct_topdisplay(void);
+int pmcpl_ct_configure(char *opt);
+
+#endif	/* _PMCSTAT_PL_CALLTREE_H_ */
diff --git a/usr.sbin/pmcstat/pmcpl_gprof.c b/usr.sbin/pmcstat/pmcpl_gprof.c
new file mode 100644
index 0000000..68137ae
--- /dev/null
+++ b/usr.sbin/pmcstat/pmcpl_gprof.c
@@ -0,0 +1,535 @@
+/*-
+ * Copyright (c) 2005-2007, Joseph Koshy
+ * Copyright (c) 2007 The FreeBSD Foundation
+ * Copyright (c) 2009, Fabien Thomas
+ * All rights reserved.
+ *
+ * Portions of this software were developed by A. Joseph Koshy under
+ * sponsorship from the FreeBSD Foundation and Google, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * Transform a hwpmc(4) log into human readable form, and into
+ * gprof(1) compatible profiles.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: src/usr.sbin/pmcstat/pmcpl_gprof.c,v 1.2 2010/04/14 21:53:27 fabient Exp $");
+
+#include <sys/param.h>
+#include <sys/endian.h>
+#include <sys/gmon.h>
+#include <sys/imgact_aout.h>
+#include <sys/imgact_elf.h>
+#include <sys/mman.h>
+#include <sys/pmc.h>
+#include <sys/queue.h>
+#include <sys/socket.h>
+#include <sys/stat.h>
+#include <sys/wait.h>
+
+#include <netinet/in.h>
+
+#include <assert.h>
+#include <curses.h>
+#include <err.h>
+#include <errno.h>
+#include <fcntl.h>
+#include <gelf.h>
+#include <libgen.h>
+#include <limits.h>
+#include <netdb.h>
+#include <pmc.h>
+#include <pmclog.h>
+#include <sysexits.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+
+#include "pmcstat.h"
+#include "pmcstat_log.h"
+#include "pmcpl_callgraph.h"
+#include "pmcpl_gprof.h"
+
+/*
+ * struct pmcstat_gmonfile tracks a given 'gmon.out' file.  These
+ * files are mmap()'ed in as needed.
+ */
+
+struct pmcstat_gmonfile {
+	LIST_ENTRY(pmcstat_gmonfile)	pgf_next; /* list of entries */
+	int		pgf_overflow;	/* whether a count overflowed */
+	pmc_id_t	pgf_pmcid;	/* id of the associated pmc */
+	size_t		pgf_nbuckets;	/* #buckets in this gmon.out */
+	unsigned int	pgf_nsamples;	/* #samples in this gmon.out */
+	pmcstat_interned_string pgf_name;	/* pathname of gmon.out file */
+	size_t		pgf_ndatabytes;	/* number of bytes mapped */
+	void		*pgf_gmondata;	/* pointer to mmap'ed data */
+	FILE		*pgf_file;	/* used when writing gmon arcs */
+};
+
+/*
+ * Prototypes
+ */
+
+static void	pmcstat_gmon_create_file(struct pmcstat_gmonfile *_pgf,
+    struct pmcstat_image *_image);
+static pmcstat_interned_string pmcstat_gmon_create_name(const char *_sd,
+    struct pmcstat_image *_img, pmc_id_t _pmcid);
+static void	pmcstat_gmon_map_file(struct pmcstat_gmonfile *_pgf);
+static void	pmcstat_gmon_unmap_file(struct pmcstat_gmonfile *_pgf);
+
+static struct pmcstat_gmonfile *pmcstat_image_find_gmonfile(struct
+    pmcstat_image *_i, pmc_id_t _id);
+
+/*
+ * Create a gmon.out file and size it.
+ */
+
+static void
+pmcstat_gmon_create_file(struct pmcstat_gmonfile *pgf,
+    struct pmcstat_image *image)
+{
+	int fd;
+	size_t count;
+	struct gmonhdr gm;
+	const char *pathname;
+	char buffer[DEFAULT_BUFFER_SIZE];
+
+	pathname = pmcstat_string_unintern(pgf->pgf_name);
+	if ((fd = open(pathname, O_RDWR|O_NOFOLLOW|O_CREAT,
+		 S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH)) < 0)
+		err(EX_OSERR, "ERROR: Cannot open \"%s\"", pathname);
+
+	gm.lpc = image->pi_start;
+	gm.hpc = image->pi_end;
+	gm.ncnt = (pgf->pgf_nbuckets * sizeof(HISTCOUNTER)) +
+	    sizeof(struct gmonhdr);
+	gm.version = GMONVERSION;
+	gm.profrate = 0;		/* use ticks */
+	gm.histcounter_type = 0;	/* compatibility with moncontrol() */
+	gm.spare[0] = gm.spare[1] = 0;
+
+	/* Write out the gmon header */
+	if (write(fd, &gm, sizeof(gm)) < 0)
+		goto error;
+
+	/* Zero fill the samples[] array */
+	(void) memset(buffer, 0, sizeof(buffer));
+
+	count = pgf->pgf_ndatabytes - sizeof(struct gmonhdr);
+	while (count > sizeof(buffer)) {
+		if (write(fd, &buffer, sizeof(buffer)) < 0)
+			goto error;
+		count -= sizeof(buffer);
+	}
+
+	if (write(fd, &buffer, count) < 0)
+		goto error;
+
+	(void) close(fd);
+
+	return;
+
+ error:
+	err(EX_OSERR, "ERROR: Cannot write \"%s\"", pathname);
+}
+
+/*
+ * Determine the full pathname of a gmon.out file for a given
+ * (image,pmcid) combination.  Return the interned string.
+ */
+
+pmcstat_interned_string
+pmcstat_gmon_create_name(const char *samplesdir, struct pmcstat_image *image,
+    pmc_id_t pmcid)
+{
+	const char *pmcname;
+	char fullpath[PATH_MAX];
+
+	pmcname = pmcstat_pmcid_to_name(pmcid);
+	if (!pmcname)
+		err(EX_SOFTWARE, "ERROR: cannot find pmcid");
+
+	(void) snprintf(fullpath, sizeof(fullpath),
+	    "%s/%s/%s", samplesdir, pmcname,
+	    pmcstat_string_unintern(image->pi_samplename));
+
+	return (pmcstat_string_intern(fullpath));
+}
+
+
+/*
+ * Mmap in a gmon.out file for processing.
+ */
+
+static void
+pmcstat_gmon_map_file(struct pmcstat_gmonfile *pgf)
+{
+	int fd;
+	const char *pathname;
+
+	pathname = pmcstat_string_unintern(pgf->pgf_name);
+
+	/* the gmon.out file must already exist */
+	if ((fd = open(pathname, O_RDWR | O_NOFOLLOW, 0)) < 0)
+		err(EX_OSERR, "ERROR: cannot open \"%s\"", pathname);
+
+	pgf->pgf_gmondata = mmap(NULL, pgf->pgf_ndatabytes,
+	    PROT_READ|PROT_WRITE, MAP_NOSYNC|MAP_SHARED, fd, 0);
+
+	if (pgf->pgf_gmondata == MAP_FAILED)
+		err(EX_OSERR, "ERROR: cannot map \"%s\"", pathname);
+
+	(void) close(fd);
+}
+
+/*
+ * Unmap a gmon.out file after sync'ing its data to disk.
+ */
+
+static void
+pmcstat_gmon_unmap_file(struct pmcstat_gmonfile *pgf)
+{
+	(void) msync(pgf->pgf_gmondata, pgf->pgf_ndatabytes,
+	    MS_SYNC);
+	(void) munmap(pgf->pgf_gmondata, pgf->pgf_ndatabytes);
+	pgf->pgf_gmondata = NULL;
+}
+
+static void
+pmcstat_gmon_append_arc(struct pmcstat_image *image, pmc_id_t pmcid,
+    uintptr_t rawfrom, uintptr_t rawto, uint32_t count)
+{
+	struct rawarc arc;	/* from <sys/gmon.h> */
+	const char *pathname;
+	struct pmcstat_gmonfile *pgf;
+
+	if ((pgf = pmcstat_image_find_gmonfile(image, pmcid)) == NULL)
+		return;
+
+	if (pgf->pgf_file == NULL) {
+		pathname = pmcstat_string_unintern(pgf->pgf_name);
+		if ((pgf->pgf_file = fopen(pathname, "a")) == NULL)
+			return;
+	}
+
+	arc.raw_frompc = rawfrom + image->pi_vaddr;
+	arc.raw_selfpc = rawto + image->pi_vaddr;
+	arc.raw_count = count;
+
+	(void) fwrite(&arc, sizeof(arc), 1, pgf->pgf_file);
+
+}
+
+static struct pmcstat_gmonfile *
+pmcstat_image_find_gmonfile(struct pmcstat_image *image, pmc_id_t pmcid)
+{
+	struct pmcstat_gmonfile *pgf;
+	LIST_FOREACH(pgf, &image->pi_gmlist, pgf_next)
+	    if (pgf->pgf_pmcid == pmcid)
+		    return (pgf);
+	return (NULL);
+}
+
+static void
+pmcstat_cgnode_do_gmon_arcs(struct pmcstat_cgnode *cg, pmc_id_t pmcid)
+{
+	struct pmcstat_cgnode *cgc;
+
+	/*
+	 * Look for child nodes that belong to the same image.
+	 */
+
+	LIST_FOREACH(cgc, &cg->pcg_children, pcg_sibling) {
+		if (cgc->pcg_image == cg->pcg_image)
+			pmcstat_gmon_append_arc(cg->pcg_image, pmcid,
+			    cgc->pcg_func, cg->pcg_func, cgc->pcg_count);
+		if (cgc->pcg_nchildren > 0)
+			pmcstat_cgnode_do_gmon_arcs(cgc, pmcid);
+	}
+}
+
+static void
+pmcstat_callgraph_do_gmon_arcs_for_pmcid(pmc_id_t pmcid)
+{
+	int n;
+	struct pmcstat_cgnode_hash *pch;
+
+	for (n = 0; n < PMCSTAT_NHASH; n++)
+		LIST_FOREACH(pch, &pmcstat_cgnode_hash[n], pch_next)
+			if (pch->pch_pmcid == pmcid &&
+			    pch->pch_cgnode->pcg_nchildren > 1)
+				pmcstat_cgnode_do_gmon_arcs(pch->pch_cgnode,
+				    pmcid);
+}
+
+
+static void
+pmcstat_callgraph_do_gmon_arcs(void)
+{
+	struct pmcstat_pmcrecord *pmcr;
+
+	LIST_FOREACH(pmcr, &pmcstat_pmcs, pr_next)
+		pmcstat_callgraph_do_gmon_arcs_for_pmcid(pmcr->pr_pmcid);
+}
+
+void
+pmcpl_gmon_initimage(struct pmcstat_image *pi)
+{
+	int count, nlen;
+	char *sn;
+	char name[NAME_MAX];
+
+	/*
+	 * Look for a suitable name for the sample files associated
+	 * with this image: if `basename(path)`+".gmon" is available,
+	 * we use that, otherwise we try iterating through
+	 * `basename(path)`+ "~" + NNN + ".gmon" till we get a free
+	 * entry.
+	 */
+	if ((sn = basename(pmcstat_string_unintern(pi->pi_execpath))) == NULL)
+		err(EX_OSERR, "ERROR: Cannot process \"%s\"",
+		    pmcstat_string_unintern(pi->pi_execpath));
+
+	nlen = strlen(sn);
+	nlen = min(nlen, (int) (sizeof(name) - sizeof(".gmon")));
+
+	snprintf(name, sizeof(name), "%.*s.gmon", nlen, sn);
+
+	/* try use the unabridged name first */
+	if (pmcstat_string_lookup(name) == NULL)
+		pi->pi_samplename = pmcstat_string_intern(name);
+	else {
+		/*
+		 * Otherwise use a prefix from the original name and
+		 * upto 3 digits.
+		 */
+		nlen = strlen(sn);
+		nlen = min(nlen, (int) (sizeof(name)-sizeof("~NNN.gmon")));
+		count = 0;
+		do {
+			if (++count > 999)
+				errx(EX_CANTCREAT, "ERROR: cannot create a "
+				    "gmon file for \"%s\"", name);
+			snprintf(name, sizeof(name), "%.*s~%3.3d.gmon",
+			    nlen, sn, count);
+			if (pmcstat_string_lookup(name) == NULL) {
+				pi->pi_samplename =
+				    pmcstat_string_intern(name);
+				count = 0;
+			}
+		} while (count > 0);
+	}
+
+	LIST_INIT(&pi->pi_gmlist);
+}
+
+void
+pmcpl_gmon_shutdownimage(struct pmcstat_image *pi)
+{
+	struct pmcstat_gmonfile *pgf, *pgftmp;
+
+	LIST_FOREACH_SAFE(pgf, &pi->pi_gmlist, pgf_next, pgftmp) {
+		if (pgf->pgf_file)
+			(void) fclose(pgf->pgf_file);
+		LIST_REMOVE(pgf, pgf_next);
+		free(pgf);
+	}
+}
+
+void
+pmcpl_gmon_newpmc(pmcstat_interned_string ps, struct pmcstat_pmcrecord *pr)
+{
+	struct stat st;
+	char fullpath[PATH_MAX];
+
+	(void) pr;
+
+	/*
+	 * Create the appropriate directory to hold gmon.out files.
+	 */
+
+	(void) snprintf(fullpath, sizeof(fullpath), "%s/%s", args.pa_samplesdir,
+	    pmcstat_string_unintern(ps));
+
+	/* If the path name exists, it should be a directory */
+	if (stat(fullpath, &st) == 0 && S_ISDIR(st.st_mode))
+		return;
+
+	if (mkdir(fullpath, S_IRWXU|S_IRGRP|S_IXGRP|S_IROTH|S_IXOTH) < 0)
+		err(EX_OSERR, "ERROR: Cannot create directory \"%s\"",
+		    fullpath);
+}
+
+/*
+ * Increment the bucket in the gmon.out file corresponding to 'pmcid'
+ * and 'pc'.
+ */
+
+void
+pmcpl_gmon_process(struct pmcstat_process *pp, struct pmcstat_pmcrecord *pmcr,
+    uint32_t nsamples, uintfptr_t *cc, int usermode, uint32_t cpu)
+{
+	struct pmcstat_pcmap *map;
+	struct pmcstat_image *image;
+	struct pmcstat_gmonfile *pgf;
+	uintfptr_t bucket;
+	HISTCOUNTER *hc;
+	pmc_id_t pmcid;
+
+	(void) nsamples; (void) usermode; (void) cpu;
+
+	map = pmcstat_process_find_map(usermode ? pp : pmcstat_kernproc, cc[0]);
+	if (map == NULL) {
+		/* Unknown offset. */
+		pmcstat_stats.ps_samples_unknown_offset++;
+		return;
+	}
+
+	assert(cc[0] >= map->ppm_lowpc && cc[0] < map->ppm_highpc);
+
+	image = map->ppm_image;
+	pmcid = pmcr->pr_pmcid;
+
+	/*
+	 * If this is the first time we are seeing a sample for
+	 * this executable image, try determine its parameters.
+	 */
+	if (image->pi_type == PMCSTAT_IMAGE_UNKNOWN)
+		pmcstat_image_determine_type(image);
+
+	assert(image->pi_type != PMCSTAT_IMAGE_UNKNOWN);
+
+	/* Ignore samples in images that we know nothing about. */
+	if (image->pi_type == PMCSTAT_IMAGE_INDETERMINABLE) {
+		pmcstat_stats.ps_samples_indeterminable++;
+		return;
+	}
+
+	/*
+	 * Find the gmon file corresponding to 'pmcid', creating it if
+	 * needed.
+	 */
+	pgf = pmcstat_image_find_gmonfile(image, pmcid);
+	if (pgf == NULL) {
+		if ((pgf = calloc(1, sizeof(*pgf))) == NULL)
+			err(EX_OSERR, "ERROR:");
+
+		pgf->pgf_gmondata = NULL;	/* mark as unmapped */
+		pgf->pgf_name = pmcstat_gmon_create_name(args.pa_samplesdir,
+		    image, pmcid);
+		pgf->pgf_pmcid = pmcid;
+		assert(image->pi_end > image->pi_start);
+		pgf->pgf_nbuckets = (image->pi_end - image->pi_start) /
+		    FUNCTION_ALIGNMENT;	/* see <machine/profile.h> */
+		pgf->pgf_ndatabytes = sizeof(struct gmonhdr) +
+		    pgf->pgf_nbuckets * sizeof(HISTCOUNTER);
+		pgf->pgf_nsamples = 0;
+		pgf->pgf_file = NULL;
+
+		pmcstat_gmon_create_file(pgf, image);
+
+		LIST_INSERT_HEAD(&image->pi_gmlist, pgf, pgf_next);
+	}
+
+	/*
+	 * Map the gmon file in if needed.  It may have been mapped
+	 * out under memory pressure.
+	 */
+	if (pgf->pgf_gmondata == NULL)
+		pmcstat_gmon_map_file(pgf);
+
+	assert(pgf->pgf_gmondata != NULL);
+
+	/*
+	 *
+	 */
+
+	bucket = (cc[0] - map->ppm_lowpc) / FUNCTION_ALIGNMENT;
+
+	assert(bucket < pgf->pgf_nbuckets);
+
+	hc = (HISTCOUNTER *) ((uintptr_t) pgf->pgf_gmondata +
+	    sizeof(struct gmonhdr));
+
+	/* saturating add */
+	if (hc[bucket] < 0xFFFFU)  /* XXX tie this to sizeof(HISTCOUNTER) */
+		hc[bucket]++;
+	else /* mark that an overflow occurred */
+		pgf->pgf_overflow = 1;
+
+	pgf->pgf_nsamples++;
+}
+
+/*
+ * Shutdown module.
+ */
+
+void
+pmcpl_gmon_shutdown(FILE *mf)
+{
+	int i;
+	struct pmcstat_gmonfile *pgf;
+	struct pmcstat_image *pi;
+
+	/*
+	 * Sync back all gprof flat profile data.
+	 */
+	for (i = 0; i < PMCSTAT_NHASH; i++) {
+		LIST_FOREACH(pi, &pmcstat_image_hash[i], pi_next) {
+			if (mf)
+				(void) fprintf(mf, " \"%s\" => \"%s\"",
+				    pmcstat_string_unintern(pi->pi_execpath),
+				    pmcstat_string_unintern(
+				    pi->pi_samplename));
+
+			/* flush gmon.out data to disk */
+			LIST_FOREACH(pgf, &pi->pi_gmlist, pgf_next) {
+				pmcstat_gmon_unmap_file(pgf);
+				if (mf)
+					(void) fprintf(mf, " %s/%d",
+					    pmcstat_pmcid_to_name(
+					    pgf->pgf_pmcid),
+					    pgf->pgf_nsamples);
+				if (pgf->pgf_overflow && args.pa_verbosity >= 1)
+					warnx("WARNING: profile \"%s\" "
+					    "overflowed.",
+					    pmcstat_string_unintern(
+					        pgf->pgf_name));
+			}
+
+			if (mf)
+				(void) fprintf(mf, "\n");
+		}
+	}
+
+	/*
+	 * Compute arcs and add these to the gprof files.
+	 */
+	if (args.pa_flags & FLAG_DO_GPROF && args.pa_graphdepth > 1)
+		pmcstat_callgraph_do_gmon_arcs();
+}
diff --git a/usr.sbin/pmcstat/pmcpl_gprof.h b/usr.sbin/pmcstat/pmcpl_gprof.h
new file mode 100644
index 0000000..a552a53
--- /dev/null
+++ b/usr.sbin/pmcstat/pmcpl_gprof.h
@@ -0,0 +1,47 @@
+/*-
+ * Copyright (c) 2005-2007, Joseph Koshy
+ * Copyright (c) 2007 The FreeBSD Foundation
+ * Copyright (c) 2009, Fabien Thomas
+ * All rights reserved.
+ *
+ * Portions of this software were developed by A. Joseph Koshy under
+ * sponsorship from the FreeBSD Foundation and Google, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: src/usr.sbin/pmcstat/pmcpl_gprof.h,v 1.1 2010/02/11 22:51:44 fabient Exp $
+ */
+
+#ifndef	_PMCSTAT_PL_GPROF_H_
+#define	_PMCSTAT_PL_GPROF_H_
+
+/* Function prototypes */
+void pmcpl_gmon_shutdown(FILE *mf);
+void pmcpl_gmon_process(
+    struct pmcstat_process *pp, struct pmcstat_pmcrecord *pmcr,
+    uint32_t nsamples, uintfptr_t *cc, int usermode, uint32_t cpu);
+void pmcpl_gmon_initimage(struct pmcstat_image *pi);
+void pmcpl_gmon_shutdownimage(struct pmcstat_image *pi);
+void pmcpl_gmon_newpmc(pmcstat_interned_string ps,
+	struct pmcstat_pmcrecord *pr);
+
+#endif	/* _PMCSTAT_PL_GPROF_H_ */
diff --git a/usr.sbin/pmcstat/pmcstat.8 b/usr.sbin/pmcstat/pmcstat.8
new file mode 100644
index 0000000..5e323a6
--- /dev/null
+++ b/usr.sbin/pmcstat/pmcstat.8
@@ -0,0 +1,456 @@
+.\" Copyright (c) 2003-2008 Joseph Koshy
+.\" Copyright (c) 2007 The FreeBSD Foundation
+.\" All rights reserved.
+.\"
+.\" Redistribution and use in source and binary forms, with or without
+.\" modification, are permitted provided that the following conditions
+.\" are met:
+.\" 1. Redistributions of source code must retain the above copyright
+.\"    notice, this list of conditions and the following disclaimer.
+.\" 2. Redistributions in binary form must reproduce the above copyright
+.\"    notice, this list of conditions and the following disclaimer in the
+.\"    documentation and/or other materials provided with the distribution.
+.\"
+.\" This software is provided by Joseph Koshy ``as is'' and
+.\" any express or implied warranties, including, but not limited to, the
+.\" implied warranties of merchantability and fitness for a particular purpose
+.\" are disclaimed.  in no event shall Joseph Koshy be liable
+.\" for any direct, indirect, incidental, special, exemplary, or consequential
+.\" damages (including, but not limited to, procurement of substitute goods
+.\" or services; loss of use, data, or profits; or business interruption)
+.\" however caused and on any theory of liability, whether in contract, strict
+.\" liability, or tort (including negligence or otherwise) arising in any way
+.\" out of the use of this software, even if advised of the possibility of
+.\" such damage.
+.\"
+.\" $FreeBSD: src/usr.sbin/pmcstat/pmcstat.8,v 1.20 2010/04/14 19:08:06 uqs Exp $
+.\"
+.Dd September 19, 2008
+.Dt PMCSTAT 8
+.Os
+.Sh NAME
+.Nm pmcstat
+.Nd "performance measurement with performance monitoring hardware"
+.Sh SYNOPSIS
+.Nm
+.Op Fl C
+.Op Fl D Ar pathname
+.Op Fl E
+.Op Fl F Ar pathname
+.Op Fl G Ar pathname
+.Op Fl M Ar mapfilename
+.Op Fl N
+.Op Fl O Ar logfilename
+.Op Fl P Ar event-spec
+.Op Fl R Ar logfilename
+.Op Fl S Ar event-spec
+.Op Fl T
+.Op Fl W
+.Op Fl c Ar cpu-spec
+.Op Fl d
+.Op Fl f Ar pluginopt
+.Op Fl g
+.Op Fl k Ar kerneldir
+.Op Fl m Ar pathname
+.Op Fl n Ar rate
+.Op Fl o Ar outputfile
+.Op Fl p Ar event-spec
+.Op Fl q
+.Op Fl r Ar fsroot
+.Op Fl s Ar event-spec
+.Op Fl t Ar process-spec
+.Op Fl v
+.Op Fl w Ar secs
+.Op Fl z Ar graphdepth
+.Op Ar command Op Ar args
+.Sh DESCRIPTION
+The
+.Nm
+utility measures system performance using the facilities provided by
+.Xr hwpmc 4 .
+.Pp
+The
+.Nm
+utility can measure both hardware events seen by the system as a
+whole, and those seen when a specified set of processes are executing
+on the system's CPUs.
+If a specific set of processes is being targeted (for example,
+if the
+.Fl t Ar process-spec
+option is specified, or if a command line is specified using
+.Ar command ) ,
+then measurement occurs till
+.Ar command
+exits, or till all target processes specified by the
+.Fl t Ar process-spec
+options exit, or till the
+.Nm
+utility is interrupted by the user.
+If a specific set of processes is not targeted for measurement, then
+.Nm
+will perform system-wide measurements till interrupted by the
+user.
+.Pp
+A given invocation of
+.Nm
+can mix allocations of system-mode and process-mode PMCs, of both
+counting and sampling flavors.
+The values of all counting PMCs are printed in human readable form
+at regular intervals by
+.Nm .
+The output of sampling PMCs may be configured to go to a log file for
+subsequent offline analysis, or, at the expense of greater
+overhead, may be configured to be printed in text form on the fly.
+.Pp
+Hardware events to measure are specified to
+.Nm
+using event specifier strings
+.Ar event-spec .
+The syntax of these event specifiers is machine dependent and is
+documented in
+.Xr pmc 3 .
+.Pp
+A process-mode PMC may be configured to be inheritable by the target
+process' current and future children.
+.Sh OPTIONS
+The following options are available:
+.Bl -tag -width indent
+.It Fl C
+Toggle between showing cumulative or incremental counts for
+subsequent counting mode PMCs specified on the command line.
+The default is to show incremental counts.
+.It Fl D Ar pathname
+Create files with per-program samples in the directory named
+by
+.Ar pathname .
+The default is to create these files in the current directory.
+.It Fl E
+Toggle showing per-process counts at the time a tracked process
+exits for subsequent process-mode PMCs specified on the command line.
+This option is useful for mapping the performance characteristics of a
+complex pipeline of processes when used in conjunction with the
+.Fl d
+option.
+The default is to not to enable per-process tracking.
+.It Fl F Ar pathname
+Print calltree (Kcachegrind) information to file
+.Ar pathname .
+If argument
+.Ar pathname
+is a
+.Dq Li -
+this information is sent to the output file specified by the
+.Fl o
+option.
+.It Fl G Ar pathname
+Print callchain information to file
+.Ar pathname .
+If argument
+.Ar pathname
+is a
+.Dq Li -
+this information is sent to the output file specified by the
+.Fl o
+option.
+.It Fl M Ar mapfilename
+Write the mapping between executable objects encountered in the event
+log and the abbreviated pathnames used for
+.Xr gprof 1
+profiles to file
+.Ar mapfilename .
+If this option is not specified, mapping information is not written.
+Argument
+.Ar mapfilename
+may be a
+.Dq Li -
+in which case this mapping information is sent to the output
+file configured by the
+.Fl o
+option.
+.It Fl N
+Toggle capturing callchain information for subsequent sampling PMCs.
+The default is for sampling PMCs to capture callchain information.
+.It Fl O Ar logfilename
+Send logging output to file
+.Ar logfilename .
+If
+.Ar logfilename
+is of the form
+.Ar hostname Ns : Ns Ar port ,
+where
+.Ar hostname
+does not start with a
+.Ql \&.
+or a
+.Ql / ,
+then
+.Nm
+will open a network socket to host
+.Ar hostname
+on port
+.Ar port .
+.Pp
+If the
+.Fl O
+option is not specified and one of the logging options is requested,
+then
+.Nm
+will print a textual form of the logged events to the configured
+output file.
+.It Fl P Ar event-spec
+Allocate a process mode sampling PMC measuring hardware events
+specified in
+.Ar event-spec .
+.It Fl R Ar logfilename
+Perform offline analysis using sampling data in file
+.Ar logfilename .
+.It Fl S Ar event-spec
+Allocate a system mode sampling PMC measuring hardware events
+specified in
+.Ar event-spec .
+.It Fl T
+Use a top like mode for sampling PMCs. The following hotkeys
+can be used: 'c+a' switch to accumulative mode, 'c+d' switch
+to delta mode, 'm' merge PMCs, 'n' change view, 'p' show next
+PMC, ' ' pause, 'q' quit. calltree only: 'f' cost under threshold
+is seen as a dot.
+.It Fl W
+Toggle logging the incremental counts seen by the threads of a
+tracked process each time they are scheduled on a CPU.
+This is an experimental feature intended to help analyse the
+dynamic behaviour of processes in the system.
+It may incur substantial overhead if enabled.
+The default is for this feature to be disabled.
+.It Fl c Ar cpu-spec
+Set the cpus for subsequent system mode PMCs specified on the
+command line to
+.Ar cpu-spec .
+Argument
+.Ar cpu-spec
+is a comma separated list of CPU numbers, or the literal
+.Sq *
+denoting all unhalted CPUs.
+The default is to allocate system mode PMCs on all unhalted
+CPUs.
+.It Fl d
+Toggle between process mode PMCs measuring events for the target
+process' current and future children or only measuring events for
+the target process.
+The default is to measure events for the target process alone.
+.It Fl f Ar pluginopt
+Pass option string to the active plugin.
+.br
+threshold=<float> do not display cost under specified value (Top).
+.br
+skiplink=0|1 replace node with cost under threshold by a dot (Top).
+.It Fl g
+Produce profiles in a format compatible with
+.Xr gprof 1 .
+A separate profile file is generated for each executable object
+encountered.
+Profile files are placed in sub-directories named by their PMC
+event name.
+.It Fl k Ar kerneldir
+Set the pathname of the kernel directory to argument
+.Ar kerneldir .
+This directory specifies where
+.Nm
+should look for the kernel and its modules.
+The default is
+.Pa /boot/kernel .
+.It Fl m Ar pathname
+Print the sampled PCs with the name, the start and ending addresses
+of the function within they live.
+The
+.Ar pathname
+argument is mandatory and indicates where informations will be stored.
+If argument
+.Ar pathname
+is a
+.Dq Li -
+this information is sent to the output file specified by the
+.Fl o
+option.
+.It Fl n Ar rate
+Set the default sampling rate for subsequent sampling mode
+PMCs specified on the command line.
+The default is to configure PMCs to sample the CPU's instruction
+pointer every 65536 events.
+.It Fl o Ar outputfile
+Send counter readings and textual representations of logged data
+to file
+.Ar outputfile .
+The default is to send output to
+.Pa stderr
+when collecting live data and to
+.Pa stdout
+when processing a pre-existing logfile.
+.It Fl p Ar event-spec
+Allocate a process mode counting PMC measuring hardware events
+specified in
+.Ar event-spec .
+.It Fl q
+Decrease verbosity.
+.It Fl r Ar fsroot
+Set the top of the filesystem hierarchy under which executables
+are located to argument
+.Ar fsroot .
+The default is
+.Pa / .
+.It Fl s Ar event-spec
+Allocate a system mode counting PMC measuring hardware events
+specified in
+.Ar event-spec .
+.It Fl t Ar process-spec
+Attach process mode PMCs to the processes named by argument
+.Ar process-spec .
+Argument
+.Ar process-spec
+may be a non-negative integer denoting a specific process id, or a
+regular expression for selecting processes based on their command names.
+.It Fl v
+Increase verbosity.
+.It Fl w Ar secs
+Print the values of all counting mode PMCs or sampling mode PMCs
+for top mode every
+.Ar secs
+seconds.
+The argument
+.Ar secs
+may be a fractional value.
+The default interval is 5 seconds.
+.It Fl z Ar graphdepth
+When printing system-wide callgraphs, limit callgraphs to the depth
+specified by argument
+.Ar graphdepth .
+.El
+.Pp
+If
+.Ar command
+is specified, it is executed using
+.Xr execvp 3 .
+.Sh EXAMPLES
+To perform system-wide statistical sampling on an AMD Athlon CPU with
+samples taken every 32768 instruction retirals and data being sampled
+to file
+.Pa sample.stat ,
+use:
+.Dl "pmcstat -O sample.stat -n 32768 -S k7-retired-instructions"
+.Pp
+To execute
+.Nm firefox
+and measure the number of data cache misses suffered
+by it and its children every 12 seconds on an AMD Athlon, use:
+.Dl "pmcstat -d -w 12 -p k7-dc-misses firefox"
+.Pp
+To measure instructions retired for all processes named
+.Dq emacs
+use:
+.Dl "pmcstat -t '^emacs$' -p instructions"
+.Pp
+To measure instructions retired for processes named
+.Dq emacs
+for a period of 10 seconds use:
+.Dl "pmcstat -t '^emacs$' -p instructions sleep 10"
+.Pp
+To count instruction tlb-misses on CPUs 0 and 2 on a Intel
+Pentium Pro/Pentium III SMP system use:
+.Dl "pmcstat -c 0,2 -s p6-itlb-miss"
+.Pp
+To collect profiling information for a specific process with pid 1234
+based on instruction cache misses seen by it use:
+.Dl "pmcstat -P ic-misses -t 1234 -O /tmp/sample.out"
+.Pp
+To perform system-wide sampling on all configured processors
+based on processor instructions retired use:
+.Dl "pmcstat -S instructions -O /tmp/sample.out"
+If callgraph capture is not desired use:
+.Dl "pmcstat -N -S instructions -O /tmp/sample.out"
+.Pp
+To send the generated event log to a remote machine use:
+.Dl "pmcstat -S instructions -O remotehost:port"
+On the remote machine, the sample log can be collected using
+.Xr nc 1 :
+.Dl "nc -l remotehost port > /tmp/sample.out"
+.Pp
+To generate
+.Xr gprof 1
+compatible profiles from a sample file use:
+.Dl "pmcstat -R /tmp/sample.out -g"
+.Pp
+To print a system-wide profile with callgraphs to file
+.Pa "foo.graph"
+use:
+.Dl "pmcstat -R /tmp/sample.out -G foo.graph"
+.Sh DIAGNOSTICS
+If option
+.Fl v
+is specified,
+.Nm
+may issue the following diagnostic messages:
+.Bl -diag -width indent
+.It "#callchain/dubious-frames"
+The number of callchain records that had an
+.Dq impossible
+value for a return address.
+.It "#exec handling errors"
+The number of
+.Xr exec 2
+events in the log file that named executables that could not be
+analyzed.
+.It "#exec/elf"
+The number of
+.Xr exec 2
+events that named ELF executables.
+.It "#exec/unknown"
+The number of
+.Xr exec 2
+events that named executables with unrecognized formats.
+.It "#samples/total"
+The total number of samples in the log file.
+.It "#samples/unclaimed"
+The number of samples that could not be correlated to a known
+executable object (i.e., to an executable, shared library, the
+kernel or the runtime loader).
+.It "#samples/unknown-object"
+The number of samples that were associated with an executable
+with an unrecognized object format.
+.El
+.Pp
+.Ex -std
+.Sh COMPATIBILITY
+Due to the limitations of the
+.Pa gmon.out
+file format,
+.Xr gprof 1
+compatible profiles generated by the
+.Fl g
+option do not contain information about calls that cross executable
+boundaries.
+The generated
+.Pa gmon.out
+files are also only meaningful for native executables.
+.Sh SEE ALSO
+.Xr gprof 1 ,
+.Xr nc 1 ,
+.Xr execvp 3 ,
+.Xr pmc 3 ,
+.Xr pmclog 3 ,
+.Xr hwpmc 4 ,
+.Xr pmccontrol 8 ,
+.Xr sysctl 8
+.Sh HISTORY
+The
+.Nm
+utility first appeared in
+.Fx 6.0 .
+It is
+.Ud
+.Sh AUTHORS
+.An Joseph Koshy Aq jkoshy@FreeBSD.org
+.Sh BUGS
+The
+.Nm
+utility cannot yet analyse
+.Xr hwpmc 4
+logs generated by non-native architectures.
diff --git a/usr.sbin/pmcstat/pmcstat.c b/usr.sbin/pmcstat/pmcstat.c
new file mode 100644
index 0000000..e970b41
--- /dev/null
+++ b/usr.sbin/pmcstat/pmcstat.c
@@ -0,0 +1,1449 @@
+/*-
+ * Copyright (c) 2003-2008, Joseph Koshy
+ * Copyright (c) 2007 The FreeBSD Foundation
+ * All rights reserved.
+ *
+ * Portions of this software were developed by A. Joseph Koshy under
+ * sponsorship from the FreeBSD Foundation and Google, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: src/usr.sbin/pmcstat/pmcstat.c,v 1.30 2010/08/03 13:46:25 fabient Exp $");
+
+#include <sys/types.h>
+#include <sys/event.h>
+#include <sys/param.h>
+#include <sys/queue.h>
+#include <sys/socket.h>
+#include <sys/stat.h>
+#include <sys/sysctl.h>
+#include <sys/time.h>
+#include <sys/ttycom.h>
+#include <sys/user.h>
+#include <sys/wait.h>
+
+#include <assert.h>
+#include <curses.h>
+#include <err.h>
+#include <errno.h>
+#include <fcntl.h>
+#include <kvm.h>
+#include <libgen.h>
+#include <limits.h>
+#include <math.h>
+#include <pmc.h>
+#include <pmclog.h>
+#include <regex.h>
+#include <signal.h>
+#include <stdarg.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sysexits.h>
+#include <unistd.h>
+
+#include "pmcstat.h"
+
+/*
+ * A given invocation of pmcstat(8) can manage multiple PMCs of both
+ * the system-wide and per-process variety.  Each of these could be in
+ * 'counting mode' or in 'sampling mode'.
+ *
+ * For 'counting mode' PMCs, pmcstat(8) will periodically issue a
+ * pmc_read() at the configured time interval and print out the value
+ * of the requested PMCs.
+ *
+ * For 'sampling mode' PMCs it can log to a file for offline analysis,
+ * or can analyse sampling data "on the fly", either by converting
+ * samples to printed textual form or by creating gprof(1) compatible
+ * profiles, one per program executed.  When creating gprof(1)
+ * profiles it can optionally merge entries from multiple processes
+ * for a given executable into a single profile file.
+ *
+ * pmcstat(8) can also execute a command line and attach PMCs to the
+ * resulting child process.  The protocol used is as follows:
+ *
+ * - parent creates a socketpair for two way communication and
+ *   fork()s.
+ * - subsequently:
+ *
+ *   /Parent/				/Child/
+ *
+ *   - Wait for childs token.
+ *					- Sends token.
+ *					- Awaits signal to start.
+ *  - Attaches PMCs to the child's pid
+ *    and starts them. Sets up
+ *    monitoring for the child.
+ *  - Signals child to start.
+ *					- Recieves signal, attempts exec().
+ *
+ * After this point normal processing can happen.
+ */
+
+/* Globals */
+
+int	pmcstat_interrupt = 0;
+int	pmcstat_displayheight = DEFAULT_DISPLAY_HEIGHT;
+int	pmcstat_displaywidth  = DEFAULT_DISPLAY_WIDTH;
+int	pmcstat_sockpair[NSOCKPAIRFD];
+int	pmcstat_kq;
+kvm_t	*pmcstat_kvm;
+struct kinfo_proc *pmcstat_plist;
+struct pmcstat_args args;
+
+void
+pmcstat_attach_pmcs(void)
+{
+	struct pmcstat_ev *ev;
+	struct pmcstat_target *pt;
+	int count;
+
+	/* Attach all process PMCs to target processes. */
+	count = 0;
+	STAILQ_FOREACH(ev, &args.pa_events, ev_next) {
+		if (PMC_IS_SYSTEM_MODE(ev->ev_mode))
+			continue;
+		SLIST_FOREACH(pt, &args.pa_targets, pt_next)
+			if (pmc_attach(ev->ev_pmcid, pt->pt_pid) == 0)
+				count++;
+			else if (errno != ESRCH)
+				err(EX_OSERR, "ERROR: cannot attach pmc "
+				    "\"%s\" to process %d", ev->ev_name,
+				    (int) pt->pt_pid);
+	}
+
+	if (count == 0)
+		errx(EX_DATAERR, "ERROR: No processes were attached to.");
+}
+
+
+void
+pmcstat_cleanup(void)
+{
+	struct pmcstat_ev *ev, *tmp;
+
+	/* release allocated PMCs. */
+	STAILQ_FOREACH_SAFE(ev, &args.pa_events, ev_next, tmp)
+	    if (ev->ev_pmcid != PMC_ID_INVALID) {
+		if (pmc_stop(ev->ev_pmcid) < 0)
+			err(EX_OSERR, "ERROR: cannot stop pmc 0x%x "
+			    "\"%s\"", ev->ev_pmcid, ev->ev_name);
+		if (pmc_release(ev->ev_pmcid) < 0)
+			err(EX_OSERR, "ERROR: cannot release pmc "
+			    "0x%x \"%s\"", ev->ev_pmcid, ev->ev_name);
+		free(ev->ev_name);
+		free(ev->ev_spec);
+		STAILQ_REMOVE(&args.pa_events, ev, pmcstat_ev, ev_next);
+		free(ev);
+	    }
+
+	/* de-configure the log file if present. */
+	if (args.pa_flags & (FLAG_HAS_PIPE | FLAG_HAS_OUTPUT_LOGFILE))
+		(void) pmc_configure_logfile(-1);
+
+	if (args.pa_logparser) {
+		pmclog_close(args.pa_logparser);
+		args.pa_logparser = NULL;
+	}
+
+	pmcstat_shutdown_logging();
+}
+
+void
+pmcstat_clone_event_descriptor(struct pmcstat_ev *ev,
+    uint32_t cpumask)
+{
+	int cpu;
+	struct pmcstat_ev *ev_clone;
+
+	while ((cpu = ffs(cpumask)) > 0) {
+		cpu--;
+
+		if ((ev_clone = malloc(sizeof(*ev_clone))) == NULL)
+			errx(EX_SOFTWARE, "ERROR: Out of memory");
+		(void) memset(ev_clone, 0, sizeof(*ev_clone));
+
+		ev_clone->ev_count = ev->ev_count;
+		ev_clone->ev_cpu   = cpu;
+		ev_clone->ev_cumulative = ev->ev_cumulative;
+		ev_clone->ev_flags = ev->ev_flags;
+		ev_clone->ev_mode  = ev->ev_mode;
+		ev_clone->ev_name  = strdup(ev->ev_name);
+		ev_clone->ev_pmcid = ev->ev_pmcid;
+		ev_clone->ev_saved = ev->ev_saved;
+		ev_clone->ev_spec  = strdup(ev->ev_spec);
+
+		STAILQ_INSERT_TAIL(&args.pa_events, ev_clone, ev_next);
+
+		cpumask &= ~(1 << cpu);
+	}
+}
+
+void
+pmcstat_create_process(void)
+{
+	char token;
+	pid_t pid;
+	struct kevent kev;
+	struct pmcstat_target *pt;
+
+	if (socketpair(AF_UNIX, SOCK_STREAM, 0, pmcstat_sockpair) < 0)
+		err(EX_OSERR, "ERROR: cannot create socket pair");
+
+	switch (pid = fork()) {
+	case -1:
+		err(EX_OSERR, "ERROR: cannot fork");
+		/*NOTREACHED*/
+
+	case 0:		/* child */
+		(void) close(pmcstat_sockpair[PARENTSOCKET]);
+
+		/* Write a token to tell our parent we've started executing. */
+		if (write(pmcstat_sockpair[CHILDSOCKET], "+", 1) != 1)
+			err(EX_OSERR, "ERROR (child): cannot write token");
+
+		/* Wait for our parent to signal us to start. */
+		if (read(pmcstat_sockpair[CHILDSOCKET], &token, 1) < 0)
+			err(EX_OSERR, "ERROR (child): cannot read token");
+		(void) close(pmcstat_sockpair[CHILDSOCKET]);
+
+		/* exec() the program requested */
+		execvp(*args.pa_argv, args.pa_argv);
+		/* and if that fails, notify the parent */
+		kill(getppid(), SIGCHLD);
+		err(EX_OSERR, "ERROR: execvp \"%s\" failed", *args.pa_argv);
+		/*NOTREACHED*/
+
+	default:	/* parent */
+		(void) close(pmcstat_sockpair[CHILDSOCKET]);
+		break;
+	}
+
+	/* Ask to be notified via a kevent when the target process exits. */
+	EV_SET(&kev, pid, EVFILT_PROC, EV_ADD|EV_ONESHOT, NOTE_EXIT, 0,
+	    NULL);
+	if (kevent(pmcstat_kq, &kev, 1, NULL, 0, NULL) < 0)
+		err(EX_OSERR, "ERROR: cannot monitor child process %d", pid);
+
+	if ((pt = malloc(sizeof(*pt))) == NULL)
+		errx(EX_SOFTWARE, "ERROR: Out of memory.");
+
+	pt->pt_pid = pid;
+	SLIST_INSERT_HEAD(&args.pa_targets, pt, pt_next);
+
+	/* Wait for the child to signal that its ready to go. */
+	if (read(pmcstat_sockpair[PARENTSOCKET], &token, 1) < 0)
+		err(EX_OSERR, "ERROR (parent): cannot read token");
+
+	return;
+}
+
+void
+pmcstat_find_targets(const char *spec)
+{
+	int n, nproc, pid, rv;
+	struct pmcstat_target *pt;
+	char errbuf[_POSIX2_LINE_MAX], *end;
+	static struct kinfo_proc *kp;
+	regex_t reg;
+	regmatch_t regmatch;
+
+	/* First check if we've been given a process id. */
+	pid = strtol(spec, &end, 0);
+	if (end != spec && pid >= 0) {
+		if ((pt = malloc(sizeof(*pt))) == NULL)
+			goto outofmemory;
+		pt->pt_pid = pid;
+		SLIST_INSERT_HEAD(&args.pa_targets, pt, pt_next);
+		return;
+	}
+
+	/* Otherwise treat arg as a regular expression naming processes. */
+	if (pmcstat_kvm == NULL) {
+		if ((pmcstat_kvm = kvm_openfiles(NULL, "/dev/null", NULL, 0,
+		    errbuf)) == NULL)
+			err(EX_OSERR, "ERROR: Cannot open kernel \"%s\"",
+			    errbuf);
+		if ((pmcstat_plist = kvm_getprocs(pmcstat_kvm, KERN_PROC_PROC,
+		    0, &nproc)) == NULL)
+			err(EX_OSERR, "ERROR: Cannot get process list: %s",
+			    kvm_geterr(pmcstat_kvm));
+	} else
+		nproc = 0;
+
+	if ((rv = regcomp(&reg, spec, REG_EXTENDED|REG_NOSUB)) != 0) {
+		regerror(rv, &reg, errbuf, sizeof(errbuf));
+		err(EX_DATAERR, "ERROR: Failed to compile regex \"%s\": %s",
+		    spec, errbuf);
+	}
+
+	for (n = 0, kp = pmcstat_plist; n < nproc; n++, kp++) {
+		if ((rv = regexec(&reg, kp->ki_comm, 1, &regmatch, 0)) == 0) {
+			if ((pt = malloc(sizeof(*pt))) == NULL)
+				goto outofmemory;
+			pt->pt_pid = kp->ki_pid;
+			SLIST_INSERT_HEAD(&args.pa_targets, pt, pt_next);
+		} else if (rv != REG_NOMATCH) {
+			regerror(rv, &reg, errbuf, sizeof(errbuf));
+			errx(EX_SOFTWARE, "ERROR: Regex evalation failed: %s",
+			    errbuf);
+		}
+	}
+
+	regfree(&reg);
+
+	return;
+
+ outofmemory:
+	errx(EX_SOFTWARE, "Out of memory.");
+	/*NOTREACHED*/
+}
+
+uint32_t
+pmcstat_get_cpumask(const char *cpuspec)
+{
+	uint32_t cpumask;
+	int cpu;
+	const char *s;
+	char *end;
+
+	s = cpuspec;
+	cpumask = 0ULL;
+
+	do {
+		cpu = strtol(s, &end, 0);
+		if (cpu < 0 || end == s)
+			errx(EX_USAGE, "ERROR: Illegal CPU specification "
+			    "\"%s\".", cpuspec);
+		cpumask |= (1 << cpu);
+		s = end + strspn(end, ", \t");
+	} while (*s);
+
+	return (cpumask);
+}
+
+void
+pmcstat_kill_process(void)
+{
+	struct pmcstat_target *pt;
+
+	assert(args.pa_flags & FLAG_HAS_COMMANDLINE);
+
+	/*
+	 * If a command line was specified, it would be the very first
+	 * in the list, before any other processes specified by -t.
+	 */
+	pt = SLIST_FIRST(&args.pa_targets);
+	assert(pt != NULL);
+
+	if (kill(pt->pt_pid, SIGINT) != 0)
+		err(EX_OSERR, "ERROR: cannot signal child process");
+}
+
+void
+pmcstat_start_pmcs(void)
+{
+	struct pmcstat_ev *ev;
+
+	STAILQ_FOREACH(ev, &args.pa_events, ev_next) {
+
+	    assert(ev->ev_pmcid != PMC_ID_INVALID);
+
+	    if (pmc_start(ev->ev_pmcid) < 0) {
+	        warn("ERROR: Cannot start pmc 0x%x \"%s\"",
+		    ev->ev_pmcid, ev->ev_name);
+		pmcstat_cleanup();
+		exit(EX_OSERR);
+	    }
+	}
+
+}
+
+void
+pmcstat_print_headers(void)
+{
+	struct pmcstat_ev *ev;
+	int c, w;
+
+	(void) fprintf(args.pa_printfile, PRINT_HEADER_PREFIX);
+
+	STAILQ_FOREACH(ev, &args.pa_events, ev_next) {
+		if (PMC_IS_SAMPLING_MODE(ev->ev_mode))
+			continue;
+
+		c = PMC_IS_SYSTEM_MODE(ev->ev_mode) ? 's' : 'p';
+
+		if (ev->ev_fieldskip != 0)
+			(void) fprintf(args.pa_printfile, "%*s",
+			    ev->ev_fieldskip, "");
+		w = ev->ev_fieldwidth - ev->ev_fieldskip - 2;
+
+		if (c == 's')
+			(void) fprintf(args.pa_printfile, "s/%02d/%-*s ",
+			    ev->ev_cpu, w-3, ev->ev_name);
+		else
+			(void) fprintf(args.pa_printfile, "p/%*s ", w,
+			    ev->ev_name);
+	}
+
+	(void) fflush(args.pa_printfile);
+}
+
+void
+pmcstat_print_counters(void)
+{
+	int extra_width;
+	struct pmcstat_ev *ev;
+	pmc_value_t value;
+
+	extra_width = sizeof(PRINT_HEADER_PREFIX) - 1;
+
+	STAILQ_FOREACH(ev, &args.pa_events, ev_next) {
+
+		/* skip sampling mode counters */
+		if (PMC_IS_SAMPLING_MODE(ev->ev_mode))
+			continue;
+
+		if (pmc_read(ev->ev_pmcid, &value) < 0)
+			err(EX_OSERR, "ERROR: Cannot read pmc "
+			    "\"%s\"", ev->ev_name);
+
+		(void) fprintf(args.pa_printfile, "%*ju ",
+		    ev->ev_fieldwidth + extra_width,
+		    (uintmax_t) ev->ev_cumulative ? value :
+		    (value - ev->ev_saved));
+
+		if (ev->ev_cumulative == 0)
+			ev->ev_saved = value;
+		extra_width = 0;
+	}
+
+	(void) fflush(args.pa_printfile);
+}
+
+/*
+ * Print output
+ */
+
+void
+pmcstat_print_pmcs(void)
+{
+	static int linecount = 0;
+
+	/* check if we need to print a header line */
+	if (++linecount > pmcstat_displayheight) {
+		(void) fprintf(args.pa_printfile, "\n");
+		linecount = 1;
+	}
+	if (linecount == 1)
+		pmcstat_print_headers();
+	(void) fprintf(args.pa_printfile, "\n");
+
+	pmcstat_print_counters();
+
+	return;
+}
+
+/*
+ * Do process profiling
+ *
+ * If a pid was specified, attach each allocated PMC to the target
+ * process.  Otherwise, fork a child and attach the PMCs to the child,
+ * and have the child exec() the target program.
+ */
+
+void
+pmcstat_start_process(void)
+{
+	/* Signal the child to proceed. */
+	if (write(pmcstat_sockpair[PARENTSOCKET], "!", 1) != 1)
+		err(EX_OSERR, "ERROR (parent): write of token failed");
+
+	(void) close(pmcstat_sockpair[PARENTSOCKET]);
+}
+
+void
+pmcstat_show_usage(void)
+{
+	errx(EX_USAGE,
+	    "[options] [commandline]\n"
+	    "\t Measure process and/or system performance using hardware\n"
+	    "\t performance monitoring counters.\n"
+	    "\t Options include:\n"
+	    "\t -C\t\t (toggle) show cumulative counts\n"
+	    "\t -D path\t create profiles in directory \"path\"\n"
+	    "\t -E\t\t (toggle) show counts at process exit\n"
+	    "\t -F file\t write a system-wide callgraph (Kcachegrind format)"
+		" to \"file\"\n"
+	    "\t -G file\t write a system-wide callgraph to \"file\"\n"
+	    "\t -M file\t print executable/gmon file map to \"file\"\n"
+	    "\t -N\t\t (toggle) capture callchains\n"
+	    "\t -O file\t send log output to \"file\"\n"
+	    "\t -P spec\t allocate a process-private sampling PMC\n"
+	    "\t -R file\t read events from \"file\"\n"
+	    "\t -S spec\t allocate a system-wide sampling PMC\n"
+	    "\t -T\t\t start in top mode\n"
+	    "\t -W\t\t (toggle) show counts per context switch\n"
+	    "\t -c cpu-list\t set cpus for subsequent system-wide PMCs\n"
+	    "\t -d\t\t (toggle) track descendants\n"
+	    "\t -f spec\t pass \"spec\" to as plugin option\n"
+	    "\t -g\t\t produce gprof(1) compatible profiles\n"
+	    "\t -k dir\t\t set the path to the kernel\n"
+	    "\t -n rate\t set sampling rate\n"
+	    "\t -o file\t send print output to \"file\"\n"
+	    "\t -p spec\t allocate a process-private counting PMC\n"
+	    "\t -q\t\t suppress verbosity\n"
+	    "\t -r fsroot\t specify FS root directory\n"
+	    "\t -s spec\t allocate a system-wide counting PMC\n"
+	    "\t -t process-spec attach to running processes matching "
+		"\"process-spec\"\n"
+	    "\t -v\t\t increase verbosity\n"
+	    "\t -w secs\t set printing time interval\n"
+	    "\t -z depth\t limit callchain display depth"
+	);
+}
+
+/*
+ * At exit handler for top mode
+ */
+
+void
+pmcstat_topexit(void)
+{
+	if (!args.pa_toptty)
+		return;
+
+	/*
+	 * Shutdown ncurses.
+	 */
+	clrtoeol();
+	refresh();
+	endwin();
+}
+
+/*
+ * Main
+ */
+
+int
+main(int argc, char **argv)
+{
+	double interval;
+	int option, npmc, ncpu, haltedcpus;
+	int c, check_driver_stats, current_cpu, current_sampling_count;
+	int do_callchain, do_descendants, do_logproccsw, do_logprocexit;
+	int do_print;
+	size_t dummy;
+	int graphdepth;
+	int pipefd[2], rfd;
+	int use_cumulative_counts;
+	short cf, cb;
+	uint32_t cpumask;
+	char *end, *tmp;
+	const char *errmsg, *graphfilename;
+	enum pmcstat_state runstate;
+	struct pmc_driverstats ds_start, ds_end;
+	struct pmcstat_ev *ev;
+	struct sigaction sa;
+	struct kevent kev;
+	struct winsize ws;
+	struct stat sb;
+	char buffer[PATH_MAX];
+
+	check_driver_stats      = 0;
+	current_cpu 		= 0;
+	current_sampling_count  = DEFAULT_SAMPLE_COUNT;
+	do_callchain		= 1;
+	do_descendants          = 0;
+	do_logproccsw           = 0;
+	do_logprocexit          = 0;
+	use_cumulative_counts   = 0;
+	graphfilename		= "-";
+	args.pa_required	= 0;
+	args.pa_flags		= 0;
+	args.pa_verbosity	= 1;
+	args.pa_logfd		= -1;
+	args.pa_fsroot		= "";
+	args.pa_kernel		= strdup("/boot/kernel");
+	args.pa_samplesdir	= ".";
+	args.pa_printfile	= stderr;
+	args.pa_graphdepth	= DEFAULT_CALLGRAPH_DEPTH;
+	args.pa_graphfile	= NULL;
+	args.pa_interval	= DEFAULT_WAIT_INTERVAL;
+	args.pa_mapfilename	= NULL;
+	args.pa_inputpath	= NULL;
+	args.pa_outputpath	= NULL;
+	args.pa_pplugin		= PMCSTAT_PL_NONE;
+	args.pa_plugin		= PMCSTAT_PL_NONE;
+	args.pa_ctdumpinstr	= 1;
+	args.pa_topmode		= PMCSTAT_TOP_DELTA;
+	args.pa_toptty		= 0;
+	args.pa_topcolor	= 0;
+	args.pa_mergepmc	= 0;
+	STAILQ_INIT(&args.pa_events);
+	SLIST_INIT(&args.pa_targets);
+	bzero(&ds_start, sizeof(ds_start));
+	bzero(&ds_end, sizeof(ds_end));
+	ev = NULL;
+
+	/*
+	 * The initial CPU mask specifies all non-halted CPUS in the
+	 * system.
+	 */
+	dummy = sizeof(int);
+	if (sysctlbyname("hw.ncpu", &ncpu, &dummy, NULL, 0) < 0)
+		err(EX_OSERR, "ERROR: Cannot determine the number of CPUs");
+	cpumask = (1 << ncpu) - 1;
+	haltedcpus = 0;
+	if (ncpu > 1) {
+		if (sysctlbyname("machdep.hlt_cpus", &haltedcpus, &dummy,
+		    NULL, 0) < 0)
+			err(EX_OSERR, "ERROR: Cannot determine which CPUs are "
+			    "halted");
+		cpumask &= ~haltedcpus;
+	}
+
+	while ((option = getopt(argc, argv,
+	    "CD:EF:G:M:NO:P:R:S:TWc:df:gk:m:n:o:p:qr:s:t:vw:z:")) != -1)
+		switch (option) {
+		case 'C':	/* cumulative values */
+			use_cumulative_counts = !use_cumulative_counts;
+			args.pa_required |= FLAG_HAS_COUNTING_PMCS;
+			break;
+
+		case 'c':	/* CPU */
+
+			if (optarg[0] == '*' && optarg[1] == '\0')
+				cpumask = ((1 << ncpu) - 1) & ~haltedcpus;
+			else
+				cpumask = pmcstat_get_cpumask(optarg);
+
+			args.pa_flags	 |= FLAGS_HAS_CPUMASK;
+			args.pa_required |= FLAG_HAS_SYSTEM_PMCS;
+			break;
+
+		case 'D':
+			if (stat(optarg, &sb) < 0)
+				err(EX_OSERR, "ERROR: Cannot stat \"%s\"",
+				    optarg);
+			if (!S_ISDIR(sb.st_mode))
+				errx(EX_USAGE, "ERROR: \"%s\" is not a "
+				    "directory.", optarg);
+			args.pa_samplesdir = optarg;
+			args.pa_flags     |= FLAG_HAS_SAMPLESDIR;
+			args.pa_required  |= FLAG_DO_GPROF;
+			break;
+
+		case 'd':	/* toggle descendents */
+			do_descendants = !do_descendants;
+			args.pa_required |= FLAG_HAS_PROCESS_PMCS;
+			break;
+
+		case 'F':	/* produce a system-wide calltree */
+			args.pa_flags |= FLAG_DO_CALLGRAPHS;
+			args.pa_plugin = PMCSTAT_PL_CALLTREE;
+			graphfilename = optarg;
+			break;
+
+		case 'f':	/* plugins options */
+			if (args.pa_plugin == PMCSTAT_PL_NONE)
+				err(EX_USAGE, "ERROR: Need -g/-G/-m/-T.");
+			pmcstat_pluginconfigure_log(optarg);
+			break;
+
+		case 'G':	/* produce a system-wide callgraph */
+			args.pa_flags |= FLAG_DO_CALLGRAPHS;
+			args.pa_plugin = PMCSTAT_PL_CALLGRAPH;
+			graphfilename = optarg;
+			break;
+
+		case 'g':	/* produce gprof compatible profiles */
+			args.pa_flags |= FLAG_DO_GPROF;
+			args.pa_pplugin = PMCSTAT_PL_CALLGRAPH;
+			args.pa_plugin	= PMCSTAT_PL_GPROF;
+			break;
+
+		case 'k':	/* pathname to the kernel */
+			free(args.pa_kernel);
+			args.pa_kernel = strdup(optarg);
+			args.pa_required |= FLAG_DO_ANALYSIS;
+			args.pa_flags    |= FLAG_HAS_KERNELPATH;
+			break;
+
+		case 'm':
+			args.pa_flags |= FLAG_DO_ANNOTATE;
+			args.pa_plugin = PMCSTAT_PL_ANNOTATE;
+			graphfilename  = optarg;
+			break;
+
+		case 'E':	/* log process exit */
+			do_logprocexit = !do_logprocexit;
+			args.pa_required |= (FLAG_HAS_PROCESS_PMCS |
+			    FLAG_HAS_COUNTING_PMCS | FLAG_HAS_OUTPUT_LOGFILE);
+			break;
+
+		case 'M':	/* mapfile */
+			args.pa_mapfilename = optarg;
+			break;
+
+		case 'N':
+			do_callchain = !do_callchain;
+			args.pa_required |= FLAG_HAS_SAMPLING_PMCS;
+			break;
+
+		case 'p':	/* process virtual counting PMC */
+		case 's':	/* system-wide counting PMC */
+		case 'P':	/* process virtual sampling PMC */
+		case 'S':	/* system-wide sampling PMC */
+			if ((ev = malloc(sizeof(*ev))) == NULL)
+				errx(EX_SOFTWARE, "ERROR: Out of memory.");
+
+			switch (option) {
+			case 'p': ev->ev_mode = PMC_MODE_TC; break;
+			case 's': ev->ev_mode = PMC_MODE_SC; break;
+			case 'P': ev->ev_mode = PMC_MODE_TS; break;
+			case 'S': ev->ev_mode = PMC_MODE_SS; break;
+			}
+
+			if (option == 'P' || option == 'p') {
+				args.pa_flags |= FLAG_HAS_PROCESS_PMCS;
+				args.pa_required |= (FLAG_HAS_COMMANDLINE |
+				    FLAG_HAS_TARGET);
+			}
+
+			if (option == 'P' || option == 'S') {
+				args.pa_flags |= FLAG_HAS_SAMPLING_PMCS;
+				args.pa_required |= (FLAG_HAS_PIPE |
+				    FLAG_HAS_OUTPUT_LOGFILE);
+			}
+
+			if (option == 'p' || option == 's')
+				args.pa_flags |= FLAG_HAS_COUNTING_PMCS;
+
+			if (option == 's' || option == 'S')
+				args.pa_flags |= FLAG_HAS_SYSTEM_PMCS;
+
+			ev->ev_spec  = strdup(optarg);
+
+			if (option == 'S' || option == 'P')
+				ev->ev_count = current_sampling_count;
+			else
+				ev->ev_count = -1;
+
+			if (option == 'S' || option == 's')
+				ev->ev_cpu = ffs(cpumask) - 1;
+			else
+				ev->ev_cpu = PMC_CPU_ANY;
+
+			ev->ev_flags = 0;
+			if (do_callchain)
+				ev->ev_flags |= PMC_F_CALLCHAIN;
+			if (do_descendants)
+				ev->ev_flags |= PMC_F_DESCENDANTS;
+			if (do_logprocexit)
+				ev->ev_flags |= PMC_F_LOG_PROCEXIT;
+			if (do_logproccsw)
+				ev->ev_flags |= PMC_F_LOG_PROCCSW;
+
+			ev->ev_cumulative  = use_cumulative_counts;
+
+			ev->ev_saved = 0LL;
+			ev->ev_pmcid = PMC_ID_INVALID;
+
+			/* extract event name */
+			c = strcspn(optarg, ", \t");
+			ev->ev_name = malloc(c + 1);
+			(void) strncpy(ev->ev_name, optarg, c);
+			*(ev->ev_name + c) = '\0';
+
+			STAILQ_INSERT_TAIL(&args.pa_events, ev, ev_next);
+
+			if (option == 's' || option == 'S')
+				pmcstat_clone_event_descriptor(ev,
+				    cpumask & ~(1 << ev->ev_cpu));
+
+			break;
+
+		case 'n':	/* sampling count */
+			current_sampling_count = strtol(optarg, &end, 0);
+			if (*end != '\0' || current_sampling_count <= 0)
+				errx(EX_USAGE,
+				    "ERROR: Illegal count value \"%s\".",
+				    optarg);
+			args.pa_required |= FLAG_HAS_SAMPLING_PMCS;
+			break;
+
+		case 'o':	/* outputfile */
+			if (args.pa_printfile != NULL)
+				(void) fclose(args.pa_printfile);
+			if ((args.pa_printfile = fopen(optarg, "w")) == NULL)
+				errx(EX_OSERR, "ERROR: cannot open \"%s\" for "
+				    "writing.", optarg);
+			args.pa_flags |= FLAG_DO_PRINT;
+			break;
+
+		case 'O':	/* sampling output */
+			if (args.pa_outputpath)
+				errx(EX_USAGE, "ERROR: option -O may only be "
+				    "specified once.");
+			args.pa_outputpath = optarg;
+			args.pa_flags |= FLAG_HAS_OUTPUT_LOGFILE;
+			break;
+
+		case 'q':	/* quiet mode */
+			args.pa_verbosity = 0;
+			break;
+
+		case 'r':	/* root FS path */
+			args.pa_fsroot = optarg;
+			break;
+
+		case 'R':	/* read an existing log file */
+			if (args.pa_inputpath != NULL)
+				errx(EX_USAGE, "ERROR: option -R may only be "
+				    "specified once.");
+			args.pa_inputpath = optarg;
+			if (args.pa_printfile == stderr)
+				args.pa_printfile = stdout;
+			args.pa_flags |= FLAG_READ_LOGFILE;
+			break;
+
+		case 't':	/* target pid or process name */
+			pmcstat_find_targets(optarg);
+
+			args.pa_flags |= FLAG_HAS_TARGET;
+			args.pa_required |= FLAG_HAS_PROCESS_PMCS;
+			break;
+
+		case 'T':	/* top mode */
+			args.pa_flags |= FLAG_DO_TOP;
+			args.pa_plugin = PMCSTAT_PL_CALLGRAPH;
+			args.pa_ctdumpinstr = 0;
+			args.pa_mergepmc = 1;
+			if (args.pa_printfile == stderr)
+				args.pa_printfile = stdout;
+			break;
+
+		case 'v':	/* verbose */
+			args.pa_verbosity++;
+			break;
+
+		case 'w':	/* wait interval */
+			interval = strtod(optarg, &end);
+			if (*end != '\0' || interval <= 0)
+				errx(EX_USAGE, "ERROR: Illegal wait interval "
+				    "value \"%s\".", optarg);
+			args.pa_flags |= FLAG_HAS_WAIT_INTERVAL;
+			args.pa_interval = interval;
+			break;
+
+		case 'W':	/* toggle LOG_CSW */
+			do_logproccsw = !do_logproccsw;
+			args.pa_required |= (FLAG_HAS_PROCESS_PMCS |
+			    FLAG_HAS_COUNTING_PMCS | FLAG_HAS_OUTPUT_LOGFILE);
+			break;
+
+		case 'z':
+			graphdepth = strtod(optarg, &end);
+			if (*end != '\0' || graphdepth <= 0)
+				errx(EX_USAGE, "ERROR: Illegal callchain "
+				    "depth \"%s\".", optarg);
+			args.pa_graphdepth = graphdepth;
+			args.pa_required |= FLAG_DO_CALLGRAPHS;
+			break;
+
+		case '?':
+		default:
+			pmcstat_show_usage();
+			break;
+
+		}
+
+	args.pa_argc = (argc -= optind);
+	args.pa_argv = (argv += optind);
+
+	/* If we read from logfile and no specified CPU mask use
+	 * the maximum CPU count.
+	 */
+	if ((args.pa_flags & FLAG_READ_LOGFILE) &&
+	    (args.pa_flags & FLAGS_HAS_CPUMASK) == 0)
+		cpumask = 0xffffffff;
+
+	args.pa_cpumask = cpumask; /* For selecting CPUs using -R. */
+
+	if (argc)	/* command line present */
+		args.pa_flags |= FLAG_HAS_COMMANDLINE;
+
+	if (args.pa_flags & (FLAG_DO_GPROF | FLAG_DO_CALLGRAPHS |
+	    FLAG_DO_ANNOTATE | FLAG_DO_TOP))
+		args.pa_flags |= FLAG_DO_ANALYSIS;
+
+	/*
+	 * Check invocation syntax.
+	 */
+
+	/* disallow -O and -R together */
+	if (args.pa_outputpath && args.pa_inputpath)
+		errx(EX_USAGE, "ERROR: options -O and -R are mutually "
+		    "exclusive.");
+
+	/* -m option is allowed with -R only. */
+	if (args.pa_flags & FLAG_DO_ANNOTATE && args.pa_inputpath == NULL)
+		errx(EX_USAGE, "ERROR: option -m requires an input file");
+
+	/* -m option is not allowed combined with -g or -G. */
+	if (args.pa_flags & FLAG_DO_ANNOTATE &&
+	    args.pa_flags & (FLAG_DO_GPROF | FLAG_DO_CALLGRAPHS))
+		errx(EX_USAGE, "ERROR: option -m and -g | -G are mutually "
+		    "exclusive");
+
+	if (args.pa_flags & FLAG_READ_LOGFILE) {
+		errmsg = NULL;
+		if (args.pa_flags & FLAG_HAS_COMMANDLINE)
+			errmsg = "a command line specification";
+		else if (args.pa_flags & FLAG_HAS_TARGET)
+			errmsg = "option -t";
+		else if (!STAILQ_EMPTY(&args.pa_events))
+			errmsg = "a PMC event specification";
+		if (errmsg)
+			errx(EX_USAGE, "ERROR: option -R may not be used with "
+			    "%s.", errmsg);
+	} else if (STAILQ_EMPTY(&args.pa_events))
+		/* All other uses require a PMC spec. */
+		pmcstat_show_usage();
+
+	/* check for -t pid without a process PMC spec */
+	if ((args.pa_required & FLAG_HAS_TARGET) &&
+	    (args.pa_flags & FLAG_HAS_PROCESS_PMCS) == 0)
+		errx(EX_USAGE, "ERROR: option -t requires a process mode PMC "
+		    "to be specified.");
+
+	/* check for process-mode options without a command or -t pid */
+	if ((args.pa_required & FLAG_HAS_PROCESS_PMCS) &&
+	    (args.pa_flags & (FLAG_HAS_COMMANDLINE | FLAG_HAS_TARGET)) == 0)
+		errx(EX_USAGE, "ERROR: options -d, -E, -p, -P, and -W require "
+		    "a command line or target process.");
+
+	/* check for -p | -P without a target process of some sort */
+	if ((args.pa_required & (FLAG_HAS_COMMANDLINE | FLAG_HAS_TARGET)) &&
+	    (args.pa_flags & (FLAG_HAS_COMMANDLINE | FLAG_HAS_TARGET)) == 0)
+		errx(EX_USAGE, "ERROR: options -P and -p require a "
+		    "target process or a command line.");
+
+	/* check for process-mode options without a process-mode PMC */
+	if ((args.pa_required & FLAG_HAS_PROCESS_PMCS) &&
+	    (args.pa_flags & FLAG_HAS_PROCESS_PMCS) == 0)
+		errx(EX_USAGE, "ERROR: options -d, -E, and -W require a "
+		    "process mode PMC to be specified.");
+
+	/* check for -c cpu with no system mode PMCs or logfile. */
+	if ((args.pa_required & FLAG_HAS_SYSTEM_PMCS) &&
+	    (args.pa_flags & FLAG_HAS_SYSTEM_PMCS) == 0 &&
+	    (args.pa_flags & FLAG_READ_LOGFILE) == 0)
+		errx(EX_USAGE, "ERROR: option -c requires at least one "
+		    "system mode PMC to be specified.");
+
+	/* check for counting mode options without a counting PMC */
+	if ((args.pa_required & FLAG_HAS_COUNTING_PMCS) &&
+	    (args.pa_flags & FLAG_HAS_COUNTING_PMCS) == 0)
+		errx(EX_USAGE, "ERROR: options -C, -W and -o require at "
+		    "least one counting mode PMC to be specified.");
+
+	/* check for sampling mode options without a sampling PMC spec */
+	if ((args.pa_required & FLAG_HAS_SAMPLING_PMCS) &&
+	    (args.pa_flags & FLAG_HAS_SAMPLING_PMCS) == 0)
+		errx(EX_USAGE, "ERROR: options -N, -n and -O require at "
+		    "least one sampling mode PMC to be specified.");
+
+	/* check if -g/-G/-m/-T are being used correctly */
+	if ((args.pa_flags & FLAG_DO_ANALYSIS) &&
+	    !(args.pa_flags & (FLAG_HAS_SAMPLING_PMCS|FLAG_READ_LOGFILE)))
+		errx(EX_USAGE, "ERROR: options -g/-G/-m/-T require sampling PMCs "
+		    "or -R to be specified.");
+
+	/* check if -O was spuriously specified */
+	if ((args.pa_flags & FLAG_HAS_OUTPUT_LOGFILE) &&
+	    (args.pa_required & FLAG_HAS_OUTPUT_LOGFILE) == 0)
+		errx(EX_USAGE,
+		    "ERROR: option -O is used only with options "
+		    "-E, -P, -S and -W.");
+
+	/* -k kernel path require -g/-G/-m/-T or -R */
+	if ((args.pa_flags & FLAG_HAS_KERNELPATH) &&
+	    (args.pa_flags & FLAG_DO_ANALYSIS) == 0 &&
+	    (args.pa_flags & FLAG_READ_LOGFILE) == 0)
+	    errx(EX_USAGE, "ERROR: option -k is only used with -g/-R/-m/-T.");
+
+	/* -D only applies to gprof output mode (-g) */
+	if ((args.pa_flags & FLAG_HAS_SAMPLESDIR) &&
+	    (args.pa_flags & FLAG_DO_GPROF) == 0)
+	    errx(EX_USAGE, "ERROR: option -D is only used with -g.");
+
+	/* -M mapfile requires -g or -R */
+	if (args.pa_mapfilename != NULL &&
+	    (args.pa_flags & FLAG_DO_GPROF) == 0 &&
+	    (args.pa_flags & FLAG_READ_LOGFILE) == 0)
+	    errx(EX_USAGE, "ERROR: option -M is only used with -g/-R.");
+
+	/*
+	 * Disallow textual output of sampling PMCs if counting PMCs
+	 * have also been asked for, mostly because the combined output
+	 * is difficult to make sense of.
+	 */
+	if ((args.pa_flags & FLAG_HAS_COUNTING_PMCS) &&
+	    (args.pa_flags & FLAG_HAS_SAMPLING_PMCS) &&
+	    ((args.pa_flags & FLAG_HAS_OUTPUT_LOGFILE) == 0))
+		errx(EX_USAGE, "ERROR: option -O is required if counting and "
+		    "sampling PMCs are specified together.");
+
+	/*
+	 * Check if "-k kerneldir" was specified, and if whether
+	 * 'kerneldir' actually refers to a a file.  If so, use
+	 * `dirname path` to determine the kernel directory.
+	 */
+	if (args.pa_flags & FLAG_HAS_KERNELPATH) {
+		(void) snprintf(buffer, sizeof(buffer), "%s%s", args.pa_fsroot,
+		    args.pa_kernel);
+		if (stat(buffer, &sb) < 0)
+			err(EX_OSERR, "ERROR: Cannot locate kernel \"%s\"",
+			    buffer);
+		if (!S_ISREG(sb.st_mode) && !S_ISDIR(sb.st_mode))
+			errx(EX_USAGE, "ERROR: \"%s\": Unsupported file type.",
+			    buffer);
+		if (!S_ISDIR(sb.st_mode)) {
+			tmp = args.pa_kernel;
+			args.pa_kernel = strdup(dirname(args.pa_kernel));
+			free(tmp);
+			(void) snprintf(buffer, sizeof(buffer), "%s%s",
+			    args.pa_fsroot, args.pa_kernel);
+			if (stat(buffer, &sb) < 0)
+				err(EX_OSERR, "ERROR: Cannot stat \"%s\"",
+				    buffer);
+			if (!S_ISDIR(sb.st_mode))
+				errx(EX_USAGE, "ERROR: \"%s\" is not a "
+				    "directory.", buffer);
+		}
+	}
+
+	/*
+	 * If we have a callgraph be created, select the outputfile.
+	 */
+	if (args.pa_flags & FLAG_DO_CALLGRAPHS) {
+		if (strcmp(graphfilename, "-") == 0)
+		    args.pa_graphfile = args.pa_printfile;
+		else {
+			args.pa_graphfile = fopen(graphfilename, "w");
+			if (args.pa_graphfile == NULL)
+				err(EX_OSERR, "ERROR: cannot open \"%s\" "
+				    "for writing", graphfilename);
+		}
+	}
+	if (args.pa_flags & FLAG_DO_ANNOTATE) {
+		args.pa_graphfile = fopen(graphfilename, "w");
+		if (args.pa_graphfile == NULL)
+			err(EX_OSERR, "ERROR: cannot open \"%s\" for writing",
+			    graphfilename);
+	}
+
+	/* if we've been asked to process a log file, skip init */
+	if ((args.pa_flags & FLAG_READ_LOGFILE) == 0) {
+		if (pmc_init() < 0)
+			err(EX_UNAVAILABLE,
+			    "ERROR: Initialization of the pmc(3) library failed");
+
+		if ((npmc = pmc_npmc(0)) < 0) /* assume all CPUs are identical */
+			err(EX_OSERR, "ERROR: Cannot determine the number of PMCs "
+			    "on CPU %d", 0);
+	}
+
+	/* Allocate a kqueue */
+	if ((pmcstat_kq = kqueue()) < 0)
+		err(EX_OSERR, "ERROR: Cannot allocate kqueue");
+
+	/* Setup the logfile as the source. */
+	if (args.pa_flags & FLAG_READ_LOGFILE) {
+		/*
+		 * Print the log in textual form if we haven't been
+		 * asked to generate profiling information.
+		 */
+		if ((args.pa_flags & FLAG_DO_ANALYSIS) == 0)
+			args.pa_flags |= FLAG_DO_PRINT;
+
+		pmcstat_initialize_logging();
+		rfd = pmcstat_open_log(args.pa_inputpath,
+		    PMCSTAT_OPEN_FOR_READ);
+		if ((args.pa_logparser = pmclog_open(rfd)) == NULL)
+			err(EX_OSERR, "ERROR: Cannot create parser");
+		if (fcntl(rfd, F_SETFL, O_NONBLOCK) < 0)
+			err(EX_OSERR, "ERROR: fcntl(2) failed");
+		EV_SET(&kev, rfd, EVFILT_READ, EV_ADD,
+		    0, 0, NULL);
+		if (kevent(pmcstat_kq, &kev, 1, NULL, 0, NULL) < 0)
+			err(EX_OSERR, "ERROR: Cannot register kevent");
+	}
+	/*
+	 * Configure the specified log file or setup a default log
+	 * consumer via a pipe.
+	 */
+	if (args.pa_required & FLAG_HAS_OUTPUT_LOGFILE) {
+		if (args.pa_outputpath)
+			args.pa_logfd = pmcstat_open_log(args.pa_outputpath,
+			    PMCSTAT_OPEN_FOR_WRITE);
+		else {
+			/*
+			 * process the log on the fly by reading it in
+			 * through a pipe.
+			 */
+			if (pipe(pipefd) < 0)
+				err(EX_OSERR, "ERROR: pipe(2) failed");
+
+			if (fcntl(pipefd[READPIPEFD], F_SETFL, O_NONBLOCK) < 0)
+				err(EX_OSERR, "ERROR: fcntl(2) failed");
+
+			EV_SET(&kev, pipefd[READPIPEFD], EVFILT_READ, EV_ADD,
+			    0, 0, NULL);
+
+			if (kevent(pmcstat_kq, &kev, 1, NULL, 0, NULL) < 0)
+				err(EX_OSERR, "ERROR: Cannot register kevent");
+
+			args.pa_logfd = pipefd[WRITEPIPEFD];
+
+			args.pa_flags |= FLAG_HAS_PIPE;
+			if ((args.pa_flags & FLAG_DO_TOP) == 0)
+				args.pa_flags |= FLAG_DO_PRINT;
+			args.pa_logparser = pmclog_open(pipefd[READPIPEFD]);
+		}
+
+		if (pmc_configure_logfile(args.pa_logfd) < 0)
+			err(EX_OSERR, "ERROR: Cannot configure log file");
+	}
+
+	/* remember to check for driver errors if we are sampling or logging */
+	check_driver_stats = (args.pa_flags & FLAG_HAS_SAMPLING_PMCS) ||
+	    (args.pa_flags & FLAG_HAS_OUTPUT_LOGFILE);
+
+	/*
+	if (args.pa_flags & FLAG_READ_LOGFILE) {
+	 * Allocate PMCs.
+	 */
+
+	STAILQ_FOREACH(ev, &args.pa_events, ev_next) {
+	    if (pmc_allocate(ev->ev_spec, ev->ev_mode,
+		    ev->ev_flags, ev->ev_cpu, &ev->ev_pmcid) < 0)
+		    err(EX_OSERR, "ERROR: Cannot allocate %s-mode pmc with "
+			"specification \"%s\"",
+			PMC_IS_SYSTEM_MODE(ev->ev_mode) ? "system" : "process",
+			ev->ev_spec);
+
+	    if (PMC_IS_SAMPLING_MODE(ev->ev_mode) &&
+		pmc_set(ev->ev_pmcid, ev->ev_count) < 0)
+		    err(EX_OSERR, "ERROR: Cannot set sampling count "
+			"for PMC \"%s\"", ev->ev_name);
+	}
+
+	/* compute printout widths */
+	STAILQ_FOREACH(ev, &args.pa_events, ev_next) {
+		int counter_width;
+		int display_width;
+		int header_width;
+
+		(void) pmc_width(ev->ev_pmcid, &counter_width);
+		header_width = strlen(ev->ev_name) + 2; /* prefix '%c/' */
+		display_width = (int) floor(counter_width / 3.32193) + 1;
+
+		if (PMC_IS_SYSTEM_MODE(ev->ev_mode))
+			header_width += 3; /* 2 digit CPU number + '/' */
+
+		if (header_width > display_width) {
+			ev->ev_fieldskip = 0;
+			ev->ev_fieldwidth = header_width;
+		} else {
+			ev->ev_fieldskip = display_width -
+			    header_width;
+			ev->ev_fieldwidth = display_width;
+		}
+	}
+
+	/*
+	 * If our output is being set to a terminal, register a handler
+	 * for window size changes.
+	 */
+
+	if (isatty(fileno(args.pa_printfile))) {
+
+		if (ioctl(fileno(args.pa_printfile), TIOCGWINSZ, &ws) < 0)
+			err(EX_OSERR, "ERROR: Cannot determine window size");
+
+		pmcstat_displayheight = ws.ws_row - 1;
+		pmcstat_displaywidth  = ws.ws_col - 1;
+
+		EV_SET(&kev, SIGWINCH, EVFILT_SIGNAL, EV_ADD, 0, 0, NULL);
+
+		if (kevent(pmcstat_kq, &kev, 1, NULL, 0, NULL) < 0)
+			err(EX_OSERR, "ERROR: Cannot register kevent for "
+			    "SIGWINCH");
+
+		args.pa_toptty = 1;
+	}
+
+	/*
+	 * Listen to key input in top mode.
+	 */
+	if (args.pa_flags & FLAG_DO_TOP) {
+		EV_SET(&kev, fileno(stdin), EVFILT_READ, EV_ADD, 0, 0, NULL);
+		if (kevent(pmcstat_kq, &kev, 1, NULL, 0, NULL) < 0)
+			err(EX_OSERR, "ERROR: Cannot register kevent");
+	}
+
+	EV_SET(&kev, SIGINT, EVFILT_SIGNAL, EV_ADD, 0, 0, NULL);
+	if (kevent(pmcstat_kq, &kev, 1, NULL, 0, NULL) < 0)
+		err(EX_OSERR, "ERROR: Cannot register kevent for SIGINT");
+
+	EV_SET(&kev, SIGIO, EVFILT_SIGNAL, EV_ADD, 0, 0, NULL);
+	if (kevent(pmcstat_kq, &kev, 1, NULL, 0, NULL) < 0)
+		err(EX_OSERR, "ERROR: Cannot register kevent for SIGIO");
+
+	/*
+	 * An exec() failure of a forked child is signalled by the
+	 * child sending the parent a SIGCHLD.  We don't register an
+	 * actual signal handler for SIGCHLD, but instead use our
+	 * kqueue to pick up the signal.
+	 */
+	EV_SET(&kev, SIGCHLD, EVFILT_SIGNAL, EV_ADD, 0, 0, NULL);
+	if (kevent(pmcstat_kq, &kev, 1, NULL, 0, NULL) < 0)
+		err(EX_OSERR, "ERROR: Cannot register kevent for SIGCHLD");
+
+	/*
+	 * Setup a timer if we have counting mode PMCs needing to be printed or
+	 * top mode plugin is active.
+	 */
+	if (((args.pa_flags & FLAG_HAS_COUNTING_PMCS) &&
+	     (args.pa_required & FLAG_HAS_OUTPUT_LOGFILE) == 0) ||
+	    (args.pa_flags & FLAG_DO_TOP)) {
+		EV_SET(&kev, 0, EVFILT_TIMER, EV_ADD, 0,
+		    args.pa_interval * 1000, NULL);
+
+		if (kevent(pmcstat_kq, &kev, 1, NULL, 0, NULL) < 0)
+			err(EX_OSERR, "ERROR: Cannot register kevent for "
+			    "timer");
+	}
+
+	/* attach PMCs to the target process, starting it if specified */
+	if (args.pa_flags & FLAG_HAS_COMMANDLINE)
+		pmcstat_create_process();
+
+	if (check_driver_stats && pmc_get_driver_stats(&ds_start) < 0)
+		err(EX_OSERR, "ERROR: Cannot retrieve driver statistics");
+
+	/* Attach process pmcs to the target process. */
+	if (args.pa_flags & (FLAG_HAS_TARGET | FLAG_HAS_COMMANDLINE)) {
+		if (SLIST_EMPTY(&args.pa_targets))
+			errx(EX_DATAERR, "ERROR: No matching target "
+			    "processes.");
+		if (args.pa_flags & FLAG_HAS_PROCESS_PMCS)
+			pmcstat_attach_pmcs();
+
+		if (pmcstat_kvm) {
+			kvm_close(pmcstat_kvm);
+			pmcstat_kvm = NULL;
+		}
+	}
+
+	/* start the pmcs */
+	pmcstat_start_pmcs();
+
+	/* start the (commandline) process if needed */
+	if (args.pa_flags & FLAG_HAS_COMMANDLINE)
+		pmcstat_start_process();
+
+	/* initialize logging */
+	pmcstat_initialize_logging();
+
+	/* Handle SIGINT using the kqueue loop */
+	sa.sa_handler = SIG_IGN;
+	sa.sa_flags   = 0;
+	(void) sigemptyset(&sa.sa_mask);
+
+	if (sigaction(SIGINT, &sa, NULL) < 0)
+		err(EX_OSERR, "ERROR: Cannot install signal handler");
+
+	/*
+	 * Setup the top mode display.
+	 */
+	if (args.pa_flags & FLAG_DO_TOP) {
+		args.pa_flags &= ~FLAG_DO_PRINT;
+
+		if (args.pa_toptty) {
+			/*
+			 * Init ncurses.
+			 */
+			initscr();
+			if(has_colors() == TRUE) {
+				args.pa_topcolor = 1;
+				start_color();
+				use_default_colors();
+				pair_content(0, &cf, &cb);
+				init_pair(1, COLOR_RED, cb);
+				init_pair(2, COLOR_YELLOW, cb);
+				init_pair(3, COLOR_GREEN, cb);
+			}
+			cbreak();
+			noecho();
+			nonl();
+			nodelay(stdscr, 1);
+			intrflush(stdscr, FALSE);
+			keypad(stdscr, TRUE);
+			clear();
+			/* Get terminal width / height with ncurses. */
+			getmaxyx(stdscr, pmcstat_displayheight, pmcstat_displaywidth);
+			pmcstat_displayheight--; pmcstat_displaywidth--;
+			atexit(pmcstat_topexit);
+		}
+	}
+
+	/*
+	 * loop till either the target process (if any) exits, or we
+	 * are killed by a SIGINT.
+	 */
+	runstate = PMCSTAT_RUNNING;
+	do_print = 0;
+	do {
+		if ((c = kevent(pmcstat_kq, NULL, 0, &kev, 1, NULL)) <= 0) {
+			if (errno != EINTR)
+				err(EX_OSERR, "ERROR: kevent failed");
+			else
+				continue;
+		}
+
+		if (kev.flags & EV_ERROR)
+			errc(EX_OSERR, kev.data, "ERROR: kevent failed");
+
+		switch (kev.filter) {
+		case EVFILT_PROC:  /* target has exited */
+			runstate = pmcstat_close_log();
+			do_print = 1;
+			break;
+
+		case EVFILT_READ:  /* log file data is present */
+			if (kev.ident == (unsigned)fileno(stdin) &&
+			    (args.pa_flags & FLAG_DO_TOP)) {
+				if (pmcstat_keypress_log())
+					runstate = pmcstat_close_log();
+			} else
+				runstate = pmcstat_process_log();
+			break;
+
+		case EVFILT_SIGNAL:
+			if (kev.ident == SIGCHLD) {
+				/*
+				 * The child process sends us a
+				 * SIGCHLD if its exec() failed.  We
+				 * wait for it to exit and then exit
+				 * ourselves.
+				 */
+				(void) wait(&c);
+				runstate = PMCSTAT_FINISHED;
+			} else if (kev.ident == SIGIO) {
+				/*
+				 * We get a SIGIO if a PMC loses all
+				 * of its targets, or if logfile
+				 * writes encounter an error.
+				 */
+				runstate = pmcstat_close_log();
+				do_print = 1; /* print PMCs at exit */
+			} else if (kev.ident == SIGINT) {
+				/* Kill the child process if we started it */
+				if (args.pa_flags & FLAG_HAS_COMMANDLINE)
+					pmcstat_kill_process();
+				/* Close the pipe to self, if present. */
+				if (args.pa_flags & FLAG_HAS_PIPE)
+					(void) close(pipefd[READPIPEFD]);
+				runstate = pmcstat_close_log();
+			} else if (kev.ident == SIGWINCH) {
+				if (ioctl(fileno(args.pa_printfile),
+					TIOCGWINSZ, &ws) < 0)
+				    err(EX_OSERR, "ERROR: Cannot determine "
+					"window size");
+				pmcstat_displayheight = ws.ws_row - 1;
+				pmcstat_displaywidth  = ws.ws_col - 1;
+			} else
+				assert(0);
+
+			break;
+
+		case EVFILT_TIMER: /* print out counting PMCs */
+			do_print = 1;
+			break;
+
+		}
+
+		if (do_print) {
+			if ((args.pa_required & FLAG_HAS_OUTPUT_LOGFILE) == 0) {
+				pmcstat_print_pmcs();
+				if (runstate == PMCSTAT_FINISHED && /* final newline */
+				    (args.pa_flags & FLAG_DO_PRINT) == 0)
+					(void) fprintf(args.pa_printfile, "\n");
+			}
+			if (args.pa_flags & FLAG_DO_TOP)
+				pmcstat_display_log();
+			do_print = 0;
+		}
+
+	} while (runstate != PMCSTAT_FINISHED);
+
+	if ((args.pa_flags & FLAG_DO_TOP) && args.pa_toptty) {
+		pmcstat_topexit();
+		args.pa_toptty = 0;
+	}
+
+	/* flush any pending log entries */
+	if (args.pa_flags & (FLAG_HAS_OUTPUT_LOGFILE | FLAG_HAS_PIPE))
+		pmc_flush_logfile();
+
+	pmcstat_cleanup();
+
+	free(args.pa_kernel);
+
+	/* check if the driver lost any samples or events */
+	if (check_driver_stats) {
+		if (pmc_get_driver_stats(&ds_end) < 0)
+			err(EX_OSERR, "ERROR: Cannot retrieve driver "
+			    "statistics");
+		if (ds_start.pm_intr_bufferfull != ds_end.pm_intr_bufferfull &&
+		    args.pa_verbosity > 0)
+			warnx("WARNING: some samples were dropped.  Please "
+			    "consider tuning the \"kern.hwpmc.nsamples\" "
+			    "tunable.");
+		if (ds_start.pm_buffer_requests_failed !=
+		    ds_end.pm_buffer_requests_failed &&
+		    args.pa_verbosity > 0)
+			warnx("WARNING: some events were discarded.  Please "
+			    "consider tuning the \"kern.hwpmc.nbuffers\" "
+			    "tunable.");
+	}
+
+	exit(EX_OK);
+}
diff --git a/usr.sbin/pmcstat/pmcstat.h b/usr.sbin/pmcstat/pmcstat.h
new file mode 100644
index 0000000..b1600e4
--- /dev/null
+++ b/usr.sbin/pmcstat/pmcstat.h
@@ -0,0 +1,184 @@
+/*-
+ * Copyright (c) 2005-2007, Joseph Koshy
+ * Copyright (c) 2007 The FreeBSD Foundation
+ * All rights reserved.
+ *
+ * Portions of this software were developed by A. Joseph Koshy under
+ * sponsorship from the FreeBSD Foundation and Google, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: src/usr.sbin/pmcstat/pmcstat.h,v 1.9 2010/08/03 13:46:25 fabient Exp $
+ */
+
+#ifndef	_PMCSTAT_H_
+#define	_PMCSTAT_H_
+
+#define	FLAG_HAS_TARGET			0x00000001	/* process target */
+#define	FLAG_HAS_WAIT_INTERVAL		0x00000002	/* -w secs */
+#define	FLAG_HAS_OUTPUT_LOGFILE		0x00000004	/* -O file or pipe */
+#define	FLAG_HAS_COMMANDLINE		0x00000008	/* command */
+#define	FLAG_HAS_SAMPLING_PMCS		0x00000010	/* -S or -P */
+#define	FLAG_HAS_COUNTING_PMCS		0x00000020	/* -s or -p */
+#define	FLAG_HAS_PROCESS_PMCS		0x00000040	/* -P or -p */
+#define	FLAG_HAS_SYSTEM_PMCS		0x00000080	/* -S or -s */
+#define	FLAG_HAS_PIPE			0x00000100	/* implicit log */
+#define	FLAG_READ_LOGFILE		0x00000200	/* -R file */
+#define	FLAG_DO_GPROF			0x00000400	/* -g */
+#define	FLAG_HAS_SAMPLESDIR		0x00000800	/* -D dir */
+#define	FLAG_HAS_KERNELPATH		0x00001000	/* -k kernel */
+#define	FLAG_DO_PRINT			0x00002000	/* -o */
+#define	FLAG_DO_CALLGRAPHS		0x00004000	/* -G or -F */
+#define	FLAG_DO_ANNOTATE		0x00008000	/* -m */
+#define	FLAG_DO_TOP			0x00010000	/* -T */
+#define	FLAG_DO_ANALYSIS		0x00020000	/* -g or -G or -m or -T */
+#define	FLAGS_HAS_CPUMASK		0x00040000	/* -c */
+
+#define	DEFAULT_SAMPLE_COUNT		65536
+#define	DEFAULT_WAIT_INTERVAL		5.0
+#define	DEFAULT_DISPLAY_HEIGHT		256		/* file virtual height */
+#define	DEFAULT_DISPLAY_WIDTH		1024		/* file virtual width */
+#define	DEFAULT_BUFFER_SIZE		4096
+#define	DEFAULT_CALLGRAPH_DEPTH		4
+
+#define	PRINT_HEADER_PREFIX		"# "
+#define	READPIPEFD			0
+#define	WRITEPIPEFD			1
+#define	NPIPEFD				2
+
+#define	NSOCKPAIRFD			2
+#define	PARENTSOCKET			0
+#define	CHILDSOCKET			1
+
+#define	PMCSTAT_OPEN_FOR_READ		0
+#define	PMCSTAT_OPEN_FOR_WRITE		1
+#define	PMCSTAT_DEFAULT_NW_HOST		"localhost"
+#define	PMCSTAT_DEFAULT_NW_PORT		"9000"
+#define	PMCSTAT_NHASH			256
+#define	PMCSTAT_HASH_MASK		0xFF
+
+#define	PMCSTAT_LDD_COMMAND		"/usr/bin/ldd"
+
+#define	PMCSTAT_PRINT_ENTRY(T,...) do {					\
+		(void) fprintf(args.pa_printfile, "%-9s", T);		\
+		(void) fprintf(args.pa_printfile, " "  __VA_ARGS__);	\
+		(void) fprintf(args.pa_printfile, "\n");		\
+	} while (0)
+
+#define PMCSTAT_PL_NONE		0
+#define PMCSTAT_PL_CALLGRAPH	1
+#define PMCSTAT_PL_GPROF	2
+#define PMCSTAT_PL_ANNOTATE	3
+#define PMCSTAT_PL_CALLTREE	4
+
+#define PMCSTAT_TOP_DELTA 	0
+#define PMCSTAT_TOP_ACCUM	1
+
+#define	min(A,B)		((A) < (B) ? (A) : (B))
+#define	max(A,B)		((A) > (B) ? (A) : (B))
+
+enum pmcstat_state {
+	PMCSTAT_FINISHED = 0,
+	PMCSTAT_EXITING  = 1,
+	PMCSTAT_RUNNING  = 2
+};
+
+struct pmcstat_ev {
+	STAILQ_ENTRY(pmcstat_ev) ev_next;
+	int		ev_count; /* associated count if in sampling mode */
+	uint32_t	ev_cpu;	  /* cpus for this event */
+	int		ev_cumulative;  /* show cumulative counts */
+	int		ev_flags; /* PMC_F_* */
+	int		ev_fieldskip;   /* #leading spaces */
+	int		ev_fieldwidth;  /* print width */
+	enum pmc_mode	ev_mode;  /* desired mode */
+	char	       *ev_name;  /* (derived) event name */
+	pmc_id_t	ev_pmcid; /* allocated ID */
+	pmc_value_t	ev_saved; /* for incremental counts */
+	char	       *ev_spec;  /* event specification */
+};
+
+struct pmcstat_target {
+	SLIST_ENTRY(pmcstat_target) pt_next;
+	pid_t		pt_pid;
+};
+
+struct pmcstat_args {
+	int	pa_flags;		/* argument flags */
+	int	pa_required;		/* required features */
+	int	pa_pplugin;		/* pre-processing plugin */
+	int	pa_plugin;		/* analysis plugin */
+	int	pa_verbosity;		/* verbosity level */
+	FILE	*pa_printfile;		/* where to send printed output */
+	int	pa_logfd;		/* output log file */
+	char	*pa_inputpath;		/* path to input log */
+	char	*pa_outputpath;		/* path to output log */
+	void	*pa_logparser;		/* log file parser */
+	const char	*pa_fsroot;	/* FS root where executables reside */
+	char	*pa_kernel;		/* pathname of the kernel */
+	const char	*pa_samplesdir;	/* directory for profile files */
+	const char	*pa_mapfilename;/* mapfile name */
+	FILE	*pa_graphfile;		/* where to send the callgraph */
+	int	pa_graphdepth;		/* print depth for callgraphs */
+	double	pa_interval;		/* printing interval in seconds */
+	uint32_t pa_cpumask;		/* filter for CPUs analysed */
+	int	pa_ctdumpinstr;		/* dump instructions with calltree */
+	int	pa_topmode;		/* delta or accumulative */
+	int	pa_toptty;		/* output to tty or file */
+	int	pa_topcolor;		/* terminal support color */
+	int	pa_mergepmc;		/* merge PMC with same name */
+	int	pa_argc;
+	char	**pa_argv;
+	STAILQ_HEAD(, pmcstat_ev) pa_events;
+	SLIST_HEAD(, pmcstat_target) pa_targets;
+};
+
+extern int pmcstat_displayheight;	/* current terminal height */
+extern int pmcstat_displaywidth;	/* current terminal width */
+extern struct pmcstat_args args;	/* command line args */
+
+/* Function prototypes */
+void	pmcstat_attach_pmcs(void);
+void	pmcstat_cleanup(void);
+void	pmcstat_clone_event_descriptor(
+    struct pmcstat_ev *_ev, uint32_t _cpumask);
+int	pmcstat_close_log(void);
+void	pmcstat_create_process(void);
+void	pmcstat_find_targets(const char *_arg);
+void	pmcstat_initialize_logging(void);
+void	pmcstat_kill_process(void);
+int	pmcstat_open_log(const char *_p, int _mode);
+void	pmcstat_print_counters(void);
+void	pmcstat_print_headers(void);
+void	pmcstat_print_pmcs(void);
+void	pmcstat_show_usage(void);
+void	pmcstat_shutdown_logging(void);
+void	pmcstat_start_pmcs(void);
+void	pmcstat_start_process(void);
+int	pmcstat_process_log(void);
+int	pmcstat_keypress_log(void);
+void	pmcstat_display_log(void);
+void	pmcstat_pluginconfigure_log(char *_opt);
+uint32_t pmcstat_get_cpumask(const char *_a);
+void    pmcstat_topexit(void);
+
+#endif	/* _PMCSTAT_H_ */
diff --git a/usr.sbin/pmcstat/pmcstat_log.c b/usr.sbin/pmcstat/pmcstat_log.c
new file mode 100644
index 0000000..374f02c
--- /dev/null
+++ b/usr.sbin/pmcstat/pmcstat_log.c
@@ -0,0 +1,2177 @@
+/*-
+ * Copyright (c) 2005-2007, Joseph Koshy
+ * Copyright (c) 2007 The FreeBSD Foundation
+ * All rights reserved.
+ *
+ * Portions of this software were developed by A. Joseph Koshy under
+ * sponsorship from the FreeBSD Foundation and Google, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * Transform a hwpmc(4) log into human readable form, and into
+ * gprof(1) compatible profiles.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: src/usr.sbin/pmcstat/pmcstat_log.c,v 1.24 2010/09/03 13:54:02 fabient Exp $");
+
+#include <sys/param.h>
+#include <sys/endian.h>
+#include <sys/gmon.h>
+#include <sys/imgact_aout.h>
+#include <sys/imgact_elf.h>
+#include <sys/mman.h>
+#include <sys/pmc.h>
+#include <sys/queue.h>
+#include <sys/socket.h>
+#include <sys/stat.h>
+#include <sys/wait.h>
+
+#include <netinet/in.h>
+
+#include <assert.h>
+#include <curses.h>
+#include <err.h>
+#include <errno.h>
+#include <fcntl.h>
+#include <gelf.h>
+#include <libgen.h>
+#include <limits.h>
+#include <netdb.h>
+#include <pmc.h>
+#include <pmclog.h>
+#include <sysexits.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+
+#include "pmcstat.h"
+#include "pmcstat_log.h"
+#include "pmcstat_top.h"
+
+#define	PMCSTAT_ALLOCATE		1
+
+/*
+ * PUBLIC INTERFACES
+ *
+ * pmcstat_initialize_logging()	initialize this module, called first
+ * pmcstat_shutdown_logging()		orderly shutdown, called last
+ * pmcstat_open_log()			open an eventlog for processing
+ * pmcstat_process_log()		print/convert an event log
+ * pmcstat_display_log()		top mode display for the log
+ * pmcstat_close_log()			finish processing an event log
+ *
+ * IMPLEMENTATION NOTES
+ *
+ * We correlate each 'callchain' or 'sample' entry seen in the event
+ * log back to an executable object in the system. Executable objects
+ * include:
+ * 	- program executables,
+ *	- shared libraries loaded by the runtime loader,
+ *	- dlopen()'ed objects loaded by the program,
+ *	- the runtime loader itself,
+ *	- the kernel and kernel modules.
+ *
+ * Each process that we know about is treated as a set of regions that
+ * map to executable objects.  Processes are described by
+ * 'pmcstat_process' structures.  Executable objects are tracked by
+ * 'pmcstat_image' structures.  The kernel and kernel modules are
+ * common to all processes (they reside at the same virtual addresses
+ * for all processes).  Individual processes can have their text
+ * segments and shared libraries loaded at process-specific locations.
+ *
+ * A given executable object can be in use by multiple processes
+ * (e.g., libc.so) and loaded at a different address in each.
+ * pmcstat_pcmap structures track per-image mappings.
+ *
+ * The sample log could have samples from multiple PMCs; we
+ * generate one 'gmon.out' profile per PMC.
+ *
+ * IMPLEMENTATION OF GMON OUTPUT
+ *
+ * Each executable object gets one 'gmon.out' profile, per PMC in
+ * use.  Creation of 'gmon.out' profiles is done lazily.  The
+ * 'gmon.out' profiles generated for a given sampling PMC are
+ * aggregates of all the samples for that particular executable
+ * object.
+ *
+ * IMPLEMENTATION OF SYSTEM-WIDE CALLGRAPH OUTPUT
+ *
+ * Each active pmcid has its own callgraph structure, described by a
+ * 'struct pmcstat_callgraph'.  Given a process id and a list of pc
+ * values, we map each pc value to a tuple (image, symbol), where
+ * 'image' denotes an executable object and 'symbol' is the closest
+ * symbol that precedes the pc value.  Each pc value in the list is
+ * also given a 'rank' that reflects its depth in the call stack.
+ */
+
+struct pmcstat_pmcs pmcstat_pmcs = LIST_HEAD_INITIALIZER(pmcstat_pmcs);
+
+/*
+ * All image descriptors are kept in a hash table.
+ */
+struct pmcstat_image_hash_list pmcstat_image_hash[PMCSTAT_NHASH];
+
+/*
+ * All process descriptors are kept in a hash table.
+ */
+struct pmcstat_process_hash_list pmcstat_process_hash[PMCSTAT_NHASH];
+
+struct pmcstat_stats pmcstat_stats; /* statistics */
+int ps_samples_period; /* samples count between top refresh. */
+
+struct pmcstat_process *pmcstat_kernproc; /* kernel 'process' */
+
+#include "pmcpl_gprof.h"
+#include "pmcpl_callgraph.h"
+#include "pmcpl_annotate.h"
+#include "pmcpl_calltree.h"
+
+struct pmc_plugins  {
+	const char 	*pl_name;	/* name */
+
+	/* configure */
+	int (*pl_configure)(char *opt);
+
+	/* init and shutdown */
+	int (*pl_init)(void);
+	void (*pl_shutdown)(FILE *mf);
+
+	/* sample processing */
+	void (*pl_process)(struct pmcstat_process *pp,
+	    struct pmcstat_pmcrecord *pmcr, uint32_t nsamples,
+	    uintfptr_t *cc, int usermode, uint32_t cpu);
+
+	/* image */
+	void (*pl_initimage)(struct pmcstat_image *pi);
+	void (*pl_shutdownimage)(struct pmcstat_image *pi);
+
+	/* pmc */
+	void (*pl_newpmc)(pmcstat_interned_string ps,
+		struct pmcstat_pmcrecord *pr);
+
+	/* top display */
+	void (*pl_topdisplay)(void);
+
+	/* top keypress */
+	int (*pl_topkeypress)(int c, WINDOW *w);
+
+} plugins[] = {
+	{
+		.pl_name		= "none",
+	},
+	{
+		.pl_name		= "callgraph",
+		.pl_init		= pmcpl_cg_init,
+		.pl_shutdown		= pmcpl_cg_shutdown,
+		.pl_process		= pmcpl_cg_process,
+		.pl_topkeypress		= pmcpl_cg_topkeypress,
+		.pl_topdisplay		= pmcpl_cg_topdisplay
+	},
+	{
+		.pl_name		= "gprof",
+		.pl_shutdown		= pmcpl_gmon_shutdown,
+		.pl_process		= pmcpl_gmon_process,
+		.pl_initimage		= pmcpl_gmon_initimage,
+		.pl_shutdownimage	= pmcpl_gmon_shutdownimage,
+		.pl_newpmc		= pmcpl_gmon_newpmc
+	},
+	{
+		.pl_name		= "annotate",
+		.pl_process		= pmcpl_annotate_process
+	},
+	{
+		.pl_name		= "calltree",
+		.pl_configure		= pmcpl_ct_configure,
+		.pl_init		= pmcpl_ct_init,
+		.pl_shutdown		= pmcpl_ct_shutdown,
+		.pl_process		= pmcpl_ct_process,
+		.pl_topkeypress		= pmcpl_ct_topkeypress,
+		.pl_topdisplay		= pmcpl_ct_topdisplay
+	},
+	{
+		.pl_name		= NULL
+	}
+};
+
+int pmcstat_mergepmc;
+
+int pmcstat_pmcinfilter = 0; /* PMC filter for top mode. */
+float pmcstat_threshold = 0.5; /* Cost filter for top mode. */
+
+/*
+ * Prototypes
+ */
+
+static struct pmcstat_image *pmcstat_image_from_path(pmcstat_interned_string
+    _path, int _iskernelmodule);
+static void pmcstat_image_get_aout_params(struct pmcstat_image *_image);
+static void pmcstat_image_get_elf_params(struct pmcstat_image *_image);
+static void	pmcstat_image_link(struct pmcstat_process *_pp,
+    struct pmcstat_image *_i, uintfptr_t _lpc);
+
+static void	pmcstat_pmcid_add(pmc_id_t _pmcid,
+    pmcstat_interned_string _name);
+
+static void	pmcstat_process_aout_exec(struct pmcstat_process *_pp,
+    struct pmcstat_image *_image, uintfptr_t _entryaddr);
+static void	pmcstat_process_elf_exec(struct pmcstat_process *_pp,
+    struct pmcstat_image *_image, uintfptr_t _entryaddr);
+static void	pmcstat_process_exec(struct pmcstat_process *_pp,
+    pmcstat_interned_string _path, uintfptr_t _entryaddr);
+static struct pmcstat_process *pmcstat_process_lookup(pid_t _pid,
+    int _allocate);
+static int	pmcstat_string_compute_hash(const char *_string);
+static void pmcstat_string_initialize(void);
+static int	pmcstat_string_lookup_hash(pmcstat_interned_string _is);
+static void pmcstat_string_shutdown(void);
+static void pmcstat_stats_reset(int _reset_global);
+
+/*
+ * A simple implementation of interned strings.  Each interned string
+ * is assigned a unique address, so that subsequent string compares
+ * can be done by a simple pointer comparision instead of using
+ * strcmp().  This speeds up hash table lookups and saves memory if
+ * duplicate strings are the norm.
+ */
+struct pmcstat_string {
+	LIST_ENTRY(pmcstat_string)	ps_next;	/* hash link */
+	int		ps_len;
+	int		ps_hash;
+	char		*ps_string;
+};
+
+static LIST_HEAD(,pmcstat_string)	pmcstat_string_hash[PMCSTAT_NHASH];
+
+/*
+ * PMC count.
+ */
+int pmcstat_npmcs;
+
+/*
+ * PMC Top mode pause state.
+ */
+int pmcstat_pause;
+
+static void
+pmcstat_stats_reset(int reset_global)
+{
+	struct pmcstat_pmcrecord *pr;
+
+	/* Flush PMCs stats. */
+	LIST_FOREACH(pr, &pmcstat_pmcs, pr_next) {
+		pr->pr_samples = 0;
+		pr->pr_dubious_frames = 0;
+	}
+	ps_samples_period = 0;
+
+	/* Flush global stats. */
+	if (reset_global)
+		bzero(&pmcstat_stats, sizeof(struct pmcstat_stats));
+}
+
+/*
+ * Compute a 'hash' value for a string.
+ */
+
+static int
+pmcstat_string_compute_hash(const char *s)
+{
+	int hash;
+
+	for (hash = 0; *s; s++)
+		hash ^= *s;
+
+	return (hash & PMCSTAT_HASH_MASK);
+}
+
+/*
+ * Intern a copy of string 's', and return a pointer to the
+ * interned structure.
+ */
+
+pmcstat_interned_string
+pmcstat_string_intern(const char *s)
+{
+	struct pmcstat_string *ps;
+	const struct pmcstat_string *cps;
+	int hash, len;
+
+	if ((cps = pmcstat_string_lookup(s)) != NULL)
+		return (cps);
+
+	hash = pmcstat_string_compute_hash(s);
+	len  = strlen(s);
+
+	if ((ps = malloc(sizeof(*ps))) == NULL)
+		err(EX_OSERR, "ERROR: Could not intern string");
+	ps->ps_len = len;
+	ps->ps_hash = hash;
+	ps->ps_string = strdup(s);
+	LIST_INSERT_HEAD(&pmcstat_string_hash[hash], ps, ps_next);
+	return ((pmcstat_interned_string) ps);
+}
+
+const char *
+pmcstat_string_unintern(pmcstat_interned_string str)
+{
+	const char *s;
+
+	s = ((const struct pmcstat_string *) str)->ps_string;
+	return (s);
+}
+
+pmcstat_interned_string
+pmcstat_string_lookup(const char *s)
+{
+	struct pmcstat_string *ps;
+	int hash, len;
+
+	hash = pmcstat_string_compute_hash(s);
+	len = strlen(s);
+
+	LIST_FOREACH(ps, &pmcstat_string_hash[hash], ps_next)
+	    if (ps->ps_len == len && ps->ps_hash == hash &&
+		strcmp(ps->ps_string, s) == 0)
+		    return (ps);
+	return (NULL);
+}
+
+static int
+pmcstat_string_lookup_hash(pmcstat_interned_string s)
+{
+	const struct pmcstat_string *ps;
+
+	ps = (const struct pmcstat_string *) s;
+	return (ps->ps_hash);
+}
+
+/*
+ * Initialize the string interning facility.
+ */
+
+static void
+pmcstat_string_initialize(void)
+{
+	int i;
+
+	for (i = 0; i < PMCSTAT_NHASH; i++)
+		LIST_INIT(&pmcstat_string_hash[i]);
+}
+
+/*
+ * Destroy the string table, free'ing up space.
+ */
+
+static void
+pmcstat_string_shutdown(void)
+{
+	int i;
+	struct pmcstat_string *ps, *pstmp;
+
+	for (i = 0; i < PMCSTAT_NHASH; i++)
+		LIST_FOREACH_SAFE(ps, &pmcstat_string_hash[i], ps_next,
+		    pstmp) {
+			LIST_REMOVE(ps, ps_next);
+			free(ps->ps_string);
+			free(ps);
+		}
+}
+
+/*
+ * Determine whether a given executable image is an A.OUT object, and
+ * if so, fill in its parameters from the text file.
+ * Sets image->pi_type.
+ */
+
+static void
+pmcstat_image_get_aout_params(struct pmcstat_image *image)
+{
+	int fd;
+	ssize_t nbytes;
+	struct exec ex;
+	const char *path;
+	char buffer[PATH_MAX];
+
+	path = pmcstat_string_unintern(image->pi_execpath);
+	assert(path != NULL);
+
+	if (image->pi_iskernelmodule)
+		errx(EX_SOFTWARE, "ERROR: a.out kernel modules are "
+		    "unsupported \"%s\"", path);
+
+	(void) snprintf(buffer, sizeof(buffer), "%s%s",
+	    args.pa_fsroot, path);
+
+	if ((fd = open(buffer, O_RDONLY, 0)) < 0 ||
+	    (nbytes = read(fd, &ex, sizeof(ex))) < 0) {
+		warn("WARNING: Cannot determine type of \"%s\"", path);
+		image->pi_type = PMCSTAT_IMAGE_INDETERMINABLE;
+		if (fd != -1)
+			(void) close(fd);
+		return;
+	}
+
+	(void) close(fd);
+
+	if ((unsigned) nbytes != sizeof(ex) ||
+	    N_BADMAG(ex))
+		return;
+
+	image->pi_type = PMCSTAT_IMAGE_AOUT;
+
+	/* TODO: the rest of a.out processing */
+
+	return;
+}
+
+/*
+ * Helper function.
+ */
+
+static int
+pmcstat_symbol_compare(const void *a, const void *b)
+{
+	const struct pmcstat_symbol *sym1, *sym2;
+
+	sym1 = (const struct pmcstat_symbol *) a;
+	sym2 = (const struct pmcstat_symbol *) b;
+
+	if (sym1->ps_end <= sym2->ps_start)
+		return (-1);
+	if (sym1->ps_start >= sym2->ps_end)
+		return (1);
+	return (0);
+}
+
+/*
+ * Map an address to a symbol in an image.
+ */
+
+struct pmcstat_symbol *
+pmcstat_symbol_search(struct pmcstat_image *image, uintfptr_t addr)
+{
+	struct pmcstat_symbol sym;
+
+	if (image->pi_symbols == NULL)
+		return (NULL);
+
+	sym.ps_name  = NULL;
+	sym.ps_start = addr;
+	sym.ps_end   = addr + 1;
+
+	return (bsearch((void *) &sym, image->pi_symbols,
+		    image->pi_symcount, sizeof(struct pmcstat_symbol),
+		    pmcstat_symbol_compare));
+}
+
+/*
+ * Add the list of symbols in the given section to the list associated
+ * with the object.
+ */
+static void
+pmcstat_image_add_symbols(struct pmcstat_image *image, Elf *e,
+    Elf_Scn *scn, GElf_Shdr *sh)
+{
+	int firsttime;
+	size_t n, newsyms, nshsyms, nfuncsyms;
+	struct pmcstat_symbol *symptr;
+	char *fnname;
+	GElf_Sym sym;
+	Elf_Data *data;
+
+	if ((data = elf_getdata(scn, NULL)) == NULL)
+		return;
+
+	/*
+	 * Determine the number of functions named in this
+	 * section.
+	 */
+
+	nshsyms = sh->sh_size / sh->sh_entsize;
+	for (n = nfuncsyms = 0; n < nshsyms; n++) {
+		if (gelf_getsym(data, (int) n, &sym) != &sym)
+			return;
+		if (GELF_ST_TYPE(sym.st_info) == STT_FUNC)
+			nfuncsyms++;
+	}
+
+	if (nfuncsyms == 0)
+		return;
+
+	/*
+	 * Allocate space for the new entries.
+	 */
+	firsttime = image->pi_symbols == NULL;
+	symptr = realloc(image->pi_symbols,
+	    sizeof(*symptr) * (image->pi_symcount + nfuncsyms));
+	if (symptr == image->pi_symbols) /* realloc() failed. */
+		return;
+	image->pi_symbols = symptr;
+
+	/*
+	 * Append new symbols to the end of the current table.
+	 */
+	symptr += image->pi_symcount;
+
+	for (n = newsyms = 0; n < nshsyms; n++) {
+		if (gelf_getsym(data, (int) n, &sym) != &sym)
+			return;
+		if (GELF_ST_TYPE(sym.st_info) != STT_FUNC)
+			continue;
+		if (sym.st_shndx == STN_UNDEF)
+			continue;
+
+		if (!firsttime && pmcstat_symbol_search(image, sym.st_value))
+			continue; /* We've seen this symbol already. */
+
+		if ((fnname = elf_strptr(e, sh->sh_link, sym.st_name))
+		    == NULL)
+			continue;
+
+		symptr->ps_name  = pmcstat_string_intern(fnname);
+		symptr->ps_start = sym.st_value - image->pi_vaddr;
+		symptr->ps_end   = symptr->ps_start + sym.st_size;
+		symptr++;
+
+		newsyms++;
+	}
+
+	image->pi_symcount += newsyms;
+
+	assert(newsyms <= nfuncsyms);
+
+	/*
+	 * Return space to the system if there were duplicates.
+	 */
+	if (newsyms < nfuncsyms)
+		image->pi_symbols = realloc(image->pi_symbols,
+		    sizeof(*symptr) * image->pi_symcount);
+
+	/*
+	 * Keep the list of symbols sorted.
+	 */
+	qsort(image->pi_symbols, image->pi_symcount, sizeof(*symptr),
+	    pmcstat_symbol_compare);
+
+	/*
+	 * Deal with function symbols that have a size of 'zero' by
+	 * making them extend to the next higher address.  These
+	 * symbols are usually defined in assembly code.
+	 */
+	for (symptr = image->pi_symbols;
+	     symptr < image->pi_symbols + (image->pi_symcount - 1);
+	     symptr++)
+		if (symptr->ps_start == symptr->ps_end)
+			symptr->ps_end = (symptr+1)->ps_start;
+}
+
+/*
+ * Examine an ELF file to determine the size of its text segment.
+ * Sets image->pi_type if anything conclusive can be determined about
+ * this image.
+ */
+
+static void
+pmcstat_image_get_elf_params(struct pmcstat_image *image)
+{
+	int fd;
+	size_t i, nph, nsh;
+	const char *path, *elfbase;
+	char *p, *endp;
+	uintfptr_t minva, maxva;
+	Elf *e;
+	Elf_Scn *scn;
+	GElf_Ehdr eh;
+	GElf_Phdr ph;
+	GElf_Shdr sh;
+	enum pmcstat_image_type image_type;
+	char buffer[PATH_MAX];
+
+	assert(image->pi_type == PMCSTAT_IMAGE_UNKNOWN);
+
+	image->pi_start = minva = ~(uintfptr_t) 0;
+	image->pi_end = maxva = (uintfptr_t) 0;
+	image->pi_type = image_type = PMCSTAT_IMAGE_INDETERMINABLE;
+	image->pi_isdynamic = 0;
+	image->pi_dynlinkerpath = NULL;
+	image->pi_vaddr = 0;
+
+	path = pmcstat_string_unintern(image->pi_execpath);
+	assert(path != NULL);
+
+	/*
+	 * Look for kernel modules under FSROOT/KERNELPATH/NAME,
+	 * and user mode executable objects under FSROOT/PATHNAME.
+	 */
+	if (image->pi_iskernelmodule)
+		(void) snprintf(buffer, sizeof(buffer), "%s%s/%s",
+		    args.pa_fsroot, args.pa_kernel, path);
+	else
+		(void) snprintf(buffer, sizeof(buffer), "%s%s",
+		    args.pa_fsroot, path);
+
+	e = NULL;
+	if ((fd = open(buffer, O_RDONLY, 0)) < 0 ||
+	    (e = elf_begin(fd, ELF_C_READ, NULL)) == NULL ||
+	    (elf_kind(e) != ELF_K_ELF)) {
+		warnx("WARNING: Cannot determine the type of \"%s\".",
+		    buffer);
+		goto done;
+	}
+
+	if (gelf_getehdr(e, &eh) != &eh) {
+		warnx("WARNING: Cannot retrieve the ELF Header for "
+		    "\"%s\": %s.", buffer, elf_errmsg(-1));
+		goto done;
+	}
+
+	if (eh.e_type != ET_EXEC && eh.e_type != ET_DYN &&
+	    !(image->pi_iskernelmodule && eh.e_type == ET_REL)) {
+		warnx("WARNING: \"%s\" is of an unsupported ELF type.",
+		    buffer);
+		goto done;
+	}
+
+	image_type = eh.e_ident[EI_CLASS] == ELFCLASS32 ?
+	    PMCSTAT_IMAGE_ELF32 : PMCSTAT_IMAGE_ELF64;
+
+	/*
+	 * Determine the virtual address where an executable would be
+	 * loaded.  Additionally, for dynamically linked executables,
+	 * save the pathname to the runtime linker.
+	 */
+	if (eh.e_type == ET_EXEC) {
+		if (elf_getphnum(e, &nph) == 0) {
+			warnx("WARNING: Could not determine the number of "
+			    "program headers in \"%s\": %s.", buffer,
+			    elf_errmsg(-1));
+			goto done;
+		}
+		for (i = 0; i < eh.e_phnum; i++) {
+			if (gelf_getphdr(e, i, &ph) != &ph) {
+				warnx("WARNING: Retrieval of PHDR entry #%ju "
+				    "in \"%s\" failed: %s.", (uintmax_t) i,
+				    buffer, elf_errmsg(-1));
+				goto done;
+			}
+			switch (ph.p_type) {
+			case PT_DYNAMIC:
+				image->pi_isdynamic = 1;
+				break;
+			case PT_INTERP:
+				if ((elfbase = elf_rawfile(e, NULL)) == NULL) {
+					warnx("WARNING: Cannot retrieve the "
+					    "interpreter for \"%s\": %s.",
+					    buffer, elf_errmsg(-1));
+					goto done;
+				}
+				image->pi_dynlinkerpath =
+				    pmcstat_string_intern(elfbase +
+				        ph.p_offset);
+				break;
+			case PT_LOAD:
+				if (ph.p_offset == 0)
+					image->pi_vaddr = ph.p_vaddr;
+				break;
+			}
+		}
+	}
+
+	/*
+	 * Get the min and max VA associated with this ELF object.
+	 */
+	if (elf_getshnum(e, &nsh) == 0) {
+		warnx("WARNING: Could not determine the number of sections "
+		    "for \"%s\": %s.", buffer, elf_errmsg(-1));
+		goto done;
+	}
+
+	for (i = 0; i < nsh; i++) {
+		if ((scn = elf_getscn(e, i)) == NULL ||
+		    gelf_getshdr(scn, &sh) != &sh) {
+			warnx("WARNING: Could not retrieve section header "
+			    "#%ju in \"%s\": %s.", (uintmax_t) i, buffer,
+			    elf_errmsg(-1));
+			goto done;
+		}
+		if (sh.sh_flags & SHF_EXECINSTR) {
+			minva = min(minva, sh.sh_addr);
+			maxva = max(maxva, sh.sh_addr + sh.sh_size);
+		}
+		if (sh.sh_type == SHT_SYMTAB || sh.sh_type == SHT_DYNSYM)
+			pmcstat_image_add_symbols(image, e, scn, &sh);
+	}
+
+	image->pi_start = minva;
+	image->pi_end   = maxva;
+	image->pi_type  = image_type;
+	image->pi_fullpath = pmcstat_string_intern(buffer);
+
+	/* Build display name
+	 */
+	endp = buffer;
+	for (p = buffer; *p; p++)
+		if (*p == '/')
+			endp = p+1;
+	image->pi_name = pmcstat_string_intern(endp);
+
+ done:
+	(void) elf_end(e);
+	if (fd >= 0)
+		(void) close(fd);
+	return;
+}
+
+/*
+ * Given an image descriptor, determine whether it is an ELF, or AOUT.
+ * If no handler claims the image, set its type to 'INDETERMINABLE'.
+ */
+
+void
+pmcstat_image_determine_type(struct pmcstat_image *image)
+{
+	assert(image->pi_type == PMCSTAT_IMAGE_UNKNOWN);
+
+	/* Try each kind of handler in turn */
+	if (image->pi_type == PMCSTAT_IMAGE_UNKNOWN)
+		pmcstat_image_get_elf_params(image);
+	if (image->pi_type == PMCSTAT_IMAGE_UNKNOWN)
+		pmcstat_image_get_aout_params(image);
+
+	/*
+	 * Otherwise, remember that we tried to determine
+	 * the object's type and had failed.
+	 */
+	if (image->pi_type == PMCSTAT_IMAGE_UNKNOWN)
+		image->pi_type = PMCSTAT_IMAGE_INDETERMINABLE;
+}
+
+/*
+ * Locate an image descriptor given an interned path, adding a fresh
+ * descriptor to the cache if necessary.  This function also finds a
+ * suitable name for this image's sample file.
+ *
+ * We defer filling in the file format specific parts of the image
+ * structure till the time we actually see a sample that would fall
+ * into this image.
+ */
+
+static struct pmcstat_image *
+pmcstat_image_from_path(pmcstat_interned_string internedpath,
+    int iskernelmodule)
+{
+	int hash;
+	struct pmcstat_image *pi;
+
+	hash = pmcstat_string_lookup_hash(internedpath);
+
+	/* First, look for an existing entry. */
+	LIST_FOREACH(pi, &pmcstat_image_hash[hash], pi_next)
+	    if (pi->pi_execpath == internedpath &&
+		  pi->pi_iskernelmodule == iskernelmodule)
+		    return (pi);
+
+	/*
+	 * Allocate a new entry and place it at the head of the hash
+	 * and LRU lists.
+	 */
+	pi = malloc(sizeof(*pi));
+	if (pi == NULL)
+		return (NULL);
+
+	pi->pi_type = PMCSTAT_IMAGE_UNKNOWN;
+	pi->pi_execpath = internedpath;
+	pi->pi_start = ~0;
+	pi->pi_end = 0;
+	pi->pi_entry = 0;
+	pi->pi_vaddr = 0;
+	pi->pi_isdynamic = 0;
+	pi->pi_iskernelmodule = iskernelmodule;
+	pi->pi_dynlinkerpath = NULL;
+	pi->pi_symbols = NULL;
+	pi->pi_symcount = 0;
+	pi->pi_addr2line = NULL;
+
+	if (plugins[args.pa_pplugin].pl_initimage != NULL)
+		plugins[args.pa_pplugin].pl_initimage(pi);
+	if (plugins[args.pa_plugin].pl_initimage != NULL)
+		plugins[args.pa_plugin].pl_initimage(pi);
+
+	LIST_INSERT_HEAD(&pmcstat_image_hash[hash], pi, pi_next);
+
+	return (pi);
+}
+
+/*
+ * Record the fact that PC values from 'start' to 'end' come from
+ * image 'image'.
+ */
+
+static void
+pmcstat_image_link(struct pmcstat_process *pp, struct pmcstat_image *image,
+    uintfptr_t start)
+{
+	struct pmcstat_pcmap *pcm, *pcmnew;
+	uintfptr_t offset;
+
+	assert(image->pi_type != PMCSTAT_IMAGE_UNKNOWN &&
+	    image->pi_type != PMCSTAT_IMAGE_INDETERMINABLE);
+
+	if ((pcmnew = malloc(sizeof(*pcmnew))) == NULL)
+		err(EX_OSERR, "ERROR: Cannot create a map entry");
+
+	/*
+	 * Adjust the map entry to only cover the text portion
+	 * of the object.
+	 */
+
+	offset = start - image->pi_vaddr;
+	pcmnew->ppm_lowpc  = image->pi_start + offset;
+	pcmnew->ppm_highpc = image->pi_end + offset;
+	pcmnew->ppm_image  = image;
+
+	assert(pcmnew->ppm_lowpc < pcmnew->ppm_highpc);
+
+	/* Overlapped mmap()'s are assumed to never occur. */
+	TAILQ_FOREACH(pcm, &pp->pp_map, ppm_next)
+	    if (pcm->ppm_lowpc >= pcmnew->ppm_highpc)
+		    break;
+
+	if (pcm == NULL)
+		TAILQ_INSERT_TAIL(&pp->pp_map, pcmnew, ppm_next);
+	else
+		TAILQ_INSERT_BEFORE(pcm, pcmnew, ppm_next);
+}
+
+/*
+ * Unmap images in the range [start..end) associated with process
+ * 'pp'.
+ */
+
+static void
+pmcstat_image_unmap(struct pmcstat_process *pp, uintfptr_t start,
+    uintfptr_t end)
+{
+	struct pmcstat_pcmap *pcm, *pcmtmp, *pcmnew;
+
+	assert(pp != NULL);
+	assert(start < end);
+
+	/*
+	 * Cases:
+	 * - we could have the range completely in the middle of an
+	 *   existing pcmap; in this case we have to split the pcmap
+	 *   structure into two (i.e., generate a 'hole').
+	 * - we could have the range covering multiple pcmaps; these
+	 *   will have to be removed.
+	 * - we could have either 'start' or 'end' falling in the
+	 *   middle of a pcmap; in this case shorten the entry.
+	 */
+	TAILQ_FOREACH_SAFE(pcm, &pp->pp_map, ppm_next, pcmtmp) {
+		assert(pcm->ppm_lowpc < pcm->ppm_highpc);
+		if (pcm->ppm_highpc <= start)
+			continue;
+		if (pcm->ppm_lowpc >= end)
+			return;
+		if (pcm->ppm_lowpc >= start && pcm->ppm_highpc <= end) {
+			/*
+			 * The current pcmap is completely inside the
+			 * unmapped range: remove it entirely.
+			 */
+			TAILQ_REMOVE(&pp->pp_map, pcm, ppm_next);
+			free(pcm);
+		} else if (pcm->ppm_lowpc < start && pcm->ppm_highpc > end) {
+			/*
+			 * Split this pcmap into two; curtail the
+			 * current map to end at [start-1], and start
+			 * the new one at [end].
+			 */
+			if ((pcmnew = malloc(sizeof(*pcmnew))) == NULL)
+				err(EX_OSERR, "ERROR: Cannot split a map "
+				    "entry");
+
+			pcmnew->ppm_image = pcm->ppm_image;
+
+			pcmnew->ppm_lowpc = end;
+			pcmnew->ppm_highpc = pcm->ppm_highpc;
+
+			pcm->ppm_highpc = start;
+
+			TAILQ_INSERT_AFTER(&pp->pp_map, pcm, pcmnew, ppm_next);
+
+			return;
+		} else if (pcm->ppm_lowpc < start && pcm->ppm_highpc <= end)
+			pcm->ppm_highpc = start;
+		else if (pcm->ppm_lowpc >= start && pcm->ppm_highpc > end)
+			pcm->ppm_lowpc = end;
+		else
+			assert(0);
+	}
+}
+
+/*
+ * Resolve file name and line number for the given address.
+ */
+int
+pmcstat_image_addr2line(struct pmcstat_image *image, uintfptr_t addr,
+    char *sourcefile, size_t sourcefile_len, unsigned *sourceline,
+    char *funcname, size_t funcname_len)
+{
+	static int addr2line_warn = 0;
+
+	char *sep, cmdline[PATH_MAX], imagepath[PATH_MAX];
+	int fd;
+
+	if (image->pi_addr2line == NULL) {
+		snprintf(imagepath, sizeof(imagepath), "%s%s.symbols",
+		    args.pa_fsroot,
+		    pmcstat_string_unintern(image->pi_fullpath));
+		fd = open(imagepath, O_RDONLY);
+		if (fd < 0) {
+			snprintf(imagepath, sizeof(imagepath), "%s%s",
+			    args.pa_fsroot,
+			    pmcstat_string_unintern(image->pi_fullpath));
+		} else
+			close(fd);
+		snprintf(cmdline, sizeof(cmdline), "addr2line -Cfe \"%s\"",
+		    imagepath);
+		image->pi_addr2line = popen(cmdline, "r+");
+		if (image->pi_addr2line == NULL) {
+			if (!addr2line_warn) {
+				addr2line_warn = 1;
+				warnx("WARNING: addr2line is needed"
+				    "for source code information.");
+			}
+			return (0);
+		}
+	}
+
+	if (feof(image->pi_addr2line) || ferror(image->pi_addr2line)) {
+		warnx("WARNING: addr2line pipe error");
+		pclose(image->pi_addr2line);
+		image->pi_addr2line = NULL;
+		return (0);
+	}
+
+	fprintf(image->pi_addr2line, "%p\n", (void *)addr);
+
+	if (fgets(funcname, funcname_len, image->pi_addr2line) == NULL) {
+		warnx("WARNING: addr2line function name read error");
+		return (0);
+	}
+	sep = strchr(funcname, '\n');
+	if (sep != NULL)
+		*sep = '\0';
+
+	if (fgets(sourcefile, sourcefile_len, image->pi_addr2line) == NULL) {
+		warnx("WARNING: addr2line source file read error");
+		return (0);
+	}
+	sep = strchr(sourcefile, ':');
+	if (sep == NULL) {
+		warnx("WARNING: addr2line source line separator missing");
+		return (0);
+	}
+	*sep = '\0';
+	*sourceline = atoi(sep+1);
+	if (*sourceline == 0)
+		return (0);
+
+	return (1);
+}
+
+/*
+ * Add a {pmcid,name} mapping.
+ */
+
+static void
+pmcstat_pmcid_add(pmc_id_t pmcid, pmcstat_interned_string ps)
+{
+	struct pmcstat_pmcrecord *pr, *prm;
+
+	/* Replace an existing name for the PMC. */
+	prm = NULL;
+	LIST_FOREACH(pr, &pmcstat_pmcs, pr_next)
+		if (pr->pr_pmcid == pmcid) {
+			pr->pr_pmcname = ps;
+			return;
+		} else if (pr->pr_pmcname == ps)
+			prm = pr;
+
+	/*
+	 * Otherwise, allocate a new descriptor and call the
+	 * plugins hook.
+	 */
+	if ((pr = malloc(sizeof(*pr))) == NULL)
+		err(EX_OSERR, "ERROR: Cannot allocate pmc record");
+
+	pr->pr_pmcid = pmcid;
+	pr->pr_pmcname = ps;
+	pr->pr_pmcin = pmcstat_npmcs++;
+	pr->pr_samples = 0;
+	pr->pr_dubious_frames = 0;
+	pr->pr_merge = prm == NULL ? pr : prm;
+
+	LIST_INSERT_HEAD(&pmcstat_pmcs, pr, pr_next);
+
+	if (plugins[args.pa_pplugin].pl_newpmc != NULL)
+		plugins[args.pa_pplugin].pl_newpmc(ps, pr);
+	if (plugins[args.pa_plugin].pl_newpmc != NULL)
+		plugins[args.pa_plugin].pl_newpmc(ps, pr);
+}
+
+/*
+ * Given a pmcid in use, find its human-readable name.
+ */
+
+const char *
+pmcstat_pmcid_to_name(pmc_id_t pmcid)
+{
+	struct pmcstat_pmcrecord *pr;
+
+	LIST_FOREACH(pr, &pmcstat_pmcs, pr_next)
+	    if (pr->pr_pmcid == pmcid)
+		    return (pmcstat_string_unintern(pr->pr_pmcname));
+
+	return NULL;
+}
+
+/*
+ * Convert PMC index to name.
+ */
+
+const char *
+pmcstat_pmcindex_to_name(int pmcin)
+{
+	struct pmcstat_pmcrecord *pr;
+
+	LIST_FOREACH(pr, &pmcstat_pmcs, pr_next)
+		if (pr->pr_pmcin == pmcin)
+			return pmcstat_string_unintern(pr->pr_pmcname);
+
+	return NULL;
+}
+
+/*
+ * Return PMC record with given index.
+ */
+
+struct pmcstat_pmcrecord *
+pmcstat_pmcindex_to_pmcr(int pmcin)
+{
+	struct pmcstat_pmcrecord *pr;
+
+	LIST_FOREACH(pr, &pmcstat_pmcs, pr_next)
+		if (pr->pr_pmcin == pmcin)
+			return pr;
+
+	return NULL;
+}
+
+/*
+ * Get PMC record by id, apply merge policy.
+ */
+
+static struct pmcstat_pmcrecord *
+pmcstat_lookup_pmcid(pmc_id_t pmcid)
+{
+	struct pmcstat_pmcrecord *pr;
+
+	LIST_FOREACH(pr, &pmcstat_pmcs, pr_next) {
+		if (pr->pr_pmcid == pmcid) {
+			if (pmcstat_mergepmc)
+				return pr->pr_merge;
+			return pr;
+		}
+	}
+
+	return NULL;
+}
+
+/*
+ * Associate an AOUT image with a process.
+ */
+
+static void
+pmcstat_process_aout_exec(struct pmcstat_process *pp,
+    struct pmcstat_image *image, uintfptr_t entryaddr)
+{
+	(void) pp;
+	(void) image;
+	(void) entryaddr;
+	/* TODO Implement a.out handling */
+}
+
+/*
+ * Associate an ELF image with a process.
+ */
+
+static void
+pmcstat_process_elf_exec(struct pmcstat_process *pp,
+    struct pmcstat_image *image, uintfptr_t entryaddr)
+{
+	uintmax_t libstart;
+	struct pmcstat_image *rtldimage;
+
+	assert(image->pi_type == PMCSTAT_IMAGE_ELF32 ||
+	    image->pi_type == PMCSTAT_IMAGE_ELF64);
+
+	/* Create a map entry for the base executable. */
+	pmcstat_image_link(pp, image, image->pi_vaddr);
+
+	/*
+	 * For dynamically linked executables we need to determine
+	 * where the dynamic linker was mapped to for this process,
+	 * Subsequent executable objects that are mapped in by the
+	 * dynamic linker will be tracked by log events of type
+	 * PMCLOG_TYPE_MAP_IN.
+	 */
+
+	if (image->pi_isdynamic) {
+
+		/*
+		 * The runtime loader gets loaded just after the maximum
+		 * possible heap address.  Like so:
+		 *
+		 * [  TEXT DATA BSS HEAP -->*RTLD  SHLIBS   <--STACK]
+		 * ^					            ^
+		 * 0				   VM_MAXUSER_ADDRESS
+
+		 *
+		 * The exact address where the loader gets mapped in
+		 * will vary according to the size of the executable
+		 * and the limits on the size of the process'es data
+		 * segment at the time of exec().  The entry address
+		 * recorded at process exec time corresponds to the
+		 * 'start' address inside the dynamic linker.  From
+		 * this we can figure out the address where the
+		 * runtime loader's file object had been mapped to.
+		 */
+		rtldimage = pmcstat_image_from_path(image->pi_dynlinkerpath, 0);
+		if (rtldimage == NULL) {
+			warnx("WARNING: Cannot find image for \"%s\".",
+			    pmcstat_string_unintern(image->pi_dynlinkerpath));
+			pmcstat_stats.ps_exec_errors++;
+			return;
+		}
+
+		if (rtldimage->pi_type == PMCSTAT_IMAGE_UNKNOWN)
+			pmcstat_image_get_elf_params(rtldimage);
+
+		if (rtldimage->pi_type != PMCSTAT_IMAGE_ELF32 &&
+		    rtldimage->pi_type != PMCSTAT_IMAGE_ELF64) {
+			warnx("WARNING: rtld not an ELF object \"%s\".",
+			    pmcstat_string_unintern(image->pi_dynlinkerpath));
+			return;
+		}
+
+		libstart = entryaddr - rtldimage->pi_entry;
+		pmcstat_image_link(pp, rtldimage, libstart);
+	}
+}
+
+/*
+ * Find the process descriptor corresponding to a PID.  If 'allocate'
+ * is zero, we return a NULL if a pid descriptor could not be found or
+ * a process descriptor process.  If 'allocate' is non-zero, then we
+ * will attempt to allocate a fresh process descriptor.  Zombie
+ * process descriptors are only removed if a fresh allocation for the
+ * same PID is requested.
+ */
+
+static struct pmcstat_process *
+pmcstat_process_lookup(pid_t pid, int allocate)
+{
+	uint32_t hash;
+	struct pmcstat_pcmap *ppm, *ppmtmp;
+	struct pmcstat_process *pp, *pptmp;
+
+	hash = (uint32_t) pid & PMCSTAT_HASH_MASK;	/* simplicity wins */
+
+	LIST_FOREACH_SAFE(pp, &pmcstat_process_hash[hash], pp_next, pptmp)
+	    if (pp->pp_pid == pid) {
+		    /* Found a descriptor, check and process zombies */
+		    if (allocate && pp->pp_isactive == 0) {
+			    /* remove maps */
+			    TAILQ_FOREACH_SAFE(ppm, &pp->pp_map, ppm_next,
+				ppmtmp) {
+				    TAILQ_REMOVE(&pp->pp_map, ppm, ppm_next);
+				    free(ppm);
+			    }
+			    /* remove process entry */
+			    LIST_REMOVE(pp, pp_next);
+			    free(pp);
+			    break;
+		    }
+		    return (pp);
+	    }
+
+	if (!allocate)
+		return (NULL);
+
+	if ((pp = malloc(sizeof(*pp))) == NULL)
+		err(EX_OSERR, "ERROR: Cannot allocate pid descriptor");
+
+	pp->pp_pid = pid;
+	pp->pp_isactive = 1;
+
+	TAILQ_INIT(&pp->pp_map);
+
+	LIST_INSERT_HEAD(&pmcstat_process_hash[hash], pp, pp_next);
+	return (pp);
+}
+
+/*
+ * Associate an image and a process.
+ */
+
+static void
+pmcstat_process_exec(struct pmcstat_process *pp,
+    pmcstat_interned_string path, uintfptr_t entryaddr)
+{
+	struct pmcstat_image *image;
+
+	if ((image = pmcstat_image_from_path(path, 0)) == NULL) {
+		pmcstat_stats.ps_exec_errors++;
+		return;
+	}
+
+	if (image->pi_type == PMCSTAT_IMAGE_UNKNOWN)
+		pmcstat_image_determine_type(image);
+
+	assert(image->pi_type != PMCSTAT_IMAGE_UNKNOWN);
+
+	switch (image->pi_type) {
+	case PMCSTAT_IMAGE_ELF32:
+	case PMCSTAT_IMAGE_ELF64:
+		pmcstat_stats.ps_exec_elf++;
+		pmcstat_process_elf_exec(pp, image, entryaddr);
+		break;
+
+	case PMCSTAT_IMAGE_AOUT:
+		pmcstat_stats.ps_exec_aout++;
+		pmcstat_process_aout_exec(pp, image, entryaddr);
+		break;
+
+	case PMCSTAT_IMAGE_INDETERMINABLE:
+		pmcstat_stats.ps_exec_indeterminable++;
+		break;
+
+	default:
+		err(EX_SOFTWARE, "ERROR: Unsupported executable type for "
+		    "\"%s\"", pmcstat_string_unintern(path));
+	}
+}
+
+
+/*
+ * Find the map entry associated with process 'p' at PC value 'pc'.
+ */
+
+struct pmcstat_pcmap *
+pmcstat_process_find_map(struct pmcstat_process *p, uintfptr_t pc)
+{
+	struct pmcstat_pcmap *ppm;
+
+	TAILQ_FOREACH(ppm, &p->pp_map, ppm_next) {
+		if (pc >= ppm->ppm_lowpc && pc < ppm->ppm_highpc)
+			return (ppm);
+		if (pc < ppm->ppm_lowpc)
+			return (NULL);
+	}
+
+	return (NULL);
+}
+
+/*
+ * Convert a hwpmc(4) log to profile information.  A system-wide
+ * callgraph is generated if FLAG_DO_CALLGRAPHS is set.  gmon.out
+ * files usable by gprof(1) are created if FLAG_DO_GPROF is set.
+ */
+static int
+pmcstat_analyze_log(void)
+{
+	uint32_t cpu, cpuflags;
+	uintfptr_t pc;
+	pid_t pid;
+	struct pmcstat_image *image;
+	struct pmcstat_process *pp, *ppnew;
+	struct pmcstat_pcmap *ppm, *ppmtmp;
+	struct pmclog_ev ev;
+	struct pmcstat_pmcrecord *pmcr;
+	pmcstat_interned_string image_path;
+
+	assert(args.pa_flags & FLAG_DO_ANALYSIS);
+
+	if (elf_version(EV_CURRENT) == EV_NONE)
+		err(EX_UNAVAILABLE, "Elf library intialization failed");
+
+	while (pmclog_read(args.pa_logparser, &ev) == 0) {
+		assert(ev.pl_state == PMCLOG_OK);
+
+		switch (ev.pl_type) {
+		case PMCLOG_TYPE_INITIALIZE:
+			if ((ev.pl_u.pl_i.pl_version & 0xFF000000) !=
+			    PMC_VERSION_MAJOR << 24 && args.pa_verbosity > 0)
+				warnx("WARNING: Log version 0x%x does not "
+				    "match compiled version 0x%x.",
+				    ev.pl_u.pl_i.pl_version,
+				    PMC_VERSION_MAJOR);
+			break;
+
+		case PMCLOG_TYPE_MAP_IN:
+			/*
+			 * Introduce an address range mapping for a
+			 * userland process or the kernel (pid == -1).
+			 *
+			 * We always allocate a process descriptor so
+			 * that subsequent samples seen for this
+			 * address range are mapped to the current
+			 * object being mapped in.
+			 */
+			pid = ev.pl_u.pl_mi.pl_pid;
+			if (pid == -1)
+				pp = pmcstat_kernproc;
+			else
+				pp = pmcstat_process_lookup(pid,
+				    PMCSTAT_ALLOCATE);
+
+			assert(pp != NULL);
+
+			image_path = pmcstat_string_intern(ev.pl_u.pl_mi.
+			    pl_pathname);
+			image = pmcstat_image_from_path(image_path, pid == -1);
+			if (image->pi_type == PMCSTAT_IMAGE_UNKNOWN)
+				pmcstat_image_determine_type(image);
+			if (image->pi_type != PMCSTAT_IMAGE_INDETERMINABLE)
+				pmcstat_image_link(pp, image,
+				    ev.pl_u.pl_mi.pl_start);
+			break;
+
+		case PMCLOG_TYPE_MAP_OUT:
+			/*
+			 * Remove an address map.
+			 */
+			pid = ev.pl_u.pl_mo.pl_pid;
+			if (pid == -1)
+				pp = pmcstat_kernproc;
+			else
+				pp = pmcstat_process_lookup(pid, 0);
+
+			if (pp == NULL)	/* unknown process */
+				break;
+
+			pmcstat_image_unmap(pp, ev.pl_u.pl_mo.pl_start,
+			    ev.pl_u.pl_mo.pl_end);
+			break;
+
+		case PMCLOG_TYPE_PCSAMPLE:
+			/*
+			 * Note: the `PCSAMPLE' log entry is not
+			 * generated by hpwmc(4) after version 2.
+			 */
+
+			/*
+			 * We bring in the gmon file for the image
+			 * currently associated with the PMC & pid
+			 * pair and increment the appropriate entry
+			 * bin inside this.
+			 */
+			pmcstat_stats.ps_samples_total++;
+			ps_samples_period++;
+
+			pc = ev.pl_u.pl_s.pl_pc;
+			pp = pmcstat_process_lookup(ev.pl_u.pl_s.pl_pid,
+			    PMCSTAT_ALLOCATE);
+
+			/* Get PMC record. */
+			pmcr = pmcstat_lookup_pmcid(ev.pl_u.pl_s.pl_pmcid);
+			assert(pmcr != NULL);
+			pmcr->pr_samples++;
+
+			/*
+			 * Call the plugins processing
+			 * TODO: move pmcstat_process_find_map inside plugins
+			 */
+
+			if (plugins[args.pa_pplugin].pl_process != NULL)
+				plugins[args.pa_pplugin].pl_process(
+				    pp, pmcr, 1, &pc,
+				    pmcstat_process_find_map(pp, pc) != NULL, 0);
+			plugins[args.pa_plugin].pl_process(
+			    pp, pmcr, 1, &pc,
+			    pmcstat_process_find_map(pp, pc) != NULL, 0);
+			break;
+
+		case PMCLOG_TYPE_CALLCHAIN:
+			pmcstat_stats.ps_samples_total++;
+			ps_samples_period++;
+
+			cpuflags = ev.pl_u.pl_cc.pl_cpuflags;
+			cpu = PMC_CALLCHAIN_CPUFLAGS_TO_CPU(cpuflags);
+
+			/* Filter on the CPU id. */
+			if ((args.pa_cpumask & (1 << cpu)) == 0) {
+				pmcstat_stats.ps_samples_skipped++;
+				break;
+			}
+
+			pp = pmcstat_process_lookup(ev.pl_u.pl_cc.pl_pid,
+			    PMCSTAT_ALLOCATE);
+
+			/* Get PMC record. */
+			pmcr = pmcstat_lookup_pmcid(ev.pl_u.pl_cc.pl_pmcid);
+			assert(pmcr != NULL);
+			pmcr->pr_samples++;
+
+			/*
+			 * Call the plugins processing
+			 */
+
+			if (plugins[args.pa_pplugin].pl_process != NULL)
+				plugins[args.pa_pplugin].pl_process(
+				    pp, pmcr,
+				    ev.pl_u.pl_cc.pl_npc,
+				    ev.pl_u.pl_cc.pl_pc,
+				    PMC_CALLCHAIN_CPUFLAGS_TO_USERMODE(cpuflags),
+				    cpu);
+			plugins[args.pa_plugin].pl_process(
+			    pp, pmcr,
+			    ev.pl_u.pl_cc.pl_npc,
+			    ev.pl_u.pl_cc.pl_pc,
+			    PMC_CALLCHAIN_CPUFLAGS_TO_USERMODE(cpuflags),
+			    cpu);
+			break;
+
+		case PMCLOG_TYPE_PMCALLOCATE:
+			/*
+			 * Record the association pmc id between this
+			 * PMC and its name.
+			 */
+			pmcstat_pmcid_add(ev.pl_u.pl_a.pl_pmcid,
+			    pmcstat_string_intern(ev.pl_u.pl_a.pl_evname));
+			break;
+
+		case PMCLOG_TYPE_PROCEXEC:
+
+			/*
+			 * Change the executable image associated with
+			 * a process.
+			 */
+			pp = pmcstat_process_lookup(ev.pl_u.pl_x.pl_pid,
+			    PMCSTAT_ALLOCATE);
+
+			/* delete the current process map */
+			TAILQ_FOREACH_SAFE(ppm, &pp->pp_map, ppm_next, ppmtmp) {
+				TAILQ_REMOVE(&pp->pp_map, ppm, ppm_next);
+				free(ppm);
+			}
+
+			/* associate this process  image */
+			image_path = pmcstat_string_intern(
+				ev.pl_u.pl_x.pl_pathname);
+			assert(image_path != NULL);
+			pmcstat_process_exec(pp, image_path,
+			    ev.pl_u.pl_x.pl_entryaddr);
+			break;
+
+		case PMCLOG_TYPE_PROCEXIT:
+
+			/*
+			 * Due to the way the log is generated, the
+			 * last few samples corresponding to a process
+			 * may appear in the log after the process
+			 * exit event is recorded.  Thus we keep the
+			 * process' descriptor and associated data
+			 * structures around, but mark the process as
+			 * having exited.
+			 */
+			pp = pmcstat_process_lookup(ev.pl_u.pl_e.pl_pid, 0);
+			if (pp == NULL)
+				break;
+			pp->pp_isactive = 0;	/* mark as a zombie */
+			break;
+
+		case PMCLOG_TYPE_SYSEXIT:
+			pp = pmcstat_process_lookup(ev.pl_u.pl_se.pl_pid, 0);
+			if (pp == NULL)
+				break;
+			pp->pp_isactive = 0;	/* make a zombie */
+			break;
+
+		case PMCLOG_TYPE_PROCFORK:
+
+			/*
+			 * Allocate a process descriptor for the new
+			 * (child) process.
+			 */
+			ppnew =
+			    pmcstat_process_lookup(ev.pl_u.pl_f.pl_newpid,
+				PMCSTAT_ALLOCATE);
+
+			/*
+			 * If we had been tracking the parent, clone
+			 * its address maps.
+			 */
+			pp = pmcstat_process_lookup(ev.pl_u.pl_f.pl_oldpid, 0);
+			if (pp == NULL)
+				break;
+			TAILQ_FOREACH(ppm, &pp->pp_map, ppm_next)
+			    pmcstat_image_link(ppnew, ppm->ppm_image,
+				ppm->ppm_lowpc);
+			break;
+
+		default:	/* other types of entries are not relevant */
+			break;
+		}
+	}
+
+	if (ev.pl_state == PMCLOG_EOF)
+		return (PMCSTAT_FINISHED);
+	else if (ev.pl_state == PMCLOG_REQUIRE_DATA)
+		return (PMCSTAT_RUNNING);
+
+	err(EX_DATAERR, "ERROR: event parsing failed (record %jd, "
+	    "offset 0x%jx)", (uintmax_t) ev.pl_count + 1, ev.pl_offset);
+}
+
+/*
+ * Print log entries as text.
+ */
+
+static int
+pmcstat_print_log(void)
+{
+	struct pmclog_ev ev;
+	uint32_t npc;
+
+	while (pmclog_read(args.pa_logparser, &ev) == 0) {
+		assert(ev.pl_state == PMCLOG_OK);
+		switch (ev.pl_type) {
+		case PMCLOG_TYPE_CALLCHAIN:
+			PMCSTAT_PRINT_ENTRY("callchain",
+			    "%d 0x%x %d %d %c", ev.pl_u.pl_cc.pl_pid,
+			    ev.pl_u.pl_cc.pl_pmcid,
+			    PMC_CALLCHAIN_CPUFLAGS_TO_CPU(ev.pl_u.pl_cc. \
+				pl_cpuflags), ev.pl_u.pl_cc.pl_npc,
+			    PMC_CALLCHAIN_CPUFLAGS_TO_USERMODE(ev.pl_u.pl_cc.\
+			        pl_cpuflags) ? 'u' : 's');
+			for (npc = 0; npc < ev.pl_u.pl_cc.pl_npc; npc++)
+				PMCSTAT_PRINT_ENTRY("...", "%p",
+				    (void *) ev.pl_u.pl_cc.pl_pc[npc]);
+			break;
+		case PMCLOG_TYPE_CLOSELOG:
+			PMCSTAT_PRINT_ENTRY("closelog",);
+			break;
+		case PMCLOG_TYPE_DROPNOTIFY:
+			PMCSTAT_PRINT_ENTRY("drop",);
+			break;
+		case PMCLOG_TYPE_INITIALIZE:
+			PMCSTAT_PRINT_ENTRY("initlog","0x%x \"%s\"",
+			    ev.pl_u.pl_i.pl_version,
+			    pmc_name_of_cputype(ev.pl_u.pl_i.pl_arch));
+			if ((ev.pl_u.pl_i.pl_version & 0xFF000000) !=
+			    PMC_VERSION_MAJOR << 24 && args.pa_verbosity > 0)
+				warnx("WARNING: Log version 0x%x != expected "
+				    "version 0x%x.", ev.pl_u.pl_i.pl_version,
+				    PMC_VERSION);
+			break;
+		case PMCLOG_TYPE_MAP_IN:
+			PMCSTAT_PRINT_ENTRY("map-in","%d %p \"%s\"",
+			    ev.pl_u.pl_mi.pl_pid,
+			    (void *) ev.pl_u.pl_mi.pl_start,
+			    ev.pl_u.pl_mi.pl_pathname);
+			break;
+		case PMCLOG_TYPE_MAP_OUT:
+			PMCSTAT_PRINT_ENTRY("map-out","%d %p %p",
+			    ev.pl_u.pl_mo.pl_pid,
+			    (void *) ev.pl_u.pl_mo.pl_start,
+			    (void *) ev.pl_u.pl_mo.pl_end);
+			break;
+		case PMCLOG_TYPE_PCSAMPLE:
+			PMCSTAT_PRINT_ENTRY("sample","0x%x %d %p %c",
+			    ev.pl_u.pl_s.pl_pmcid,
+			    ev.pl_u.pl_s.pl_pid,
+			    (void *) ev.pl_u.pl_s.pl_pc,
+			    ev.pl_u.pl_s.pl_usermode ? 'u' : 's');
+			break;
+		case PMCLOG_TYPE_PMCALLOCATE:
+			PMCSTAT_PRINT_ENTRY("allocate","0x%x \"%s\" 0x%x",
+			    ev.pl_u.pl_a.pl_pmcid,
+			    ev.pl_u.pl_a.pl_evname,
+			    ev.pl_u.pl_a.pl_flags);
+			break;
+		case PMCLOG_TYPE_PMCATTACH:
+			PMCSTAT_PRINT_ENTRY("attach","0x%x %d \"%s\"",
+			    ev.pl_u.pl_t.pl_pmcid,
+			    ev.pl_u.pl_t.pl_pid,
+			    ev.pl_u.pl_t.pl_pathname);
+			break;
+		case PMCLOG_TYPE_PMCDETACH:
+			PMCSTAT_PRINT_ENTRY("detach","0x%x %d",
+			    ev.pl_u.pl_d.pl_pmcid,
+			    ev.pl_u.pl_d.pl_pid);
+			break;
+		case PMCLOG_TYPE_PROCCSW:
+			PMCSTAT_PRINT_ENTRY("cswval","0x%x %d %jd",
+			    ev.pl_u.pl_c.pl_pmcid,
+			    ev.pl_u.pl_c.pl_pid,
+			    ev.pl_u.pl_c.pl_value);
+			break;
+		case PMCLOG_TYPE_PROCEXEC:
+			PMCSTAT_PRINT_ENTRY("exec","0x%x %d %p \"%s\"",
+			    ev.pl_u.pl_x.pl_pmcid,
+			    ev.pl_u.pl_x.pl_pid,
+			    (void *) ev.pl_u.pl_x.pl_entryaddr,
+			    ev.pl_u.pl_x.pl_pathname);
+			break;
+		case PMCLOG_TYPE_PROCEXIT:
+			PMCSTAT_PRINT_ENTRY("exitval","0x%x %d %jd",
+			    ev.pl_u.pl_e.pl_pmcid,
+			    ev.pl_u.pl_e.pl_pid,
+			    ev.pl_u.pl_e.pl_value);
+			break;
+		case PMCLOG_TYPE_PROCFORK:
+			PMCSTAT_PRINT_ENTRY("fork","%d %d",
+			    ev.pl_u.pl_f.pl_oldpid,
+			    ev.pl_u.pl_f.pl_newpid);
+			break;
+		case PMCLOG_TYPE_USERDATA:
+			PMCSTAT_PRINT_ENTRY("userdata","0x%x",
+			    ev.pl_u.pl_u.pl_userdata);
+			break;
+		case PMCLOG_TYPE_SYSEXIT:
+			PMCSTAT_PRINT_ENTRY("exit","%d",
+			    ev.pl_u.pl_se.pl_pid);
+			break;
+		default:
+			fprintf(args.pa_printfile, "unknown event (type %d).\n",
+			    ev.pl_type);
+		}
+	}
+
+	if (ev.pl_state == PMCLOG_EOF)
+		return (PMCSTAT_FINISHED);
+	else if (ev.pl_state ==  PMCLOG_REQUIRE_DATA)
+		return (PMCSTAT_RUNNING);
+
+	errx(EX_DATAERR, "ERROR: event parsing failed "
+	    "(record %jd, offset 0x%jx).",
+	    (uintmax_t) ev.pl_count + 1, ev.pl_offset);
+	/*NOTREACHED*/
+}
+
+/*
+ * Public Interfaces.
+ */
+
+/*
+ * Close a logfile, after first flushing all in-module queued data.
+ */
+
+int
+pmcstat_close_log(void)
+{
+	/* If a local logfile is configured ask the kernel to stop
+	 * and flush data. Kernel will close the file when data is flushed
+	 * so keep the status to EXITING.
+	 */
+	if (args.pa_logfd != -1) {
+		if (pmc_flush_logfile() < 0)
+			err(EX_OSERR, "ERROR: logging failed");
+	}
+
+	return (args.pa_flags & FLAG_HAS_PIPE ? PMCSTAT_EXITING :
+	    PMCSTAT_FINISHED);
+}
+
+
+
+/*
+ * Open a log file, for reading or writing.
+ *
+ * The function returns the fd of a successfully opened log or -1 in
+ * case of failure.
+ */
+
+int
+pmcstat_open_log(const char *path, int mode)
+{
+	int error, fd, cfd;
+	size_t hlen;
+	const char *p, *errstr;
+	struct addrinfo hints, *res, *res0;
+	char hostname[MAXHOSTNAMELEN];
+
+	errstr = NULL;
+	fd = -1;
+
+	/*
+	 * If 'path' is "-" then open one of stdin or stdout depending
+	 * on the value of 'mode'.
+	 *
+	 * If 'path' contains a ':' and does not start with a '/' or '.',
+	 * and is being opened for writing, treat it as a "host:port"
+	 * specification and open a network socket.
+	 *
+	 * Otherwise, treat 'path' as a file name and open that.
+	 */
+	if (path[0] == '-' && path[1] == '\0')
+		fd = (mode == PMCSTAT_OPEN_FOR_READ) ? 0 : 1;
+	else if (path[0] != '/' &&
+	    path[0] != '.' && strchr(path, ':') != NULL) {
+
+		p = strrchr(path, ':');
+		hlen = p - path;
+		if (p == path || hlen >= sizeof(hostname)) {
+			errstr = strerror(EINVAL);
+			goto done;
+		}
+
+		assert(hlen < sizeof(hostname));
+		(void) strncpy(hostname, path, hlen);
+		hostname[hlen] = '\0';
+
+		(void) memset(&hints, 0, sizeof(hints));
+		hints.ai_family = AF_UNSPEC;
+		hints.ai_socktype = SOCK_STREAM;
+		if ((error = getaddrinfo(hostname, p+1, &hints, &res0)) != 0) {
+			errstr = gai_strerror(error);
+			goto done;
+		}
+
+		fd = -1;
+		for (res = res0; res; res = res->ai_next) {
+			if ((fd = socket(res->ai_family, res->ai_socktype,
+			    res->ai_protocol)) < 0) {
+				errstr = strerror(errno);
+				continue;
+			}
+			if (mode == PMCSTAT_OPEN_FOR_READ) {
+				if (bind(fd, res->ai_addr, res->ai_addrlen) < 0) {
+					errstr = strerror(errno);
+					(void) close(fd);
+					fd = -1;
+					continue;
+				}
+				listen(fd, 1);
+				cfd = accept(fd, NULL, NULL);
+				(void) close(fd);
+				if (cfd < 0) {
+					errstr = strerror(errno);
+					fd = -1;
+					break;
+				}
+				fd = cfd;
+			} else {
+				if (connect(fd, res->ai_addr, res->ai_addrlen) < 0) {
+					errstr = strerror(errno);
+					(void) close(fd);
+					fd = -1;
+					continue;
+				}
+			}
+			errstr = NULL;
+			break;
+		}
+		freeaddrinfo(res0);
+
+	} else if ((fd = open(path, mode == PMCSTAT_OPEN_FOR_READ ?
+		    O_RDONLY : (O_WRONLY|O_CREAT|O_TRUNC),
+		    S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH)) < 0)
+			errstr = strerror(errno);
+
+  done:
+	if (errstr)
+		errx(EX_OSERR, "ERROR: Cannot open \"%s\" for %s: %s.", path,
+		    (mode == PMCSTAT_OPEN_FOR_READ ? "reading" : "writing"),
+		    errstr);
+
+	return (fd);
+}
+
+/*
+ * Process a log file in offline analysis mode.
+ */
+
+int
+pmcstat_process_log(void)
+{
+
+	/*
+	 * If analysis has not been asked for, just print the log to
+	 * the current output file.
+	 */
+	if (args.pa_flags & FLAG_DO_PRINT)
+		return (pmcstat_print_log());
+	else
+		return (pmcstat_analyze_log());
+}
+
+/*
+ * Refresh top display.
+ */
+
+static void
+pmcstat_refresh_top(void)
+{
+	int v_attrs;
+	float v;
+	char pmcname[40];
+	struct pmcstat_pmcrecord *pmcpr;
+
+	/* If in pause mode do not refresh display. */
+	if (pmcstat_pause)
+		return;
+
+	/* Wait until PMC pop in the log. */
+	pmcpr = pmcstat_pmcindex_to_pmcr(pmcstat_pmcinfilter);
+	if (pmcpr == NULL)
+		return;
+
+	/* Format PMC name. */
+	if (pmcstat_mergepmc)
+		snprintf(pmcname, sizeof(pmcname), "[%s]",
+		    pmcstat_string_unintern(pmcpr->pr_pmcname));
+	else
+		snprintf(pmcname, sizeof(pmcname), "%s.%d",
+		    pmcstat_string_unintern(pmcpr->pr_pmcname),
+		    pmcstat_pmcinfilter);
+
+	/* Format samples count. */
+	if (ps_samples_period > 0)
+		v = (pmcpr->pr_samples * 100.0) / ps_samples_period;
+	else
+		v = 0.;
+	v_attrs = PMCSTAT_ATTRPERCENT(v);
+
+	PMCSTAT_PRINTBEGIN();
+	PMCSTAT_PRINTW("PMC: %s Samples: %u ",
+	    pmcname,
+	    pmcpr->pr_samples);
+	PMCSTAT_ATTRON(v_attrs);
+	PMCSTAT_PRINTW("(%.1f%%) ", v);
+	PMCSTAT_ATTROFF(v_attrs);
+	PMCSTAT_PRINTW(", %u unresolved\n\n",
+	    pmcpr->pr_dubious_frames);
+	if (plugins[args.pa_plugin].pl_topdisplay != NULL)
+		plugins[args.pa_plugin].pl_topdisplay();
+	PMCSTAT_PRINTEND();
+}
+
+/*
+ * Find the next pmc index to display.
+ */
+
+static void
+pmcstat_changefilter(void)
+{
+	int pmcin;
+	struct pmcstat_pmcrecord *pmcr;
+
+	/*
+	 * Find the next merge target.
+	 */
+	if (pmcstat_mergepmc) {
+		pmcin = pmcstat_pmcinfilter;
+
+		do {
+			pmcr = pmcstat_pmcindex_to_pmcr(pmcstat_pmcinfilter);
+			if (pmcr == NULL || pmcr == pmcr->pr_merge)
+				break;
+
+			pmcstat_pmcinfilter++;
+			if (pmcstat_pmcinfilter >= pmcstat_npmcs)
+				pmcstat_pmcinfilter = 0;
+
+		} while (pmcstat_pmcinfilter != pmcin);
+	}
+}
+
+/*
+ * Top mode keypress.
+ */
+
+int
+pmcstat_keypress_log(void)
+{
+	int c, ret = 0;
+	WINDOW *w;
+
+	w = newwin(1, 0, 1, 0);
+	c = wgetch(w);
+	wprintw(w, "Key: %c => ", c);
+	switch (c) {
+	case 'c':
+		wprintw(w, "enter mode 'd' or 'a' => ");
+		c = wgetch(w);
+		if (c == 'd') {
+			args.pa_topmode = PMCSTAT_TOP_DELTA;
+			wprintw(w, "switching to delta mode");
+		} else {
+			args.pa_topmode = PMCSTAT_TOP_ACCUM;
+			wprintw(w, "switching to accumulation mode");
+		}
+		break;
+	case 'm':
+		pmcstat_mergepmc = !pmcstat_mergepmc;
+		/*
+		 * Changing merge state require data reset.
+		 */
+		if (plugins[args.pa_plugin].pl_shutdown != NULL)
+			plugins[args.pa_plugin].pl_shutdown(NULL);
+		pmcstat_stats_reset(0);
+		if (plugins[args.pa_plugin].pl_init != NULL)
+			plugins[args.pa_plugin].pl_init();
+
+		/* Update filter to be on a merge target. */
+		pmcstat_changefilter();
+		wprintw(w, "merge PMC %s", pmcstat_mergepmc ? "on" : "off");
+		break;
+	case 'n':
+		/* Close current plugin. */
+		if (plugins[args.pa_plugin].pl_shutdown != NULL)
+			plugins[args.pa_plugin].pl_shutdown(NULL);
+
+		/* Find next top display available. */
+		do {
+			args.pa_plugin++;
+			if (plugins[args.pa_plugin].pl_name == NULL)
+				args.pa_plugin = 0;
+		} while (plugins[args.pa_plugin].pl_topdisplay == NULL);
+
+		/* Open new plugin. */
+		pmcstat_stats_reset(0);
+		if (plugins[args.pa_plugin].pl_init != NULL)
+			plugins[args.pa_plugin].pl_init();
+		wprintw(w, "switching to plugin %s",
+		    plugins[args.pa_plugin].pl_name);
+		break;
+	case 'p':
+		pmcstat_pmcinfilter++;
+		if (pmcstat_pmcinfilter >= pmcstat_npmcs)
+			pmcstat_pmcinfilter = 0;
+		pmcstat_changefilter();
+		wprintw(w, "switching to PMC %s.%d",
+		    pmcstat_pmcindex_to_name(pmcstat_pmcinfilter),
+		    pmcstat_pmcinfilter);
+		break;
+	case ' ':
+		pmcstat_pause = !pmcstat_pause;
+		if (pmcstat_pause)
+			wprintw(w, "pause => press space again to continue");
+		break;
+	case 'q':
+		wprintw(w, "exiting...");
+		ret = 1;
+		break;
+	default:
+		if (plugins[args.pa_plugin].pl_topkeypress != NULL)
+			if (plugins[args.pa_plugin].pl_topkeypress(c, w))
+				ret = 1;
+	}
+
+	wrefresh(w);
+	delwin(w);
+	return ret;
+}
+
+
+/*
+ * Top mode display.
+ */
+
+void
+pmcstat_display_log(void)
+{
+
+	pmcstat_refresh_top();
+
+	/* Reset everythings if delta mode. */
+	if (args.pa_topmode == PMCSTAT_TOP_DELTA) {
+		if (plugins[args.pa_plugin].pl_shutdown != NULL)
+			plugins[args.pa_plugin].pl_shutdown(NULL);
+		pmcstat_stats_reset(0);
+		if (plugins[args.pa_plugin].pl_init != NULL)
+			plugins[args.pa_plugin].pl_init();
+	}
+
+}
+
+/*
+ * Configure a plugins.
+ */
+
+void
+pmcstat_pluginconfigure_log(char *opt)
+{
+
+	if (strncmp(opt, "threshold=", 10) == 0) {
+		pmcstat_threshold = atof(opt+10);
+	} else {
+		if (plugins[args.pa_plugin].pl_configure != NULL) {
+			if (!plugins[args.pa_plugin].pl_configure(opt))
+				err(EX_USAGE,
+				    "ERROR: unknown option <%s>.", opt);
+		}
+	}
+}
+
+/*
+ * Initialize module.
+ */
+
+void
+pmcstat_initialize_logging(void)
+{
+	int i;
+
+	/* use a convenient format for 'ldd' output */
+	if (setenv("LD_TRACE_LOADED_OBJECTS_FMT1","%o \"%p\" %x\n",1) != 0)
+		err(EX_OSERR, "ERROR: Cannot setenv");
+
+	/* Initialize hash tables */
+	pmcstat_string_initialize();
+	for (i = 0; i < PMCSTAT_NHASH; i++) {
+		LIST_INIT(&pmcstat_image_hash[i]);
+		LIST_INIT(&pmcstat_process_hash[i]);
+	}
+
+	/*
+	 * Create a fake 'process' entry for the kernel with pid -1.
+	 * hwpmc(4) will subsequently inform us about where the kernel
+	 * and any loaded kernel modules are mapped.
+	 */
+	if ((pmcstat_kernproc = pmcstat_process_lookup((pid_t) -1,
+		 PMCSTAT_ALLOCATE)) == NULL)
+		err(EX_OSERR, "ERROR: Cannot initialize logging");
+
+	/* PMC count. */
+	pmcstat_npmcs = 0;
+
+	/* Merge PMC with same name. */
+	pmcstat_mergepmc = args.pa_mergepmc;
+
+	/*
+	 * Initialize plugins
+	 */
+
+	if (plugins[args.pa_pplugin].pl_init != NULL)
+		plugins[args.pa_pplugin].pl_init();
+	if (plugins[args.pa_plugin].pl_init != NULL)
+		plugins[args.pa_plugin].pl_init();
+}
+
+/*
+ * Shutdown module.
+ */
+
+void
+pmcstat_shutdown_logging(void)
+{
+	int i;
+	FILE *mf;
+	struct pmcstat_image *pi, *pitmp;
+	struct pmcstat_process *pp, *pptmp;
+	struct pmcstat_pcmap *ppm, *ppmtmp;
+
+	/* determine where to send the map file */
+	mf = NULL;
+	if (args.pa_mapfilename != NULL)
+		mf = (strcmp(args.pa_mapfilename, "-") == 0) ?
+		    args.pa_printfile : fopen(args.pa_mapfilename, "w");
+
+	if (mf == NULL && args.pa_flags & FLAG_DO_GPROF &&
+	    args.pa_verbosity >= 2)
+		mf = args.pa_printfile;
+
+	if (mf)
+		(void) fprintf(mf, "MAP:\n");
+
+	/*
+	 * Shutdown the plugins
+	 */
+
+	if (plugins[args.pa_plugin].pl_shutdown != NULL)
+		plugins[args.pa_plugin].pl_shutdown(mf);
+	if (plugins[args.pa_pplugin].pl_shutdown != NULL)
+		plugins[args.pa_pplugin].pl_shutdown(mf);
+
+	for (i = 0; i < PMCSTAT_NHASH; i++) {
+		LIST_FOREACH_SAFE(pi, &pmcstat_image_hash[i], pi_next,
+		    pitmp) {
+			if (plugins[args.pa_plugin].pl_shutdownimage != NULL)
+				plugins[args.pa_plugin].pl_shutdownimage(pi);
+			if (plugins[args.pa_pplugin].pl_shutdownimage != NULL)
+				plugins[args.pa_pplugin].pl_shutdownimage(pi);
+
+			free(pi->pi_symbols);
+			if (pi->pi_addr2line != NULL)
+				pclose(pi->pi_addr2line);
+			LIST_REMOVE(pi, pi_next);
+			free(pi);
+		}
+
+		LIST_FOREACH_SAFE(pp, &pmcstat_process_hash[i], pp_next,
+		    pptmp) {
+			TAILQ_FOREACH_SAFE(ppm, &pp->pp_map, ppm_next, ppmtmp) {
+				TAILQ_REMOVE(&pp->pp_map, ppm, ppm_next);
+				free(ppm);
+			}
+			LIST_REMOVE(pp, pp_next);
+			free(pp);
+		}
+	}
+
+	pmcstat_string_shutdown();
+
+	/*
+	 * Print errors unless -q was specified.  Print all statistics
+	 * if verbosity > 1.
+	 */
+#define	PRINT(N,V) do {							\
+		if (pmcstat_stats.ps_##V || args.pa_verbosity >= 2)	\
+			(void) fprintf(args.pa_printfile, " %-40s %d\n",\
+			    N, pmcstat_stats.ps_##V);			\
+	} while (0)
+
+	if (args.pa_verbosity >= 1 && (args.pa_flags & FLAG_DO_ANALYSIS)) {
+		(void) fprintf(args.pa_printfile, "CONVERSION STATISTICS:\n");
+		PRINT("#exec/a.out", exec_aout);
+		PRINT("#exec/elf", exec_elf);
+		PRINT("#exec/unknown", exec_indeterminable);
+		PRINT("#exec handling errors", exec_errors);
+		PRINT("#samples/total", samples_total);
+		PRINT("#samples/unclaimed", samples_unknown_offset);
+		PRINT("#samples/unknown-object", samples_indeterminable);
+		PRINT("#samples/unknown-function", samples_unknown_function);
+		PRINT("#callchain/dubious-frames", callchain_dubious_frames);
+	}
+
+	if (mf)
+		(void) fclose(mf);
+}
diff --git a/usr.sbin/pmcstat/pmcstat_log.h b/usr.sbin/pmcstat/pmcstat_log.h
new file mode 100644
index 0000000..0bc8b1c
--- /dev/null
+++ b/usr.sbin/pmcstat/pmcstat_log.h
@@ -0,0 +1,198 @@
+/*-
+ * Copyright (c) 2005-2007, Joseph Koshy
+ * Copyright (c) 2007 The FreeBSD Foundation
+ * Copyright (c) 2009, Fabien Thomas
+ * All rights reserved.
+ *
+ * Portions of this software were developed by A. Joseph Koshy under
+ * sponsorship from the FreeBSD Foundation and Google, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: src/usr.sbin/pmcstat/pmcstat_log.h,v 1.3 2010/09/03 13:54:02 fabient Exp $
+ */
+
+#ifndef	_PMCSTAT_LOG_H_
+#define	_PMCSTAT_LOG_H_
+
+typedef const void *pmcstat_interned_string;
+
+/*
+ * A 'pmcstat_process' structure models processes.  Each process is
+ * associated with a set of pmcstat_pcmap structures that map
+ * addresses inside it to executable objects.  This set is implemented
+ * as a list, kept sorted in ascending order of mapped addresses.
+ *
+ * 'pp_pid' holds the pid of the process.  When a process exits, the
+ * 'pp_isactive' field is set to zero, but the process structure is
+ * not immediately reclaimed because there may still be samples in the
+ * log for this process.
+ */
+
+struct pmcstat_process {
+	LIST_ENTRY(pmcstat_process) pp_next;	/* hash-next */
+	pid_t			pp_pid;		/* associated pid */
+	int			pp_isactive;	/* whether active */
+	uintfptr_t		pp_entryaddr;	/* entry address */
+	TAILQ_HEAD(,pmcstat_pcmap) pp_map;	/* address range map */
+};
+extern LIST_HEAD(pmcstat_process_hash_list, pmcstat_process) pmcstat_process_hash[PMCSTAT_NHASH];
+
+/*
+ * A 'pmcstat_image' structure describes an executable program on
+ * disk.  'pi_execpath' is a cookie representing the pathname of
+ * the executable.  'pi_start' and 'pi_end' are the least and greatest
+ * virtual addresses for the text segments in the executable.
+ * 'pi_gmonlist' contains a linked list of gmon.out files associated
+ * with this image.
+ */
+
+enum pmcstat_image_type {
+	PMCSTAT_IMAGE_UNKNOWN = 0,	/* never looked at the image */
+	PMCSTAT_IMAGE_INDETERMINABLE,	/* can't tell what the image is */
+	PMCSTAT_IMAGE_ELF32,		/* ELF 32 bit object */
+	PMCSTAT_IMAGE_ELF64,		/* ELF 64 bit object */
+	PMCSTAT_IMAGE_AOUT		/* AOUT object */
+};
+
+struct pmcstat_image {
+	LIST_ENTRY(pmcstat_image) pi_next;	/* hash link */
+	TAILQ_ENTRY(pmcstat_image) pi_lru;	/* LRU list */
+	pmcstat_interned_string	pi_execpath;    /* cookie */
+	pmcstat_interned_string pi_samplename;  /* sample path name */
+	pmcstat_interned_string pi_fullpath;    /* path to FS object */
+	pmcstat_interned_string pi_name;	/* display name */
+
+	enum pmcstat_image_type pi_type;	/* executable type */
+
+	/*
+	 * Executables have pi_start and pi_end; these are zero
+	 * for shared libraries.
+	 */
+	uintfptr_t	pi_start;	/* start address (inclusive) */
+	uintfptr_t	pi_end;		/* end address (exclusive) */
+	uintfptr_t	pi_entry;	/* entry address */
+	uintfptr_t	pi_vaddr;	/* virtual address where loaded */
+	int		pi_isdynamic;	/* whether a dynamic object */
+	int		pi_iskernelmodule;
+	pmcstat_interned_string pi_dynlinkerpath; /* path in .interp */
+
+	/* All symbols associated with this object. */
+	struct pmcstat_symbol *pi_symbols;
+	size_t		pi_symcount;
+
+	/* Handle to addr2line for this image. */
+	FILE *pi_addr2line;
+
+	/*
+	 * Plugins private data
+	 */
+
+	/* gprof:
+	 * An image can be associated with one or more gmon.out files;
+	 * one per PMC.
+	 */
+	LIST_HEAD(,pmcstat_gmonfile) pi_gmlist;
+};
+extern LIST_HEAD(pmcstat_image_hash_list, pmcstat_image) pmcstat_image_hash[PMCSTAT_NHASH];
+
+/*
+ * A 'pmcstat_pcmap' structure maps a virtual address range to an
+ * underlying 'pmcstat_image' descriptor.
+ */
+struct pmcstat_pcmap {
+	TAILQ_ENTRY(pmcstat_pcmap) ppm_next;
+	uintfptr_t	ppm_lowpc;
+	uintfptr_t	ppm_highpc;
+	struct pmcstat_image *ppm_image;
+};
+
+/*
+ * Each function symbol tracked by pmcstat(8).
+ */
+
+struct pmcstat_symbol {
+	pmcstat_interned_string ps_name;
+	uint64_t	ps_start;
+	uint64_t	ps_end;
+};
+
+/*
+ * 'pmcstat_pmcrecord' is a mapping from PMC ids to human-readable
+ * names.
+ */
+
+struct pmcstat_pmcrecord {
+	LIST_ENTRY(pmcstat_pmcrecord)	pr_next;
+	pmc_id_t			pr_pmcid;
+	int				pr_pmcin;
+	pmcstat_interned_string		pr_pmcname;
+	int				pr_samples;
+	int				pr_dubious_frames;
+	struct pmcstat_pmcrecord	*pr_merge;
+};
+extern LIST_HEAD(pmcstat_pmcs, pmcstat_pmcrecord) pmcstat_pmcs; /* PMC list */
+
+/*
+ * Misc. statistics
+ */
+struct pmcstat_stats {
+	int ps_exec_aout;	/* # a.out executables seen */
+	int ps_exec_elf;	/* # elf executables seen */
+	int ps_exec_errors;	/* # errors processing executables */
+	int ps_exec_indeterminable; /* # unknown executables seen */
+	int ps_samples_total;	/* total number of samples processed */
+	int ps_samples_skipped; /* #samples filtered out for any reason */
+	int ps_samples_unknown_offset;	/* #samples of rank 0 not in a map */
+	int ps_samples_indeterminable;	/* #samples in indeterminable images */
+	int ps_samples_unknown_function;/* #samples with unknown function at offset */
+	int ps_callchain_dubious_frames;/* #dubious frame pointers seen */
+};
+extern struct pmcstat_stats pmcstat_stats; /* statistics */
+
+extern struct pmcstat_process *pmcstat_kernproc; /* kernel 'process' */
+
+extern int pmcstat_npmcs; /* PMC count. */
+
+/*
+ * Top mode global options.
+ */
+float pmcstat_threshold; /* Threshold to filter node. */
+int pmcstat_pmcinfilter; /* PMC index displayed. */
+
+/* Function prototypes */
+const char *pmcstat_pmcid_to_name(pmc_id_t _pmcid);
+const char *pmcstat_pmcindex_to_name(int pmcin);
+struct pmcstat_pmcrecord *pmcstat_pmcindex_to_pmcr(int pmcin);
+struct pmcstat_pcmap *pmcstat_process_find_map(struct pmcstat_process *_p,
+	uintfptr_t _pc);
+struct pmcstat_symbol *pmcstat_symbol_search(struct pmcstat_image *image,
+	uintfptr_t addr);
+const char *pmcstat_string_unintern(pmcstat_interned_string _is);
+pmcstat_interned_string pmcstat_string_intern(const char *_s);
+void pmcstat_image_determine_type(struct pmcstat_image *_image);
+pmcstat_interned_string pmcstat_string_lookup(const char *_s);
+int pmcstat_image_addr2line(struct pmcstat_image *image, uintfptr_t addr,
+    char *sourcefile, size_t sourcefile_len, unsigned *sourceline,
+    char *funcname, size_t funcname_len);
+
+#endif	/* _PMCSTAT_LOG_H_ */
diff --git a/usr.sbin/pmcstat/pmcstat_top.h b/usr.sbin/pmcstat/pmcstat_top.h
new file mode 100644
index 0000000..2226b11
--- /dev/null
+++ b/usr.sbin/pmcstat/pmcstat_top.h
@@ -0,0 +1,75 @@
+/*-
+ * Copyright (c) 2009, Fabien Thomas
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: src/usr.sbin/pmcstat/pmcstat_top.h,v 1.1 2010/02/11 22:51:44 fabient Exp $
+ */
+
+#ifndef	_PMCSTAT_TOP_H_
+#define	_PMCSTAT_TOP_H_
+
+/* Return the ncurses attributes for the given value. */
+#define PMCSTAT_ATTRPERCENT(b) 					\
+    ((b) > 10.0 ? (args.pa_topcolor ? COLOR_PAIR(1) : A_BOLD) :	\
+    ((b) >  5.0 ? (args.pa_topcolor ? COLOR_PAIR(2) : 0) : 	\
+    ((b) >  2.5 ? (args.pa_topcolor ? COLOR_PAIR(3) : 0) : 0)))
+
+/* Print to the default ncurse windows if on a terminal or to the file. */
+#define PMCSTAT_PRINTW(...) do {			\
+	if (args.pa_toptty)				\
+		printw(__VA_ARGS__);			\
+	else						\
+		fprintf(args.pa_printfile, __VA_ARGS__);\
+} while (0)
+
+/* If ncurses mode active set attributes. */
+#define PMCSTAT_ATTRON(b) do {				\
+	if (args.pa_toptty)				\
+		attron(b);				\
+} while (0)
+
+/* If ncurses mode active unset attributes. */
+#define PMCSTAT_ATTROFF(b) do {				\
+	if (args.pa_toptty)				\
+		attroff(b);				\
+} while (0)
+
+/* Erase screen and set cursor to top left. */
+#define PMCSTAT_PRINTBEGIN() do {			\
+	if (args.pa_toptty)				\
+		clear();				\
+} while (0)
+
+/* Flush buffer to backend. */
+#define PMCSTAT_PRINTEND() do {				\
+	if (!args.pa_toptty) {				\
+		PMCSTAT_PRINTW("---\n");		\
+		fflush(args.pa_printfile);		\
+	} else						\
+		refresh();				\
+} while (0)
+
+/* Function prototypes */
+
+#endif	/* _PMCSTAT_TOP_H_ */
-- 
1.7.0.5

